ATMEL ATDS1120PC

Features • Comprehensive CPLD/PLD Design Environment User-friendly Microsoft Windows™ Interface (Win 95, Win 98, Win NT) Powerful Project Navigator – Utilizes Intelligent Device Fitters for Automatic Logic Synthesis and Device Resource Assignment – Allows Design Specification with Schematic Entry or the ABEL-HDL Integrated ABEL Text Design Entry and Synthesis – Friendly Windows-based User Interface is Easy to Learn and Use – ABEL-HDL Design Entry Provides Detailed Support for Programmable Logic Devices Atmel-Synario – Full Hierarchical Support Makes Large Designs Easier to Manage; Large All-behavioral Designs can be Created without Drawing any Schematics CPLD/PLD Integrated Verilog™ Timing Simulator (Optional) – Fast, Functional Simulation is Performed Directly from the Schematic Design or Behavioral Source File, Providing Quick Feedback on Logic Errors as the Design is Entered Software – Full Timing Simulation with Delay-annotated Models Provides Comprehensive Support for Timing Problems in Routed Devices – Logic-analyzer-like Waveform Viewer Provides Flexible Results Viewing, and Updates Every Time you Single-step the Simulator ATDS1100PC – Cross-probing Capabilities between the Schematic and Waveform Viewer Tie Simulation Results Directly Back to the Source Design, Making Results Easier to Interpret ATDS1120PC – Interactive Debugging Provides Force/Preset/Monitor Access to all of the Design’s Signals, for Fast and Easy, On-the-fly Changes ATDS1130PC – Industry-standard Verilog HDL Simulation Language Ensures Timely Support for New Device Architectures ATDS1140PC IEEE 1076 VHDL Synthesis and Simulation (Optional) Description Atmel-Synario is an integrated CPLD/PLD design tool. It supports all proprietary, and JEDEC standard devices offered by Atmel. The usual CAE tool capability is combined with CPLD specific functionality. A tightly integrated Windows environment gives the user a friendly, and powerful interface. The system combines schematic and behav- ioral entry methods. Functional and timing simulation are also supported. An intelligent design manager, supervises file manipulation and controls the design flow. This function allows a user to move quickly from one design to another and evaluate different implementations for an optimal solution. Rev. 0714C–09/99 1 Project Navigator Atmel-Synario Project Navigator is the core of the system. can be performed independently of the complete flow. Or, It is a powerful and simple design flow controller. Built-in you can perform a complete compilation in a single step. intelligence, gives file and run option knowledge for each Project Navigator will netlist all the schematics in your device. Select the ATF1500 and all the steps required to design, and compile, optimize, and synthesize all the design, simulate, compile and fit will appear. Change to behavioral modules. If only a portion of the design changes ATF22V10 and the steps change accordingly. You may (a module or a single schematic), you don’t have to netlist even choose to design without a particular architecture and and compile the whole design. Project Navigator knows pick it later in the design process (Virtual or Generic everything else is current by keeping track of all the files. Device). Finally, processing options are intelligently defaulted (but can also be customized). Detailed device-specific help is Project Navigator also tracks and displays status of the available for each step. design process. Each design step is clearly delineated, and 2 ATDS1100PC/1120PC/1130PC/1140PC ATDS1100PC/1120PC/1130PC/1140PC ECS – Schematic Entry Atmel-Synario schematic tool is a MS Windows-based down the hierarchy. Run a design-rule check, and errors environment. Schematic Capture in Navigator mode gives appear in a box; click on an error, and the schematic jumps an online view of the connectivity database. Push into a to the page and location of the error. Whenever a new lower-level schematic and upper level signal names are device is targeted, libraries are changed automatically. visible below. Highlight a net and you can follow it up and Device-independent Design Device-independent design is a useful design technique. It frees the designer from architectural knowledge, and allows the best device fit to each application. Until now each architecture required a different library, with different symbols. Atmel-Synario solves this problem with its power- ful and unique device-independent library. Using the standard building blocks the device-independent library provides, you can draw entire schematics that can be tar- geted to any device. The symbols have all the “smarts” to map efficiently and simulate correctly in any target device. You can build device-independent soft macros the same way. If you desire architecture specific functions, simply use the Atmel-Specific library for more efficient utilization. Now going from a 5 ns ATF16V8C to a high-density ATF1508 CPLD is only a compilation away. 3 ABEL Integration into Atmel-Synario: Behavioral Entry and Simulation ABEL is one of the tools integrated into Atmel-Synario. Therefore, importing existing PLD designs into a larger designs is straight forward. Adding new logic, and reimple- menting into a larger CPLD is simple. Experienced ABEL users can get started using Synario ABEL tool, then gradu- ally use more of the extended Atmel-Synario capability. Atmel-Synario Behavioral Entry has hierarchical capability. Large, all-behavioral designs can be entered without draw- ing any schematics. Device-specific logic synthesis allows easy design migration to all supported devices. Fastest way to migrate from simple PLDs to CPLDs: Use existing legacy designs in new designs Convert from one architecture to another Upgrade designs to new technologies ABEL – Functional Simulation VHDL – Synthesis Option ABEL has built-in functional simulation capability. This Atmel-Synario gives you full VHDL support. IEEE-1076 allows for early design cycle verification (before fitting). compliant synthesis is tightly integrated into the environ- This also enables quick design on small projects. Full ment, which allows quick implementation into all supported Synario functionality with legacy ABEL designs is also an devices. Atmel-Synario VHDL provides a full package of advantage of ABEL functional simulation. IEEE-1076 analysis, synthesis, and source-level simulation capability. Even mixing VHDL entry with ABEL and sche- matics is a simple task. A full capability VHDL design environment can be created with an additional functional simulator. 4 ATDS1100PC/1120PC/1130PC/1140PC ATDS1100PC/1120PC/1130PC/1140PC Verilog – Functional and Timing Simulation Option Verilog simulation is another of the Atmel-Synario tools. applied. Then press “go”. In batch mode, you can start and This standard simulation package gives functional and full stop simulation from the control panel. Or you can explore timing simulation. The simulation package is fully compati- your circuit’s functionality interactively. Verilog language ble with Open-Verilog, which allows construction of support also assures timely device support. powerful test benches and result analysis and summary The Verilog simulation option includes a waveform viewer functions. Atmel-Synario Simulation creates simulation display that resembles a logic analyzer format. The wave- models directly from Synario’s source files. This, coupled form viewer updates whenever you simulate, even after with an extremely fast simulator, quickly tells you whether each step of single-step session. Once a simulation runs, your logic is correct while you’re entering it – even before the values at the cursor in the waveform viewer are the synthesis and fitting steps. After fitting to a specific “dynamically backnotated” into the schematic. This allows device, the user may verify the desired timing. Solve tough you to debug your hierarchical design by viewing the logic timing problems with full delay-annotated simulation mod- values of the buried nets in the schematic as you move the els created by the fitter. cursor in the waveform viewer. To view a new signal, just Atmel-Synario Simulator doesn’t need architecture specific “probe” the new in the schematic and the signal will appear libraries and models. Simply identify which portion of the in the waveform viewer. design you want to simulate and the stimulus you want Note: Cross-probing between the schematic and waveform viewer ties simulation results directly back to the source for faster and easier interpretation. Results update each time you single-step the simulator. Multiple entry methods: Use the best one fir the application Mix methods for efficient design Quick translation of existing designs 5 Waveform Editor/Viewer Fast simulation analysis and debug are at your fingertips viewing. It’s simple to add, delete, or move signals and with waveform editor. The powerful waveform editor show buses as a group. The viewer display is updated enables simple stimulus generation, and easy result while simulating (for each simulation step). Peak VHDL – Simulator Option The Accolade Peak VHDL professional edition simulator is standards. Built-in, accelerated support for IEEE-1164 a powerful, easy-to-use system for design entry and simu- standard logic is included as well as support for IEEE- lation using VHDL. The product includes advanced, high- 1076.3 (synthesis/numeric) package. A VHDL hierarchy speed VHDL analyzer and elaborator, and support for browser, waveform interface and context-sensitive VHDL IEEE-1076.1987 and IEEE-1076.1993 language code editor add to the powerful capabilities of this option. 6 ATDS1100PC/1120PC/1130PC/1140PC ATDS1100PC/1120PC/1130PC/1140PC Ordering Information Part Number System Description ATDS1100PC Atmel-Synario Basic Schematic and ABEL entry with fitters ATDS1120PC Atmel-Synario Verilog Simulation (Option) Verilog functional and timing simulator ATDS1130PC Atmel-Synario VHDL Synthesis (Option) Synthesis - IEEE-1076.1993 ATDS1140PC Atmel-Synario VHDL Simulation (Option) Peak VHDL simulator System Requirements Environment Windows (95, 98 or NT) RAM 16MB Hard Disk 80MB Processor Intel or compatible Pentium Parallel Port For security key Microsoft Mouse or compatible Pointing device System Peripherals CD-ROM For program loading and updates 3-1/2" disk drive For program updates 7 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway 1150 E. Cheyenne Mtn. Blvd. San Jose, CA 95131 Colorado Springs, CO 80906 TEL (408) 441-0311 TEL (719) 576-3300 FAX (408) 487-2600 FAX (719) 540-1759 Europe Atmel Rousset Atmel U.K., Ltd. Zone Industrielle Coliseum Business Centre 13106 Rousset Cedex Riverside Way France Camberley, Surrey GU15 3YL TEL (33) 4-4253-6000 England FAX (33) 4-4253-6001 TEL (44) 1276-686-677 FAX (44) 1276-686-697 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 © Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ® ™ Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. Terms and product names in this document may be trademarks of others. 0714C–09/99/xM