ANALOG DEVICES AD602

Dual, Low Noise, Wideband Variable Gain Amplifiers AD600/AD602 FEATURES FUNCTIONAL BLOCK DIAGRAM GAT1 2 channels with independent gain control Linear in dB gain response PRECISION PASSIVE SCALING GATING INPUT ATTENUATOR 2 gain ranges REFERENCE INTERFACE AD600: 0 dB to 40 dB C1HI V G A1OP AD602: –10 dB to +30 dB C1LO Accurate absolute gain: ±0.3 dB A1CM GAIN CONTROL Low input noise: 1.4 nV/√Hz INTERFACE RF2 2.24kΩ (AD600) Low distortion: −60 dBc THD at ±1 V output 0dB –12.04dB –22.08dB –36.12dB 694Ω (AD602) High bandwidth: dc to 35 MHz (−3 dB) –6.02dB –18.06dB –30.1dB –42.14dB RF1 20Ω Stable group delay: ±2 ns A1HI FIXED-GAIN Low power: 125 mW (maximum) per amplifier AMPLIFIER A1LO 500Ω 62.5Ω 41.07dB (AD600) R-2R LADDER NETWORK Signal gating function for each amplifier 31.07dB (AD602) Drive high speed ADCs Figure 1. Functional Block Diagram of a Single Channel of the AD600/AD602 MIL-STD-883-compliant and DESC versions available The gain-control interfaces are fully differential, providing an APPLICATIONS input resistance of ~15 MΩ and a scale factor of 32 dB/V (that Ultrasound and sonar time-gain controls is, 31.25 mV/dB) defined by an internal voltage reference. The High performance audio and RF AGC systems response time of this interface is less than 1 μs. Each channel Signal measurement also has an independent gating facility that optionally blocks signal transmission and sets the dc output level to within a few GENERAL DESCRIPTION millivolts of the output ground. The gating control input is 1 The AD600/AD602 dual-channel, low noise, variable gain TTL- and CMOS-compatible. amplifiers are optimized for use in ultrasound imaging systems The maximum gain of the AD600 is 41.07 dB, and the maximum but are applicable to any application requiring precise gain, low gain of the AD602 is 31.07 dB; the −3 dB bandwidth of both noise and distortion, and wide bandwidth. Each independent models is nominally 35 MHz, essentially independent of the channel provides a gain of 0 dB to +40 dB in the AD600 and gain. The SNR for a 1 V rms output and a 1 MHz noise −10 dB to +30 dB in the AD602. The lower gain of the AD602 bandwidth is typically 76 dB for the AD600 and 86 dB for the results in an improved signal-to-noise ratio (SNR) at the output. AD602. The amplitude response is flat within ±0.5 dB from However, both products have the same 1.4 nV/√Hz input noise 100 kHz to 10 MHz; over this frequency range, the group delay spectral density. The decibel gain is directly proportional to the varies by less than ±2 ns at all gain settings. control voltage, accurately calibrated, and supply and temper- ature stable. Each amplifier channel can drive 100 Ω load impedances with low distortion. For example, the peak specified output is ±2.5 V To achieve the difficult performance objectives, a proprietary minimum into a 500 Ω load or ±1 V into a 100 Ω load. For a circuit form, the X-AMP®, was developed. Each channel of the 200 Ω load in shunt with 5 pF, the total harmonic distortion for X-AMP comprises a variable attenuator of 0 dB to −42.14 dB a ±1 V sinusoidal output at 10 MHz is typically −60 dBc. followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs and can benefit The AD600J/AD602J are specified for operation from 0°C to 70°C from the use of negative feedback to precisely define the gain and are available in 16-lead PDIP (N) and 16-lead SOIC packages. and dynamics. The attenuator is realized as a 7-stage R-2R The AD600A/AD602A are specified for operation from −40°C to ladder network having an input resistance of 100 Ω, laser +85°C and are available in 16-lead CERDIP (Q) and 16-lead SOIC trimmed to ±2%. The attenuation between tap points is 6.02 dB; packages. The AD600S/AD602S are specified for operation from the gain-control circuit provides continuous interpolation between −55°C to +125°C, are available in a 16-lead CERDIP (Q) package, these taps. The resulting control function is linear in dB. and are MIL-STD-883-compliant. The AD600S/AD602S are also available under DESC SMD 5962-94572. 1 Patented. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00538-001 AD600/AD602 TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 15  Applications ....................................................................................... 1  Time-Gain Control (TGC) and Time-Variable Gain (TVG) ................................................................................. 15  General Description ......................................................................... 1  Increasing Output Drive ............................................................ 15  Functional Block Diagram .............................................................. 1  Driving Capacitive Loads .......................................................... 15  Revision History ............................................................................... 2  Realizing Other Gain Ranges ................................................... 16  Specif ica t ions ..................................................................................... 3  Ultralow Noise VCA .................................................................. 16  Absolute Maximum Ratings ............................................................ 5  Low Noise, 6 dB Preamplifier ................................................... 16  ESD Caution .................................................................................. 5  Low Noise AGC Amplifier with 80 dB Gain Range .............. 17  Pin Configuration and Function Descriptions ............................. 6  Wide Range, RMS-Linear dB Measurement System Typical Performance Characteristics ............................................. 7  (2 MHz AGC Amplifier with RMS Detector) ........................ 19  Theory of Operation ...................................................................... 10  100 dB to 120 dB RMS Responding Constant Bandwidth Noise Performance ..................................................................... 10  AGC Systems with High Accuracy Decibel Outputs ............ 21  Gain-Control Interface .............................................................. 11  100 dB RMS/AGC System with Minimal Gain Error Signal-Gating Inputs .................................................................. 11  (Parallel Gain with Offset) ........................................................ 22  Common-Mode Rejection ........................................................ 11  120 dB RMS/AGC System with Optimal SNR (Sequential Gain) ....................................................................... 23  Achieving 80 dB Gain Range .................................................... 11  Outline Dimensions ....................................................................... 27  Sequential Mode (Maximum SNR) ......................................... 12  Ordering Guide .......................................................................... 29  Parallel Mode (Simplest Gain-Control Interface) .................. 13  Low Ripple Mode (Minimum Gain Error) ............................. 13  REVISION HISTORY 10/08—Rev. E to Rev. F 5/02—Rev. B to Rev. C Changes to Power Supply Parameter, Table 1 ............................... 3 Changes to Specifications ................................................................. 2 Changes to Figure 41 ...................................................................... 20 Renumber Tables and TPCs ................................................... Global Changes to Figure 45 ...................................................................... 21 8/01—Rev. A to Rev. B Changes to Figure 47 ...................................................................... 22 Changes to Accuracy Section of AD600A/AD602A column ...... 2 Changes to Figure 51 ...................................................................... 24 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 29 1/06—Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 5 Changes to The Gain-Control Interface Section ........................ 11 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 3/04—Rev. C to Rev. D Changes to Specifications ................................................................ 2 Changes to Ordering Guide ............................................................ 3 Changes to Figure 3 .......................................................................... 8 Changes to Figure 29 ...................................................................... 18 Updated Outline Dimensions ....................................................... 20 Rev. F | Page 2 of 32 AD600/AD602 SPECIFICATIONS Each amplifier section at TA = 25°C, VS = ±5 V, −625 mV ≤ VG ≤ +625 mV, RL = 500 Ω, and CL = 5 pF, unless otherwise noted. Specifications for the AD600/AD602 are identical, unless otherwise noted. Table 1. 1 1 AD600J/AD602J AD600A/AD602A Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Pin 2 to Pin 3; Pin 6 to Pin 7 98 100 102 95 100 105 Ω Input Capacitance 2 2 pF 2 Input Noise Spectral Density 1.4 1.4 nV/√Hz Noise Figure RS = 50 Ω, maximum gain 5.3 5.3 dB RS = 200 Ω, maximum gain 2 2 dB Common-Mode Rejection Ratio f = 100 kHz 30 30 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth VOUT = 100 mV rms 35 35 MHz Slew Rate 275 275 V/μs 3 Peak Output R ≥ 500 Ω ±2.5 ±3 ±2.5 ±3 V L Output Impedance f ≤ 10 MHz 2 2 Ω Output Short-Circuit Current 50 50 mA Group Delay Change vs. Gain f = 3 MHz; full gain range ±2 ±2 ns Group Delay Change vs. Frequency VG = 0 V, f = 1 MHz to 10 MHz ±2 ±2 ns Total Harmonic Distortion RL= 200 Ω, VOUT = ±1 V peak, RPD = 1 kΩ −60 −60 dBc ACCURACY AD600 Gain Error 0 dB to 3 dB gain 0 +0.5 +1 −0.5 +0.5 +1.5 dB 3 dB to 37 dB gain ±0.2 ±0.2 dB −0.5 +0.5 −1.0 +1.0 37 dB to 40 dB gain −1 −0.5 0 −1.5 −0.5 +0.5 dB 4 Maximum Output Offset Voltage V = –625 mV to +625 mV 10 50 10 65 mV G Output Offset Variation V = –625 mV to +625 mV 10 10 mV G 50 65 AD602 Gain Error –10 dB to –7 dB gain 0 +0.5 +1 –0.5 +0.5 +1.5 dB –7 dB to +27 dB gain −0.5 ±0.2 +0.5 −1.0 ±0.2 +1.0 dB 27 dB to 30 dB gain −0.5 −0.5 dB −1 0 −1.5 +0.5 4 Maximum Output Offset Voltage VG = −625 mV to +625 mV 5 30 10 45 mV Output Offset Variation V = −625 mV to +625 mV 5 30 10 45 mV G GAIN CONTROL INTERFACE Gain Scaling Factor +3 dB to +37 dB (AD600); 31.7 32 32.3 30.5 32 33.5 dB/V −7 dB to +27 dB (AD602) Common-Mode Range −0.75 +2.5 −0.75 +2.5 V Input Bias Current 0.35 1 0.35 1 μA Input Offset Current 10 50 10 50 nA Differential Input Resistance Pin 1 to Pin 16; Pin 8 to Pin 9 15 15 MΩ Response Rate Full 40 dB gain change 40 40 dB/μs Rev. F | Page 3 of 32 AD600/AD602 1 1 AD600J/AD602J AD600A/AD602A Parameter Conditions Min Typ Max Min Typ Max Unit SIGNAL GATING INTERFACE Logic Input Low (Output On) 0.8 0.8 V Logic Input High (Output Off) 2.4 2.4 V Response Time On to off, off to on 0.3 0.3 μs Input Resistance Pin 4 to Pin 3; Pin 5 to Pin 6 30 30 kΩ Output Gated Off Output Offset Voltage ±10 ±100 ±10 ±400 mV Output Noise Spectral Density 65 65 nV/√Hz Signal Feedthrough @ 1 MHz AD600 −80 −80 dB AD602 −70 −70 dB POWER SUPPLY Specified Operating Range ±4.75 ±5.25 ±4.75 ±5.25 V Quiescent Current Each channel 11 12.5 11 14 mA 1 Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units. 2 Typical open- or short-circuited input; noise is lower when the system is set to maximum gain and the input is short-circuited. This figure includes the effects of both voltage and current noise sources. 3 With an additional 1 kΩ pull-down resistor, if R < 500 Ω. L 4 The dc gain of the main amplifier in the AD600 is ×113; therefore, an input offset of only 100 μV becomes an 11.3 mV output offset. In the AD602, the amplifier gain is ×35.7; therefore, an input offset of 100 μV becomes a 3.57 mV output offset. Rev. F | Page 4 of 32 AD600/AD602 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage ± V ±7.5 V S rating only; functional operation of the device at these or any Input Voltages other conditions above those indicated in the operational Pin 1, Pin 8, Pin 9, Pin 16 ±VS section of this specification is not implied. Exposure to absolute Pin 2, Pin 3, Pin 6, Pin 7 ±2 V continuous maximum rating conditions for extended periods may affect ±VS for 10 ms device reliability. Pin 4, Pin 5 ±V S Internal Power Dissipation 600 mW Operating Temperature Range ESD CAUTION J Grade 0°C to 70°C A Grade −40°C to +85°C S Grade −55°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C θJA 16-Lead PDIP 85°C/W 16-Lead SOIC 100°C/W 16-Lead CERDIP 120°C/W Rev. F | Page 5 of 32 AD600/AD602 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C1LO 1 16 C1HI A1HI A1CM 2 15 + A1 A1LO 3 14 A1OP – GAT1 4 13 VPOS REF VNEG GAT2 5 12 – A2LO 6 11 A2OP A2 A2HI 7 + 10 A2CM 8 9 C2LO C2HI AD600/ AD602 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 C1LO CH1 Gain-Control Input Low. Positive voltage reduces CH1 gain. 2 A1HI CH1 Signal Input High. Positive voltage increases CH1 output. 3 A1LO CH1 Signal Input Low. Usually connected to CH1 input ground. 4 GAT1 CH1 Gating Input. A logic high shuts off the CH1 signal path. 5 GAT2 CH2 Gating Input. A logic high shuts off the CH2 signal path. 6 A2LO CH2 Signal Input Low. Usually connected to CH2 input ground. 7 A2HI CH2 Signal Input High. Positive voltage increases CH2 output. 8 C2LO CH2 Gain-Control Input Low. Positive voltage reduces CH2 gain. 9 C2HI CH2 Gain-Control Input High. Positive voltage increases CH2 gain. 10 A2CM CH2 Common. Usually connected to CH2 output ground. 11 A2OP CH2 Output. 12 VNEG Negative Supply for Both Amplifiers. 13 VPOS Positive Supply for Both Amplifiers. 14 A1OP CH1 Output. 15 A1CM CH1 Common. Usually connected to CH1 output ground. 16 C1HI CH1 Gain-Control Input High. Positive voltage increases CH1 gain. Rev. F | Page 6 of 32 00538-002 AD600/AD602 TYPICAL PERFORMANCE CHARACTERISTICS 0.45 10.0 9.8 0.35 9.6 0.25 9.4 0.15 9.2 0.05 9.0 –0.05 8.8 –0.15 8.6 –0.25 8.4 –0.35 8.2 –0.45 8.0 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 GAIN CONTROL VOLTAGE (V) GAIN CONTROL VOLTAGE (V) Figure 3. Gain Error vs. Gain Control Voltage Figure 6. AD600 and AD602 Typical Group Delay vs. VC V =0V G 10dB/DIV CENTER 20dB FREQ 1MHz 10kHz/DIV 17dB 0° –45° –90° 100k 1M 10M 100M FREQUENCY (Hz) Figure 4. AD600 Frequency and Phase Response vs. Gain Figure 7. Third-Order Intermodulation Distortion, V = 2 V p-p, R = 500 Ω OUT L –1.0 –1.2 –1.4 10dB –1.6 7dB –1.8 –2.0 0° –2.2 –2.4 –45° –2.6 –90° –2.8 –3.0 –3.2 –3.4 100k 1M 10M 100M 0 50 100 200 500 1000 2000 FREQUENCY (Hz) LOAD RESISTANCE (Ω) Figure 5. AD602 Frequency and Phase Response vs. Gain Figure 8. Typical Output Voltage vs. Load Resistance (Negative Output Swing Limits First) Rev. F | Page 7 of 32 GAIN ERROR (dB) 00538-005 00538-004 00538-003 NEGATIVE OUTPUT VOLTAGE LIMIT (V) GROUP DELAY (ns) 00538-007 00538-006 00538-008 AD600/AD602 102 50mV 101 GAIN = 40dB 100 100 90 99 GAIN = 20dB 98 97 GAIN = 0dB 96 95 10 0% 94 5V 100ns 93 92 100k 1M 10M 100M FREQUENCY (Hz) Figure 9. Input Impedance vs. Frequency Figure 12. Gating Feedthrough to Output, Gating Off to On 6 50mV 5 100 4 AD600 90 3 2 AD602 1 0 –1 10 0% –2 5V 100ns –3 –4 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 GAIN CONTROL VOLTAGE (V) Figure 10. Output Offset Voltage vs. Gain Control Voltage Figure 13. Gating Feedthrough to Output, Gating On to Off (Control Channel Feedthrough) 1V VOUT 1µs 1V 100 100 90 90 10 10 0% 0% 1V VC 100mV 500ns Figure 11. Gain Control Channel Response Time. Top: Output Voltage, 2 V Figure 14. Transient Response, Medium and High Gain Maximum, Bottom: Gain Control Voltage V = ±625 mV C Rev. F | Page 8 of 32 OUTPUT OFFSETVOLTAGE (mV) INPUT IMPEDANCE (Ω) INPUT OUTPUT 00538-011 00538-010 00538-009 INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT 00538-014 00538-013 00538-012 AD600/AD602 10 AD600: G = 20dB 500mV 5 AD602: G = 10dB BOTH: V = 100mV rms CM 100 0 V =±5V S 90 R = 500Ω L –5 T = 25°C A –10 AD600 –15 –20 –25 10 0% –30 AD602 1V 200ns –35 –40 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 15. Input Stage Overload Recovery Time Figure 18. CMRR vs. Frequency 20 1V 10 100 0 90 –10 AD600 –20 –30 AD602 –40 AD600: G = 40dB –50 10 AD602: G = 30dB 0% BOTH: R = 500Ω L –60 V =0V IN 200mV 500ns –70 R =50Ω S –80 100k 1M 10M 100M FREQUENCY (Hz) Figure 16. Output Stage Overload Recovery Time Figure 19. PSRR vs. Frequency 10 AD600: CH1 G = 40dB, V = 0 IN 500mV 0 CH2 G = 20dB, V = 100mV IN AD602: CH1 G = 30dB, V = 0 IN 100 –10 CH2 G = 0dB, V = 316mV IN 90 BOTH: V = 1V rms1, R = 50Ω OUT S –20 R = 500Ω L CH1 V OUT CROSSTALK = 20log –30 CH2 V IN –40 AD600 –50 10 –60 0% –70 AD602 1V 500ns –80 –90 100k 1M 10M 100M FREQUENCY (Hz) Figure 17. Transient Response Minimum Gain Figure 20. Crosstalk Between A1 and A2 vs. Frequency Rev. F | Page 9 of 32 INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT 00538-017 00538-016 00538-015 CROSSTALK (dB) PSRR (dB) CMRR (dB) 00538-019 00538-018 00538-020 AD600/AD602 THEORY OF OPERATION The AD600/AD602 have the same general design and features. The signal applied at the input of the ladder network is They comprise two fixed gain amplifiers, each preceded by a attenuated by 6.02 dB by each section; thus, the attenuation to voltage-controlled attenuator of 0 dB to 42.14 dB with independent each of the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB, control interfaces, each having a scaling factor of 32 dB per volt. 24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique circuit The AD600 amplifiers are laser trimmed to a gain of 41.07 dB technique is employed to interpolate between these tap points, (×113), providing a control range of −1.07 dB to +41.07 dB indicated by the slider in Figure 21, providing continuous (0 dB to +40 dB with overlap). The AD602 amplifiers have a gain attenuation from 0 dB to 42.14 dB. of 31.07 dB (×35.8) and provide an overall gain of −11.07 dB to To understand the AD600/AD602, it helps to think in terms of +31.07 dB (−10 dB to +30 dB with overlap). a mechanical means for moving this slider from left to right; in The advantage of this topology is that the amplifier can use fact, it is voltage controlled. The details of the control interface negative feedback to increase the accuracy of its gain. In are discussed later. Note that the gain is exactly determined at addition, because the amplifier does not have to handle large all times and a linear decibel relationship is guaranteed auto- signals at its input, the distortion can be very low. Another matically between the gain and the control parameter that feature of this approach is that the small-signal gain and phase determines the position of the slider. In practice, the gain response, and thus the pulse response, are essentially deviates from the ideal law by about ±0.2 dB peak (see Figure 28). independent of gain. Note that the signal inputs are not fully differential. A1LO, A1CM Figure 21 is a simplified schematic of one channel. The input (for CH1), A2LO, and A2CM (for CH2) provide separate access attenuator is a 7-stage R-2R ladder network, using untrimmed to the input and output grounds. This recognizes that, even when resistors of nominally R = 62.5 Ω, which results in a characteristic using a ground plane, small differences arise in the voltages at resistance of 125 Ω ± 20%. A shunt resistor is included at the these nodes. It is important that A1LO and A2LO be connected input and laser trimmed to establish a more exact input directly to the input ground(s). Significant impedance in these resistance of 100 Ω ± 2%, which ensures accurate operation connections reduces the gain accuracy. A1CM and A2CM (gain and HP corner frequency) when used in conjunction with should be connected to the load ground(s). external resistors or capacitors. NOISE PERFORMANCE GAT1 An important reason for using this approach is the superior PRECISION PASSIVE SCALING GATING noise performance that can be achieved. The nominal resistance INPUT ATTENUATOR REFERENCE INTERFACE seen at the inner tap points of the attenuator is 41.7 Ω (one third of C1HI 125 Ω), which, at 27°C, exhibits a Johnson noise spectral density V A1OP G C1LO (NSD) of 0.84 nV/√Hz (that is, √4kTR), a large fraction of the A1CM GAIN CONTROL total input noise. The first stage of the amplifier contributes INTERFACE RF2 another 1.12 nV/√Hz, for a total input noise of 1.4 nV/√Hz. 2.24kΩ (AD600) 0dB –12.04dB –22.08dB –36.12dB 694Ω (AD602) The noise at the 0 dB tap depends on whether the input is –6.02dB –18.06dB –30.1dB –42.14dB RF1 20Ω A1HI short-circuited or open-circuited. When shorted, the minimum FIXED-GAIN NSD of 1.12 nV/√Hz is achieved. When open, the resistance of A1LO AMPLIFIER 500Ω 62.5Ω R-2R LADDER NETWORK 41.07dB (AD600) 100 Ω at the first tap generates 1.29 nV/√Hz, so the noise 31.07dB (AD602) increases to 1.71 nV/√Hz. This last calculation would be important Figure 21. Simplified Block Diagram of a Single Channel of the AD600/AD602 if the AD600 were preceded, for example, by a 900 Ω resistor to The nominal maximum signal at input A1HI is 1 V rms (±1.4 V allow operation from inputs up to ±10 V rms. However, in most peak) when using the recommended ±5 V supplies, although cases, the low impedance of the source limits the maximum operation to ±2 V peak is permissible with some increase in HF noise resistance. distortion and feedthrough. Each attenuator is provided with a separate signal LO connection for use in rejecting common mode, the voltage between input and output grounds. Circuitry is included to provide rejection of up to ±100 mV. Rev. F | Page 10 of 32 00538-021 AD600/AD602 It is apparent from the foregoing that it is essential to use a low For example, the gain-control input can be fed differentially to resistance in the design of the ladder network to achieve low the inputs or single-ended by simply grounding the unused noise. In some applications, this can be inconvenient, requiring input. In another example, if the gain is controlled by a DAC providing a positive-only, ground-referenced output, the gain the use of an external buffer or preamplifier. However, very few amplifiers combine the needed low noise with low distortion at control LO pin (either C1LO or C2LO) should be biased to a maximum input levels, and the power consumption required to fixed offset of 625 mV to set the gain to 0 dB when gain control achieve this performance is quite high (due to the need to HI (C1HI or C2HI) is at zero and to set the gain to 40 dB when maintain very low resistance values while also coping with large at 1.25 V. inputs). On the other hand, there is little value in providing a It is a simple matter to include a voltage divider to achieve other buffer with high input impedance because the usual reason for scaling factors. When using an 8-bit DAC with an FS output of this—the minimization of loading of a high resistance source— 2.55 V (10 mV/bit), a 1.6 divider ratio (generating 6.25 mV/bit) is not compatible with low noise. results in a gain setting resolution of 0.2 dB/bit. The process of Apart from the small variations just mentioned, the SNR at the cascading the two sections of an AD600 or AD602 when various output is essentially independent of the attenuator setting, options exist for gain control is explained in the Achieving 80 DB because the maximum undistorted output is 1 V rms, and the Gain Range section. NSD at the output of the AD600 is fixed at 113 × 114 nV/√Hz, SIGNAL-GATING INPUTS or 158 nV/√Hz. Therefore, in a 1 MHz bandwidth, the output Each amplifier section of the AD600/AD602 is equipped with a SNR is 76 dB. The input NSD of the AD600/AD602 is the same signal-gating function, controlled by a TTL or CMOS logic but, because of the 10 dB lower gain in the AD602’s fixed input (GAT1 or GAT2). The ground references for these inputs amplifier, its output SNR is 10 dB better, or 86 dB in a 1 MHz are the signal input grounds A1LO and A2LO, respectively. bandwidth. Operation of the channel is unaffected when this input is LO or GAIN-CONTROL INTERFACE left open-circuited. Signal transmission is blocked when this The attenuation is controlled through a differential, high input is HI. The dc output level of the channel is set to within a impedance (15 MΩ) input, with a scaling factor that is laser few millivolts of the output ground (A1CM or A2CM), and trimmed to 32 dB per volt, that is, 31.25 mV/dB. Each of the simultaneously the noise level drops significantly. The reduction two amplifiers has its own control interface. An internal band in noise and spurious signal feedthrough is useful in ultrasound gap reference ensures stability of the scaling with respect to beam-forming applications, where many amplifier outputs are supply and temperature variations and is the only circuitry summed. common to both channels. COMMON-MODE REJECTION When the differential input voltage V = 0 V, the attenuator G A special circuit technique provides rejection of voltages slider is centered, providing an attenuation of +21.07 dB, appearing between input grounds (A1LO and A2LO) and resulting in an overall gain of +20 dB (= –21.07 dB + +41.07 dB). output grounds (A1CM and A2CM). This is necessary because When the control input is −625 mV, the gain is lowered by of the op amp form of the amplifier, as shown in Figure 21. +20 dB (= +0.625 × +32) to 0 dB; when set to +625 mV, the The feedback voltage is developed across the RF1 resistor gain is increased by +20 dB to +40 dB. When this interface is (which, to achieve low noise, has a value of only 20 Ω). The overdriven in either direction, the gain approaches either voltage developed across this resistor is referenced to the input −1.07 dB (= −42.14 dB + +41.07 dB) or +41.07 dB (= 0 + common, so the output voltage is also referred to that node. +41.07 dB), respectively. For zero differential signal input between A1HI and A1LO, the The gain of the AD600 can be calculated by output A1OP simply follows the voltage at A1CM. Note that the Gain (dB) = 32 VG + 20 (1) range of voltage differences that can exist between A1LO and A1CM (or A2LO and A2CM) is limited to about ±100 mV. where VG is in volts. Figure 18 shows the typical common-mode rejection ratio vs. For the AD602, the expression is frequency. Gain (dB) = 32 V + 10 (2) G ACHIEVING 80 dB GAIN RANGE Operation is specified for V in the range from −625 mV dc to G The two amplifier sections of the X-AMP can be connected in +625 mV dc. The high impedance gain-control input ensures series to achieve higher gain. In this mode, the output of A1 minimal loading when driving many amplifiers in multiple- (A1OP and A1CM) drives the input of A2 via a high-pass channel applications. The differential input configuration network (usually just a capacitor) that rejects the dc offset. provides flexibility in choosing the appropriate signal levels The nominal gain range is now –2 dB to +82 dB for the AD600 and polarities for various control schemes. or −22 dB to +62 dB for the AD602. Rev. F | Page 11 of 32 AD600/AD602 85 There are several options in connecting the gain-control inputs. 80 The choice depends on the desired SNR and gain error (output 75 ripple). The following examples feature the AD600; the 70 arguments generally apply to the AD602, with appropriate 65 changes to the gain values. 60 SEQUENTIAL MODE (MAXIMUM SNR) 55 In the sequential mode of operation, the SNR is maintained at 50 its highest level for as much of the gain control range as 45 possible, as shown in Figure 22. Note here that the gain range is 40 0 dB to 80 dB. Figure 23, Figure 24, and Figure 25 show the 35 general connections to accomplish this. Both gain-control 30 inputs, C1HI and C2HI, are driven in parallel by a positive-only, –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 ground-referenced source with a range of 0 V to 2.5 V. V G Figure 22. SNR vs. Control Voltage Sequential Control (1 MHz Bandwidth) An auxiliary amplifier that senses the voltage difference between input and output commons is provided to reject this common voltage. A2 A1 –40.00dB –41.07dB –40.00dB –42.14dB OUTPUT INPUT 41.07dB 1.07dB 41.07dB 0dB 0dB C1HI C1LO C2HI C2LO V V G1 G2 V = 0.592V V = 1.908V O1 O2 V = 0V C Figure 23. AD600 Gain Control Input Calculations for Sequential Control Operation (A) A1 A2 –0.51dB –1.07dB –0.51dB –41.63dB OUTPUT INPUT 41.07dB 41.07dB 40.56dB 40dB 0dB C1HI C1LO C2HI C2LO V V G1 G2 V = 0.592V O1 V = 1.908V O2 V = 1.25V C Figure 24. AD600 Gain Control Input Calculations for Sequential Control Operation (B) A2 A1 0dB 38.93dB 0dB –2.14dB INPUT OUTPUT 41.07dB 41.07dB 41.07dB 0dB 80dB C1HI C1LO C2HI C2LO V V G2 G1 V = 0.592V V = 1.908V O1 O2 V = 2.5V C Figure 25. AD600 Gain Control Input Calculations for Sequential Control Operation (C) Rev. F | Page 12 of 32 SNR (dB) 00538-023 00538-056 00538-055 00538-022 AD600/AD602 The gains are offset such that the gain of A2 is increased only PARALLEL MODE (SIMPLEST GAIN-CONTROL after the gain of A1 has reached its maximum value (see Figure 26). INTERFACE) Note that, for a differential input of −700 mV or less, the gain of In this mode, the gain-control voltage is applied to both inputs a single amplifier (A1 or A2) is at its minimum value of −1.07 dB; in parallel—C1HI and C2HI are connected to the control for a differential input of +700 mV or more, the gain is at its voltage, and C1LO and C2LO are optionally connected to an maximum value of +41.07 dB. Control inputs beyond these offset voltage of 0.625 V. The gain scaling is then doubled to limits do not affect the gain and can be tolerated without damage or 64dB/V, requiring only 1.25 V for an 80 dB change of gain. In foldover in the response. See the Specifications section for more this case, the amplitude of the gain ripple is also doubled, as is details on the allowable voltage range. The gain is now shown in Figure 29, and the instantaneous SNR at the output of Gain (dB) = 32 V (3) C A2 decreases linearly as the gain is increased (see Figure 30). where V is the applied control voltage. C LOW RIPPLE MODE (MINIMUM GAIN ERROR) +41.07dB As shown in Figure 28 and Figure 29, the output ripple is +40.56dB periodic. By offsetting the gains of A1 and A2 by half the +38.93dB A1 A2 period of the ripple, or 3 dB, the residual gain errors of the two * +20dB amplifiers can be made to cancel. Figure 31 shows the much * lower gain ripple when configured in this manner. Figure 32 +1.07dB –0.56dB plots the SNR as a function of gain; it is very similar to that in –1.07dB the parallel mode. 0.592 1.908 0 0.625 1.25 1.875 2.5 V (V) C GAIN –2.14 0 20 40 60 80 82.14 (dB) *GAIN OFFSET OF 1.07dB, OR 33.44mV Figure 26. Explanation of Offset Calibration for Sequential Control When V is set to zero, V = −0.592 V and the gain of A1 is C G1 1.07 dB (recall that the gain of each amplifier section is 0 dB for VG = 625 mV); meanwhile, VG2 = −1.908 V, so the gain of A2 is −1.07 dB. The overall gain is thus 0 dB (see Figure 23). When VC = 1.25 V, VG1 = 1.25 V – 0.592 V = 0.658 V, which sets the gain of A1 to 40.56 dB, while V = 1.25 V – 1.908 V = −0.658 V, G2 which sets the gain of A2 at −0.56 dB. The overall gain is now 40 dB (see Figure 24). When V = 2.5 V, the gain of A1 is 41.07 dB C and the gain of A2 is 38.93 dB, resulting in an overall gain of 80 dB (see Figure 25). This mode of operation is further clarified by Figure 27, which is a plot of the separate gains of A1 and A2 and the overall gain vs. the control voltage. Figure 28 is a plot of the gain error of the cascaded amplifiers vs. the control voltage. Rev. F | Page 13 of 32 00538-024 AD600/AD602 75 90 80 70 70 65 60 60 50 55 40 A1 50 30 COMBINED 45 20 A2 40 10 35 0 30 –10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 V V C C Figure 27. Plot of Separate and Overall Gains in Sequential Control Figure 30. SNR for Cascaded Stages—Parallel Control 5 1.2 4 1.0 3 0.8 2 0.6 1 0.4 0 0.2 –1 0.0 –2 –0.2 –3 –0.4 –4 –0.6 –5 –0.8 –6 –1.0 –7 –1.2 –8 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 V C V C Figure 28. Gain Error for Cascaded Stages—Sequential Control Figure 31. Gain Error for Cascaded Stages—Low Ripple Mode 5 80 4 75 3 70 2 65 1 60 0 –1 55 –2 50 –3 45 –4 40 –5 –6 35 –0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 V V C C Figure 29. Gain Error for Cascaded Stages—Parallel Control Figure 32. SNR vs. Control Voltage—Low Ripple Mode Rev. F | Page 14 of 32 GAIN ERROR (dB) OVERALL GAIN (dB) GAIN ERROR (dB) 00538-026 00538-025 00538-027 GAIN ERROR (dB) SNR (dB) SNR (dB) 00538-030 00538-028 00538-029 AD600/AD602 APPLICATIONS INFORMATION CONTROL VOLTAGE, The full potential of any high performance amplifier can be V G realized only by careful attention to details in its applications. VOLTAGE-OUTPUT DAC +625mV The following pages describe fully tested circuits in which many 0dB 40dB V G A1 such details have already been considered. However, as is always GAIN true of high accuracy, high speed analog circuits, the schematic C1LO C1HI –625mV 1 16 is only part of the story; this is no less true for the AD600/ A1HI A1CM 2 15 + AD602. Appropriate choices in the overall board layout and the A1 A1LO A1OP 3 14 type and placement of power supply decoupling components – GAT1 VPOS +5V 4 13 are very important. As explained previously, the input grounds REF VNEG A1LO and A2LO must use the shortest possible connections. GAT2 5 12 –5V A2LO 6 – A2OP The following circuits show examples of time-gain control for 11 A2 ultrasound and sonar, methods for increasing the output drive, A2CM A2HI 7 + 10 and AGC amplifiers for audio and RF/IF signal processing C2LO 8 9 C2HI AD600 OR using both peak and rms detectors. These circuits also illustrate AD602 methods of cascading X-AMPs for either maintaining the Figure 33. The Simplest Application of the X-AMP Is as a TGC or TVG Amplifier optimal SNR or maximizing the accuracy of the gain-control in Ultrasound or Sonar (Only A1 Connections Shown for Simplicity) voltage for use in signal measurement. These AGC circuits can INCREASING OUTPUT DRIVE be modified for use as voltage-controlled amplifiers in sonar and ultrasound applications by removing the detector and The AD600/AD602 output stage has limited capability for substituting a DAC or other voltage source for supplying the negative-load driving capability. For driving loads less than control voltage. 500 Ω, the load drive can be increased by approximately 5 mA by connecting a 1 kΩ pull-down resistor from the output to the TIME-GAIN CONTROL (TGC) AND TIME-VARIABLE negative supply (see Figure 34). GAIN (TVG) DRIVING CAPACITIVE LOADS Ultrasound and sonar systems share a similar requirement: both need to provide an exponential increase in gain in response to a For driving capacitive loads of greater than 5 pF, insert a 10 Ω linear control voltage, that is, a gain control that is linear in dB. resistor between the output and the load. This lowers the Figure 33 shows the AD600/AD602 configured for a control possibility of oscillation. voltage ramp starting at −625 mV and ending at +625 mV for a GAIN-CONTROL gain-control range of 40 dB. The polarity of the gain-control VOLTAGE voltage can be reversed, and the control voltage inputs, C1HI and C1LO, can be reversed to achieve the same effect. The gain- C1LO C1HI 1 16 control voltage can be supplied by a voltage output DAC, such A1HI A1CM V as the AD7244, which contains two complete DACs, operates IN 2 15 + A1 A1LO A1OP from ±5 V supplies, has an internal reference of +3 V, and 3 14 – GAT1 VPOS provides ±3 V of output swing. As such, it is well suited for use 4 +5V 1kΩ 13 REF with the AD600/AD602, needing only a few resistors to scale VNEG GAT2 5 12 ADDED the output voltage of the DACs to the levels needed by the –5V PULL-DOWN A2LO 6 – 11 A2OP RESISTOR AD600/AD602. A2 7 A2CM A2HI + 10 C2LO 8 9 C2HI AD600/ AD602 Figure 34. Adding a 1 kΩ Pull-Down Resistor Increases the X-AMP Output Drive by About 5 mA (Only A1 Connections Shown for Simplicity) Rev. F | Page 15 of 32 00538-031 00538-032 AD600/AD602 REALIZING OTHER GAIN RANGES LOW NOISE, 6 dB PREAMPLIFIER Larger gain ranges can be accommodated by cascading In some ultrasound applications, a high input impedance amplifiers. Combinations built by cascading two amplifiers preamplifier is needed to avoid the signal attenuation that include −20 dB to +60 dB (using one AD602), −10 dB to +70 dB results from loading the transducer by the 100 Ω input resistance (using ½ of an AD602 followed by ½ of an AD600), and 0 dB to of the X-AMP. High gain cannot be tolerated because the 80 dB (using one AD600). In multiple-channel applications, peak transducer signal is typically ±0.5 V, whereas the peak extra protection against oscillation can be provided by using input capability of the AD600 or AD602 is only slightly more amplifier sections from different packages. than ±1 V. A gain of 2 is a suitable choice. It can be shown that, if the preamplifier’s overall referred-to-input (RTI) noise is the ULTRALOW NOISE VCA same as that due to the X-AMP alone (1.4 nV/√Hz), the input The two channels of the AD600 or AD602 can operate in noise of nX2 preamplifier must be √(3/4) times as large, that is, parallel to achieve a 3 dB improvement in noise level, providing 1.2 nV/√Hz. 1 nV/√Hz without any loss of gain accuracy or bandwidth. +5V In the simplest case, as shown in Figure 35, the signal inputs, R1 1µF 49.9Ω A1HI and A2HI, are tied directly together. The outputs, A1OP R2 and A2OP, are summed via R1 and R2 (100 Ω each), and the 174Ω control inputs, C1HI/C2HI and C1LO/C2LO, operate in Q1 parallel. Using these connections, both the input and output MRF904 resistances are 50 Ω. Thus, when driven from a 50 Ω source and terminated in a 50 Ω load, the gain is reduced by 12 dB, so the R3 1µF 562Ω 0.1µF R4 gain range becomes –12 dB to +28 dB for the AD600 and −22 dB 42.2Ω –5V to +18 dB for the AD602. The peak input capability remains V INPUT IN unaffected (1 V rms at the IC pins, or 2 V rms from an GROUND 100Ω +5V R5 R OF X-AMP unloaded 50 Ω source). The loading on each output, with a IN 42.2Ω 0.1µF R6 50 Ω load, is effectively 200 Ω because the load current is 1µF 562Ω shared between the two channels, so the overall amplifier still OUTPUT GROUND Q2 meets its specified maximum output and distortion levels for a MM4049 200 Ω load. This amplifier can deliver a maximum sine wave power of 10 dBm to the load. R7 1µF 174Ω GAIN-CONTROL VOLTAGE R8 V 49.9Ω G –+ –5V C1LO C1HI Figure 36. A Low Noise Preamplifier for the AD600/AD602 1 16 A1CM A1HI An inexpensive circuit using complementary transistor types 2 15 + A1 A1OP 100Ω A1LO chosen for their low r is shown in Figure 36. The gain is bb 3 14 – VPOS V determined by the ratio of the net collector load resistance to GAT1 OUT +5V 4 13 REF V the net emitter resistance. It is an open-loop amplifier. The gain IN GAT2 VNEG 5 12 –5V 50Ω is ×2 (6 dB) only into a 100 Ω load, assumed to be provided by A2LO A2OP 100Ω – 6 11 the input resistance of the X-AMP; R2 and R7 are in shunt with A2 A2CM A2HI + 7 10 this load, and their value is important in defining the gain. For C2LO C2HI small-signal inputs, both transistors contribute an equal trans- 8 9 AD600 OR conductance that is rendered less sensitive to signal level by the AD602 emitter resistors, R4 and R5. They also play a dominant role in Figure 35. An Ultralow Noise VCA Using the AD600 or AD602 setting the gain. Rev. F | Page 16 of 32 00538-033 00538-034 AD600/AD602 This is a Class AB amplifier. As V increases in a positive IN LOW NOISE AGC AMPLIFIER WITH 80 dB GAIN direction, Q1 conducts more heavily and its r becomes lower e RANGE while Q2 increases. Conversely, increasingly negative values of Figure 37 provides an example of the ease with which the VIN result in the re of Q2 decreasing, while the re of Q1 increases. AD600 can be connected as an AGC amplifier. A1 and A2 are The design is chosen such that the net emitter resistance is cascaded, with 6 dB of attenuation introduced by the 100 Ω essentially independent of the instantaneous value of VIN, Resistor R1, while a time constant of 5 ns is formed by C1 and resulting in moderately low distortion. Low values of resistance the 50 Ω of net resistance at the input of A2. This has the dual and moderately high bias currents are important in achieving effect of lowering the overall gain range from 0 dB to +80 dB to the low noise, wide bandwidth, and low distortion of this −6 dB to +74 dB and introducing a single-pole, low-pass filter preamplifier. Heavy decoupling prevents noise on the power with a −3 dB frequency of about 32 MHz. This ensures stability supply lines from being conveyed to the input of the X-AMP. at the maximum gain for a slight reduction in the overall bandwidth. The C4 capacitor blocks the small dc offset voltage Table 4. Measured Preamplifier Performance at the output of A1 (which may otherwise saturate A2 at its Measurement Value Unit maximum gain) and introduces a high-pass corner at about Gain (f = 30 MHz) 6 dB 8 kHz, useful in eliminating low frequency noise and spurious Bandwidth (−3 dB) 250 MHz signals that can be present at the input. Input Signal for 1 dB Compression 1 V p-p Distortion VIN = 200 mV p-p HD2 0.27 % HD3 0.14 % V = 500 mV p-p HD2 0.44 % IN HD3 0.58 % System Input Noise 1.03 nV/√Hz Spectral Density (NSD) (Preamp Plus X-AMP) Input Resistance 1.4 kΩ Input Capacitance 15 pF Input Bias Current ±150 μA Power Supply Voltage ±5 V Quiescent Current 15 mA +5V R3 46.4kΩ +5V R4 3.74kΩ V ´ G 300µA AD590 +5V (AT 300K) C1HI C1LO 1 16 C2 FB A1HI A1CM 0.1µF RF C4 1µF 2 15 R1 + INPUT 0.1µF Q1 +5V DEC A1 100Ω A1LO A1OP 2N3904 3 14 – 0.1µF C1 GAT1 VPOS –5V DEC 100pF 4 13 +5V DEC + REF R2 GAT2 VNEG FB C3 –5V DEC 5 12 806Ω V PTAT 15pF – 1% A2LO A2OP 6 – 11 RF –5V A2 OUTPUT A2HI A2CM POWER SUPPLY 7 + 10 DECOUPLING NETWORK C2LO C2HI 8 9 AD600 Figure 37. This Accurate HF AGC Amplifier Uses Three Active Components Rev. F | Page 17 of 32 00538-035 AD600/AD602 A simple half-wave detector is used based on Q1 and R2. The An offset of 375 mV is applied to the inverting gain-control average current into Capacitor C2 is the difference between the inputs C1LO and C2LO. Therefore, the nominal –625 mV to current provided by the AD590 (300 μA at 300 K, 27°C) and the +625 mV range for V is translated upward (at V ´) to –0.25 V G G collector current of Q1. In turn, the control voltage, VG, is the for minimum gain to +1 V for maximum gain. This prevents time integral of this error current. When VG (thus the gain) is Q1 from going into heavy saturation at low gains and leaves stable, the rectified current in Q1 must, on average, balance sufficient headroom of 4 V for the AD590 to operate correctly exactly the current in the AD590. If the output of A2 is too small at high gains when using a 5 V supply. to do this, V ramps up, causing the gain to increase until Q1 G In fact, the 6 dB interstage attenuator means that the overall conducts sufficiently. The operation of this control system follows. gain of this AGC system actually runs from –6 dB to +74 dB. First, consider the particular case where R2 is zero and the Thus, an input of 2 V rms would be required to produce a output voltage, V , is a square wave at, for example, 100 kHz, 1 V rms output at the minimum gain, which exceeds the 1 V rms OUT well above the corner frequency of the control loop. During the maximum input specification of the AD600. The available gain time VOUT is negative, Q1 conducts. When VOUT is positive, it is range is therefore 0 dB to 74 dB (or X1 to X5000). Because the cut off. Because the average collector current is forced to be gain scaling is 15.625 mV/dB (because of the cascaded stages), 300 μA and the square wave has a 50% duty-cycle, the current the minimum value of VG´ is actually increased by 6 × +15.625 mV, when conducting must be 600 μA. With R2 omitted, the peak or about 94 mV, to −156 mV, so the risk of saturation in Q1 is value of V would be just the V of Q1 at 600 μA (typically reduced. OUT BE about 700 mV) or 2 V p-p. This voltage, thus the amplitude at BE The emitter circuit of Q1 is somewhat inductive (due to its which the output stabilizes, has a strong negative temperature finite ft and base resistance). Consequently, the effective value of coefficient (TC), typically –1.7 mV/°C. While this may not be R2 increases with frequency. This results in an increase in the troublesome in some applications, the correct value of R2 stabilized output amplitude at high frequencies, but for the renders the output stable with temperature. addition of C3, determined experimentally to be 15 pF for the To understand this, first note that the current in the AD590 is 2N3904 for maximum response flatness. Alternatively, a faster closely proportional to absolute temperature (PTAT). In fact, transistor can be used here to reduce HF peaking. Figure 38 this IC is intended for use as a thermometer. For the moment, shows the ac response at the stabilized output level of about assume that the signal is a square wave. When Q1 is conducting, 1.3 rms. Figure 39 demonstrates the output stabilization for the VOUT is the sum of VBE and a voltage that is PTAT and that can sine wave inputs of 1 mV rms to 1 V rms at frequencies of 100 kHz, be chosen to have an equal but opposite TC of the base-to- 1 MHz, and 10 MHz. emitter voltage. This is actually nothing more than the band gap voltage reference principle thinly disguised. When R2 is chosen so that the sum of the voltage across it and the V of Q1 is close BE to the band gap voltage of about 1.2 V, V is stable over a wide OUT range of temperatures, provided that Q1 and the AD590 share the same thermal environment. Because the average emitter current is 600 μA during each half- cycle of the square wave, a resistor of 833 Ω would add a PTAT 3dB voltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In practice, the optimum value of R2 depends on the transistor used and, to a lesser extent, on the waveform for which the temperature stability is to be optimized; for the devices shown 0.1 1 10 100 and sine wave signals, the recommended value is 806 Ω. This FREQUENCY (MHz) resistor also serves to lower the peak current in Q1, and the Figure 38. AC Response at the Stabilized Output Level of 1.3 V rms 200 Hz LP filter it forms with C2 helps to minimize distortion due to ripple in VG. Note that the output amplitude under sine wave conditions is higher than for a square wave because the average value of the current for an ideal rectifier would be 0.637 times as large, causing the output amplitude to be 1.88 V (= 1.2/0.637), or 1.33 V rms. In practice, the somewhat nonideal rectifier results in the sine wave output being regulated to about 1.275 V rms. Rev. F | Page 18 of 32 AGC OUTPUT CHANGE (dB) 00538-036 AD600/AD602 These problems can be eliminated using an AD636 as the detector element in an AGC loop, in which the difference between the rms output of the amplifier and a fixed dc reference +0.2 are nulled in a loop integrator. The dynamic range and the 100kHz accuracy with which the signal can be determined are now 0 entirely dependent on the amplifier used in the AGC system. 1MHz Because the input to the rms-dc converter is forced to a –0.2 10MHz constant amplitude, close to its maximum input capability, the –0.4 bandwidth is no longer signal dependent. If the amplifier has an exactly exponential (linear-dB) gain-control law, its control voltage, V , is forced by the AGC loop to have the general form G V IN() rms 0.001 0.01 0.1 1 (4) V =V log10 OUT SCALE INPUT AMPLITUDE (V rms) V REF Figure 39. Output Stabilization vs. rms Input for Sine Wave Inputs at 100 kHz, 1 MHz, and 10 MHz Figure 41 shows a practical wide dynamic range rms-responding measurement system using the AD600. Note that the signal While the band gap principle used here sets the output output of this system is available at A2OP, and the circuit can be amplitude to 1.2 V (for the square wave case), the stabilization used as a wideband AGC amplifier with an rms-responding point can be set to any higher amplitude, up to the maximum detector. This circuit can handle inputs from 100 μV to 1 V rms output of ±(V − 2) V that the AD600 can support. It is only S with a constant measurement bandwidth of 20 Hz to 2 MHz, necessary to split R2 into two components of appropriate ratio limited primarily by the AD636 rms converter. Its logarithmic whose parallel sum remains close to the zero-TC value of output is a loadable voltage accurately calibrated to 100 mV/dB 806 Ω. Figure 40 shows this and how the output can be raised or 2 V per decade, which simplifies the interpretation of the without altering the temperature stability. reading when using a DVM and is arranged to be −4 V for 5V an input of 100 μV rms, 0 V for 10 mV, and +4 V for a 1 V rms 300µA input. In terms of Equation 4, V is 10 mV and V is 2 V. AD590 REF SCALE (AT 300K) TO AD600 PIN 16 Note that the peak log output of ±4 V requires the use of ±6 V C2 supplies for the dual op amp U3 (AD712), although lower 1µF Q1 supplies suffice for the AD600 and AD636. If only ±5 V supplies 2N3904 are available, it is necessary to either use a reduced value for R2B V (say 1 V, in which case the peak output would be only SCALE + C3 R2 = R2A || R2B ≈ 806Ω V ±2 V) or restrict the dynamic range of the signal to about 60 dB. R2A PTAT 15pF – RF As in the previous case, the two amplifiers of the AD600 are TO AD600 PIN 11 OUTPUT used in cascade. However, the 6 dB attenuator and low-pass Figure 40. Modification in Detector to Raise Output to 2 V rms filter found in Figure 21 are replaced by a unity gain buffer amplifier, U3A, whose 4 MHz bandwidth eliminates the risk of WIDE RANGE, RMS-LINEAR dB MEASUREMENT instability at the highest gains. The buffer also allows the use of SYSTEM (2 MHz AGC AMPLIFIER WITH RMS a high impedance coupling network (C1/R3) that introduces a DETECTOR) high-pass corner at about 12 Hz. An input attenuator of 10 dB Monolithic rms-dc converters provide an inexpensive means to (0.316×) is now provided by R1 + R2 operating in parallel with measure the rms value of a signal of arbitrary waveform; they the input resistance of 100 Ω of the AD600. The adjustment can also provide a low accuracy logarithmic (decibel-scaled) provides exact calibration of the logarithmic intercept, VREF, in output. However, they have certain shortcomings. The first of critical applications, but R1 and R2 can be replaced by a fixed these is their restricted dynamic range, typically only 50 dB. resistor of 215 Ω if very close calibration is not needed because More troublesome is that the bandwidth is roughly proportional the input resistance of the AD600 (and all other key parameters to the signal level; for example, when the AD600/AD602 are of it and the AD636) is already laser trimmed for accurate used in conjunction with the AD636, as shown in Figure 41, the operation. This attenuator allows inputs as large as ±4 V to be AD636 provides a 3 dB bandwidth of 900 kHz for an input of accepted, that is, signals with an rms value of 1 V combined 100 mV rms but has a bandwidth of only 100 kHz for a 10 mV rms with a crest factor of up to 4. input. Its logarithmic output is unbuffered, uncalibrated, and not stable over temperature. Considerable support circuitry, including at least two adjustments and a special high TC resistor, is required to provide a useful output. Rev. F | Page 19 of 32 RELATIVE OUTPUT (dB) 00538-038 00538-037 AD600/AD602 V rms AF/RF C4 C1 OUTPUT 4.7µF 0.1µF +6V DEC CAL +6V 0dB C1LO C1HI 1 14 1 16 V +V R1 IN S INPUT 115Ω A1CM FB A1HI U2 1V rms 2 NC 2 NC 13 15 + AD636 MAX R2 200Ω 0.1µF A1 A1OP A1LO (SINE WAVE) –6V +6V 3 –V NC 12 3 14 S – DEC DEC R7 GAT1 VPOS +6V 4 C NC 11 56.2kΩ 0.1µF 4 13 AV DEC –6V REF VNEG GAT2 DEC –6V C2 dB COM 10 R3 5 12 5 R6 DEC 2µF 133kΩ 3.16kΩ FB A2LO A2OP BUF OUT R 9 – 6 6 11 L +316.2mV A2 A2CM A2HI BUF IN I 7 8 U3A 7 + 10 OUT –6V POWER SUPPLY C2LO C2HI 1/2 8 9 DECOUPLING U3B AD712 U1 1/2 NETWORK C3 AD600 AD712 1µF V OUT V G R5 R4 +100mV/dB 15.625mV/dB 16.2kΩ 3.01kΩ 0V = 0dB (AT 10mV rms) NC = NO CONNECT Figure 41. The Output of This Three-IC Circuit Is Proportional to the Decibel Value of the rms Input The output of A2 is ac-coupled via another 12 Hz high-pass To check the operation, assume that an input of 10 mV rms is filter formed by C2 and the 6.7 kΩ input resistance of the applied to the input, which results in a voltage of 3.16 mV rms AD636. The averaging time constant for the rms-dc converter at the input to A1, due to the 10 dB loss in the attenuator. If the system operates as claimed, V is determined by C4. The unbuffered output of the AD636 (at OUT (and, hence, VG) should be 0. Pin 8) is compared with a fixed voltage of 316 mV set by the This being the case, the gain of both A1 and A2 is 20 dB, and positive supply voltage of 6 V and the R6 and R7 resistors. VREF the output of the AD600 is therefore 100 times (40 dB) greater is proportional to this voltage, and systems requiring greater than its input, which evaluates to 316 mV rms, the input calibration accuracy should replace the supply-dependent required at the AD636 to balance the loop. Finally, note that, reference with a more stable source. unlike most AGC circuits that need strong temperature compensation for the internal kT/q scaling, these voltages, and Any difference in these voltages is integrated by the U3B thus the output of this measurement system, are temperature op amp, with a time constant of 3 ms formed by the parallel stable, arising directly from the fundamental and exact sum of R6/R7 and C3. If the output of the AD600 is too high, exponential attenuation of the ladder networks in the AD600. V rms is greater than the setpoint of 316 mV, causing the output of U3B—that is, VOUT—to ramp up (note that the integrator is Typical results are presented for a sine wave input at 100 kHz. noninverting). A fraction of VOUT is connected to the inverting Figure 42 shows that the output is held close to the setpoint of gain-control inputs of the AD600, causing the gain to be 316 mV rms over an input range in excess of 80 dB. reduced, as required, until V rms is exactly equal to 316 mV, at 450 which time the ac voltage at the output of A2 is forced to be 425 exactly 316 mV rms. This fraction is set by R4 and R5 such that 400 a 15.625 mV change in the control voltages of A1 and A2— 375 which would change the gain of the cascaded amplifiers by 350 1 dB—requires a change of 100 mV at VOUT. Note here that, 325 because A2 is forced to operate at an output level well below its 300 capacity, waveforms of high crest factor can be tolerated 275 throughout the amplifier. 250 225 200 175 150 10µ 100µ 1m 10m 100m 1 10 INPUT SIGNAL (V rms) Figure 42. RMS Output of A2 Held Close to the Setpoint 316 mV for an Input Range of over 80 dB Rev. F | Page 20 of 32 V (mV) OUT 00538-040 00538-039 AD600/AD602 This system can, of course, be used as an AGC amplifier in This ripple can be canceled whenever the X-AMP stages are which the rms value of the input is leveled. Figure 43 shows the cascaded by introducing a 3 dB offset between the two pairs of decibel output voltage. More revealing is Figure 44, which control voltages. A simple means to achieve this is shown in shows that the deviation from the ideal output predicted by Figure 45: the voltages at C1HI and C2HI are split by ±46.875 mV, Equation 1 over the input range 80 μV to 500 mV rms is within or ±1.5 dB. Alternatively, either one of these pins can be offset ±0.5 dB, and within ±1 dB for the 80 dB range from 80 μV to by 3 dB and a 1.5 dB gain adjustment made at the input 800 mV. By suitable choice of the input attenuator, R1 + R2, this attenuator (R1 + R2). can be centered to cover any range from a low of 25 mV to C1HI 16 1 V IN 250 mV to a high of 1 mV to 10 V, with appropriate correction A1CM 15 2 NC to the value of V . Note that V is not affected by the REF SCALE A1OP 14 3 –V –6V DEC S changes in the range. The gain ripple of ±0.2 dB seen in this VPOS U2 13 +6V DEC 4 C U1 AV curve is the result of the finite interpolation error of the AD636 VNEG AD600 C2 12 –6V DEC 5 NC dB X-AMP. Note that it occurs with a periodicity of 12 dB, twice 2µF A2OP 11 6 NC BUF OUT the separation between the tap points (because of the two A2CM 10 7 BUF IN cascaded stages). C2HI 9 5 4 –46.875mV +46.875mV –6V +6V 3 DEC DEC 78.7Ω 78.7Ω 10kΩ 10kΩ 2 3dB OFFSET NC = NO CONNECT MODIFICATION 1 Figure 45. Reducing the Gain Error Ripple 0 The error curve shown in Figure 46 demonstrates that, over the –1 central portion of the range, the output voltage can be maintained –2 close to the ideal value. The penalty for this modification is –3 higher errors at the extremities of the range. The next two applications show how three amplifier sections can be cascaded –4 to extend the nominal conversion range to 120 dB, with the –5 10µ 100µ 1m 10m 100m 1 10 inclusion of simple LP filters of the type shown in Figure 37. INPUT SIGNAL (V rms) Very low errors can then be maintained over a 100 dB range. Figure 43. The Decibel Output of the Circuit in Figure 41 Is Linear over an 2.5 80 dB Range 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 –0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.5 –2.0 10µ 100µ 1m 10m 100m 1 10 –2.5 INPUT SIGNAL (V rms) 10µ 100µ 1m 10m 100m 1 10 Figure 46. Using a 3 dB Offset Network Reduces Ripple INPUT SIGNAL (V rms) Figure 44. Data from Figure 42 Presented as the Deviation 100 dB TO 120 dB RMS RESPONDING CONSTANT from the Ideal Output Given in Equation 4 BANDWIDTH AGC SYSTEMS WITH HIGH ACCURACY DECIBEL OUTPUTS The next two applications double as both AGC amplifiers and measurement systems. In both, precise gain offsets are used to achieve either a high gain linearity of ±0.1 dB over the full 100 dB range or the optimal SNR at any gain. Rev. F | Page 21 of 32 OUTPUT ERROR (dB) V (V) OUT 00538-041 00538-042 OUTPUT ERROR (dB) 00538-044 00538-043 AD600/AD602 C1LO C1LO C1HI C1HI 1 16 1 16 INPUT R2 A1HI A1CM A1HI A1CM 1V rms C1 C4 2 15 2 15 487Ω + + MAX 0.1µF 2µF A1 A1 U3A A1LO A1OP A1LO A1OP (SINE WAVE) V 3 14 R3 3 14 OUT – 1/4 – R1 200Ω GAT1 AD713 GAT1 VPOS VPOS +5V +5V 133kΩ 4 13 4 13 DEC DEC REF REF GAT2 GAT2 VNEG VNEG C2 –5V –5V 5 12 5 12 R5 0.1µF DEC DEC 1.58kΩ A2OP A2LO A2LO – – 6 11 6 11 A2OP R4 A2 U3B A2 C3 A2HI A2CM A2HI A2CM 133kΩ 220pF 7 + 10 7 + 10 1/4 C2HI C2LO C2LO AD713 C2HI 8 9 8 9 U1 AD600 U2 AD600 +2dB –2dB +5V +62.5mV –62.5mV 0dB –5V +5V FB R7 R8 R9 R6 0.1µF 127Ω 127Ω 10kΩ 10kΩ +5V DEC C5 22µF 0.1µF –5V +5V DEC DEC FB 1 V +V 14 S IN U4 AD636 NC 2 13 NC –5V R11 –5V 46.4kΩ NC 12 POWER SUPPLY 3 –V S DEC +5V DEC DECOUPLING C6 C NC NETWORK 4 AV 11 R10 R15 4.7µF 3.16kΩ 19.6kΩ COM 5 10 dB R16 R14 6 R 9 6.65kΩ BUF OUT L 301kΩ U3C V LOG I 7 BUF IN OUT 8 Q1 1/4 R12 2N3906 AD713 +316.2mV 11.3kΩ R13 NC = NO CONNECT 3.01kΩ Figure 47. RMS Responding AGC Circuit with 100 dB Dynamic Range 5 100 dB RMS/AGC SYSTEM WITH MINIMAL GAIN 4 ERROR (PARALLEL GAIN WITH OFFSET) 3 Figure 47 shows an rms-responding AGC circuit that can be 2 used equally well as an accurate measurement system. It accepts inputs of 10 μV to 1 V rms (−100 dBV to 0 dBV) with generous 1 overrange. Figure 48 shows the logarithmic output, VLOG, which 0 is accurately scaled 1 V per decade, that is, 50 mV/dB, with an –1 intercept (V = 0) at 3.16 mV rms (−50 dBV). Gain offsets of LOG –2 ±2 dB were introduced between the amplifiers, provided by the –3 ±62.5 mV introduced by R6 to R9. These offsets cancel a small gain ripple that arises in the X-AMP from its finite interpolation –4 error, which has a period of 18 dB in the individual VCA –5 1µ 10µ 100µ 1m 10m 100m 1 10 sections. The gain ripple of all three amplifier sections without INPUT SIGNAL (V rms) this offset (in which case, the gain errors simply add) is shown Figure 48. VLOG Plotted vs. VIN for Figure 47’s Circuit Showing 120 dB AGC Range in Figure 49; it is still a remarkably low ±0.25 dB over the 108 dB range from 6 μV to 1.5 V rms. However, with the gain offsets connected, the gain linearity remains under ±0.1 dB over the specified 100 dB range (see Figure 50). Rev. F | Page 22 of 32 LOGARITHMIC OUTPUT (V) 00538-046 00538-045 AD600/AD602 2.0 The rms value of V is generated at Pin 8 of the AD636; the LOG averaging time for this process is determined by C5, and the 1.5 value shown results in less than 1% rms error at 20 Hz. The 1.0 slowly varying V rms is compared with a fixed reference of 316 mV, derived from the positive supply by R10/R11. Any 0.5 difference between these two voltages is integrated in C6, in 0.1 0 conjunction with the U3C op amp, the output of which is VLOG. –0.1 A fraction of this voltage, determined by R12 and R13, is –0.5 returned to the gain control inputs of all AD600 sections. –1.0 An increase in V lowers the gain because this voltage is LOG connected to the inverting polarity control inputs. –1.5 In this case, the gains of all three VCA sections are varied –2.0 1µ 10µ 100µ 1m 10m 100m 1 10 simultaneously, so the scaling is not 32 dB/V but 96 dB/V or INPUT SIGNAL (V rms) 10.42 mV/dB. The fraction of VLOG required to set its scaling to Figure 49. Gain Error for Figure 41 Without the 2 dB Offset Modification 50 mV/dB is therefore 10.42/50 or 0.208. The resulting full- 2.0 scale range of V is nominally ±2.5 V. This scaling allows the LOG 1.5 circuit to operate from ±5 V supplies. Optionally, the scaling can be altered to 100 mV/dB, which 1.0 would be more easily interpreted when VLOG is displayed on a 0.5 DVM by increasing R12 to 25.5 kΩ. The full-scale output of 0.1 0 ±5 V then requires the use of supply voltages of at least ±7.5 V. –0.1 A simple attenuator of 16.6 ± 1.25 dB is formed by R2/R3 –0.5 and the 100 Ω input resistance of the AD600. This allows the –1.0 reference level of the decibel output to be precisely set to 0 for an input of 3.16 mV rms and thus center the 100 dB range –1.5 between 10 μV and 1 V. In many applications, R2/R3 can be –2.0 1µ 10µ 100µ 1m 10m 100m 1 10 replaced by a fixed resistor of 590 Ω. For example, in AGC INPUT SIGNAL (V rms) applications, neither the slope nor the intercept of the Figure 50. Adding the 2 dB Offsets Improves the Linearization logarithmic output is important. The maximum gain of this circuit is 120 dB. If no filtering were A few additional components (R14 to R16 and Q1) improve the used, the noise spectral density of the AD600 (1.4 nV/√Hz) accuracy of V at the top end of the signal range (that is, for LOG would amount to an input noise of 8.28 μV rms in the full small gains). The gain starts rolling off when the input to the bandwidth (35 MHz). At a gain of one million, the output noise first amplifier, U1A, reaches 0 dB. To compensate for this non- would dominate. Consequently, some reduction of bandwidth is linearity, Q1 turns on at V ~ 1.5 V and increases the feedback LOG mandatory and, in the circuit of Figure 47, it is due mostly to a to the control inputs of the AD600s, thereby needing a smaller single-pole, low-pass filter R5/C3 that provides a −3 dB voltage at VLOG to maintain the input to the AD636 to the frequency of 458 kHz, which reduces the worst-case output setpoint of 316 mV rms. noise (at V ) to about 100 mV rms at a gain of 100 dB. Of AGC 120 dB RMS/AGC SYSTEM WITH OPTIMAL SNR course, the bandwidth (and therefore the output noise) could be (SEQUENTIAL GAIN) further reduced, for example, in audio applications, merely by In the last case, all gains are adjusted simultaneously, resulting increasing C3. The value chosen for this application is optimal in an output SNR that is always less than optimal. The use of in minimizing the error in the VLOG output for small input signals. sequential gain control results in a major improvement in SNR, The AD600 is dc-coupled, but even miniscule offset voltages at with only a slight penalty in the accuracy of VLOG and no the input would overload the output at high gains; thus, high- penalty in the stabilization accuracy of VAGC. The idea is to pass filtering is also needed. To provide operation at low increase the gain of the earlier stages first (as the signal level frequencies, two simple 0s at about 12 Hz are provided by decreases) and maintain the highest SNR throughout the R1/C1 and R4/C2; the U3A and U3B (AD713) op amp sections amplifier chain. This can be easily achieved with the AD600 are used to provide impedance buffering because the input because its gain is accurate even when the control input is resistance of the AD600 is only 100 Ω. A further 0 at 12 Hz is overdriven. That is, each gain control window of 1.25 V is provided by C4 and the 6.7 kΩ input resistance of the AD636 used fully before moving to the next amplifier to the right. rms converter. Rev. F | Page 23 of 32 GAIN ERROR (dB) GAIN ERROR (dB) 00538-048 00538-047 AD600/AD602 Figure 51 shows the circuit for the sequential control scheme. read 0 dB when V is 3.16 mV rms and to center the 100 dB IN R6 to R9 with R16 provide offsets of 42.14 dB between the range between 10 μV rms and 1 V rms input. R5 and C3 individual amplifiers to ensure smooth transitions between the provide a 3 dB noise bandwidth of 30 kHz. R12 to R15 change gain of each successive X-AMP, with the sequence of gain the scaling from 625 mV/decade at the control inputs to increase being U1A, then U1B, and then U2A. The adjustable 1 V/decade at the output. At the same time, R12 to R15 center attenuator provided by R3 + R17 and the 100 Ω input resistance the dynamic range at 60 dB, which occurs if the VG of U1B is of U1A, as well as the fixed 6 dB attenuation provided by R2 equal to 0. These arrangements ensure that the VLOG still fits and the input resistance of U1B, are included both to set V to within the ±6 V supplies. LOG 0dB ADJUST C1LO C1HI C1LO C1HI R3 1 16 1 16 R17 INPUT 200Ω 115Ω R2 A1HI A1CM A1CM A1HI C1 C4 2 15 2 15 100Ω + + V 0.1µF 2µF OUT A1 A1 U3A A1LO A1OP A1OP A1LO 3 14 3 14 1/4 – – R1 AD713 GAT1 GAT1 VPOS VPOS +5V +6V 4 13 4 13 133kΩ DEC DEC REF REF GAT2 GAT2 VNEG VNEG –6V C2 –5V 5 12 R5 5 12 DEC 0.1µF DEC 5.36kΩ A2OP A2LO A2LO 6 – 11 6 – 11 A2OP A2 U3B A2 R4 C3 A2HI A2CM A2HI A2CM 0.001µF 7 + 10 133kΩ 7 + 10 1/4 C2LO C2HI C2LO AD713 C2HI 8 9 8 9 U2 AD600 U1 AD600 R6 R7 R8 R9 R16 3.4kΩ 1kΩ 294Ω 1kΩ 287Ω +6V +6V C5 FB 22µF +6V DEC 0.1µF +6V DEC +V 1 V 14 IN S 0.1µF –6V U4 NC 2 13 NC DEC AD636 R11 56.2kΩ –6V FB 3 –V NC 12 S DEC C6 4 C 11 NC AV R10 4.7µF –6V 3.16kΩ POWER SUPPLY COM 10 NC 5 dB DECOUPLING NETWORK 6 BUF OUT R 9 NC L V U3C LOG +6V DEC 7 BUF IN I 8 OUT 1/4 R15 R13 R12 AD713 +316.2mV 5.11kΩ 866Ω 1kΩ R14 NC = NO CONNECT 7.32kΩ Figure 51. 120 dB Dynamic Range RMS Responding Circuit Optimized for SNR Rev. F | Page 24 of 32 00538-049 AD600/AD602 5 400 4 3 350 2 1 0 300 –1 –2 250 –3 –4 –5 200 1µ 10µ 100µ 1m 10m 100m 1 10 1µ 10µ 100µ 1m 10m 100m 1 10 INPUT SIGNAL (V rms) INPUT SIGNAL (V rms) Figure 52. VLOG Is Linear over the Full 120 dB Range Figure 54. V Remains Close to Its Setpoint of AGC 316 mV rms over the Full 120 dB Range Figure 52 shows VLOG to be linear over a full 120 dB range. 90 Figure 53 shows the error ripple due to the individual gain V SCALE = 10.417mV/dB C 80 functions bounded by ±0.2 dB (dotted lines) from 6 μV to 2 V. The small perturbations at about 200 μV and 20 mV, caused by 70 the impracticality of matching the gain functions perfectly, are 60 the only sign that the gains are now sequential. Figure 54 is a 50 plot of V that remains very close to its set value of 316 mV rms AGC over the full 120 dB range. 40 To compare the SNRs in the simultaneous and sequential 30 modes of operation more directly, all interstage attenuation was 20 eliminated (R2 and R3 in Figure 47 and R2 in Figure 51), the 10 input of U1A was shorted, R5 was selected to provide a 20 kHz bandwidth (R5 = 7.87 kΩ), and only the gain control was 0 –833.2 –625.0 –416.6 –208.3 0 208.3 416.6 625.0 833.2 varied, using an external source. The rms value of the noise was V (mV) C then measured at V and expressed as an SNR relative to OUT Figure 55. SNR vs. Control Voltage for Parallel Gain Control (See Figure 47) 0 dBV, which is almost the maximum output capability of the In contrast, the SNR for the sequential mode is shown in Figure 56. AD600. Results for the simultaneous mode can be seen in U1A always acts as a fixed noise source; varying its gain has no Figure 55. The SNR degrades uniformly as the gain is increased. Note that, because the inverting gain control was used, the gain influence on the output noise. This is a feature of the X-AMP in this curve and in Figure 56 decreases for more positive values technique. Therefore, for the first 40 dB of control range of the gain-control voltage. (actually slightly more, as is explained later), when only this 2.0 VCA section has its gain varied, the SNR remains constant. During this time, the gains of U1B and U2A are at their 1.5 minimum value of −1.07 dB. 1.0 90 V SCALE = 31.25mV/dB C 80 0.5 0.2 70 0 –0.2 60 –0.5 50 –1.0 40 –1.5 30 –2.0 1µ 10µ 100µ 1m 10m 100m 1 10 20 INPUT SIGNAL (V rms) 10 Figure 53. Error Ripple Caused by the Individual Gain Functions 0 –1.183 –0.558 0.067 0.692 1.317 1.942 2.567 3.192 3.817 V (V) C Figure 56. SNR vs. Control Voltage for Sequential Gain Control (See Figure 51) Rev. F | Page 25 of 32 GAIN ERROR (dB) LOGARITHMIC OUTPUT (V) 00538-050 00538-051 GAIN ERROR (mV) SNR (dB) SNR (dB) 00538-054 00538-053 00538-052 AD600/AD602 For the next 40 dB of control range, the gain of U1A remains This arrangement of staggered gains can be easily implemented fixed at its maximum value of 41.07 dB and only the gain of because, when the control inputs of the AD600 are overdriven, U1B is varied, while that of U2A remains at its minimum value the gain limits to its maximum or minimum values without side effects. This eliminates the need for awkward nonlinear shaping of −1.07 dB. In this interval, the fixed output noise of U1A is amplified by the increasing gain of U1B, and the SNR circuits that have previously been used to break up the gain progressively decreases. range of multistage AGC amplifiers. The precise values of the AD600’s maximum and minimum gain (not 0 dB and +40 dB Once U1B reaches its maximum gain of 41.07 dB, its output but −1.07 dB and +41.07 dB) explain the rather odd values of also becomes a gain-independent noise source; this noise is the offset values that are used. presented to U2A. As the control voltage is further increased, the gains of both U1A and U1B remain fixed at their maximum The optimization of the output SNR is of obvious value in AGC value of 41.07 dB, and the SNR continues to decrease. Figure 56 systems. However, in applications where these circuits are clearly shows this because the maximum SNR of 90 dB is considered for their wide range logarithmic measurement extended for the first 40 dB of input signal before it starts to roll off. capabilities, the inevitable degradation of the SNR at high gains need not seriously impair their utility. In fact, the bandwidth of the circuit shown in Figure 47 was specifically chosen to improve measurement accuracy by altering the shape of the log error curve at low signal levels (see Figure 53). Rev. F | Page 26 of 32 AD600/AD602 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 8 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE PLANE 0.014 (0.36) 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 57. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 0.098 (2.49) MAX 16 9 0.310 (7.87) 0.220 (5.59) 1 8 PIN 1 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 0.200 (5.08) (3.81) MIN 0.125 (3.18) 0.015 (0.38) SEATING 15° 0.023 (0.58) 0.070 (1.78) PLANE 0.008 (0.20) 0° 0.014 (0.36) 0.030 (0.76) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 58. 16-Lead Ceramic Dual In-Line Package [CERDIP] (Q-16) Dimensions shown in inches and (millimeters) Rev. F | Page 27 of 32 073106-B AD600/AD602 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 8 10.00 (0.3937) 1.27 (0.0500) 45° BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 59. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. F | Page 28 of 32 0.75 (0.0295) 0.25 (0.0098) 032707-B AD600/AD602 ORDERING GUIDE Model Gain Range Temperature Range Package Description Package Option AD600AQ 0 dB to 40 dB −40°C to +85°C 16-Lead CERDIP Q-16 AD600AR 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600AR-REEL 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600AR-REEL7 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD600ARZ 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD600ARZ-R7 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD600ARZ-RL 0 dB to 40 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD600JN 0 dB to 40 dB 0°C to 70°C 16-Lead PDIP N-16 1 AD600JNZ 0 dB to 40 dB 0°C to 70°C 16-Lead PDIP N-16 AD600JR 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JR-REEL 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD600JR-REEL7 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD600JRZ 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD600JRZ-R7 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD600JRZ-RL 0 dB to 40 dB 0°C to 70°C 16-Lead SOIC_W RW-16 2 AD600SQ/883B 0 dB to 40 dB −55°C to +125°C 16-Lead CERDIP Q-16 AD602AQ −10 dB to +30 dB −40°C to +85°C 16-Lead CERDIP Q-16 AD602AR −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602AR-REEL −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602AR-REEL7 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD602ARZ −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD602ARZ-R7 −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 1 AD602ARZ-RL −10 dB to +30 dB −40°C to +85°C 16-Lead SOIC_W RW-16 AD602JCHIPS DIE AD602JN −10 dB to +30 dB 0°C to 70°C 16-Lead PDIP N-16 1 AD602JNZ −10 dB to +30 dB 0°C to 70°C 16-Lead PDIP N-16 AD602JR −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JR-REEL –10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 AD602JR-REEL7 −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD602JRZ −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD602JRZ-R7 –10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 1 AD602JRZ-RL −10 dB to +30 dB 0°C to 70°C 16-Lead SOIC_W RW-16 3 AD602SQ/883B −10 dB to +30 dB −55°C to +125°C 16-Lead CERDIP Q-16 1 Z = RoHS Compliant Part. 2 Refers to AD600/AD602 military data sheet. Also available as 5962-9457201MEA. 3 Refers to AD600/AD602 military data sheet. Also available as 5962-9457202MEA. Rev. F | Page 29 of 32 AD600/AD602 NOTES Rev. F | Page 30 of 32 AD600/AD602 NOTES Rev. F | Page 31 of 32 AD600/AD602 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00538-0-10/08(F) Rev. F | Page 32 of 32