ANALOG DEVICES AD578

True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL Data Sheet AD5781 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V V CC DD REFPF REFPS Single 18-bit DAC, ±0.5 LSB INL 7.5 nV/√Hz noise spectral density 6.8kΩ 6.8kΩ AD5781 0.05 LSB long-term linearity stability A1 IOV R FB CC R1 R FB <0.05 ppm/°C temperature drift INV SDIN INPUT 1 μs settling time 18 18 SHIFT 18-BIT DAC SCLK V OUT REGISTER DAC REG 1.4 nV-sec glitch impulse AND SYNC CONTROL Operating temperature range: −40°C to +125°C LOGIC SDO 20-lead TSSOP package 6kΩ LDAC Wide power supply range of up to ±16.5 V CLR 35 MHz Schmitt triggered digital interface POWER-ON-RESET AND CLEAR LOGIC RESET 1.8 V compatible digital interface DGND V AGND V V APPLICATIONS SS REFNF REFNS Figure 1. Medical instrumentation Test and measurement Table 1. Complementary Devices Industrial control Part No. Description Scientific and aerospace instrumentation AD8675 Ultraprecision, 36 V, 2.8 nV/√Hz rail-to-rail Data acquisition systems output op amp Digital gain and offset adjustment AD8676 Ultraprecision, 36 V, 2.8 nV/√Hz dual rail-to- rail output op amp Power supply control ADA4898-1 High voltage, low noise, low distortion, unity gain stable, high speed op amp Table 2. Related Devices Part No. Description AD5791 20-bit, 1 ppm accurate DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC GENERAL DESCRIPTION 1 The AD5781 is a single 18-bit, unbuffered voltage output DAC PRODUCT HIGHLIGHTS that operates from a bipolar supply of up to 33 V. The AD5781 1. True 18-Bit Accuracy. accepts a positive reference input range of 5 V to V − 2.5 V and DD 2. Wide Power Supply Range of Up to ±16.5 V. a negative reference input range of V + 2.5 V to 0 V. The SS 3. −40°C to +125°C Operating Temperature Range. AD5781 offers a relative accuracy specification of ±0.5 LSB 4. Low 7.5 nV/√Hz Noise. maximum, and operation is guaranteed monotonic with a ±0.5 5. Low 0.05 ppm/°C Temperature Drift. LSB DNL maximum specification. The part uses a versatile 3-wire serial interface that operates at clock rates of up to 35 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V and in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state. 1 Protected by U.S. Patent No 7884747, and other patents are pending. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09092-001 AD5781 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Architecture....................................................................... 20  Applications....................................................................................... 1  Hardware Control Pins.............................................................. 21  Functional Block Diagram .............................................................. 1  On-Chip Registers...................................................................... 22  General Description ......................................................................... 1  AD5781 Features ............................................................................ 25  Product Highlights ........................................................................... 1  Power-On to 0 V......................................................................... 25  Revision History ............................................................................... 2  Configuring the AD5781 .......................................................... 25  Specifications..................................................................................... 3  DAC Output State ...................................................................... 25  Timing Characteristics ................................................................ 5  Linearity Compensation............................................................ 25  Absolute Maximum Ratings............................................................ 8  Output Amplifier Configuration.............................................. 25  ESD Caution.................................................................................. 8  Applications Information .............................................................. 27  Pin Configuration and Function Description .............................. 9  Typical Operating Circuit ......................................................... 27  Typical Performance Characteristics ........................................... 10  Evaluation Board........................................................................ 27  Terminology .................................................................................... 18  Outline Dimensions....................................................................... 28  Theory of Operation ...................................................................... 20  Ordering Guide .......................................................................... 28  REVISION HISTORY 11/11—Rev. B to Rev. C Changes to Specifications Section...................................................3 Added Figure 48; Renumbered Sequentially .............................. 17 Deleted t Parameter from Timing Specifications Section, 14 Change to Ideal Transfer Function Equation.............................. 22 Table 4 .................................................................................................5 Changes to Figure 2 and Figure 3....................................................6 9/11—Rev. A to Rev. B Changes to Figure 4...........................................................................7 Added Patent Note ........................................................................... 1 Replaced Figure 42 and Figure 43 ................................................ 16 Changes to Table 3............................................................................ 3 Added New Figure 44, Figure 45, and Figure 46, Renumbered Changes to OPGND Description, Table 12 ................................ 23 Sequentially ..................................................................................... 16 8/11—Rev. 0 to Rev. A 7/10—Revision 0: Initial Version Change to Features Section ............................................................. 1 Rev. C | Page 2 of 28 Data Sheet AD5781 SPECIFICATIONS VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 3. 1 A, B Version Parameter Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE Resolution 18 Bits Integral Nonlinearity Error (Relative −0.5 ±0.25 +0.5 LSB B version, V = +10 V, V = −10 V REFP REFN Accuracy) 3 −0.5 ±0.25 +0.5 LSB B version, V = +10 V, V = 0 V REFP REFN 3 −1 ±0.5 +1 LSB B version, VREFP = +5 V, VREFN = 0 V 4 −4 ±2 +4 LSB A version Differential Nonlinearity Error −0.5 ±0.25 +0.5 LSB VREFP = +10 V, VREFN = −10 V 3 −0.5 ±0.25 +0.5 LSB V = +10 V, V = 0 V REFP REFN 3 −1 ±0.5 +1 LSB V = +5 V, V = 0 V REFP REFN 5 Linearity Error Long-Term Stability 0.04 LSB After 500 hours at T = 125°C A 0.05 LSB After 1000 hours at TA = 125°C 0.03 LSB After 1000 hours t TA = 100°C 3 Full-Scale Error −1.75 ±0.25 +1.75 LSB VREFP = +10 V, VREFN = −10 V 3 −2.75 ±0.062 +2.75 LSB V = +10 V, V = 0 V REFP REFN 3 −5.25 ±0.2 +5.25 LSB V = +5 V, V = 0 V REFP REFN 3 −1 ±0.25 +1 LSB VREFP = +10 V, VREFN = −10 V , TA = 0°C to 105°C 3 −1 ±0.062 +1 LSB VREFP = 10 V, VREFN = 0 V , TA = 0°C to 105°C 3 −1.5 ±0.2 +1.5 LSB V = 5 V, V = 0 V , T = 0°C to 105°C REFP REFN A 3 Full-Scale Error Temperature Coefficient ±0.02 ppm FSR/°C 3 Zero-Scale Error −1.75 ±0.025 +1.75 LSB V = +10 V, V = −10 V REFP REFN 3 −2.5 ±0.38 +2.5 LSB VREFP = +10 V, VREFN = 0 V 3 −5.25 ±0.19 +5.25 LSB VREFP = +5 V, VREFN = 0 V 3 −1 ±0.025 +1 LSB V = +10 V, V = −10 V , REFP REFN T = 0°C to 105°C A 3 −1 ±0.38 +1 LSB V = 10 V, V = 0 V , T = 0°C to 105°C REFP REFN A 3 −1.5 ±0.19 +1.5 LSB VREFP = 5 V, VREFN = 0 V , TA = 0°C to 105°C 3 Zero-Scale Error Temperature Coefficient ±0.04 ppm FSR/°C 3 Gain Error −6 ±0.3 +6 ppm FSR VREFP = +10 V, VREFN = −10 V 3 −10 ±0.4 +10 ppm FSR V = +10 V, V = 0 V REFP REFN 3 −20 ±0.4 +20 ppm FSR V = +5 V, V = 0 V REFP REFN 3 Gain Error Temperature Coefficient ±0.04 ppm FSR/°C R1, RFB Matching 0.01 % 3 OUTPUT CHARACTERISTICS Output Voltage Range V V V REFN REFP Output Slew Rate 50 V/μs Unbuffered output, 10 MΩ||20 pF load Output Voltage Settling Time 1 μs 10 V step to 0.02%, using AD845 buffer in unity-gain mode 6 1 μs 125 code step to ±1 LSB Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale 7.5 nV/√Hz at 10 kHz, DAC code = midscale 7.5 nV/√Hz at 100 kHz, DAC code = midscale Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 7 10 Hz bandwidth Rev. C | Page 3 of 28 AD5781 Data Sheet 1 A, B Version Parameter Min Typ Max Unit Test Conditions/Comments Midscale Glitch Impulse 3.1 nV-sec VREFP = +10 V, VREFN = −10 V 1.7 nV-sec V = +10 V, V = 0 V REFP REFN 1.4 nV-sec V = +5 V, V = 0 V REFP REFN 6 MSB Segment Glitch Impulse 9.1 nV-sec V = +10 V, V = −10 V, see Figure 43 REFP REFN 3.6 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 44 1.9 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 45 Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp Digital Feedthrough 0.4 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output 6 kΩ Clamped to Ground) Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate 3 REFERENCE INPUTS VREFP Input Range 5 VDD − 2.5 V V V Input Range V + 2.5 V 0 REFN SS DC Input Impedance 5 6.6 kΩ V , V , code dependent, REFP REFN typical at midscale code Input Capacitance 15 pF VREFP, VREFN 3 LOGIC INPUTS 8 Input Current −1 +1 μA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF 3 LOGIC OUTPUT (SDO) Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA Output High Voltage, V IOV − 0.5 V IOV = 1.71 V to 5.5 V, sourcing 1 mA OH CC CC High Impedance Leakage Current ±1 μA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOV CC V 7.5 V + 33 V DD SS V V − 33 −2.5 V SS DD VCC 2.7 5.5 V IOVCC 1.71 5.5 V IOVCC ≤ VCC IDD 4.2 5.2 mA I 4 4.9 mA SS I 600 900 μA CC IOICC 52 140 μA SDO disabled 3, 9 DC Power Supply Rejection Ratio ±0.6 μV/V VDD ± 10%, VSS = 15 V ±0.6 μV/V VSS ± 10%, VDD = 15 V 3 AC Power Supply Rejection Ratio 95 dB V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 95 dB V ± 200 mV, 50 Hz/60 Hz, V = 15 V SS DD 1 Temperature range: −40°C to +125°C, typical conditions: T = 25°C, V = +15 V, V = −15 V, V = +10 V, V = −10 V. A DD SS REFP REFN 2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 Valid for all voltage reference spans. 5 Guaranteed by design and characterization, not production tested. 6 The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 7 Includes noise contribution from AD8676BRZ voltage reference buffers. 8 Current flowing in an individual logic pin. 9 Includes PSRR of AD8676BRZ voltage reference buffers. Rev. C | Page 4 of 28 Data Sheet AD5781 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Limit Parameter IOV = 1.71 V to 3.3 V IOV = 3.3 V to 5.5 V Unit Test Conditions/Comments CC CC 2 t1 40 28 ns min SCLK cycle time 92 60 ns min SCLK cycle time (readback and daisy-chain modes) t 15 10 ns min SCLK high time 2 t 9 5 ns min SCLK low time 3 t4 5 5 ns min SYNC to SCLK falling edge setup time t5 2 2 ns min SCLK falling edge to SYNC rising edge hold time t6 48 40 ns min Minimum SYNC high time t 8 6 ns min SYNC rising edge to next SCLK falling edge ignore 7 t 9 7 ns min Data setup time 8 t 12 7 ns min Data hold time 9 t10 13 10 ns min LDAC falling edge to SYNC falling edge t11 20 16 ns min SYNC rising edge to LDAC falling edge t12 14 11 ns min LDAC pulse width low t 130 130 ns typ LDAC falling edge to output response time 13 t 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) 14 t 50 50 ns min 15 CLR pulse width low t16 140 140 ns typ CLR pulse activation time t17 0 0 ns min SYNC falling edge to first SCLK rising edge t 65 60 ns max SYNC rising edge to SDO tristate (C = 50 pF) 18 L t 62 45 ns max SCLK rising edge to SDO valid (C = 50 pF) 19 L t 0 0 ns min SYNC rising edge to SCLK rising edge ignore 20 t21 35 35 ns typ RESET pulse width low t22 150 150 ns typ RESET pulse activation time 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes. Rev. C | Page 5 of 28 AD5781 Data Sheet t t 1 7 SCLK 1 2 24 t t t 6 3 2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t t 12 10 t 11 LDAC t V 13 OUT t V 14 OUT t 15 CLR t 16 V OUT t 21 RESET t 22 V OUT Figure 2. Write Mode Timing Diagram t 20 t t t 17 1 7 SCLK 12 2 4 1 2 24 t t t 3 2 6 t t 17 5 t t 5 4 SYNC t 9 t 8 SDIN DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION t 18 REGISTER TO BE READ t 19 SDO DB23 DB0 REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. C | Page 6 of 28 09092-002 09092-003 Data Sheet AD5781 t t 20 t 1 17 SCLK 12 24 25 26 48 t t t 3 2 6 t 5 t 4 SYNC t 9 t 8 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N – 1 INPUT WORD FOR DAC N t t 18 19 SDO DB23 DB0 DB23 DB0 UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. C | Page 7 of 28 09092-004 AD5781 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +34 V DD maximum rating conditions for extended periods may affect VSS to AGND −34 V to +0.3 V device reliability. VDD to VSS −0.3 V to +34 V This device is a high performance integrated circuit with an VCC to DGND −0.3 V to +7 V ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions IOV to DGND −0.3 V to V + 3 V or +7 V CC CC (whichever is less) should be taken for handling and assembly. Digital Inputs to DGND + 0.3 V or −0.3 V to IOVCC +7 V (whichever is less) ESD CAUTION VOUT to AGND −0.3 V to VDD + 0.3 V VREFPF to AGND −0.3 V to VDD + 0.3 V V to AGND −0.3 V to V + 0.3 V REFPS DD V to AGND V − 0.3 V to +0.3 V REFNF SS VREFNS to AGND VSS − 0.3 V to +0.3 V DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to + 125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C TJ max Power Dissipation (TJ max − TA)/θJA TSSOP Package θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.5 kV Rev. C | Page 8 of 28 Data Sheet AD5781 PIN CONFIGURATION AND FUNCTION DESCRIPTION INV 1 20 R FB V 2 19 AGND OUT V 3 18 V REFPS SS AD5781 4 V 17 V TOP VIEW REFPF REFNS (Not to Scale) 16 V 5 V DD REFNF 6 RESET 15 DGND 7 14 CLR SYNC 8 13 LDAC SCLK 9 12 V SDIN CC 10 11 IOV SDO CC Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 INV Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details. 2 V Analog Output Voltage. OUT 3 VREFPS Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFPF pin. See the AD5781 Features section for further details. 4 V Positive Reference Force Voltage Input. A voltage range of 5 V to V − 2.5 V can be connected. A unity gain amplifier REFPF DD must be connected at these pin, in conjunction with the VREFPS pin. See AD5781 Features section for further details. 5 V Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. V should be decoupled to DD DD AGND. 6 RESET Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status. 7 CLR Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 8 LDAC Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin should not be left unconnected. 9 V Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. V should be decoupled to DGND. CC CC 10 IOV Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of CC 1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC. 11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input. 12 SDIN Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock rates of up to 35 MHz. 14 SYNC Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The input shift register is updated on the rising edge of SYNC. 15 DGND Ground Reference Pin for Digital Circuitry. 16 VREFNF Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the V pin. See the AD5781 Features section for further details. REFNS 17 V Negative Reference Sense Voltage Input. A voltage range of V + 2.5 V to 0 V can be connected. A unity gain amplifier REFNS SS must be connected at these pin, in conjunction with the VREFNF pin. See the AD5781 Features section for further details. 18 V Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. V should be decoupled to SS SS AGND. 19 AGND Ground Reference Pin for Analog Circuitry. 20 R Feedback Connection for External Amplifier. See the AD5781 Features section for further details. FB Rev. C | Page 9 of 28 09092-005 AD5781 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 T = +125°C T = +25°C A AD8676 REFERENCE BUFFERS A T = +25°C T = –40°C 0.4 0.4 AD8675 OUTPUT BUFFER A A T = –40°C T = +125°C V = +10V A A REFP 0.3 0.3 V = 0V REFN V = +15V DD 0.2 0.2 V = –15V SS 0.1 0.1 0 0 –0.1 –0.1 AD8676 REFERENCE BUFFERS –0.2 –0.2 AD8675 OUTPUT BUFFER V = +10V –0.3 REFP –0.3 V = –10V REFN V = +15V DD –0.4 –0.4 V = –15V SS –0.5 –0.5 0 50000 100000 150000 200000 250000 0 50000 100000 150000 200000 250000 DAC CODE DAC CODE Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 9. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, X2 Gain Mode 0.5 0.5 T = +125°C T = +125°C AD8676 REFERENCE BUFFERS A AD8676 REFERENCE BUFFERS A T = +25°C 0.4 0.4 T = +25°C AD8675 OUTPUT BUFFER A AD8675 OUTPUT BUFFER A T = –40°C T = –40°C A V = +10V A REFP 0.3 0.3 V = –10V REFN V = +15V DD 0.2 0.2 V = –15V SS 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 V = +10V REFP –0.3 –0.3 V = 0V REFN V = +15V DD –0.4 –0.4 V = –15V SS –0.5 –0.5 0 50000 100000 150000 200000 250000 0 50000 100000 150000 200000 250000 DAC CODE DAC CODE Figure 7. Integral Nonlinearity Error vs. DAC Code, +10 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span 1.0 0.5 T = +125°C AD8676 REFERENCE BUFFERS T = +125°C A A T = +25°C 0.8 0.4 AD8675 OUTPUT BUFFER T = +25°C A A T = –40°C V = +10V T = –40°C A REFP A 0.6 0.3 V = 0V REFN V = +15V DD V = –15V 0.4 0.2 SS 0.2 0.1 0 0 –0.2 –0.1 –0.4 AD8676 REFERENCE BUFFERS –0.2 AD8675 OUTPUT BUFFER –0.6 –0.3 V = +5V REFP V = 0V REFN –0.8 V = +15V –0.4 DD V = –15V SS –1.0 –0.5 0 50000 100000 150000 200000 250000 0 50000 100000 150000 200000 250000 DAC CODE DAC CODE Figure 8. Integral Nonlinearity Error vs. DAC Code, +5 V Span Figure 11. Differential Nonlinearity Error vs. DAC Code, +10 V Span Rev. C | Page 10 of 28 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 09092-008 09092-007 09092-006 INL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 09092-011 09092-010 09092-009 Data Sheet AD5781 0.5 0.3 AD8676 REFERENCE BUFFERS T = +125°C A AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER T = +25°C A 0.4 AD8675 OUTPUT BUFFER 0.2 V = +5V T = –40°C REFP A V = +15V DD V = 0V REFN 0.3 V = –15V SS 0.1 0.2 0 0.1 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 ±10V SPAN MAX DNL +10V SPAN MAX DNL –0.4 V = +15V –0.4 +5V SPAN MAX DNL ±10V SPAN MIN DNL DD V = –15V +10V SPAN MIN DNL +5V SPAN MIN DNL SS –0.5 –0.5 0 50000 100000 150000 200000 250000 –55 –35 –15 5 25 45 65 85 105 125 DAC CODE TEMPERATURE (°C) Figure 12. Differential Nonlinearity Error vs. DAC Code, +5 V Span Figure 15. Differential Nonlinearity Error vs. Temperature 0.5 0.14 T = +25°C AD8676 REFERENCE BUFFERS A T = –40°C 0.4 AD8675 OUTPUT BUFFER 0.12 A T = +125°C V = +10V A REFP 0.3 0.10 V = 0V REFN INL MAX V = +15V DD 0.2 V = –15V 0.08 SS T = 25°C 0.1 0.06 A V = +10V REFP 0 0.04 V = –10V REFN AD8676 REFERENCE BUFFERS –0.1 0.02 AD8675 OUTPUT BUFFER –0.2 0 INL MIN –0.3 –0.02 –0.4 –0.04 –0.5 –0.06 0 50000 100000 150000 200000 250000 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 DAC CODE V /|V | (V) DD SS Figure 13. Differential Nonlinearity Error vs. DAC Code, ±10 V Span, Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span X2 Gain Mode 0.5 0.4 AD8676 REFERENCE BUFFERS 0.4 AD8675 OUTPUT BUFFER V = +15V 0.3 DD 0.3 V = –15V INL MAX SS 0.2 0.2 T = 25°C 0.1 A 0.1 V = +5V REFP V = 0V 0 REFN AD8676 REFERENCE BUFFERS 0 –0.1 AD8675 OUTPUT BUFFER –0.2 –0.1 –0.3 ±10V SPAN MAX INL +10V SPAN MAX INL –0.2 +5V SPAN MAX INL ±10V SPAN MIN INL –0.4 INL MIN +10V SPAN MIN INL +5V SPAN MIN INL –0.5 –0.3 –55 –35 –15 5 25 45 65 85 105 125 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V (V) TEMPERATURE (°C) DD –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 14. Integral Nonlinearity Error vs. Temperature Figure 17. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span Rev. C | Page 11 of 28 INL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 09092-013 09092-012 09092-014 INL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 09092-017 09092-015 09092-016 AD5781 Data Sheet 0.08 0.14 T = 25°C A 0.06 V = +5V 0.12 REFP DNL MAX V = 0V REFN AD8676 REFERENCE BUFFERS 0.04 0.10 AD8675 OUTPUT BUFFER 0.02 T = 25°C A 0.08 V = +10V REFP 0 V = –10V REFN AD8676 REFERENCE BUFFERS 0.06 AD8675 OUTPUT BUFFER –0.02 0.04 –0.04 0.02 –0.06 DNL MIN 0 –0.08 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V (V) DD V /|V | (V) DD SS –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 21. Zero-Scale Error vs. Supply Voltage, +5 V Span 0.10 0.05 T = 25°C A V = +10V REFP 0.04 V = –10V 0.05 REFN AD8676 REFERENCE BUFFERS DNL MAX AD8675 OUTPUT BUFFER 0.03 0 0.02 T = 25°C A –0.05 V = +5V REFP V = 0V REFN 0.01 AD8676 REFERENCE BUFFERS –0.10 AD8675 OUTPUT BUFFER 0 –0.15 DNL MIN –0.01 –0.20 –0.02 –0.25 –0.03 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V (V) DD V /|V | (V) DD SS –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 19. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span 0.14 0.05 0.12 0 0.10 –0.05 0.08 0.06 –0.10 T = 25°C A 0.04 V = +10V T = 25°C REFP A V = –10V V = +5V REFP REFN –0.15 V = 0V AD8676 REFERENCE BUFFERS REFN 0.02 AD8675 OUTPUT BUFFER AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0 –0.20 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V (V) V /|V | (V) DD DD SS –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 23. Midscale Error vs. Supply Voltage, +5 V Span Rev. C | Page 12 of 28 DNL ERROR (LSB) DNL ERROR (LSB) ZERO-SCALE ERROR (LSB) 09092-020 09092-018 09092-019 MID-SCALE ERROR (LSB) MID-SCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 09092-021 09092-022 09092-023 Data Sheet AD5781 –0.015 0.10 T = 25°C A 0.05 V = +5V REFP –0.020 V = 0V REFN 0 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER –0.05 –0.025 –0.10 –0.030 –0.15 –0.20 –0.035 –0.25 T = 25°C A V = +10V REFP –0.30 V = –10V –0.040 REFN AD8676 REFERENCE BUFFERS –0.35 AD8675 OUTPUT BUFFER –0.045 –0.40 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V (V) V /|V | (V) DD DD SS –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span Figure 27. Gain Error vs. Supply Voltage, +5 V Span 0.07 0.15 0.06 0.10 INL MAX 0.05 0.05 0.04 T = 25°C A V = +15V 0.03 DD V = –15V 0 SS AD8676 REFERENCE BUFFERS 0.02 AD8675 OUTPUT BUFFER –0.05 0.01 T = 25°C A V = +5V REFP 0 V = 0V REFN –0.10 INL MIN AD8676 REFERENCE BUFFERS –0.01 AD8675 OUTPUT BUFFER –0.02 –0.15 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V (V) DD V /|V | (V) REFP REFN –2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5 V (V) SS Figure 25. Full-Scale Error vs. Supply Voltage, +5 V Span Figure 28. Integral Nonlinearity Error vs. Reference Voltage –0.30 0.10 T = 25°C A DNL MAX V = +10V REFP –0.35 V = –10V REFN 0.05 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER –0.40 T = 25°C 0 A –0.45 V = +15V DD V = –15V SS AD8676 REFERENCE BUFFERS –0.50 AD8675 OUTPUT BUFFER –0.05 –0.55 –0.10 –0.60 DNL MIN –0.65 –0.15 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) V /|V | (V) DD SS REFP REFN Figure 26. Gain Error vs. Supply Voltage, ±10 V Span Figure 29. Differential Nonlinearity Error vs. Reference Voltage Rev. C | Page 13 of 28 FULL-SCALE ERROR (LSB) GAIN ERROR (ppm FSR) FULL-SCALE ERROR (LSB) 09092-026 09092-025 09092-024 GAIN ERROR (ppm FSR) DNL ERROR (LSB) INL ERROR (LSB) 09092-029 09092-028 09092-027 AD5781 Data Sheet 0.16 –0.30 T = 25°C A V = +15V 0.14 DD = –15V –0.35 V SS AD8676 REFERENCE BUFFERS 0.12 AD8675 OUTPUT BUFFER –0.40 0.10 T = 25°C A –0.45 0.08 V = +15V DD V = –15V SS AD8676 REFERENCE BUFFERS 0.06 AD8675 OUTPUT BUFFER –0.50 0.04 –0.55 0.02 0 –0.60 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) V /|V | (V) REFP REFN REFP REFN Figure 30. Zero-Scale Error vs. Reference Voltage Figure 33. Gain Error vs. Reference Voltage 0.03 0.3 ±10V SPAN +10V SPAN 0.2 0.02 ±5V SPAN 0.1 0.01 0 0 –0.1 –0.01 –0.2 AD8676 REFERENCE BUFFERS T = 25°C A –0.02 AD8675 OUTPUT BUFFER V = +15V DD –0.3 V = –15V V = +15V SS DD –0.03 V = –15V AD8676 REFERENCE BUFFERS SS –0.4 V = +10V AD8675 OUTPUT BUFFER REFP V = –15V REFN –0.04 –0.5 –0.05 –0.6 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –55 –35 –15 5 25 45 65 85 105 125 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 31. Midscale Error vs. Reference Voltage Figure 34. Full-Scale Error vs. Temperature 0.04 0.40 ±10V SPAN T = 25°C A +10V SPAN 0.03 0.35 V = +15V DD ±5V SPAN V = –15V SS AD8676 REFERENCE BUFFERS 0.02 0.30 AD8675 OUTPUT BUFFER 0.01 0.25 0 0.20 –0.01 0.15 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.10 V = +15V –0.02 DD V = –15V SS V = +10V REFP 0.05 –0.03 V = –15V REFN 0 –0.04 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –55 –35 –15 5 25 45 65 85 105 125 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 32. Full-Scale Error vs. Reference Voltage Figure 35. Midscale Error vs. Temperature Rev. C | Page 14 of 28 FULL-SCALE ERROR (LSB) MID-SCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 09092-030 09092-032 09092-031 GAIN ERROR (ppm FSR) FULL-SCALE ERROR (LSB) MID-SCALE ERROR (LSB) 09092-035 09092-034 09092-033 Data Sheet AD5781 1.2 5 ±10V SPAN T = 25°C A 1.0 +10V SPAN 4 ±5V SPAN I DD 0.8 3 0.6 2 0.4 1 0.2 0 0 –1 –0.2 AD8676 REFERENCE BUFFERS –2 AD8675 OUTPUT BUFFER –0.4 V = +15V DD V = –15V –3 SS –0.6 I SS V = +10V REFP V = –15V –4 –0.8 REFN –1.0 –5 –20 –15 –10 –5 0 5 10 15 20 –55 –35 –15 5 25 45 65 85 105 125 V , V (V) TEMPERATURE (°C) DD SS Figure 36. Zero-Scale Error vs. Temperature Figure 39. Power Supply Currents vs. Power Supply Voltages 4 ±10V SPAN AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER +10V SPAN 3 V = +15V +5V SPAN DD V = –15V SS 2 V = +10V REFP V = –15V REFN 1 V = +15V DD V = –15V SS 0 V = +10V REFP 3 V = –10V REFN AD8676 REFERENCE BUFFERS –1 OUTPUT UNBUFFERED LOAD = 10MΩ||20pF –2 –3 –4 4 –5 CH3 5V CH4 5V 200ns –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 37. Gain Error vs. Temperature Figure 40. Rising Full-Scale Voltage Step 900 IOV = 5V, LOGIC VOLTAGE CC V = +15V T = 25°C DD A INCREASING V = –15V SS 800 IOV = 5V, LOGIC VOLTAGE CC V = +10V REFP DECREASING V = –10V REFN 700 IOV = 3V, LOGIC VOLTAGE CC AD8676 REFERENCE BUFFERS INCREASING OUTPUT UNBUFFERED IOV = 3V, LOGIC VOLTAGE 600 CC LOAD = 10MΩ||20pF DECREASING 500 3 400 300 200 100 4 0 CH3 5V CH4 5V 200ns 01 23 4 5 6 LOGIC INPUT VOLTAGE (V) Figure 38. IOICC vs. Logic Input Voltage Figure 41. Falling Full-Scale Voltage Step Rev. C | Page 15 of 28 ZERO-SCALE ERROR (LSBs) IOI (µA) GAIN ERROR (ppm FSR) CC 09092-038 09092-037 09092-036 I , I (mA) DD SS 09092-041 09092-040 09092-039 AD5781 Data Sheet 10.8 3.0 ±10V V 5V V REF REF OUTPUT GAIN OF 1 OUTPUT GAIN OF 1 2.6 10.6 BIAS COMPENSATION MODE BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER RC LOW-PASS FILTER 2.2 NEGATIVE CODE 10.4 CHANGE POSITIVE CODE 1.8 CHANGE 10.2 1.4 10.0 1.0 9.8 0.6 9.6 0.2 9.4 –0.2 01 2 3 4 5 TIME (µs) CODE Figure 45. 6 MSB Segment Glitch Energy for 5 V V Figure 42. 125 Code Step Settling Time REF 10 40 ±10V V 5V V REF REF 9 OUTPUT GAIN OF 1 OUTPUT GAIN OF 1 NEGATIVE CODE BIAS COMPENSATION MODE BIAS COMPENSATION MODE CHANGE 30 20pF COMPENSATION CAPACITOR 20pF COMPENSATION CAPACITOR 8 RC LOW-PASS FILTER RC LOW-PASS FILTER 7 20 6 5 POSITIVE CODE 10 CHANGE 4 0 3 2 C = 143pF + 0pF X –10 C = 143pF + 220pF X 1 C = 143pF + 470pF X C = 143pF + 1,000pF X 0 –20 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (µs) CODE Figure 46. Midscale Peak-to-Peak Glitch for ±10 V Figure 43. 6 MSB Segment Glitch Energy for ±10 V VREF 800 4.0 T = 25°C A 10V V MID-SCALE CODE LOADED REF V = +15V OUTPUT GAIN OF 1 DD OUTPUT UNBUFFERED 3.5 V = –15V 600 BIAS COMPENSATION MODE SS AD8676 REFERENCE BUFFERS V = +10V 20pF COMPENSATION CAPACITOR REFP POSITIVE CODE V = –10V REFN 3.0 RC LOW-PASS FILTER CHANGE 400 NEGATIVE CODE CHANGE 2.5 200 2.0 0 1.5 –200 1.0 –400 0.5 0 –600 0 1 23 4 567 8 9 10 TIME (Seconds) CODE Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Figure 44. 6 MSB Segment Glitch Energy for 10 V VREF Rev. C | Page 16 of 28 V (mV) OUTPUT GLITCH (nV–sec) OUTPUT GLITCH (nV–sec) OUT 16384 16384 65536 65536 114688 114688 163840 163840 212992 212992 262144 262144 311296 311296 360448 360448 409600 409600 458752 458752 507904 507904 557056 557056 606208 606208 655360 655360 704512 704512 753664 753664 802816 802816 851968 851968 901120 901120 950272 950272 999424 999424 09092-060 09092-059 09092-063 V (mV) OUTPUT VOLTAGE (nV) OUT OUTPUT GLITCH (nV–sec) 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 09092-044 09092-061 09092-062 Data Sheet AD5781 100 V = +15V DD V = –15V SS V = +10V REFP V = –10V REFN CODE = MIDSCALE 10 1 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 48. Noise Spectral Density vs. Frequency 350 T = 25°C A V = +15V DD 300 V = –15V SS V = +10V REFP 250 V = –10V REFN AD8675 OUTPUT BUFFER 200 150 100 50 0 –50 –1 01 2 3456 TIME (µs) Figure 49. Glitch Impulse on Removal of Output Clamp Rev. C | Page 17 of 28 NSD (nV/ Hz) OUTPUT VOLTAGE (mV) 09092-049 09092-064 AD5781 Data Sheet TERMINOLOGY Relative Accuracy Midscale Error Temperature Coefficient Relative accuracy, or integral nonlinearity (INL), is a measure of Midscale error temperature coefficient is a measure of the the maximum deviation, in LSB, from a straight line passing change in mid-scale error with a change in temperature. It is through the endpoints of the DAC transfer function. A typical expressed in ppm FSR/°C. INL error vs. code plot is shown in Figure 6. Output Slew Rate Differential Nonlinearity (DNL) Slew rate is a measure of the limitation in the rate of change of Differential nonlinearity is the difference between the measured the output voltage. The slew rate of the AD5781 output voltage change and the ideal 1 LSB change between any two adjacent is determined by the capacitive load presented to the V pin. OUT codes. A specified differential nonlinearity of ±1 LSB maximum The capacitive load in conjunction with the 3.4 kΩ output ensures monotonicity. This DAC is guaranteed monotonic. A impedance of the AD5781 set the slew rate. Slew rate is typical DNL error vs. code plot is shown in Figure 10. measured from 10% to 90% of the output voltage change and is expressed in V/μs. Linearity Error Long-Term Stability Linearity error long-term stability is a measure of the stability of Output Voltage Settling Time the linearity of the DAC over a long period of time. It is Output voltage settling time is the amount of time it takes for specified in LSB for a time period of 500 hours and 1000 hours the output voltage to settle to a specified level for a specified at an elevated ambient temperature. change in voltage. For fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 kΩ Zero-Scale Error output impedance of the AD5781, in which case, it is the Zero-scale error is a measure of the output error when zero-scale amplifier that determines the settling time. code (0x00000) is loaded to the DAC register. Ideally, the output voltage should be VREFNS. Zero-scale error is expressed in LSBs. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the Zero-Scale Error Temperature Coefficient analog output when the input code in the DAC register changes Zero-scale error temperature coefficient is a measure of the state. It is specified as the area of the glitch in nV-sec and is change in zero-scale error with a change in temperature. It is measured when the digital input code is changed by 1 LSB at expressed in ppm FSR/°C. the major carry transition (see Figure 43). Full-Scale Error Output Enabled Glitch Impulse Full-scale error is a measure of the output error when full-scale Output enabled glitch impulse is the impulse injected into the code (0x3FFFF) is loaded to the DAC register. Ideally, the analog output when the clamp to ground on the DAC output is output voltage should be V − 1 LSB. Full-scale error is REFPS removed. It is specified as the area of the glitch in nV-sec (see expressed in LSBs. Figure 49). Full-Scale Error Temperature Coefficient Digital Feedthrough Full-scale error temperature coefficient is a measure of the Digital feedthrough is a measure of the impulse injected into change in full-scale error with a change in temperature. It is the analog output of the DAC from the digital inputs of the expressed in ppm FSR/°C. DAC but is measured when the DAC output is not updated. It is Gain Error specified in nV-sec and measured with a full-scale code change Gain error is a measure of the span error of the DAC. It is the on the data bus, that is, from all 0s to all 1s, and vice versa. deviation in slope of the DAC transfer characteristic from ideal, Spurious Free Dynamic Range (SFDR) expressed in ppm of the full-scale range. Spurious free dynamic range is the usable dynamic range of a Gain Error Temperature Coefficient DAC before spurious noise interferes or distorts the fundamental Gain error temperature coefficient is a measure of the change in signal. It is measured by the difference in amplitude between the gain error with a change in temperature. It is expressed in ppm fundamental and the largest harmonically or nonharmonically FSR/°C. related spur from dc to full Nyquist bandwidth (half the DAC Midscale Error sampling rate, or f /2). SFDR is measured when the signal is a S Midscale error is a measure of the output error when midscale digitally generated sine wave. code (0x20000) is loaded to the DAC register. Ideally, the output Total Harmonic Distortion (THD) voltage should be (V – V )/2 +V . Midscale error is REFPS REFNS REFNS Total harmonic distortion is the ratio of the rms sum of the expressed in LSBs. harmonics of the DAC output to the fundamental value. Only the second to fifth harmonics are included. Rev. C | Page 18 of 28 Data Sheet AD5781 DC Power Supply Rejection Ratio. AC Power Supply Rejection Ratio (AC PSRR) DC power supply rejection ratio is a measure of the rejection of AC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given amplitude and frequency to the DAC. It is measured for a given dc change in power supply voltage and is expressed in μV/V. change in power supply voltage and is expressed in decibels. Rev. C | Page 19 of 28 AD5781 Data Sheet THEORY OF OPERATION RR R V The AD5781 is a high accuracy, fast settling, single, 18-bit, OUT .......... ..................... 2R serial input, voltage output DAC. It operates from a VDD supply 2R 2R 2R 2R 2R 2R .......... ..................... S0 S1 S11 E62 E61 E0 voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V. V REFPF Data is written to the AD5781 in a 24-bit word format via a 3-wire V REFPS serial interface. The AD5781 incorporates a power-on reset V REFNF V REFNS circuit that ensures the DAC output powers up to 0 V with the 12-BIT R-R LADDER SIX MSBs DECODED INTO V pin clamped to AGND through a ~6 kΩ internal resistor. OUT 63 EQUAL SEGMENTS DAC ARCHITECTURE Figure 50. DAC Ladder Structure Serial Interface The architecture of the AD5781 consists of two matched DAC The AD5781 has a 3-wire serial interface (SYNC, SCLK, and sections. A simplified circuit diagram is shown in Figure 50. SDIN) that is compatible with SPI, QSPI, and MICROWIRE The six MSBs of the 18-bit data-word are decoded to drive 63 interface standards, as well as most DSPs (see Figure 2 for a switches, E0 to E62. Each of these switches connects one of 63 timing diagram). matched resistors to either the VREFP or VREFN voltage. The Input Shift Register remaining 12 bits of the data-word drive the S0 to S11 switches The input shift register is 24 bits wide. Data is loaded into the of a 12-bit voltage mode R-R ladder network. device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of a R/W bit, three address bits, and twenty data bits as shown in Table 7. The timing diagram for this operation is shown in Figure 2. Table 7. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB0 R/W Register address Register data Table 8. Decoding the Input Shift Register R/ W Register Address Description 1 X 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. C | Page 20 of 28 09092-053 Data Sheet AD5781 Standalone Operation AD5781* CONTROLLER The serial interface works with both a continuous and noncon- DATA OUT SDIN tinuous serial clock. A continuous SCLK source can be used SERIAL CLOCK SCLK only if SYNC is held low for the correct number of clock cycles. CONTROL OUT SYNC In gated clock mode, a burst clock containing the exact number SYNC of clock cycles must be used, and must be taken high DATA IN SDO after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must SDIN SYNC be applied to SCLK before is brought high again. If AD5781* th SYNC is brought high before the 24 falling SCLK edge, the SCLK data written is invalid. If more than 24 falling SCLK edges are SYNC applied before SYNC is brought high, the input data is also invalid. The input shift register is updated on the rising edge of SDO SYNC SYNC . For another serial transfer to take place, must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the SDIN addressed register. Once the write cycle is complete, the output AD5781* can be updated by taking LDAC low while SYNC is high. SCLK Daisy-Chain Operation SYNC For systems that contain several devices, the SDO pin can be used to daisy chain several devices together. Daisy-chain mode SDO can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the *ADDITIONAL PINS OMITTED FOR CLARITY. write cycle. SCLK is continuously applied to the input shift Figure 51. Daisy-Chain Block Diagram register when SYNC is low. If more than 24 clock pulses are Readback applied, the data ripples out of the shift register and appears on The contents of all the on-chip registers can be read back via the SDO line. This data is clocked out on the rising edge of the SDO pin. Table 8 outlines how the registers are decoded. SCLK and is valid on the falling edge. By connecting the SDO After a register has been addressed for a read, the next 24 clock of the first device to the SDIN input of the next device in the cycles clock the data out on the SDO pin. The clocks must be chain, a multidevice interface is constructed. Each device in the SYNC SYNC applied while is low. When is returned high, the system requires 24 clock pulses. Therefore, the total number of SDO pin is placed in tristate. For a read of a single register, the clock cycles must equal 24 × N, where N is the total number of NOP function can be used to clock out the data. Alternatively, AD5781 devices in the chain. When the serial transfer to all if more than one register is to be read, the data of the first SYNC devices is complete, is taken high. This latches the input register to be addressed can be clocked out at the same time the data in each device in the daisy chain and prevents any further second register to be read is being addressed. The SDO pin data from being clocked into the input shift register. The serial must be enabled to complete a readback operation. The SDO clock can be a continuous or a gated clock. pin is enabled by default. A continuous SCLK source can be used only if SYNC is held HARDWARE CONTROL PINS low for the correct number of clock cycles. In gated clock mode, LDAC Load DAC Function ( ) a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to After data has been transferred into the input register of the latch the data. DAC, there are two ways to update the DAC register and DAC output. Depending on the status of both SYNC and LDAC, one In any one daisy-chain sequence, writes to the DAC register of two update modes is selected: synchronous DAC updating or should not be mixed with writes to any of the other registers. asynchronous DAC updating. All writes to the daisy-chained parts should be either writes to the DAC registers or writes to the control, clearcode, or Synchronous DAC Update software control register. LDAC In this mode, is held low while data is being clocked into the input shift register. The DAC output is updated on the rising SYNC edge of . Rev. C | Page 21 of 28 09092-058 AD5781 Data Sheet Asynchronous Clear Function (CLR) Asynchronous DAC Update The CLR pin is an active low clear that allows the output to be In this mode, LDAC is held high while data is being clocked cleared to a user defined value. The 18-bit clear code value is into the input shift register. The DAC output is asynchronously programmed to the clearcode register (see Table 13). It is LDAC SYNC updated by taking low after has been taken high. necessary to maintain CLR low for a minimum amount of time LDAC The update now occurs on the falling edge of . CLR to complete the operation (see Figure 2). When the signal Reset Function (RESET) LDAC is returned high, the output remains at the clear value (if The AD5781 can be reset to its power-on state by two means: is high) until a new value is loaded to the DAC register. The RESET pin or by utilizing the software either by asserting the CLR output cannot be updated with a new value while the pin is RESET RESET control function (see Table 14). If the pin is not low. A clear operation can also be performed by setting the CLR used, it should be hardwired to IOV . CC bit in the software control register (see Table 14). Table 9. Hardware Control Pins Truth Table LDAC CLR RESET Function 1 1 X XX 0 The AD5781 is in reset mode. The device cannot be programmed. 1 1 X XX The AD5781 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clear code value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clear code value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clear code value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. ON-CHIP REGISTERS DAC Register Table 10 outlines how data is written to and read from the DAC register. Table 10. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0 R/W Register address DAC register data 1 1 R/W 0 0 1 18-bits of data X XX 1 X is don’t care. The following equation describes the ideal transfer function of the DAC: (V −V )×D REFP REFN V = +V OUT REFN 18 2 −1 where: VREFN is the negative voltage applied at the VREFNS input pin. VREFP is the positive voltage applied at the VREFPS input pin. D is the 18-bit code programmed to the DAC. Rev. C | Page 22 of 28 Data Sheet AD5781 Control Register The control register controls the mode of operation of the AD5781. Table 11. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19...DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W Register address Control register data R/W 0 1 0 Reserved Reserved LIN COMP SDODIS BIN/2sC DACTRI OPGND RBUF Reserved Table 12. Control Register Functions Function Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 54. This allows an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details. 1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 53 so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section for further details. OPGND Output ground clamp control. 0: DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit DACTRI DAC tristate control. 0: DAC is in normal operating mode. 1: (default) DAC is in tristate mode. BIN/2sC DAC register coding select. 0: (default) DAC register uses twos complement coding. 1: DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) SDO pin is enabled. 1: SDO pin is disabled (tristate). LIN COMP Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details. 0 0 0 0 (Default) reference input span up to 10 V. 1 1 0 0 Reference input span of 20 V. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. Table 13. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0 R/W Register address Clearcode register data 1 1 R/W 0 1 1 18-bits of data X X 1 X is don’t care. Rev. C | Page 23 of 28 AD5781 Data Sheet Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 14. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB3 DB2 DB1 DB0 W Register address Software control register data R/ 1 2 0 1 0 0 Reserved RESET CLR LDAC 1 LDAC The CLR function has no effect if the pin is low. 2 The LDAC function has no effect if the CLR pin is low. Table 15. Software Control Register Functions Function Description LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. RESET Setting this bit to 1 returns the AD5781 to its power-on state. Rev. C | Page 24 of 28 Data Sheet AD5781 AD5781 FEATURES Unity Gain Configuration POWER-ON TO 0 V Figure 52 shows an output amplifier configured for unity gain, The AD5781 contains a power-on reset circuit that, as well as in this configuration the output spans from VREFN to VREFP. resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in V REFP tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 kΩ resistor. The DAC remains 1/2 AD8676 in this state until programmed otherwise via the control V V register. This is a useful feature in applications where it is REFPF REFPS R important to know the state of the DAC output while it is in the R1 FB R FB A1 process of powering up. AD8675, 6.8kΩ 6.8kΩ ADA4898-1, INV ADA4004-1 CONFIGURING THE AD5781 18-BIT DAC V V OUT OUT After power-on, the AD5781 must be configured to put it into normal operating mode before programming the output. To do AD5781 this, the control register must be programmed. The DAC is V V REFNF REFNS removed from tristate by clearing the DACTRI bit, and the output clamp is removed by clearing the OPGND bit. At this 1/2 AD8676 point, the output goes to VREFN unless an alternative value is first programmed to the DAC register. V REFN Figure 52. Output Amplifier in Unity Gain Configuration DAC OUTPUT STATE A second unity gain configuration for the output amplifier is The DAC output can be placed in one of three states, controlled one that removes an offset from the input bias currents of the by the DACTRI and OPGND bits of the control register, as amplifier. It does this by inserting a resistance in the feedback shown in Table 16. path of the amplifier that is equal to the output resistance of the Table 16. AD5781 Output State Truth Table DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 DACTRI OPGND Output State and RFB in parallel, a resistance equal to the DAC resistance is 0 0 Normal operating mode. available on-chip. Because the resistors are all on one piece of 0 1 Output is clamped via ~6 kΩ to AGND. silicon, they are temperature coefficient matched. To enable this 1 0 Output is in tristate. mode of operation, the RBUF bit of the control register must be set 1 1 Output is clamped via ~6 kΩ to AGND. to Logic 1. Figure 53 shows how the output amplifier is connected to the AD5781. In this configuration, the output amplifier is in LINEARITY COMPENSATION unity gain and the output spans from VREFN to VREFP. This unity The integral nonlinearity (INL) of the AD5781 can vary gain configuration allows a capacitor to be placed in the according to the applied reference voltage span; the LIN COMP amplifier feedback path to improve dynamic performance. bits of the control register can be programmed to compensate V REFP for this variation in INL. The specifications in this data sheet are obtained with LIN COMP = 0000 for reference spans up to 1/2 AD8676 and including 10 V and with LIN COMP = 1100 for a reference span of 20 V. The default value of the LIN COMP bits is 0000. V V REFPF REFPS OUTPUT AMPLIFIER CONFIGURATION R FB 10pF There are a number of different ways that an output amplifier R1 6.8kΩ R 6.8kΩ FB can be connected to the AD5781, depending on the voltage INV V OUT 18-BIT references applied and the desired output voltage span. DAC V OUT AD8675, ADA4898-1, ADA4004-1 AD5781 V V REFNF REFNS 1/2 AD8676 V REFN Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current Compensation Rev. C | Page 25 of 28 09092-054 09092-055 AD5781 Data Sheet V REFP Gain of Two Configuration Figure 54 shows an output amplifier configured for a gain of 1/2 AD8676 two. The gain is set by the internal matched 6.8 kΩ resistors, which are exactly twice the DAC resistance, having the effect V V REFPF REFPS of removing an offset from the input bias current of the external R R 1 FB R FB amplifier. In this configuration, the output spans from 2 × V − A1 REFN 6.8kΩ 6.8kΩ 10pF V to V This configuration is used to generate a bipolar REFP REFP. INV output span from a single-ended reference input, with V = REFN V OUT 18-BIT DAC V 0 V. For this mode of operation, the RBUF bit of the control OUT AD8675, register must be cleared to Logic 0. ADA4898-1, ADA4004-1 AD5781 V V REFNF REFNS 1/2 AD8676 V = 0V REFN Figure 54. Output Amplifier in Gain of Two Configuration Rev. C | Page 26 of 28 09092-056 Data Sheet AD5781 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 55. Typical Operating Circuit Figure 55 shows a typical operating circuit for the AD5781 EVALUATION BOARD using an AD8676 for reference buffers and an AD8675 as an An evaluation board is available for the AD5781 to aid output buffer. To meet the specified linearity, force sense buffers designers in evaluating the high performance of the part with must be used on the reference inputs. Because the output minimum effort. The AD5781 evaluation kit includes a impedance of the AD5781 is 3.4 kΩ, an output buffer is populated and tested AD5781 PCB. The evaluation board required for driving low resistive, high capacitive loads. interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program the AD5781. The software runs on any PC that has Microsoft® Windows® XP (SP2) or Vista (32 bits) installed. The EVAL- AD5781 data sheet is available, which gives full details on the operation of the evaluation board Rev. C | Page 27 of 28 09092-057 AD5781 Data Sheet OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 8° 0.60 0.30 0° 0.45 COPLANARITY 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range INL Package Description Package Option AD5781BRUZ −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20 AD5781BRUZ-REEL7 −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20 AD5781ARUZ −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20 AD5781ARUZ-REEL7 −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20 EVAL-AD5781SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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