ANALOG DEVICES AD5764

Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5764 FEATURES GENERAL DESCRIPTION Complete quad, 16-bit digital-to-analog The AD5764 is a quad, 16-bit, serial input, bipolar voltage converter (DAC) output DAC that operates from supply voltages of ±11.4 V to Programmable output range ±16.5 V. Nominal full-scale output range is ±10 V. The AD5764 ±10 V, ±10.2564 V, or ±10.5263 V provides integrated output amplifiers, reference buffers, and ±1 LSB maximum INL error, ±1 LSB maximum DNL error proprietary power-up/power-down control circuitry. The part Low noise: 60 nV/√Hz also features a digital I/O port that is programmed via the serial Settling time: 10 μs maximum interface. The part incorporates digital offset and gain adjust Integrated reference buffers registers per channel. Output control during power-up/brownout The AD5764 is a high performance converter that offers guar- Programmable short-circuit protection anteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low Simultaneous updating via LDAC noise, and 10 μs settling time. During power-up (when the CLR Asynchronous to zero code supply voltages are changing), VOUTx is clamped to 0 V via a Digital offset and gain adjust low impedance path. Logic output control pins The AD5764 uses a serial interface that operates at clock rates of DSP-/microcontroller-compatible serial interface up to 30 MHz and is compatible with DSP and microcontroller Temperature range: −40°C to +85°C 1 interface standards. Double buffering allows the simultaneous iCMOS process technology updating of all DACs. The input coding is programmable to APPLICATIONS either twos complement or offset binary formats. The asynchro- nous clear function clears the data register to either bipolar zero or Industrial automation zero scale depending on the coding used. The AD5764 is ideal Open-loop/closed-loop servo control for both closed-loop servo control and open-loop control appli- Process control cations. The AD5764 is available in a 32-lead TQFP, and offers Data acquisition systems guaranteed specifications over the −40°C to +85°C industrial Automatic test equipment temperature range. See Figure 1 for the functional block diagram. Automotive test and measurement High accuracy instrumentation Table 1. Related Devices Part No. Description AD5764R AD5764 with internal voltage reference AD5744R Complete quad, 14-bit, high accuracy, serial input, bipolar voltage output DAC with internal voltage reference 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies, allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD5764 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 21 Applications....................................................................................... 1 Data Register............................................................................... 21 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 21 Revision History ............................................................................... 2 Fine Gain Register...................................................................... 22 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 22 Specifications..................................................................................... 4 Offset and Gain Adjustment Worked Example...................... 23 AC Performance Characteristics ................................................ 5 Design Features............................................................................... 24 Timing Characteristics ................................................................ 6 Analog Output Control ............................................................. 24 Absolute Maximum Ratings............................................................ 9 Digital Offset and Gain Control............................................... 24 ESD Caution.................................................................................. 9 Programmable Short-Circuit Protection ................................ 24 Pin Configuration and Function Descriptions........................... 10 Digital I/O Port........................................................................... 24 Typical Performance Characteristics ........................................... 12 Local Ground Offset Adjust...................................................... 24 Terminology .................................................................................... 17 Applications Information .............................................................. 25 Theory of Operation ...................................................................... 18 Typical Operating Circuit ......................................................... 25 DAC Architecture....................................................................... 18 Layout Guidelines........................................................................... 27 Reference Buffers........................................................................ 18 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 18 Microprocessor Interfacing....................................................... 27 Simultaneous Updating via LDAC........................................... 19 Evaluation Board........................................................................ 27 Outline Dimensions....................................................................... 28 Transfer Function ....................................................................... 20 Ordering Guide .......................................................................... 28 CLR Asynchronous Clear ( )....................................................... 20 REVISION HISTORY 9/11—Rev. E to Rev. F Changes to Table 20 ....................................................................... 26 Changed 30 MHz to 50 MHz Throughout.................................... 1 Deleted AD5764 to MC68HC11 Interface Section.................... 27 Changes to t , t , and t Parameters, Table 4.................................. 6 Deleted Figure 38; Renumbered Sequentially ............................ 27 1 2 3 Deleted AD5764 to 8XC51 Interface Section, Figure 39, 7/11—Rev. D to Rev. E AD5764 to ADSP-2101 Interface Section, Figure 40, and Changed 30 MHz to 50 MHz Throughout.................................... 1 AD5764 to PIC16C6x/PIC16C7x Interface Section .................. 28 Changes to t1, t2, and t3 Parameters, Table 4.................................. 6 04/08—Rev. A to Rev. B 8/09—Rev. C to Rev. D Changes to Table Summary Statement, Specifications Section...4 Changes to Table 2 and Table 3 Endnotes ..................................... 6 Changes to Power Requirements Parameter, Table 2 and Changes to t6 Parameter and Endnotes, Table 4........................... 7 Table Summary Statement................................................................5 1/09—Rev. B to Rev. C Changes to t Parameter, Table 4 ....................................................6 16 Changes to General Description Section ...................................... 1 Changes to Table 6.......................................................................... 10 Changes to Figure 1.......................................................................... 3 Changed VSS/VDD to AVSS/AVDD in Typical Performance Changes to Table 2 Conditions ....................................................... 4 Characteristics Section .................................................................. 13 Changes to Table 3 Conditions ....................................................... 5 Changes to Table 16 ....................................................................... 22 Changes to Table 4 Conditions ....................................................... 6 Changes to Table 18 ....................................................................... 23 Changes to Figure 5.......................................................................... 8 Changes to Typical Operating Circuit Section........................... 28 Changes to Table 5............................................................................ 9 Changes to AD5764 to ADSP-2101 Section ............................... 29 Changes to Table 6.......................................................................... 10 Changes to Ordering Guide .......................................................... 30 Changes to Figure 34...................................................................... 19 1/07—Rev. 0 to Rev. A Changes to Table 7 and Table 10................................................... 20 Changes to Absolute Maximum Ratings..................................... 10 Added Table 8; Renumbered Sequentially .................................. 20 Changes to Figure 25 and Figure 26............................................. 16 Changes to Table 11 and Table 12 ................................................ 21 Changes to Digital Offset and Gain Control Section ................ 24 3/06—Revision 0: Initial Version Rev. F | Page 2 of 28 Data Sheet AD5764 FUNCTIONAL BLOCK DIAGRAM PGND AV AV AV AV REFGND REFAB RSTOUT RSTIN DD SS DD SS VOLTAGE DV CC MONITOR REFERENCE AND AD5764 BUFFERS CONTROL DGND ISCC 16 16 G1 INPUT DATA DAC A SDIN VOUTA REG A REG A INPUT SHIFT G2 SCLK REGISTER GAIN REG A AND SYNC AGNDA CONTROL OFFSET REG A LOGIC SDO 16 G1 INPUT DATA DAC B VOUTB REG B REG B G2 GAIN REG B AGNDB OFFSET REG B D0 16 G1 INPUT DATA D1 DAC C VOUTC REG C REG C G2 GAIN REG C AGNDC OFFSET REG C BIN/2sCOMP 16 G1 INPUT DATA DAC D VOUTD REG D REG D G2 GAIN REG D AGNDD CLR OFFSET REG D REFERENCE BUFFERS LDAC REFCD Figure 1. Rev. F | Page 3 of 28 05303-001 AD5764 Data Sheet SPECIFICATIONS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter A Grade B Grade C Grade Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 16 16 16 Bits Relative Accuracy (INL) ±4 ±2 ±1 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic Bipolar Zero Error ±2 ±2 ±2 mV max At 25°C; error at other temperatures obtained using bipolar zero TC Bipolar Zero Temperature ±2 ±2 ±2 ppm FSR/°C max 1 Coefficient (TC) Zero-Scale Error ±2 ±2 ±2 mV max At 25°C; error at other temperatures obtained using zero-scale TC 1 Zero-Scale TC ±2 ±2 ±2 ppm FSR/°C max Gain Error ±0.02 ±0.02 ±0.02 % FSR max At 25°C; error at other temperatures obtained using gain TC 1 Gain TC ±2 ±2 ±2 ppm FSR/°C max 1 DC Crosstalk 0.5 0.5 0.5 LSB max 1 REFERENCE INPUT Reference Input Voltage 5 5 5 V nom ±1% for specified performance DC Input Impedance 1 1 1 MΩ min Typically 100 MΩ Input Current ±10 ±10 ±10 μA max Typically ±30 nA Reference Range 1 to 7 1 to 7 1 to 7 V min to V max 1 OUTPUT CHARACTERISTICS 2 Output Voltage Range ±10.5263 ±10.5263 ±10.5263 V min to V max AV /AV = ±11.4 V, V = 5 V DD SS REFIN ±14 ±14 ±14 V min to V max AV /AV = ±16.5 V, V = 7 V DD SS REFIN Output Voltage Drift vs. Time ±13 ±13 ±13 ppm FSR/ 500 hours typ ±15 ±15 ±15 ppm FSR/ 1000 hours typ Short-Circuit Current 10 10 10 mA typ R = 6 kΩ, see Figure 31 ISCC Load Current ±1 ±1 ±1 mA max For specified performance Capacitive Load Stability RLOAD = ∞ 200 200 200 pF max R = 10 kΩ 1000 1000 1000 pF max LOAD DC Output Impedance 0.3 0.3 0.3 Ω max DIGITAL INPUTS DVCC = 2.7 V to 5.25 V, JEDEC compliant Input High Voltage, V 2 2 2 V min IH Input Low Voltage, V 0.8 0.8 0.8 V max IL Input Current ±1 ±1 ±1 μA max Per pin Pin Capacitance 10 10 10 pF max Per pin Rev. F | Page 4 of 28 Data Sheet AD5764 Parameter A Grade B Grade C Grade Unit Test Conditions/Comments 1 DIGITAL OUTPUTS (D0, D1, SDO) Output Low Voltage 0.4 0.4 0.4 V max DVCC = 5 V ± 5%, sinking 200 μA Output High Voltage DVCC − 1 DVCC − 1 DVCC − 1 V min DVCC = 5 V ± 5%, sourcing 200 μA Output Low Voltage 0.4 0.4 0.4 V max DV = 2.7 V to 3.6 V, sinking 200 μA CC Output High Voltage DV − 0.5 DV − 0.5 DV − 0.5 V min DV = 2.7 V to 3.6 V, sourcing 200 μA CC CC CC CC High Impedance Leakage Current ±1 ±1 ±1 μA max SDO only High Impedance Output 5 5 5 pF typ SDO only Capacitance POWER REQUIREMENTS AVDD/AVSS ±11.4 to ±11.4 to ±11.4 to V min to V max ±16.5 ±16.5 ±16.5 DV 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 V min to V max CC 1 Power Supply Sensitivity ∆V /∆ΑV −85 −85 −85 dB typ OUT DD AIDD 3.5 3.5 3.5 mA/channel max Outputs unloaded AISS 2.75 2.75 2.75 mA/channel max Outputs unloaded DICC 1.2 1.2 1.2 mA max VIH = DVCC, VIL = DGND, 750 μA typical Power Dissipation 275 275 275 mW typ ±12 V operation output unloaded 1 Guaranteed by design and characterization; not production tested. 2 Output amplifier headroom requirement is 1.4 V minimum. AC PERFORMANCE CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter A Grade B Grade C Grade Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE Output Voltage Settling Time 8 8 8 μs typ Full-scale step to ±1 LSB 10 10 10 μs max 2 2 2 μs typ 512 LSB step settling Slew Rate 5 5 5 V/μs typ Digital-to-Analog Glitch Energy 8 8 8 nV-sec typ Glitch Impulse Peak Amplitude 25 25 25 mV max Channel-to-Channel Isolation 80 80 80 dB typ DAC-to-DAC Crosstalk 8 8 8 nV-sec typ Digital Crosstalk 2 2 2 nV-sec typ Digital Feedthrough 2 2 2 nV-sec typ Effect of input bus activity on DAC outputs Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 0.1 LSB p-p typ Output Noise (0.1 Hz to 100 kHz) 45 45 45 μV rms max 1/f Corner Frequency 1 1 1 kHz typ Output Noise Spectral Density 60 60 60 nV/√Hz typ Measured at 10 kHz Complete System Output Noise Spectral 80 80 80 nV/√Hz typ Measured at 10 kHz 2 Density 1 Guaranteed by design and characterization; not production tested. 2 Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier. Rev. F | Page 5 of 28 AD5764 Data Sheet TIMING CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 4. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 4 th t 13 ns min 24 SCLK falling edge to SYNC rising edge 5 t 90 ns min 6 Minimum SYNC high time t7 2 ns min Data setup time t8 5 ns min Data hold time t 1.7 μs min SYNC rising edge to LDAC falling edge (all DACs updated) 9 480 ns min SYNC rising edge to LDAC falling edge (single DAC updated) t 10 ns min LDAC pulse width low 10 t11 500 ns max LDAC falling edge to DAC output response time t12 10 μs max DAC output settling time t13 10 ns min CLR pulse width low t 2 μs max CLR pulse activation time 14 5, 6 t 25 ns max SCLK rising edge to SDO valid 15 t 13 ns min rising edge to SCLK falling edge 16 SYNC t17 2 μs max SYNC rising edge to DAC output response time (LDAC = 0) t18 170 ns min LDAC falling edge to SYNC rising edge 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.2 V. R F CC 3 See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. Rev. F | Page 6 of 28 Data Sheet AD5764 Timing Diagrams t 1 SCLK 12 24 t t t 3 2 6 t t 4 5 SYNC t 8 t 7 SDIN DB23 DB0 t t 10 10 t 9 LDAC t t 18 12 t 11 VOUTx LDAC = 0 t 12 t 17 VOUTx t 13 CLR t 14 VOUTx Figure 2. Serial Interface Timing Diagram t 1 SCLK 24 48 t t t 3 2 t 6 5 t 16 t 4 SYNC t 8 t 7 DB23 DB0 DB23 DB0 SDIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N–1 t 15 DB23 DB0 SDO t UNDEFINED INPUT WORD FOR DAC N 9 t 10 LDAC Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 7 of 28 05303-002 05303-003 AD5764 Data Sheet SCLK 24 48 SYNC DB23 DB0 DB23 DB0 SDIN NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram 200µA I OL V (MIN) OR TO SDO OH PIN V (MAX) OL C L 50pF 200µA I OH Figure 5. Load Circuit for SDO Timing Diagram Rev. F | Page 8 of 28 05303-005 05303-004 Data Sheet AD5764 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those listed in the operational sections Parameter Rating of this specification is not implied. Exposure to absolute AV to AGNDx, DGND −0.3 V to +17 V DD maximum rating conditions for extended periods may affect AVSS to AGNDx, DGND +0.3 V to −17 V device reliability. DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) ESD CAUTION Digital Outputs to DGND −0.3 V to DV + 0.3 V CC REFAB, REFCD to AGNDx, PGND −0.3 V to AV + 0.3 V DD VOUTA, VOUTB, VOUTC, VOUTD to AVSS to AVDD AGNDx AGNDx to DGND −0.3 V to +0.3 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 32-Lead TQFP θ Thermal Impedance 65°C/W JA θ Thermal Impedance 12°C/W JC Lead Temperature JEDEC industry standard Soldering J-STD-020 Rev. F | Page 9 of 28 AD5764 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 SYNC 1 24 AGNDA PIN 1 2 23 VOUTA SCLK 3 22 VOUTB SDIN AD5764 4 21 AGNDB SDO TOP VIEW 5 (Not to Scale) 20 AGNDC CLR 6 19 VOUTC LDAC 7 18 VOUTD D0 8 17 AGNDD D1 9 10 11 12 13 14 15 16 NC = NO CONNECT Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 4 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. 5 CLR Negative Edge Triggered Input. Asserting this pin sets the data register to 0x0000. There is an internal pull-up device on this logic input. Therefore, this pin can be left floating and defaults to a Logic 1 condition. 6 LDAC Load DAC. Logic input. This is used to update the data register and consequently the analog outputs. When tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input shift register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 7, 8 D0, D1 Digital I/O Port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV . CC When programmed as outputs, D0 and D1 are referenced by DVCC and DGND. 9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. 10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. 11 DGND Digital Ground. 12 DVCC Digital Supply. Voltage ranges from 2.7 V to 5.25 V. 13, 31 AVDD Positive Analog Supply. Voltage ranges from 11.4 V to 16.5 V. 14 PGND Ground Reference Point for Analog Circuitry. 15, 30 AV Negative Analog Supply. Voltage ranges from −11.4 V to −16.5 V. SS 16 ISCC Resistor Connection for Pin Programmable Short-Circuit Current. This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for further details. 17 AGNDD Ground Reference Pin for DAC D Output Amplifier. 18 VOUTD Analog Output Voltage of DAC D. This pin is a buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 19 VOUTC Analog Output Voltage of DAC C. This pin is a buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 20 AGNDC Ground Reference Pin for DAC C Output Amplifier. Rev. F | Page 10 of 28 BIN/2sCOMP RSTOUT AV RSTIN DD AV DGND SS DV NC CC AV REFGND DD NC PGND AV REFCD SS REFAB ISCC 05303-006 Data Sheet AD5764 Pin No. Mnemonic Description 21 AGNDB Ground Reference Pin for DAC B Output Amplifier. 22 VOUTB Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 23 VOUTA Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 24 AGNDA Ground Reference Pin for DAC A Output Amplifier. 25 REFAB External Reference Voltage Input for Channel A and Channel B. Reference input range is 1 V to 7 V; programs the full-scale output voltage. VREFIN = 5 V for specified performance. 26 REFCD External Reference Voltage Input for Channel C and Channel D. Reference input range is 1 V to 7 V; programs the full-scale output voltage. V = 5 V for specified performance. REFIN 27, 29 NC No Connect. 28 REFGND Reference Ground Return for the Reference Generator and Buffers. 32 BIN/2sCOMP Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to DVCC, input coding is offset binary. When hardwired to DGND, input coding is twos complement (see Table 7 and Table 8). Rev. F | Page 11 of 28 AD5764 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 T = 25°C T = 25°C A A 0.8 AV /AV = ±15V 0.8 AV /AV = ±12V DD SS DD SS V = 5V V = 5V REFIN REFIN 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000 DAC CODE DAC CODE Figure 7. Integral Nonlinearity Error vs. Code, Figure 10. Differential Nonlinearity Error vs. Code, AV /AV = ±15 V AV /AV = ±12 V DD SS DD SS 1.0 0.5 T = 25°C T = 25°C A A AV /AV = ±12V AV /AV = ±15V 0.8 DD SS DD SS 0.4 V = 5V V = 5V REFIN REFIN 0.6 0.3 0.4 0.2 0.2 0 0.1 –0.2 –0.4 0 –0.6 –0.1 –0.8 –1.0 –0.2 0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100 DAC CODE TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. Code, Figure 11. Integral Nonlinearity Error vs. Temperature, AV /AV = ±12 V AV /AV = ±15 V DD SS DD SS 1.0 0.5 T = 25°C A T = 25°C A 0.8 AV /AV = ±15V DD SS AV /AV = ±12V DD SS V = 5V REFIN 0.4 V = 5V REFIN 0.6 0.4 0.3 0.2 0 0.2 –0.2 0.1 –0.4 –0.6 0 –0.8 –1.0 –0.1 0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100 DAC CODE TEMPERATURE (°C) Figure 9. Differential Nonlinearity Error vs. Code, Figure 12. Integral Nonlinearity Error vs. Temperature, AV /AV = ±15 V AV /AV = ±12 V DD SS DD SS Rev. F | Page 12 of 28 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 05303-011 05303-008 05303-007 INL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 05303-016 05303-015 05303-012 Data Sheet AD5764 0.15 0.15 T = 25°C A V = 5V REFIN 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 T = 25°C A –0.20 –0.20 AV /AV = ±15V DD SS V = 5V REFIN –0.25 –0.25 –40 –20 0 20 40 60 80 100 11.4 12.4 13.4 14.4 15.4 16.4 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 13. Differential Nonlinearity Error vs. Temperature, Figure 16. Differential Nonlinearity Error vs. Supply Voltage AVDD/AVSS = ±15 V 0.8 0.15 T = 25°C A AV /AV = ±16.5V DD SS 0.6 0.10 0.4 0.05 0.2 0 0 –0.05 –0.2 –0.10 –0.4 –0.15 –0.6 T = 25°C A –0.20 –0.8 AV /AV = ±12V DD SS V = 5V REFIN –1.0 –0.25 –40 –20 0 20 40 60 80 100 17 2 3 4 56 TEMPERATURE (°C) REFERENCE VOLTAGE (V) Figure 17. Integral Nonlinearity Error vs. Reference Voltage, Figure 14. Differential Nonlinearity Error vs. Temperature, AV /AV = ±16.5 V AVDD/AVSS = ±12 V DD SS 0.5 0.4 T = 25°C T = 25°C A A AV /AV = ±16.5V V = 5V DD SS REFIN 0.3 0.4 0.2 0.3 0.1 0.2 0 0.1 –0.1 0 –0.2 –0.1 –0.3 –0.4 –0.2 11.4 12.4 13.4 14.4 15.4 16.4 17 2 3 4 56 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 15. Integral Nonlinearity Error vs. Supply Voltage Figure 18. Differential Nonlinearity Error vs. Reference Voltage, AVDD/AVSS = ±16.5 V Rev. F | Page 13 of 28 INL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 05303-023 05303-020 05303-019 DNL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 05303-031 05303-027 05303-025 AD5764 Data Sheet 0.6 0.8 T = 25°C A V = 5V REFIN AV /AV = ±15V 0.4 AV /AV = ±16.5V DD SS DD SS 0.6 0.2 0 0.4 –0.2 AV /AV = ±12V DD SS –0.4 0.2 –0.6 –0.8 0 –1.0 –1.2 –0.2 –1.4 –1.6 –0.4 17 2 3 4 56 –40 –20 0 20 40 60 80 100 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 19. Total Unadjusted Error vs. Reference Voltage, Figure 22. Bipolar Zero Error vs. Temperature AVDD/AVSS = ±16.5 V 1.4 14 V = 5V REFIN T = 25°C A V = 5V REFIN 1.2 13 1.0 |I | DD AV /AV = ±12V DD SS 12 0.8 0.6 11 0.4 AV /AV = ±15V 10 DD SS 0.2 |I | SS 9 0 –0.2 8 –40 –20 0 20 40 60 80 100 11.4 12.4 13.4 14.4 15.4 16.4 TEMPERATURE (°C) AV /AV (V) DD SS Figure 23. Gain Error vs. Temperature Figure 20. I /I vs. AV /AV DD SS DD SS 0.0014 0.25 T = 25°C AV /AV = ±15V A V = 5V REFIN DD SS 0.20 0.0013 5V 0.15 0.0012 AV /AV = ±12V DD SS 0.10 0.0011 0.05 0.0010 0 –0.05 0.0009 –0.10 0.0008 –0.15 3V 0.0007 –0.20 0.0006 –0.25 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 –40 –20 0 20 40 60 80 100 V TEMPERATURE (°C) LOGIC Figure 21. Zero-Scale Error vs. Temperature Figure 24. DICC vs. Logic Input Voltage Rev. F | Page 14 of 28 ZERO-SCALE ERROR (mV) I /I (mA) TUE (mV) DD SS 05303-038 05303-037 05303-035 DI (mA) CC GAIN ERROR (mV) BIPOLAR ZERO ERROR (mV) 05303-040 05303-039 05303-041 Data Sheet AD5764 7000 AV /AV = ±15V T = 25°C DD SS A V = 5V T = 25°C REFIN A 6000 RI = 6kΩ SCC V = 5V REFIN AV /AV = ±15V DD SS 5000 AV /AV = ±12V DD SS 4000 3000 2000 1000 0 1 1µs/DIV –1000 CH1 3.00V M1.00µs CH1 –120mV –10 –5 0 5 10 SOURCE/SINK CURRENT (mA) Figure 27. Full-Scale Settling Time Figure 25. Source and Sink Capability of Output Amplifier with Positive Full Scale Loaded –4 10000 T = 25°C A –6 V = 5V 9000 REFIN RI = 6kΩ SCC –8 8000 15V SUPPLIES –10 7000 –12 6000 12V SUPPLIES –14 5000 –16 4000 –18 3000 –20 2000 AV /AV = ±12V DD SS V = 5V REFIN –22 1000 T = 25°C A 0x8000 TO 0x7FFF –24 0 500ns/DIV –26 –1000 –2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –12 –7 –2 3 8 TIME (µs) SOURCE/SINK CURRENT (mA) Figure 26. Source and Sink Capability of Output Amplifier with Figure 28. Major Code Transition Glitch Energy, AVDD/AVSS = ±12 V Negative Full Scale Loaded Rev. F | Page 15 of 28 OUTPUT VOLTAGE DELTA (µV) OUTPUT VOLTAGE DELTA (µV) 05303-043 05303-042 V (mV) OUT 05303-044 05303-047 AD5764 Data Sheet 10 AV /AV = ±15V DD SS AV /AV = ±15V DD SS MIDSCALE LOADED 9 T = 25°C A V = 0V REFIN V = 5V REFIN 8 7 6 4 5 4 3 2 1 50µV/DIV 0 CH4 50.0µV M1.00s CH4 26µV 01 20 40 60 80 10020 RI (kΩ) SCC Figure 31. Short-Circuit Current vs. RI Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) SCC T AV /AV = ±12V DD SS V = 5V REFIN 1 T = 25°C A 2 RAMP TIME = 100µs LOAD = 200pF||10kΩ 3 B CH1 10.0V CH2 10.0V M100µs A CH1 7.80mV W B CH3 10.0mV T 29.60% W Figure 30. V vs. AV /AV on Power-Up OUT DD SS Rev. F | Page 16 of 28 05303-048 05303-055 SHORT-CIRCUIT CURRENT (mA) 05303-050 Data Sheet AD5764 TERMINOLOGY Total Unadjusted Error Relative Accuracy or Integral Nonlinearity (INL) Total unadjusted error (TUE) is a measure of the output error For the DAC, relative accuracy or integral nonlinearity (INL) is considering all the various errors. A plot of total unadjusted a measure of the maximum deviation, in LSBs, from a straight error vs. reference voltage can be seen in Figure 19. line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7. Zero-Scale Error Temperature Coefficient (TC) Zero-scale error TC is a measure of the change in zero-scale Differential Nonlinearity (DNL) error with a change in temperature. Zero-scale error TC is Differential nonlinearity is the difference between the measured expressed in ppm FSR/°C. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum Gain Error Temperature Coefficient (TC) ensures monotonicity. This DAC is guaranteed monotonic. A Gain error TC is a measure of the change in gain error with typical DNL vs. code plot can be seen in Figure 9. changes in temperature. Gain error TC is expressed in ppm FSR/°C. Monotonicity A DAC is monotonic if the output either increases or remains Digital-to-Analog Glitch Energy constant for increasing digital input code. The AD5764 is Digital-to-analog glitch impulse is the impulse injected into the monotonic over its full operating temperature range. analog output when the input code in the data register changes state. It is normally specified as the area of the glitch in nV-sec, Bipolar Zero Error and is measured when the digital input code is changed by 1 LSB at Bipolar zero error is the deviation of the analog output from the the major carry transition (0x7FFF to 0x8000); see Figure 28. ideal half-scale output of 0 V when the data register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement Digital Feedthrough coding). A plot of bipolar zero error vs. temperature can be seen Digital feedthrough is a measure of the impulse injected into in Figure 22. the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is speci- Bipolar Zero Temperature Coefficient (TC) fied in nV-sec and measured with a full-scale code change on Bipolar zero TC is the measure of the change in the bipolar zero the data bus, that is, from all 0s to all 1s, and vice versa. error with a change in temperature. It is expressed in ppm FSR/°C. Power Supply Sensitivity Full-Scale Error Power supply sensitivity indicates how the output of the DAC is Full-scale error is a measure of the output error when full-scale affected by changes in the power supply voltage. code is loaded to the data register. Ideally, the output voltage should be 2 × V − 1 LSB. Full-scale error is expressed in DC Crosstalk REF percentage of full-scale range. DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured Negative Full-Scale Error/Zero-Scale Error with a full-scale output change on one DAC while monitoring Negative full-scale error is the error in the DAC output voltage another DAC, and is expressed in LSBs. when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the data register. Ideally, the output voltage DAC-to-DAC Crosstalk should be −2 × VREF. A plot of zero-scale error vs. temperature DAC-to-DAC crosstalk is the glitch impulse transferred to the can be seen in Figure 21. output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and Output Voltage Settling Time analog crosstalk. It is measured by loading one of the DACs with Output voltage settling time is the amount of time it takes for the LDAC a full-scale code change (all 0s to all 1s and vice versa) with output to settle to a specified level for a full-scale input change. low and monitoring the output of another DAC. The energy of Slew Rate the glitch is expressed in nV-sec. The slew rate of a device is a limitation in the rate of change of Channel-to-Channel Isolation the output voltage. The output slewing speed of a voltage-output Channel-to-channel isolation is the ratio of the amplitude of the DAC is usually limited by the slew rate of the amplifier used at signal at the output of one DAC to a sine wave on the reference its output. Slew rate is measured from 10% to 90% of the output input of another DAC. It is measured in dB. signal and is given in V/μs. Digital Crosstalk Gain Error Digital crosstalk is a measure of the impulse injected into the Gain error is a measure of the span error of the DAC. It is the analog output of one DAC from the digital inputs of another DAC, deviation in slope of the DAC transfer characteristic from the but is measured when the DAC output is not updated. It is specified ideal, expressed as a percentage of the full-scale range. A plot of in nV-sec and measured with a full-scale code change on the data gain error vs. temperature can be seen in Figure 23. bus, that is, from all 0s to all 1s, and vice versa. Rev. F | Page 17 of 28 AD5764 Data Sheet THEORY OF OPERATION The AD5764 is a quad, 16-bit, serial input, bipolar voltage output SERIAL INTERFACE DAC and operates from supply voltages of ±11.4 V to ±16.5 V and The AD5764 is controlled over a versatile 3-wire serial interface has a buffered output voltage of up to ±10.5263 V. Data is written to that operates at clock rates of up to 30 MHz and is compatible the AD5764 in a 24-bit word format, via a 3-wire serial interface. with SPI, QSPI™, MICROWIRE™, and DSP standards. The device also offers an SDO pin that is available for daisy- Input Shift Register chaining or readback. The input shift register is 24 bits wide. Data is loaded into the The AD5764 incorporates a power-on reset circuit, which ensures device MSB first as a 24-bit word under the control of a serial that the data register powers up loaded with 0x0000. The AD5764 clock input, SCLK. The input shift register consists of a read/ features a digital I/O port that can be programmed via the serial write bit, three register select bits, three DAC address bits, and interface, on-chip reference buffers and per channel digital gain, 16 data bits, as shown in Table 9. The timing diagram for this and offset registers. operation is shown in Figure 2. DAC ARCHITECTURE Upon power-up, the data register is loaded with zero code The DAC architecture of the AD5764 consists of a 16-bit, (0x0000), and the outputs are clamped to 0 V via a low imped- current mode, segmented R-2R DAC. The simplified circuit ance path. The outputs can be updated with the zero code value diagram for the DAC section is shown in Figure 32. LDAC CLR at this time by asserting either or . The corresponding The four MSBs of the 16-bit data word are decoded to drive 2sCOMP output voltage depends on the state of the BIN/ pin. If 15 switches, E1 to E15. Each of these switches connects one of 2sCOMP the BIN/ pin is tied to DGND, the data coding is twos the 15 matched resistors to either AGNDx or IOUT. The remain- complement, and the outputs update to 0 V. If the BIN/2sCOMP ing 12 bits of the data-word drive Switch S0 to Switch S11 of pin is tied to DVCC, the data coding is offset binary, and the the 12-bit R-2R ladder network. outputs update to negative full scale. To power up the outputs RR R with zero code loaded to the outputs, hold the CLR pin low V REF during power-up. 2R 2R 2R 2R 2R 2R 2R Standalone Operation R/8 The serial interface works with both a continuous and noncon- E15 E14 E1 S0 S11 S10 tinuous serial clock. A continuous SCLK source can only be IOUT used if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number VOUTx AGNDx SYNC of clock cycles must be used and must be taken high after 4 MSBs DECODED INTO 12-BIT, R-2R LADDER 15 EQUAL SEGMENTS SYNC the final clock to latch the data. The first falling edge of Figure 32. DAC Ladder Structure starts the write cycle. Exactly 24 falling clock edges must be SYNC SYNC applied to SCLK before is brought high again. If is REFERENCE BUFFERS th brought high before the 24 falling SCLK edge, the data written The AD5764 operates with an external reference. The reference is invalid. If more than 24 falling SCLK edges are applied before inputs (REFAB and REFCD) have an input range up to 7 V. This SYNC is brought high, the input data is also invalid. The input input voltage is used to provide a buffered positive and negative SYNC shift register addressed is updated on the rising edge of . reference for the DAC cores. The positive reference is given by SYNC For another serial transfer to take place, must be brought +V = 2 × V REF REF low again. After the end of the serial data transfer, data is The negative reference to the DAC cores is given by automatically transferred from the input shift register to the addressed register. −V = −2 × V REF REF When the data has been transferred into the chosen register of These positive and negative reference voltages (along with the the addressed DAC, the data register and outputs can be gain register values) define the output ranges of the DACs. updated by taking LDAC low. Rev. F | Page 18 of 28 05303-060 Data Sheet AD5764 Daisy-Chain Operation disable bit; this bit is cleared by default. Readback mode is invoked W by setting the R/ bit = 1 in the serial input shift register write. 1 1 68HC11 AD5764 W With R/ = 1, Bit A2 to Bit A0, in association with Bit REG2, MOSI SDIN Bit REG1, and Bit REG0, select the register to be read. The SCK SCLK remaining data bits in the write sequence are don’t cares. During PC7 SYNC the next SPI write, the data appearing on the SDO output PC6 LDAC contain the data from the previously addressed register. For a MISO SDO read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The SDIN readback diagram in Figure 4 shows the readback sequence. For 1 AD5764 example, to read back the fine gain register of Channel A on the AD5764, implement the following: SCLK 1. Write 0xA0XXXX to the AD5764 input shift register. This SYNC configures the AD5764 for read mode with the fine gain LDAC register of Channel A selected. Note that all the data bits, SDO DB15 to DB0, are don’t cares. 2. Follow this with a second write, an NOP condition, SDIN 0x00XXXX. During this write, the data from the fine gain 1 AD5764 register is clocked out on the SDO line, that is, data clocked SCLK out contain the data from the fine gain register in Bit DB5 SYNC to Bit DB0. LDAC SIMULTANEOUS UPDATING VIA LDAC SDO Depending on the status of both SYNC and LDAC, and after 1 ADDITIONAL PINS OMITTED FOR CLARITY data has been transferred into the input register of the DACs, Figure 33. Daisy-Chaining the AD5764 there are two ways in which the data register and DAC outputs can be updated. For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain Individual DAC Updating mode can be useful in system diagnostics and in reducing the LDAC In this mode, is held low while data is being clocked into SYNC number of serial interface lines. The first falling edge of the input shift register. The addressed DAC output is updated starts the write cycle. The SCLK is continuously applied to the on the rising edge of SYNC. SYNC input shift register when is low. If more than 24 clock Simultaneous Updating of All DACs pulses are applied, the data ripples out of the input shift register LDAC In this mode, is held high while data is being clocked and appears on the SDO line. This data is clocked out on the into the input shift register. All DAC outputs are updated by rising edge of SCLK and is valid on the falling edge. By connect- LDAC SYNC ing the SDO of the first device to the SDIN input of the next device taking low any time after has been taken high. in the chain, a multidevice interface is constructed. Each device in The update now occurs on the falling edge of LDAC. the system requires 24 clock pulses. Therefore, the total number of OUTPUT I/V AMPLIFIER clock cycles must equal 24N, where N is the total number of 16-BIT V REFIN V AD5764 devices in the chain. When the serial transfer to all OUTx DAC devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further DATA LDAC REGISTER data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. SYNC A continuous SCLK source can only be used if is held low INPUT REGISTER for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, SCLK and SYNC must be taken high after the final clock to latch the data. INTERFACE SDO SYNC LOGIC SDIN Readback Operation Figure 34. Simplified Serial Interface of Input Loading Circuitry Before a readback operation is initiated, the SDO pin must be for One DAC Channel enabled by writing to the function register and clearing the SDO Rev. F | Page 19 of 28 05303-061 05303-062 AD5764 Data Sheet The output voltage expression for the AD5764 is given by TRANSFER FUNCTION ⎡ D ⎤ Table 7 and Table 8 show the ideal input code to output voltage V =−2×V + 4×V OUT REFIN REFIN ⎢ ⎥ relationship for the AD5764 for both offset binary and twos 65,536 ⎣ ⎦ complement data coding, respectively. where: Table 7. Ideal Output Voltage to Input Code Relationship— D is the decimal equivalent of the code loaded to the DAC. Offset Binary Data Coding VREFIN is the reference voltage applied at the REFAB/REFCD pins. Digital Input Analog Output MSB LSB VOUTx ASYNCHRONOUS CLEAR (CLR) 1111 1111 1111 1111 +2 VREF × (32,767/32,768) CLR is a negative edge triggered clear that allows the outputs to 1000 0000 0000 0001 +2 V × (1/32,768) REF be cleared to either 0 V (twos complement coding) or negative 1000 0000 0000 0000 0 V full scale (offset binary coding). It is necessary to maintain CLR 0111 1111 1111 1111 −2 V × (1/32,768) REF low for a minimum amount of time (see Figure 2) for the operation 0000 0000 0000 0000 −2 V × (32,767/32,768) REF to complete. When the CLR signal is returned high, the output remains at the cleared value until a new value is programmed. If Table 8. Ideal Output Voltage to Input Code Relationship— CLR at power-on, is at 0 V, then all DAC outputs are updated Twos Complement Data Coding with the clear value. A clear can also be initiated through software Digital Input Analog Output by writing Command 0x04XXXX to the AD5764. MSB LSB VOUTx 0111 1111 1111 1111 +2 V × (32,767/32,768) REF 0000 0000 0000 0001 +2 V × (1/32,768) REF 0000 0000 0000 0000 0 V 1111 1111 1111 1111 −2 VREF × (1/32,768) 1000 0000 0000 0000 −2 VREF × (32,767/32,768) Table 9. Input Shift Register Bit Map MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15:DB0 R/W 0 REG2 REG1 REG0 A2 A1 A0 Data Table 10. Input Shift Register Bit Functions Bit Description R/W Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a read or write operation is to the data register, offset register, coarse gain register, fine gain register, or function register. REG2 REG1 REG0 Function 0 0 0 Function register 0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register A2, A1, A0 These bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All DACs Data Data bits. Rev. F | Page 20 of 28 Data Sheet AD5764 FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 11 and Table 12. Table 11. Function Register Options REG2 REG1 REG0 A2 A1 A0 DB15:DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 NOP, data = don’t care 0 0 0 0 0 1 Don’t care Local ground D1 direction D1 value D0 direction D0 value SDO disable offset adjust 0 0 0 1 0 0 Clear, data = don’t care 0 0 0 1 0 1 Load, data = don’t care Table 12. Explanation of Function Register Options Option Description NOP No operation instruction used in readback operations. Local Ground Offset Adjust Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset adjust function (default). Refer to the Design Features section for further details. D0/D1 Direction Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Design Features section for further details. D0/D1 Value I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Load Addressing this function updates the data register and consequently the analog outputs. DATA REGISTER The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The data bits are in Position DB15 to Position DB0, as shown in Table 13. Table 13. Programming the Data Register Bit Map REG2 REG1 REG0 A2 A1 A0 DB15:DB0 0 1 0 DAC address 16-bit DAC data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC, as shown in Table 14 and Table 15. Table 14. Programming the Coarse Gain Register Bit Map REG2 REG1 REG0 A2 A1 A0 DB15: DB2 DB1 DB0 0 1 1 DAC address Don’t care CG1 CG0 Table 15. Output Range Selection Output Range CG1 CG0 ±10 V (Default) 0 0 ±10.2564 V 0 1 ±10.5263 V 1 0 Rev. F | Page 21 of 28 AD5764 Data Sheet FINE GAIN REGISTER OFFSET REGISTER The fine gain register is addressed by setting the three REG bits The offset register is addressed by setting the three REG bits to to 100. The DAC address bits select with which DAC channel 101. The DAC address bits select with which DAC channel the the data transfer is to take place (see Table 10). The fine gain data transfer is to take place (see Table 10). The AD5764 offset register is a 6-bit register and allows the user to adjust the gain register is an 8-bit register and allows the user to adjust the offset of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB of each channel by −16 LSBs to +15.875 LSBs in increments of increments, as shown in Table 16 and Table 17. The adjustment ⅛ LSB, as shown in Table 18 and Table 19. The offset register is made to both the positive full-scale points and the negative coding is twos complement. full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos complement. Table 16. Programming the Fine Gain Register Bit Map REG2 REG1 REG0 A2 A1 A0 DB15:DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0 Table 17. Fine Gain Register Options Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0 +31 LSBs 0 1 1 1 1 1 +30 LSBs 0 1 1 1 1 0 … … … … … … … +2 LSBs 0 0 0 0 1 0 +1 LSB 0 0 0 0 0 1 No Adjustment (Default) 0 0 0 0 0 0 −1 LSB 1 1 1 1 1 1 −2 LSBs 1 1 1 1 1 0 … … … … … … … −31 LSBs 1 0 0 0 0 1 −32 LSBs 1 0 0 0 0 0 Table 18. Programming the Offset Register Bit Map REG2 REG1 REG0 A2 A1 A0 DB15:DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 DAC address Don’t care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 Table 19. AD5764 Offset Register Options Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 +15.875 LSBs 0 1 1 1 1 1 1 1 +15.75 LSBs 0 1 1 1 1 1 1 0 … … … … … … … … … +0.25 LSBs 0 0 0 0 0 0 1 0 +0.125 LSBs 0 0 0 0 0 0 0 1 No Adjustment (Default) 0 0 0 0 0 0 0 0 −0.125 LSBs 1 1 1 1 1 1 1 1 −0.25 LSBs 1 1 1 1 1 1 1 0 … … … … … … … … … −15.875 LSBs 1 0 0 0 0 0 0 1 −16 LSBs 1 0 0 0 0 0 0 0 Rev. F | Page 22 of 28 Data Sheet AD5764 Convert this to a negative twos complement number by inverting OFFSET AND GAIN ADJUSTMENT WORKED all bits and adding 1 to obtain 11110000, the value that should EXAMPLE be programmed to the offset register. Using the information provided in the Fine Gain Register and Offset Register sections, the following worked example demon- Note that this twos complement conversion is not necessary in the case of a positive offset adjustment. The value to be programmed to strates how the AD5764 functions can be used to eliminate both the offset register is simply the binary representation of the offset and gain errors. Because the AD5764 is factory calibrated, adjustment value. offset and gain errors should be negligible. However, errors can be introduced by the system that the AD5764 is operating within; Removing Gain Error for example, a voltage reference value that is not equal to 5 V The AD5764 can eliminate a gain error at negative full-scale introduces a gain error. An output range of ±10 V and twos output in the range of −9.77 mV to +9.46 mV with a step size of complement data coding is assumed. ½ of a 16-bit LSB. Removing Offset Error Calculate the step size of the gain adjustment. The AD5764 can eliminate an offset error in the range of −4.88 mV 20 to +4.84 mV with a step size of ⅛ of a 16-bit LSB. Gain Adjust StepSize= = 152.59 μV 16 2 × 2 Calculate the step size of the offset adjustment. Measure the gain error by programming 0x8000 to the data 20 Offset Adjust Step Size= = 38.14 μV register and measuring the resulting output voltage. The gain 16 2 × 8 error is the difference between this value and −10 V. For this example, the gain error is −1.2 mV. Measure the offset error by programming 0x0000 to the data register and measuring the resulting output voltage. For this Calculate how many gain adjustment steps this value represents. example, the measured value is 614 μV. Measured Gain Value Number of Steps= = Calculate the number of offset adjustment steps that this value Gain Step Size represents. 1.2 mV = 8 Steps Measured Offset Value 152.59 μV Numberof Steps= = Offset Step Size The gain error measured is negative (in terms of magnitude); 614 μV therefore, a positive adjustment of eight steps is required. The = 16 Steps 38.14 μV gain register is 6 bits wide and the coding is twos complement, the required gain register value can be determined as follows: The offset error measured is positive, therefore, a negative Convert the adjustment value to binary: 001000. adjustment of 16 steps is required. The offset register is eight The value to be programmed to the gain register is simply this bits wide and the coding is twos complement. The required binary number. offset register value can be calculated as follows: Convert the adjustment value to binary: 00010000. Rev. F | Page 23 of 28 AD5764 Data Sheet DESIGN FEATURES PROGRAMMABLE SHORT-CIRCUIT PROTECTION ANALOG OUTPUT CONTROL The short-circuit current of the output amplifiers can be pro- In many industrial process control applications, it is vital that grammed by inserting an external resistor between the ISCC the output voltage be controlled during power-up and during pin and PGND. The programmable range for the current is 500 μA brownout conditions. When the supply voltages are changing, to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. the VOUTx pins are clamped to 0 V via a low impedance path. The resistor value is calculated as follows: To prevent the output amp being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 35). These condi- 60 R= tions are maintained until the power supplies stabilize and a I SC valid word is written to the data register. At this time, G2 opens and If the ISCC pin is left unconnected, the short-circuit current G1 closes. Both transmission gates are also externally controllable limit defaults to 5 mA. Note that limiting the short-circuit RSTIN RSTIN via the reset logic ( ) control input. For instance, if current to a small value can affect the slew rate of the output RSTIN is driven from a battery supervisor chip, the input is when driving into a capacitive load; therefore, the value of the driven low to open G1 and close G2 upon power-down or during programmed short circuit should take into account the size of a brownout. Conversely, the on-chip voltage detector output the capacitive load being driven. (RSTOUT) is also available to the user to control other parts of DIGITAL I/O PORT the system. The basic transmission gate functionality is shown in Figure 35. The AD5764 contains a 2-bit digital I/O port (D1 and D0). RSTOUT RSTIN These bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial VOLTAGE interface. The I/O port signals are referenced to DVCC and DGND. MONITOR AND When configured as outputs, they can be used as control signals CONTROL to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic G1 signals from limit switches can, for example, be applied to D0 VOUTA and D1 and can be read back via the digital interface. G2 LOCAL GROUND OFFSET ADJUST AGNDA The AD5764 incorporates a local ground offset adjust feature Figure 35. Analog Output Control Circuitry that, when enabled in the function register, adjusts the DAC DIGITAL OFFSET AND GAIN CONTROL outputs for voltage differences between the individual DAC ground The AD5764 incorporates a digital offset adjust function with a pins, AGNDx, and the REFGND pin, ensuring that the DAC ±16 LSB adjust range and 0.125 LSB resolution. The coarse gain output voltages are always with respect to the local DAC ground register allows the user to adjust the AD5764 full-scale output pin. For instance, if Pin AGNDA is at +5 mV with respect to the range. The full-scale output can be programmed to achieve full- REFGND pin and VOUTA is measured with respect to AGNDA, scale ranges of ±10 V, ±10.2564 V, and ±10.5263 V. A fine gain a −5 mV error results, enabling the local ground offset adjust trim is also provided. feature to adjust VOUTA by +5 mV, eliminating the error. Rev. F | Page 24 of 28 05303-063 Data Sheet AD5764 APPLICATIONS INFORMATION reference and associated buffers. This leads to an overall savings TYPICAL OPERATING CIRCUIT in both cost and board space. Figure 36 shows the typical operating circuit for the AD5764. The only external components needed for this precision 16-bit In Figure 36, AVDD is connected to +15 V and AVSS is connected DAC are a reference voltage source, decoupling capacitors on to −15 V. However, AVDD can operate with supplies from +11.4 V to +16.5 V and AV can operate with supplies from −11.4 V to the supply pins and reference inputs, and an optional short- SS −16.5 V. circuit current setting resistor. Because the device incorporates reference buffers, it eliminates the need for an external bipolar +15V ADR02 2 6 VIN VOUT GND 4 +15V –15V 10µF 10µF 100nF 100nF 100nF BIN/2sCOMP 32 31 30 29 28 27 26 25 +5V SYNC 1 SYNC AGNDA 24 SCLK 2 SCLK VOUTA 23 VOUTA 3 VOUTB 22 SDIN SDIN VOUTB 4 21 SDO SDO AGNDB AD5764 5 20 CLR AGNDC 6 19 LDAC LDAC VOUTC VOUTC 7 D0 VOUTD 18 D0 VOUTD 8 D1 AGNDD 17 D1 9 10 11 12 13 14 15 16 RSTOUT RSTIN 10µF 100nF NC = NO CONNECT 10µF +5V +15V –15V Figure 36. Typical Operating Circuit Rev. F | Page 25 of 28 RSTOUT BIN/2sCOMP AV RSTIN DD 100nF DGND AV SS DV NC CC 100nF AV REFGND DD PGND NC 10µF AV REFCD SS ISCC REFAB 05303-064 AD5764 Data Sheet Precision Voltage Reference Selection voltage to a voltage other than the nominal. The trim adjust- ment can also be used at temperature to trim out any error. To achieve the optimum performance from the AD5764 over its full operating temperature range, a precision voltage reference Long-term drift is a measure of how much the reference output must be used. Consideration should be given to the selection of voltage drifts over time. A reference with a tight long-term drift a precision voltage reference. The AD5764 has two reference specification ensures that the overall solution remains relatively inputs, REFAB and REFCD. The voltages applied to the refer- stable over its entire lifetime. ence inputs are used to provide a buffered positive and negative The temperature coefficient of a reference output voltage affects reference for the DAC cores. Therefore, any error in the voltage INL, DNL, and TUE. Choose a reference with a tight temperature reference is reflected in the outputs of the device. coefficient specification to reduce the dependence of the DAC There are four possible sources of error to consider when output voltage on ambient conditions. choosing a voltage reference for high accuracy applications: In high accuracy applications, which have a relatively low noise initial accuracy, temperature coefficient of the output voltage, budget, reference output voltage noise needs to be considered. long-term drift, and output voltage noise. Choosing a reference with as low an output noise voltage as Initial accuracy error on the output voltage of an external refer- practical for the system resolution required is important. Precision ence can lead to a full-scale error in the DAC. Therefore, to voltage references such as the ADR435 (XFET® design) produce minimize these errors, a reference with low initial accuracy low output noise in the 0.1 Hz to 10 Hz region. However, as the error specification is preferred. Choosing a reference with an circuit bandwidth increases, filtering the output of the reference output trim adjustment, such as the ADR425, allows a system may be required to minimize the output noise. designer to trim system errors out by setting the reference Table 20. Some Precision References Recommended for Use with the AD5764 Part No. Initial Accuracy (mV Max) Long-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ) ADR435 ±2 40 3 8 ADR425 ±2 50 3 3.4 ADR02 ±5 50 3 10 ADR395 ±5 50 9 8 Rev. F | Page 26 of 28 Data Sheet AD5764 LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration interfaces because the number of interface lines is kept to a of the power supply and ground return layout helps to ensure the minimum. Figure 37 shows a 4-channel isolated interface to the rated performance. The PCB on which the AD5764 is mounted AD5764 using an ADuM1400. For more information, go to must be designed so that the analog and digital sections are sepa- www.analog.com. rated and confined to certain areas of the board. If the AD5764 is MICROCONTROLLER ADuM1400* in a system where multiple devices require an AGND-to-DGND V V OA SERIAL CLOCK IA ENCODE DECODE TO SCLK OUT connection, the connection is to be made at one point only. The V V IB OB SERIAL DATA star ground point is established as close as possible to the device. ENCODE DECODE TO SDIN OUT The AD5764 must have ample supply bypassing of 10 μF in parallel V V OC IC ENCODE DECODE SYNC OUT TO SYNC with 0.1 μF on each supply, located as close to the package as V V OD ID possible, ideally right up against the device. The 10 μF capacitors CONTROL OUT ENCODE DECODE TO LDAC are the tantalum bead type. The 0.1 μF capacitor must have low *ADDITIONAL PINS OMITTED FOR CLARITY. effective series resistance (ESR) and low effective series inductance Figure 37. Isolated Interface (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient MICROPROCESSOR INTERFACING currents due to internal logic switching. Microprocessor interfacing to the AD5764 is via a serial bus that uses a standard protocol that is compatible with micro- The power supply lines of the AD5764 must be as large a trace controllers and DSP processors. The communications channel as possible to provide low impedance paths and reduce the effects is a 3-wire (minimum) interface consisting of a clock signal, a of glitches on the power supply line. Fast switching signals, such as data signal, and a synchronization signal. The AD5764 requires clocks, must be shielded with digital ground to avoid radiating noise to other parts of the board, and must never be run near a 24-bit data-word with data valid on the falling edge of SCLK. the reference inputs. A ground line routed between the SDIN For all the interfaces, the DAC output update can be performed and SCLK lines helps reduce crosstalk between them (not required automatically when all the data is clocked in, or it can be done on a multilayer board, which has a separate ground plane; however, LDAC under the control of . The contents of the data register it is helpful to separate the lines). It is essential to minimize noise can be read using the readback function. on the reference inputs because it couples through to the DAC EVALUATION BOARD output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each other. The AD5764 comes with a full evaluation board to aid designers This reduces the effects of feedthrough on the board. A microstrip in evaluating the high performance of the part with minimum technique is recommended, but not always possible with a double- effort. All that is required with the evaluation board is a power sided board. In this technique, the component side of the board supply and a PC. The AD5764 evaluation kit includes a populated, is dedicated to the ground plane, and signal traces are placed on tested AD5764 PCB. The evaluation board interfaces to the USB the solder side. port of the PC. Software is available with the evaluation board, which allows the user to easily program the AD5764. The software GALVANICALLY ISOLATED INTERFACE runs on any PC that has Microsoft® Windows® 2000/NT/XP In many process control applications, it is necessary to provide installed. an isolation barrier between the controller and the unit being The EVAL-AD5764EB data sheet is available, which gives full controlled to protect and isolate the controlling circuitry from details on the operation of the evaluation board. any hazardous common-mode voltages that may occur. Isocoup- lers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5764 makes it ideal for isolated Rev. F | Page 27 of 28 05303-065 AD5764 Data Sheet OUTLINE DIMENSIONS 1.20 0.75 MAX 9.00 BSC SQ 0.60 0.45 32 25 1 24 PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN) 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 8 17 3.5° 0.15 0° 9 16 SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A 0.80 0.45 BSC 0.37 LEAD PITCH VIEW A 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ABA Figure 38. 32-Lead Thin Plastic Quad Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model INL Temperature Range Package Description Package Option AD5764ASUZ ±4 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 AD5764ASUZ-REEL7 ±4 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 AD5764BSUZ ±2 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 AD5764BSUZ-REEL7 ±2 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 AD5764CSUZ ±1 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 AD5764CSUZ-REEL7 ±1 LSB max −40°C to +85°C 32-Lead TQFP SU-32-2 EVAL-AD5764EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05303-0-9/11(F) Rev. F | Page 28 of 28 020607-A