ANALOG DEVICES AD5680

® 5 V 18-Bit nanoDAC in a SOT-23 AD5680 FEATURES FUNCTIONAL BLOCK DIAGRAM V V REF GND DD Single 18-bit nanoDAC 18-bit monotonic V POWER-ON FB 12-bit accuracy guaranteed RESET Tiny 8-lead SOT-23 package OUTPUT V OUT BUFFER Power-on reset to zero scale/midscale REF(+) DAC 4.5 V to 5.5 V power supply 18-BIT DAC REGISTER Serial interface Rail-to-rail operation INPUT SYNC interrupt facility CONTROL LOGIC Temperature range: −40°C to +105°C APPLICATIONS AD5680 Closed-loop process control SYNC SCLK DIN Low bandwidth data acquisition systems Figure 1. Portable battery-powered instruments Gain and offset adjustment Precision setpoint control GENERAL DESCRIPTION The AD5680, a member of the nanoDAC family, is a single, The AD5680 uses a versatile 3-wire serial interface that operates 18-bit buffered voltage-out digital-to-analog converter that at clock rates up to 30 MHz, and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. operates from a single 4.5 V to 5.5 V supply and is 18-bit monotonic. PRODUCT HIGHLIGHTS The AD5680 requires an external reference voltage to set the 1. 18 bits of resolution. output range of the DAC. The part incorporates a power-on 2. 12-bit accuracy guaranteed for 18-bit DAC. reset circuit that ensures the DAC output powers up to 0 V (AD5680-1) or to midscale (AD5680-2) and remains there until 3. Available in an 8-lead SOT-23. a valid write takes place. 4. Low power; typically consumes 1.6 mW at 5 V. The low power consumption of this part in normal operation 5. Power-on reset to zero scale or to midscale. makes it ideally suited to portable battery-operated equipment. RELATED DEVICES The power consumption is 1.6 mW at 5 V. AD5662—16-bit DAC in SOT-23. The AD5680 on-chip precision output amplifier allows rail-to- rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05854-001 AD5680 TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier........................................................................ 11 Applications....................................................................................... 1 Interpolator Architecture .......................................................... 11 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 12 General Description ......................................................................... 1 Input Shift Register .................................................................... 12 Product Highlights ........................................................................... 1 SYNC Interrupt .......................................................................... 12 Related Devices ................................................................................. 1 Power-On Reset.......................................................................... 12 Revision History ............................................................................... 2 Microprocessor Interfacing....................................................... 13 Specifications..................................................................................... 3 Applications..................................................................................... 14 Timing Characteristics ................................................................ 4 Closed-Loop Applications ........................................................ 14 Absolute Maximum Ratings............................................................ 5 Filter ............................................................................................. 14 ESD Caution.................................................................................. 5 Choosing a Reference for the AD5680.................................... 15 Pin Configuration and Function Descriptions............................. 6 Using a Reference as a Power Supply for the AD5680 .......... 16 Typical Performance Characteristics ............................................. 7 Using the AD5680 with a Galvanically Isolated Interface .... 16 Terminology .................................................................................... 10 Power Supply Bypassing and Grounding................................ 16 Theory of Operation ...................................................................... 11 Outline Dimensions ....................................................................... 17 DAC Section................................................................................ 11 Ordering Guide .......................................................................... 17 Resistor String............................................................................. 11 REVISION HISTORY 3/07—Rev. 0 to Rev. A Changes to Input Shift Register Section ...................................... 12 Changes to Figure 25...................................................................... 12 6/06—Revision 0: Initial Version Rev. A | Page 2 of 20 AD5680 SPECIFICATIONS VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Grade Parameter Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE Resolution 18 Bits Relative Accuracy ±32 ±64 LSB 3 Differential Nonlinearity ±1 LSB Measured in 50 Hz system bandwidth ±2 LSB Measured in 300 Hz system bandwidth Zero-Code Error 2 10 mV All 0s loaded to DAC register Full-Scale Error −0.2 −1 % FSR All 1s loaded to DAC register Offset Error ±10 mV Gain Error ±1.5 % FSR Zero-Code Error Drift ±2 μV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10% 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V V DD Output Voltage Settling Time 80 85 μs ¼ to ¾ scale change settling to ±8 LSB, RL = 2 kΩ; 0 pF < CL < 200 pF Slew Rate 1.5 V/μs ¼ to ¾ scale Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L 4 Output Noise Spectral Density 80 nV/√Hz DAC code = midscale, 10 kHz 4 Output Noise (0.1 Hz to 10 Hz) 25 μV p-p DAC code = midscale 4 Total Harmonic Distortion (THD) −80 dB VREF = 2 V ± 300 mV p-p, f = 200 Hz Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry Digital Feedthrough 0.2 nV-s DC Output Impedance 0.5 Ω 4 Short-Circuit Current 30 mA VDD = 5 V REFERENCE INPUT Reference Current 40 75 μA V = V = 5 V REF DD 5 Reference Input Range 0.75 VDD V Reference Input Impedance 125 kΩ LOGIC INPUTS Input Current ±2 μA All digital inputs VINL, Input Low Voltage 0.8 V VDD = 5 V VINH, Input High Voltage 2 V VDD = 5 V Pin Capacitance 3 pF POWER REQUIREMENTS VDD 4.5 5.5 V All digital inputs at 0 V or VDD I (Normal Mode) DAC active and excluding load current DD V = 4.5 V to 5.5 V 325 450 μA V = V and V = GND DD IH DD IL POWER EFFICIENCY I /I 85 % I = 2 mA, V = 5 V OUT DD LOAD DD 1 Temperature range for B version is −40°C to +105°C, typical at +25°C. 2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096. 3 Guaranteed by design and characterization; not production tested. 4 Output unloaded. 5 Reference input range at ambient where maximum DNL specification is achievable. Rev. A | Page 3 of 20 AD5680 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter V = 4.5 V to 5.5 V Unit Conditions/Comments DD 1 t1 33 ns min SCLK cycle time t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t 13 ns min 4 SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t6 4.5 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t 33 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t10 0 ns min SCLK falling edge to SYNC fall ignore 1 Maximum SCLK frequency is 30 MHz at V = 4.5 V to 5.5 V. DD t 10 t 1 t 9 SCLK t t 2 8 t t 3 7 t 4 SYNC t 6 t 5 DB23 DIN DB0 Figure 2. Serial Write Operation Rev. A | Page 4 of 20 05854-002 AD5680 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND −0.3 V to +7 V DD other conditions above those indicated in the operational V to GND −0.3 V to V + 0.3 V OUT DD section of this specification is not implied. Exposure to absolute VFB to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect VREF to GND −0.3 V to VDD + 0.3 V device reliability. Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance SOT-23 Package (4-Layer Board) 119°C/W Reflow Soldering Peak Temperature Pb-free 260°C Rev. A | Page 5 of 20 AD5680 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 8 GND DD AD5680 V 2 7 DIN REF TOP VIEW V 3 6 SCLK FB (Not to Scale) V 4 5 SYNC OUT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND. 2 VREF Reference Voltage Input. 3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. 4 V Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. OUT 5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. th The DAC is updated following the 24 clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. SYNC 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 7 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 8 GND Ground. Ground reference point for all circuitry on the part. Rev. A | Page 6 of 20 05854-003 AD5680 TYPICAL PERFORMANCE CHARACTERISTICS 40 0 V = V = 5V DD REF V = 5V DD T = 25°C 32 A –0.02 24 –0.04 GAIN ERROR 16 –0.06 8 –0.08 0 –0.10 –8 –0.12 –16 –0.14 FULL-SCALE ERROR –24 –0.16 –32 –0.18 –40 –0.20 0 40k 80k 120k 160k 200k 240k –40 –20 0 20 40 60 80 100 CODE TEMPERATURE (°C) Figure 7. Gain Error and Full-Scale Error vs. Temperature Figure 4. Typical INL Plot 1.5 1.0 V = V = 5V DD REF T = 25°C 0.8 A 1.0 ZERO-SCALE ERROR 0.6 0.5 0.4 0 0.2 –0.5 0 –0.2 –1.0 –0.4 –1.5 OFFSET ERROR –0.6 –2.0 –0.8 –2.5 –1.0 –40 –2008 20 40 600 100 0 25k 50k 75k 100k 125k 150k 175k 200k 225k 250k TEMPERATURE (°C) CODE Figure 5. Typical DNL Plot in 50 Hz System Bandwidth Figure 8. Zero-Scale Error and Offset Error vs. Temperature ±4 0.20 V = 4.5V TO 5.5V DD V = V = 5V, 3V DAC LOADED WITH DD REF T = –40°C TO +105°C ZERO SCALE – T = 25°C 0.15 A SINKING CURRENT 0.10 ±2 0.05 0 –0.05 ±1 –0.10 –0.15 DAC LOADED WITH FULL SCALE – –0.20 SOURCING CURRENT –0.25 0 0 300 >300 –5 –4 –3 –2 –1 0 1 235 4 50 I (mA) SYSTEM BANDWIDTH (Hz) Figure 6. DNL Performance vs. System Bandwidth Figure 9. Headroom at Rails vs. Source and Sink Current Rev. A | Page 7 of 20 D SB) NL (L DNL ERROR (LSB) INL ERROR (LSB) 05854-029 05854-028 05854-042 ERROR VOLTAGE (V) ERROR (mV) ERROR (% FSR) 05854-014 05854-043 05854-044 AD5680 450 V = V = 5V DD REF T = 25°C A SCLK 400 1 350 D IN 300 250 2 200 Δ: 1.52V Δ: 64.8µs 150 @: 1.20V V OUT 100 50 3 0 CH1 2.00V CH2 2.00V M 20.0µs CH4 1.30V 0 4000 8000 12000 16000 20000 24000 CH3 1.00V CODE Figure 10. Supply Current vs. Code Figure 13. Full-Scale Settling Time, 5 V 350 V = V = 5V DD REF 300 V DD 1 250 200 V REF V OUT 2 C3 MAX 284mV 150 V OUT C3 MIN 100 –52mV V OUT 50 3 0 CH1 3.00V CH2 3.00V M 100µs CH1 2.40V –40 –20 0 20 40 60 80 100 CH3 100mV TEMPERATURE (°C) Figure 11. Supply Current vs. Temperature Figure 14. Power-On Reset to 0 V 700 T = 25°C A 600 V V = 5V DD DD 1 500 2 400 V REF V OUT C3 MAX 2.5V 300 V OUT C3 MIN 200 –40mV V OUT 100 3 0 CH1 3.00V CH2 3.00V M 100µs CH1 2.40V 05 1 234 CH3 500mV V (V) LOGIC Figure 12. Supply Current vs. Logic Input Voltage Figure 15. Power-On Reset to Midscale Rev. A | Page 8 of 20 I (µA) I (µA) I (µA) DD DD DD 05854-004 05854-006 05854-007 05854-017 05854-016 05854-015 AD5680 2.502500 16 V = V = 5V DD REF V = V 2.502250 REF DD T = 25°C A T = 25°C A 2.502000 13ns/SAMPLE NUMBER 14 1 LSB CHANGE AROUND 2.501750 MIDSCALE (0x20000 TO 0x1FFFF) 2.501500 V = 3V GLITCH IMPULSE = 2.723nV-s DD 12 2.501250 2.501000 2.500750 10 2.500500 2.500250 V = 5V DD 2.500000 8 2.499750 2.499500 6 2.499250 2.499000 2.498750 4 0 50 100 150 200 250 300 350 400 450 500 550 01 2 3 4 5 6 781 9 0 SAMPLE NUMBER CAPACITANCE (nF) Figure 16. Digital-to-Analog Glitch Impulse (Negative) Figure 19. Settling Time vs. Capacitive Load 2.5010 V = V = 5V V = V = 5V DD REF DD REF T = 25°C T = 25°C 2.5008 A A DAC LOADED WITH MIDSCALE DAC LOADED WITH MIDSCALE 2.5006 DIGITAL FEEDTHROUGH = 0.201nV 2.5004 2.5002 2.5000 V REF 1 2.4998 2.4996 2.4994 2.4992 2.4990 2.4988 2.4986 5s/DIV 50 100 150 200 250 300 350 400 450 500 0 SAMPLES × 6.5ns Figure 17. Digital Feedthrough Figure 20. 0.1 Hz to 10 Hz Output Noise Plot –20 1000 V = 5V V = V = 5V DD REF DD T = 25°C T = 25°C A A 900 –30 MIDSCALE LOADED FULL SCALE LOADED V = 2V ±300mV p-p REF 800 –40 700 –50 600 –60 500 400 –70 300 –80 200 –90 100 –100 0 100 1k 10k 100k 1M 01 1 234567890 FREQUENCY (Hz) FREQUENCY (kHz) Figure 18. Total Harmonic Distortion Figure 21. Noise Spectral Density Rev. A | Page 9 of 20 AMPLITUDE AMPLITUDE (dB) 05854-018 05854-020 05854-005 NOISE (nV/ Hz) TIME (µs) 5µV/DIV 05854-019 05854-013 05854-027 AD5680 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) DC Power Supply Rejection Ratio (PSRR) For the DAC, relative accuracy or integral nonlinearity is a This indicates how the output of the DAC is affected by changes measurement of the maximum deviation, in LSBs, from a in the supply voltage. PSRR is the ratio of the change in VOUT to straight line passing through the endpoints of the DAC transfer a change in VDD for full-scale output of the DAC. It is measured function. Figure 4 shows a typical INL vs. code plot. in dB. V is held at 2 V, and V is varied by ±10%. REF DD Differential Nonlinearity (DNL) Output Voltage Settling Time Differential nonlinearity is the difference between the measured This is the amount of time it takes for the output of a DAC to change and the ideal 1 LSB change between any two adjacent settle to a specified level for a ¼ to ¾ full-scale input change th codes. A specified differential nonlinearity of ±1 LSB maximum and is measured from the 24 falling edge of SCLK. ensures monotonicity. Figure 5 shows a typical DNL vs. code Digital-to-Analog Glitch Impulse plot. Digital-to-analog glitch impulse is injected into the analog Zero-Code Error output when the input code in the DAC register changes state. Zero-code error is a measurement of the output error when It is normally specified as the area of the glitch in nV-s, and is zero code (0x00000) is loaded to the DAC register. Ideally, the measured when the digital input code is changed by 1 LSB at output should be 0 V. The zero-code error is always positive in the major carry transition (0x1FFFF to 0x20000). See Figure 16. the AD5680 because the output of the DAC cannot go below Digital Feedthrough 0 V. It is due to a combination of the offset errors in the DAC Digital feedthrough is a measure of the impulse injected into and the output amplifier. Zero-code error is expressed in mV. A the analog output of the DAC from the digital inputs of the plot of zero-code error vs. temperature can be seen in Figure 8. DAC, but is measured when the DAC output is not updated. It Full-Scale Error is specified in nV-s and measured with a full-scale code change Full-scale error is a measurement of the output error when full- on the data bus, that is, from all 0s to all 1s and vice versa. scale code (0x3FFFF) is loaded to the DAC register. Ideally, the Total Harmonic Distortion (THD) output should be V − 1 LSB. Full-scale error is expressed in DD This is the difference between an ideal sine wave and its percent of full-scale range. attenuated version using the DAC. The sine wave is used as the Gain Error reference for the DAC. The THD is a measurement of the This is a measure of the span error of the DAC. It is the deviation harmonics present on the DAC output. It is measured in dB. in slope of the DAC transfer characteristic from ideal, expressed Noise Spectral Density as a percent of the full-scale range. This is a measurement of the internally generated random Zero-Code Error Drift noise. Random noise is characterized as a spectral density This is a measurement of the change in zero-code error with a (voltage per √Hz). It is measured by loading the DAC to change in temperature. It is expressed in μV/°C. midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 21 shows a plot of noise spectral density. Gain Temperature Coefficient This is a measurement of the change in gain error with a change in temperature. It is expressed in (ppm of full-scale range)/°C. Offset Error Offset error is a measure of the difference between V (actual) OUT and V (ideal), expressed in mV in the linear region of the OUT transfer function. Offset error is measured on the AD5680 with Code 2048 loaded in the DAC register. It can be negative or positive. Rev. A | Page 10 of 20 AD5680 THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5680 DAC is fabricated on a CMOS process. The The output buffer amplifier can generate rail-to-rail voltages on architecture consists of a string DAC followed by an output its output, which gives an output range of 0 V to V . This output DD buffer amplifier. Figure 22 shows a block diagram of the DAC buffer amplifier has a gain of 2 derived from a 50 kΩ resistor architecture. divider network in the feedback path. The output amplifier’s V inverting input is available to the user, allowing for remote DD R V FB sensing. This VFB pin must be connected to VOUT for normal R REF (+) operation. It can drive a load of 2 kΩ in parallel with 1000 pF to RESISTOR GND. The source and sink capabilities of the output amplifier can DAC REGISTER V OUT STRING be seen in Figure 9. The slew rate is 1.5 V/μs with a ¼ to ¾ full- REF (–) OUTPUT scale settling time of 10 μs. AMPLIFIER GND INTERPOLATOR ARCHITECTURE Figure 22. DAC Architecture The AD5680 contains a 16-bit DAC with an internal clock generator and interpolator. The voltage levels generated by the Because the input coding to the DAC is straight binary, the ideal 16-bit, 1 LSB step can be subdivided using the interpolator to output voltage is given by increase the resolution to 18 bits. ⎛ D ⎞ ⎜ ⎟ V =V × OUT REF ⎜ ⎟ The 18-bit input code can be divided into two segments: 262,144 ⎝ ⎠ 16-bit DAC code (DB19 to DB4) and 2-bit interpolator code where D is the decimal equivalent of the binary code that is (DB3 and DB2). The input to the DAC is switched between a loaded to the DAC register. It can range from 0 to 262,143. 16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB (for example, Code 1024). The 2-bit interpolator code deter- RESISTOR STRING mines the duty cycle of the switching and hence the 18-bit The resistor string section is shown in Figure 23. It is simply a code level. See Table 5 for an example. string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is Table 5. tapped off to be fed into the output amplifier. The voltage is 16-Bit 2-Bit tapped off by closing one of the switches connecting the string 18-Bit Code DAC Code Interpolator Code to the amplifier. Because it is a string of resistors, it is guaranteed Duty monotonic. DB19 to DB2 DB19 to DB4 DB3 DB2 Cycle 4092 1023 0 0 0 4093 1023 0 1 25% R 4094 1023 1 0 50% 4095 1023 1 1 75% R 4096 1024 0 0 0 The DAC output voltage is given by the average value of TO OUTPUT R AMPLIFIER the waveform switching between 16-bit code (C) and 16-bit code + 1 (C + 1). The output voltage is a function of the duty cycle of the switching. FILTER PLANT 18-BIT INPUT CODE C MUX DAC 18 16 V OUT C + 1 16 R +1 C + 1 75% DUTY CYCLE C C + 1 50% DUTY CYCLE C INTERPOLATOR R 2 C + 1 25% DUTY CYCLE C CLK Figure 23. Resistor String Figure 24. Interpolation Architecture Rev. A | Page 11 of 20 05854-031 05854-030 05854-032 AD5680 SERIAL INTERFACE INPUT SHIFT REGISTER The AD5680 has a 3-wire serial interface (SYNC, SCLK, and The input shift register is 24 bits wide (see Figure 25). The first two bits are don’t care bits. Bit DB21 and Bit DB20 are reserved DIN) that is compatible with SPI, QSPI, and MICROWIRE bits and should be set to 0. The next 18 bits are the data bits interface standards as well as with most DSPs. See Figure 2 for followed by two don’t care bits. These are transferred to the a timing diagram of a typical write sequence. th DAC register on the 24 falling edge of SCLK. The write sequence begins by bringing the SYNC line low. Data SYNC INTERRUPT from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high In a normal write sequence, the SYNC line is kept low for at as 30 MHz, making the AD5680 compatible with high speed least 24 falling edges of SCLK, and the DAC is updated on the th DSPs. On the 24 falling clock edge, the last data bit is clocked th 24 falling edge. However, if SYNC is brought high before the in and the programmed function is executed, that is, a change th 24 falling edge, this acts as an interrupt to the write sequence. in DAC register contents occurs. At this stage, the SYNC line The shift register is reset and the write sequence is seen as invalid. can be kept low or brought high. In either case, it must be Neither an update of the DAC register contents nor a change in brought high for a minimum of 33 ns before the next write the operating mode occurs (see Figure 26). sequence so that a falling edge of can initiate the next SYNC POWER-ON RESET write sequence. Because the SYNC buffer draws more current The AD5680 family contains a power-on reset circuit that when V = 2 V than it does when V = 0.8 V, should be IN IN SYNC controls the output voltage during power-up. The AD5680-1 idled low between write sequences for even lower power DAC output powers up to 0 V, and the AD5680-2 DAC output operation. As mentioned previously, it must, however, be powers up to midscale. The output remains there until a valid brought high again just before the next write sequence. write sequence is made to the DAC. This is useful in applications where it is important to know the output state of the DAC while it is in the process of powering up. DB23 (MSB) DB0 (LSB) XX 00 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XX DATA BITS RESERVED BITS Figure 25. Input Register Contents SCLK SYNC DB23 DB0 DB23 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE: TH TH SYNC HIGH BEFORE 24 FALLING EDGE OUTPUT UPDATES ON THE 24 FALLING EDGE Figure 26. SYNC Interrupt Facility Rev. A | Page 12 of 20 05854-034 05854-033 AD5680 AD5680 to 80C51/80L51 Interface MICROPROCESSOR INTERFACING AD5680 to Blackfin® ADSP-BF53x Interface Figure 29 shows a serial interface between the AD5680 and the 80C51/80L51 microcontroller. The setup for the interface is as Figure 27 shows a serial interface between the AD5680 and follows. TxD of the 80C51/80L51 drives SCLK of the AD5680, the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x while RxD drives the serial data line of the part. The SYNC processor family incorporates two dual-channel synchronous signal is again derived from a bit-programmable pin on the port. serial ports, SPORT1 and SPORT0, for serial and multiprocessor In this case, port line P3.3 is used. When data is to be transmitted communications. Using SPORT0 to connect to the AD5680, the to the AD5680, P3.3 is taken low. The 80C51/80L51 transmits setup for the interface is as follows. DT0PRI drives the DIN pin data in 8-bit bytes only; thus, only eight falling clock edges occur of the AD5680, while TSCLK0 drives the SCLK of the part. The in the transmit cycle. To load data to the DAC, P3.3 is left low SYNC is driven from TFS0. after the first eight bits are transmitted, and a second write cycle ADSP-BF53x* AD5680* is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The TFS0 SYNC AD5680 must receive data with the MSB first. The 80C51/80L51 DTOPRI DIN transmit routine should take this into account. TSCLK0 SCLK 80C51/80L51* AD5680* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. AD5680 to Blackfin ADSP-BF53x Interface P3.3 SYNC AD5680 to 68HC11/68L11 Interface TxD SCLK Figure 28 shows a serial interface between the AD5680 and the RxD DIN 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5680, while the MOSI output drives *ADDITIONAL PINS OMITTED FOR CLARITY. the serial data line of the DAC. Figure 29. AD5680 to 80C51/80L51 Interface The SYNC signal is derived from a port line (PC7). The setup AD5680 to MICROWIRE Interface conditions for correct operation of this interface are as follows: Figure 30 shows an interface between the AD5680 and any The 68HC11/68L11 is configured with its CPOL bit as 0 and its MICROWIRE-compatible device. Serial data is shifted out on CPHA bit as 1. When data is being transmitted to the DAC, the the falling edge of the serial clock and is clocked into the AD5680 SYNC line is taken low (PC7). When the 68HC11/68L11 is on the rising edge of the SK. configured this way, data appearing on the MOSI output is valid AD5680* MICROWIRE* on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To CS SYNC load data to the AD5680, PC7 is left low after the first eight bits SK SCLK are transferred, and a second serial write operation is performed SO DIN to the DAC; PC7 is taken high at the end of this procedure. *ADDITIONAL PINS OMITTED FOR CLARITY. 68HC11/68L11* AD5680* Figure 30. AD5680 to MICROWIRE Interface PC7 SYNC SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 28. AD5680 to 68HC11/68L11 Interface Rev. A | Page 13 of 20 05854-036 05854-035 05854-038 05854-037 AD5680 APPLICATIONS CLOSED-LOOP APPLICATIONS Δ: 2.09ms @: 1.28ms The AD5680 is suitable for closed-loop low bandwidth applica- 2 tions. Ideally, the system bandwidth acts as a filter on the DAC output. (See the Filter section for details of the DAC output prefiltering and postfiltering.) The DAC updates at the interpolation frequency of 10 kHz. 1 PLANT CONTROLLER DAC CODE 4092 CODE 4094 M 500µs CH2 1.4V CH1 20.0µV CH2 5V ADC Figure 33. DAC Output with 50 Hz Filter on Output Figure 31. Typical Closed-Loop Application FILTER Δ: 2.09ms @: 1.28ms 2 The DAC output voltage for code transition 4092 to 4094 can be seen in Figure 32. This is the DAC output unfiltered. Code 4092 does not have any interpolation but Code 4094 has interpolation with a 50% duty cycle (see Table 5). Figure 33 shows the DAC output with a 50 Hz passive RC filter and Figure 34 shows the 1 output with a 300 Hz passive RC filter. An RC combination of 320 kΩ and 10 nF has been used to achieve the 50 Hz cutoff frequency, and an RC combination of 81 kΩ and 10 nF has CODE 4092 CODE 4094 been used to achieve the 300 Hz cutoff frequency. M 500µs CH2 1.4V CH1 20.0µV CH2 5V Figure 34. DAC Output with 300 Hz Filter on Output CODE 4092 CODE 4094 1 M 500µs CH4 0V CH1 20.0µV Figure 32. DAC Output Unfiltered Rev. A | Page 14 of 20 05854-024 05854-039 05854-026 05854-025 AD5680 Long-term drift is a measurement of how much the reference CHOOSING A REFERENCE FOR THE AD5680 drifts over time. A reference with a tight long-term drift speci- To achieve the optimum performance from the AD5680, choose fication ensures that the overall solution remains relatively stable a precision voltage reference carefully. The AD5680 has only during its entire lifetime. one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore, any The temperature coefficient of a reference’s output voltage error in the reference is reflected in the DAC. affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce temperature When choosing a voltage reference for high accuracy applica- dependence of the DAC output voltage in ambient conditions. tions, the sources of error are initial accuracy, ppm drift, long- In high accuracy applications, which have a relatively low noise term drift, and output voltage noise. Initial accuracy on the budget, reference output voltage noise needs to be considered. It output voltage of the DAC leads to a full-scale error in the DAC. is important to choose a reference with as low an output noise To minimize these errors, a reference with high initial accuracy is preferred. In addition, choosing a reference with an output voltage as is practical for the system noise resolution required. trim adjustment, such as the ADR425, allows a system designer Precision voltage references such as the ADR425 produce low to trim out system errors by setting a reference voltage to a output noise in the 0.1 Hz to 10 Hz range. Examples of recom- voltage other than the nominal. The trim adjustment can also mended precision references for use as supply to the AD5680 are shown in the Table 6. be used at temperature to trim out any error. Table 6. Partial List of Precision References for Use with the AD5680 Part No. Initial Accuracy (mV max) Temperature Drift (ppm/°C max) 0.1 Hz to 10 Hz Noise (μV p-p typ) V (V) OUT ADR425±2 3 3.4 5 ADR395±6 25 5 5 REF195±2 5 50 5 Rev. A | Page 15 of 20 AD5680 5V USING A REFERENCE AS A POWER SUPPLY FOR REGULATOR 10µF 0.1µF THE AD5680 POWER Because the supply current required by the AD5680 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 35). This is especially V DD SCLK V V SCLK OA IA useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V, for example, 15 V. ADuM130x AD5680 The voltage reference outputs a steady supply voltage for the AD5680; see Table 6 for a suitable reference. If the low dropout V SYNC V SDI V OUT IB OB REF195 is used, it must supply 325 μA of current to the AD5680, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC V V DIN DATA OC IC GND output) is 325 μA + (5 V/5 kΩ) = 1.33 mA Figure 36. AD5680 with a Galvanically Isolated Interface The load regulation of the REF195 is typically 2 ppm/mA, which results in a 2.7 ppm (13.5 μV) error for the 1.33 mA POWER SUPPLY BYPASSING AND GROUNDING current drawn from it. This corresponds to a 0.177 LSB error. When accuracy is important in a circuit, it is helpful to carefully 15V consider the power supply and ground return layout on the board. 5V The printed circuit board containing the AD5680 should have REF195 250µA separate analog and digital sections, each having its own area of the board. If the AD5680 is in a system where other devices require an AGND-to-DGND connection, the connection should V V SYNC DD REF 3-WIRE V = 0V TO 5V OUT be made at one point only. This ground point should be as close SERIAL SCLK AD5680 INTERFACE as possible to the AD5680. DIN The power supply to the AD5680 should be bypassed with 10 μF Figure 35. REF195 as Power Supply to the AD5680 and 0.1 μF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 μF capacitor ideally right USING THE AD5680 WITH A GALVANICALLY up against the device. The 10 μF capacitors should be the tanta- ISOLATED INTERFACE lum bead type. It is important that the 0.1 μF capacitor has low In process-control applications in industrial environments, it is effective series resistance (ESR) and effective series inductance often necessary to use a galvanically isolated interface to protect (ESI), for example, common ceramic types of capacitors. This and isolate the controlling circuitry from any hazardous common- 0.1 μF capacitor provides a low impedance path to ground for mode voltages that might occur in the area where the DAC is high frequencies caused by transient currents due to internal functioning. Isocouplers provide isolation in excess of 3 kV. The logic switching. AD5680 uses a 3-wire serial logic interface, so the ADuM130x The power supply line itself should have as large a trace as 3-channel digital isolator provides the required isolation (see possible to provide a low impedance path and to reduce glitch Figure 36). The power supply to the part also needs to be isolated, effects on the supply line. Clocks and other fast switching digital which is done by using a transformer. On the DAC side of the signals should be shielded from other parts of the board by transformer, a 5 V regulator provides the 5 V supply required digital ground. Avoid crossover of digital and analog signals if for the AD5680. possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout tech- nique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. A | Page 16 of 20 05854-040 05854-041 AD5680 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 13 2 4 PIN 1 INDICATOR 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.60 8° 0.38 0.45 0.15 MAX 4° SEATING 0.30 0.22 PLANE 0° COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 37. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Package Package Power-On Model Temperature Range Description Option Reset to Code Accuracy Branding 1 AD5680BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 Zero ±64 LSB INL D3C 1 AD5680BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 Zero ±64 LSB INL D3C 1 AD5680BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 Midscale ±64 LSB INL D3D 1 AD5680BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 Midscale ±64 LSB INL D3D EVAL-AD5680EB Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 17 of 20 AD5680 NOTES Rev. A | Page 18 of 20 AD5680 NOTES Rev. A | Page 19 of 20 AD5680 NOTES ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05854-0-3/07(A) TTTT Rev. A | Page 20 of 20