ANALOG DEVICES AD5678

4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP AD5678 FEATURES FUNCTIONAL BLOCK DIAGRAM V /V V REFIN REFOUT DD Low power octal DAC with AD5678 1.25V/2.5V Four 16-bit DACs REF BUFFER Four 12-bit DACs INPUT DAC STRING V A LDAC OUT REGISTER REGISTER DAC A 14-lead/16-lead TSSOP BUFFER INPUT DAC STRING V B OUT REGISTER DAC B REGISTER On-chip 1.25 V/2.5 V, 5 ppm/°C reference BUFFER DAC INPUT STRING SCLK V C OUT Power down to 400 nA @ 5 V, 200 nA @ 3 V REGISTER REGISTER DAC C INTERFACE BUFFER 2.7 V to 5.5 V power supply INPUT DAC STRING SYNC LOGIC V D OUT REGISTER REGISTER DAC D Guaranteed monotonic by design BUFFER INPUT DAC STRING DIN V E OUT REGISTER REGISTER DAC E Power-on reset to zero scale BUFFER INPUT DAC STRING V F REGISTER OUT 3 power-down functions REGISTER DAC F BUFFER DAC Hardware LDAC and LDAC override function INPUT STRING V G OUT REGISTER REGISTER DAC G CLR function to programmable code BUFFER INPUT DAC STRING V H OUT REGISTER REGISTER DAC H Rail-to-rail operation POWER-DOWN POWER-ON LOGIC RESET 1 GND LDAC 1 CLR APPLICATIONS 1 RU-16 PACKAGE ONLY Figure 1. Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage current sources Programmable attenuators GENERAL DESCRIPTION The AD5678 is a low power, octal, buffered voltage-output The outputs of all DACs can be updated simultaneously using the function, with the added functionality of user- DAC with four 12-bit DACs and four 16-bit DACs in a single LDAC package. All devices operate from a single 2.7 V to 5.5 V supply selectable DAC channels to simultaneously update. There is and are guaranteed monotonic by design. also an asynchronous that clears all DACs to a software- CLR selectable code—0 V, midscale, or full scale. The AD5678 has an on-chip reference with an internal gain of 2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full- The AD5678 utilizes a versatile 3-wire serial interface that scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C operates at clock rates of up to 50 MHz and is compatible with reference, giving a full-scale output of 5 V. The on-board standard SPI®, QSPI™, MICROWIRE™, and DSP interface reference is off at power-up, allowing the use of an external standards. The on-chip precision output amplifier enables rail- reference. The internal reference is enabled via a software write. to-rail output swing. The part incorporates a power-on reset circuit that ensures that PRODUCT HIGHLIGHTS the DAC output powers up to 0 V and remains powered up at 1. Octal DAC (four 12-bit DACs and four 16-bit DACs). this level until a valid write takes place. The part contains a 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. power-down feature that reduces the current consumption of 3. Available in 14-lead/16-lead TSSOP. the device to 400 nA at 5 V and provides software-selectable 4. Power-on reset to 0 V. output loads while in power-down mode for any or all DAC 5. Power-down capability. When powered down, the DAC channels. typically consumes 200 nA at 3 V and 400 nA at 5 V. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05299-001 AD5678 TABLE OF CONTENTS Features .............................................................................................. 1 D/A Section................................................................................. 20 Applications....................................................................................... 1 Resistor String............................................................................. 20 Functional Block Diagram .............................................................. 1 Internal Reference ...................................................................... 20 General Description ......................................................................... 1 Output Amplifier........................................................................ 21 Product Highlights ........................................................................... 1 Serial Interface ............................................................................ 21 Revision History ............................................................................... 2 Input Shift Register .................................................................... 22 Specifications..................................................................................... 3 Interrupt .......................................................................... 22 SYNC AC Characteristics........................................................................ 7 Internal Reference Register....................................................... 23 Timing Characteristics ................................................................ 8 Power-On Reset.......................................................................... 23 Absolute Maximum Ratings............................................................ 9 Power-Down Modes .................................................................. 23 ESD Caution.................................................................................. 9 Clear Code Register ................................................................... 23 Pin Configuration and Function Descriptions........................... 10 Function .......................................................................... 25 LDAC Typical Performance Characteristics ........................................... 11 Power Supply Bypassing and Grounding................................ 25 Terminology .................................................................................... 18 Outline Dimensions....................................................................... 26 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 26 REVISION HISTORY 2/11—Rev. B to Rev. C Changes to Zero-Code Error Parameter and Offset Error Parameter, Table 1............................................................................. 3 Changes to Zero-Code Error Parameter and Offset Error Parameter, Table 2............................................................................. 5 2/09—Rev. A to Rev. B Changes to Reference Current Parameter, Table 1....................... 3 Change to IDD (Normal Mode) Parameter, Table 1 ...................... 4 Changes to Reference Current Parameter, Table 2....................... 5 Change to IDD (Normal Mode) Parameter, Table 2 ...................... 6 11/05—Rev. 0 to Rev. A Change to General Description ...................................................... 1 Change to Specifications.................................................................. 3 Replaced Figure 48 ......................................................................... 22 Change to the Power-Down Modes Section ............................... 23 10/05—Revision 0: Initial Version Rev. C | Page 2 of 28 AD5678 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5678 (DAC C, D, E, F) Resolution 12 12 Bits Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5678 (DAC A, B, G, H) Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 6) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 17) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 18) Gain Error ±1 ±1 % FSR Gain Temperature ±2.5 ±2.5 ppm Of FSR/°C Coefficient Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection –80 –80 dB VDD ± 10% Ratio DC Crosstalk 10 10 μV Due to full-scale output change, (External Reference) R = 2 kΩ to GND or V L DD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode; VDD = 5 V REFERENCE INPUTS Reference Input Voltage VDD VDD V ±1% for specified performance Reference Current 35 55 35 55 μA VREF = VDD = 5.5 V (per DAC channel) Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ Per DAC channel REFERENCE OUTPUT Output Voltage AD5678-2 2.495 2.505 2.495 2.505 V At ambient 3 Reference TC ±5 ±10 ±5 ±10 ppm/°C Reference Output Impedance 7.5 7.5 kΩ 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, VINL 0.8 0.8 V VDD = 5 V Input High Voltage, VINH 2 2 V VDD = 5 V Pin Capacitance 3 3 pF Rev. C | Page 3 of 28 AD5678 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V All digital inputs at 0 or V , DD DD DAC active, excludes load current 4 I (Normal Mode) V = V and V = GND DD IH DD IL VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off VDD = 4.5 V to 5.5 V 2 2.6 2 2.6 mA Internal reference on 5 IDD (All Power-Down Modes) V = 4.5 V to 5.5 V 0.4 1 0.4 1 μA V = V and V = GND DD IH DD IL 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. Rev. C | Page 4 of 28 AD5678 V = 2.7 V to 3.6 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5678 (DAC C, D, E, F) Resolution 12 12 Bits Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 12) AD5678 (DAC A, B, G, H) Resolution 16 16 Bits Relative Accuracy ±32 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (See Figure 6) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (See Figure 17) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (See Figure 18) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV Offset Temperature Coefficient 1.7 1.7 μV/°C DC Power Supply Rejection –80 –80 dB V ± 10% DD Ratio DC Crosstalk 10 10 μV Due to full-scale output change, (External Reference) RL = 2 kΩ to GND or VDD 4.5 4.5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) RL = 2 kΩ to GND or VDD 4.5 4.5 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 3 V DD Power-Up Time 4 4 μs Coming out of power-down mode; V = 3 V DD REFERENCE INPUTS Reference Input Voltage V V V ±1% for specified performance DD DD Reference Current 20 55 20 55 μA V = V = 3.6 V (per DAC channel) REF DD Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ Per DAC channel REFERENCE OUTPUT Output Voltage AD5678-1 1.247 1.253 1.247 1.253 V At ambient 3 Reference TC ±5 ±15 ±5 ±15 ppm/°C Reference Output Impedance 7.5 7.5 kΩ Rev. C | Page 5 of 28 AD5678 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 3 V INL DD Input High Voltage, V 2 2 V V = 3 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 2.7 3.6 2.7 3.6 V DD All digital inputs at 0 or VDD, DAC active, excludes load current 4 IDD (Normal Mode) VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1.2 1.7 1.2 1.7 mA Internal reference off V = 2.7 V to 3.6 V 1.7 2.6 1.7 2.6 mA Internal reference on DD 5 I (All Power-Down Modes) DD VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 μA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. Rev. C | Page 6 of 28 AD5678 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. 1, 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 6 10 μs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34) Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz REF Digital Crosstalk 0.5 nV-s Analog Crosstalk 2.5 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.2 V p-p Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz 100 nV/√Hz DAC code = 0x8400, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. C | Page 7 of 28 AD5678 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD 1 t1 20 ns min SCLK cycle time t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 13 ns min to SCLK falling edge set-up time 4 SYNC t5 4 ns min Data set-up time t6 4 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t 15 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t10 0 ns min SCLK falling edge to SYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min SCLK falling edge to LDAC rising edge t 5 ns min CLR pulse width low 13 t 0 ns min SCLK falling edge to LDAC falling edge 14 t 300 ns typ CLR pulse activation time 15 1 Maximum SCLK frequency is 50 MHz at V = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. DD t 10 t 1 t 9 SCLK t 2 t 8 t t 7 t 3 4 SYNC t 6 t 5 DIN DB31 DB0 t 11 t 14 1 LDAC t 12 2 LDAC t 13 CLR t V 15 OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. C | Page 8 of 28 05299-002 AD5678 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating Stresses above those listed under Absolute Maximum Ratings V to GND −0.3 V to +7 V DD may cause permanent damage to the device. This is a stress Digital Input Voltage to GND −0.3 V to V + 0.3 V DD rating only; functional operation of the device at these or any VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V other conditions above those indicated in the operational Operating Temperature Range section of this specification is not implied. Exposure to absolute Industrial (B Version) −40°C to +105°C maximum rating conditions for extended periods may affect Storage Temperature Range −65°C to +150°C device reliability. Junction Temperature (T ) 150°C J MAX TSSOP Package Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 150.4°C/W Lead Temperature, Soldering SnPb 240°C Pb Free 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 9 of 28 AD5678 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 16 LDAC SCLK SYNC 1 14 SCLK 2 15 SYNC DIN 2 13 V DIN 3 14 DD V GND DD AD5678 V A 3 12 GND V A 4 13 V B OUT OUT TOP VIEW OUT AD5678 (Not to Scale) V C 4 11 V B TOP VIEW V C 5 12 V D OUT OUT OUT OUT (Not to Scale) V E 5 10 V D V E 6 11 V F OUT OUT OUT OUT V G 6 9 V F V G 7 10 V H OUT OUT OUT OUT V /V 7 8 V H 8 REFIN REFOUT OUT /V 9 CLR V REFIN REFOUT Figure 3. 14-Lead TSSOP (RU-14) Figure 4. 16-Lead TSSOP (RU-16) Table 6. Pin Function Descriptions Pin No. 14-Lead 16-Lead TSSOP TSSOP Mnemonic Description N/A 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. 1 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before nd the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 2 3 V DD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 3 4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 11 13 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 5 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 10 12 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 7 8 V /V REFIN REFOUT The AD5678 has a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. N/A 9 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 5 6 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 9 11 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. 6 7 V G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. OUT 8 10 V H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. OUT 12 14 GND Ground Reference Point for All Circuitry on the Part. 13 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. C | Page 10 of 28 05299-003 05299-004 AD5678 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 10 V = 5V DD V = V = 5V DD REF 0.8 V = 2.5V REFOUT 8 T = 25°C T = 25°C A A 0.6 6 0.4 4 0.2 2 0 0 –0.2 –2 –0.4 –4 –0.6 –6 –0.8 –8 –1.0 –10 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE CODE Figure 5. INL—16-Bit DAC Figure 8. DNL 16-Bit DAC, 2.5 V Internal Reference 10 V = 3V DD 1.0 8 V = 1.25V REFOUT V = V = 5V DD REF T = 25°C A 0.8 T = 25°C A 6 0.6 4 0.4 2 0.2 0 0 –2 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 0 10k 20k 30k 40k 50k 60k CODE CODE Figure 6. DNL—16-Bit DAC Figure 9. INL—16-Bit DAC, 1.25 V Internal Reference 10 1.0 V = 5V V = 3V DD DD 8 V = 2.5V 0.8 V = 1.25V REFOUT REFOUT T = 25°C T = 25°C A A 6 0.6 4 0.4 2 0.2 0 0 –2 –0.2 –0.4 –4 –0.6 –6 –0.8 –8 –10 –1.0 CODE CODE Figure 7. INL—16-Bit DAC, 2.5 V Internal Reference Figure 10. DNL—16-Bit DAC, 1.25 V Internal Reference Rev. C | Page 11 of 28 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000 05299-013 05299-012 05299-011 DNL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 0 0 0 5000 5000 5000 10000 10000 10000 15000 15000 15000 20000 20000 20000 25000 25000 25000 30000 30000 30000 35000 35000 35000 40000 40000 40000 45000 45000 45000 50000 50000 50000 55000 55000 55000 60000 60000 60000 65000 65000 65000 05299-016 05299-015 05299-014 AD5678 1.0 V = V = 5V 0.20 DD REF T = 25°C 0.8 A V = 5V DD V = 2.5V REFOUT 0.15 0.6 T = 25°C A 0.4 0.10 0.2 0.05 0 0 –0.2 –0.05 –0.4 –0.6 –0.10 –0.8 –0.15 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 –0.20 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 11. INL—12-Bit DAC Figure 14. DNL 12-Bit DAC, 2.5 V Internal Reference 0.20 V = V = 5V 1.0 DD REF T = 25°C A V = 3V DD 0.15 0.8 V = 1.25V REFOUT T = 25°C A 0.6 0.10 0.4 0.05 0.2 0 0 –0.05 –0.2 –0.4 –0.10 –0.6 –0.15 –0.8 –0.20 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 12. DNL—12-Bit DAC Figure 15. INL—12-Bit DAC, 1.25 V Internal Reference 0.20 1.0 V = 5V V = 3V DD DD 0.8 V = 2.5V V = 1.25V REFOUT REFOUT 0.15 T = 25°C T = 25°C A A 0.6 0.10 0.4 0.05 0.2 0 0 –0.2 –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –0.20 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 13. INL—12-Bit DAC, 2.5 V Internal Reference Figure 16. DNL—12-Bit DAC, 1.25 V Internal Reference Rev. C | Page 12 of 28 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 05299-047 05299-046 05299-045 DNL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 05299-050 05299-049 05299-048 AD5678 1.0 0 V = 5V T = 25°C A DD –0.02 0.5 ZERO-SCALE ERROR –0.04 GAIN ERROR 0 –0.06 –0.08 –0.5 –0.10 –1.0 –0.12 –0.14 –1.5 FULL-SCALE ERROR –0.16 –2.0 OFFSET ERROR –0.18 –2.5 –0.20 2.7 3.2 3.7 4.2 4.7 5.2 –40 –20 0 20 40 60 80 100 V (V) TEMPERATURE (°C) DD Figure 17. Gain Error and Full-Scale Error vs. Temperature Figure 20. Zero-Scale Error and Offset Error vs. Supply Voltage 20 1.5 V = 3.6V DD V = 5.5V 18 DD 1.0 ZERO-SCALE ERROR 16 0.5 14 0 12 10 –0.5 8 –1.0 6 –1.5 4 OFFSET ERROR –2.0 2 0 –2.5 –40 –2008 20 40 600 100 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 I (mA) TEMPERATURE (°C) DD Figure 18. Zero-Scale Error and Offset Error vs. Temperature Figure 21. I Histogram with External Reference DD 1.0 14 V = 3.6V DD V = 5.5V DD 12 0.5 GAIN ERROR 10 0 V = 1.25V V = 2.5V REFOUT REFOUT 8 FULL-SCALE ERROR –0.5 6 –1.0 4 –1.5 2 –2.0 0 2.7 3.2 3.7 4.2 4.7 5.2 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 V (V) I (mA) DD DD Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage Figure 22. I Histogram with Internal Reference DD Rev. C | Page 13 of 28 ERROR (% FSR) ERROR (mV) ERROR (% FSR) 05299-019 05299-018 05299-017 FREQUENCY FREQUENCY ERROR (mV) 05299-022 05299-021 05299-020 AD5678 0.50 2.0 T = 25°C V = V = 5V DAC LOADED WITH DAC LOADED WITH A DD REF 0.40 FULL-SCALE ZERO-SCALE 1.8 SOURCING CURRENT SINKING CURRENT 0.30 1.6 1.4 0.20 V = 3V 0.10 DD 1.2 V = V = 3V V = 1.25V DD REF REFOUT 1.0 0 0.8 –0.10 0.6 –0.20 V = 5V 0.4 –0.30 DD V = 2.5V REFOUT 0.2 –0.40 –0.50 0 –10 –8 –6 –4 –2 0 2 461 8 0 512 10512 20512 30512 40512 50512 60512 CURRENT (mA) CODE Figure 23. Headroom at Rails vs. Source and Sink Figure 26. Supply Current vs. Code 6.00 1.6 V = V = 5.5V DD REFIN V = 5V DD FULL SCALE V = 2.5V REFOUT 1.4 5.00 T = 25°C A 1.2 3/4 SCALE 4.00 V = V = 3.6V DD REFIN 1.0 3.00 MIDSCALE 0.8 2.00 1/4 SCALE 0.6 1.00 0.4 0 ZERO SCALE 0.2 –1.00 0 –30 –20 –10 0 10 20 30 –40 –20 0 20 40 60 80 100 CURRENT (mA) TEMPERATURE (°C) Figure 24. AD5678-2 Source and Sink Capability Figure 27. Supply Current vs. Temperature 1.6 4.00 T =25°C A V = 3V DD V = 1.25V REFOUT 1.4 T = 25°C A 3.00 FULL SCALE 1.2 1.0 3/4 SCALE 2.00 0.8 MIDSCALE 1.00 0.6 1/4 SCALE 0.4 0 ZERO SCALE 0.2 0 –1.00 2.7 3.2 3.7 4.2 4.7 5.2 –30 –20 –10 0 10 20 30 V (V) CURRENT (mA) DD Figure 25. AD5678-1 Source and Sink Capability Figure 28. Supply Current vs. Supply Voltage Rev. C | Page 14 of 28 V (V) V (V) ERROR VOLTAGE (V) OUT OUT 05299-025 05299-024 05299-023 I (mA) I (mA) I (mA) DD DD DD 05299-028 05299-027 05299-026 AD5678 8 T = 25°C A V = V = 5V DD REF 7 T = 25°C A 6 5 V DD 4 1 V = 5V 3 DD 2 1 2 V OUT V = 3V DD 0 01 234 5 6 CH1 2.0V CH2 1.0V M100μs 125MS/s 8.0ns/pt V (V) LOGIC A CH1 1.28V Figure 29. Supply Current vs. Logic Input Voltage Figure 32. Power-On Reset to Midscale SYNC 1 SLCK 3 V = V = 5V DD REF T = 25°C A FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND V OUT V = 909mV/DIV OUT V = 5V DD 1 2 CH1 5.0V CH2 500mV M400ns A CH1 1.4V TIME BASE = 4μs/DIV CH3 5.0V Figure 30. Full-Scale Settling Time, 5 V Figure 33. Exiting Power-Down to Midscale 2.505 2.504 V = 5V DD V = V = 5V DD REF 2.503 V = 2.5V REFOUT T = 25°C A 2.502 T = 25°C A 2.501 4ns/SAMPLE NUMBER 2.500 GLITCH IMPULSE = 3.55nV-s 2.499 1 LSB CHANGE AROUND 2.498 MIDSCALE (0x8000 TO 0x7FFF) 2.497 2.496 2.495 2.494 V DD 2.493 1 2.492 2.491 2.490 MAX(C2)* 2.489 420.0mV 2.488 2 2.487 V OUT 2.486 2.485 0 64 128 192 256 320 384 448 512 CH1 2.0V CH2 500mV M100μs 125MS/s 8.0ns/pt A CH1 1.28V SAMPLE Figure 31. Power-On Reset to 0 V Figure 34. Digital-to-Analog Glitch Impulse (Negative) Rev. C | Page 15 of 28 I (mA) DD 05299-031 05299-030 05299-029 V (V) OUT 05299-033 05299-032 05299-034 AD5678 2.5000 V = 5V 2.4995 DD V = 2.5V REFOUT T = 25°C A 2.4990 DAC LOADED WITH MIDSCALE 2.4985 2.4980 2.4975 1 2.4970 2.4965 2.4960 V = 5V DD V = 2.5V REFOUT 2.4955 T = 25°C A 4ns/SAMPLE NUMBER 2.4950 0 64 128 192 256 320 384 448 512 SAMPLE 5s/DIV Figure 35. Analog Crosstalk Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 2.4900 V = 3V DD 2.4895 V = 1.25V REFOUT T = 25°C A 2.4890 DAC LOADED WITH MIDSCALE 2.4885 2.4880 1 2.4875 2.4870 2.4865 V = 5V DD V = 2.5V REFOUT 2.4860 T = 25°C A 4ns/SAMPLE NUMBER 2.4855 0 64 128 192 256 320 384 448 512 4s/DIV SAMPLE Figure 36. DAC-to-DAC Crosstalk Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 T =25°C A MIDSCALE LOADED 700 V = V = 5V DD REF T = 25°C A 600 DAC LOADED WITH MIDSCALE 500 400 1 300 V =5V DD V =2.5V REFOUT 200 100 V =3V DD V = 1.25V REFOUT 0 Y AXIS = 2μV/DIV 100 1000 10000 100000 1000000 X AXIS = 4s/DIV FREQUENCY (Hz) Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 40. Noise Spectral Density, Internal Reference Rev. C | Page 16 of 28 V (V) V (V) OUT OUT 05299-037 05299-036 05299-035 OUTPUT NOISE (nV/√Hz) 5μV/DIV 10μV/DIV 05299-039 05299-038 05299-040 AD5678 –20 V =5V DD T =25°C A –30 DAC LOADED WITH FULL SCALE CLR 3 V = 2V ± 0.3V p-p REF –40 V F –50 OUT –60 –70 –80 V B OUT –90 4 4 2 –100 2k 4k 6k 8k 10k CH2 1.0V M200ns A CH3 1.10V CH3 5.0V CH4 1.0V FREQUENCY (Hz) Figure 41. Total Harmonic Distortion Figure 43. Hardware CLR 16 5 V = 5V V = V DD REF DD T = 25°C A T = 25°C A 0 14 –5 V = 3V DD 12 –10 –15 10 –20 V = 5V 8 DD –25 –30 6 –35 4 –40 01 2 3 4 5 6 781 9 0 10k 100k 1M 10M CAPACITANCE (nF) FREQUENCY (Hz) Figure 42. Settling Time vs. Capacitive Load Figure 44. Multiplying Bandwidth Rev. C | Page 17 of 28 TIME (μs) (dB) 05299-042 05299-041 (dB) 05299-043 05299-044 AD5678 TERMINOLOGY Full-Scale Error Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is Full-scale error is a measure of the output error when full-scale a measure of the maximum deviation in LSBs from a straight code (0xFFFF) is loaded into the DAC register. Ideally, the line passing through the endpoints of the DAC transfer output should be VDD − 1 LSB. Full-scale error is expressed as a function. Figure 5, Figure 7, and Figure 9 show plots of typical percentage of the full-scale range. Figure 17 shows a plot of INL vs. code. typical full-scale error vs. temperature. Differential Nonlinearity Digital-to-Analog Glitch Impulse Differential nonlinearity (DNL) is the difference between the Digital-to-analog glitch impulse is the impulse injected into the measured change and the ideal 1 LSB change between any two analog output when the input code in the DAC register changes adjacent codes. A specified differential nonlinearity of ±1 LSB state. It is normally specified as the area of the glitch in nV-s maximum ensures monotonicity. This DAC is guaranteed mono- and is measured when the digital input code is changed by tonic by design. Figure 6, Figure 8, and Figure 10 show plots of 1 LSB at the major carry transition (0x7FFF to 0x8000). See typical DNL vs. code. Figure 34. Offset Error DC Power Supply Rejection Ratio (PSRR) Offset error is a measure of the difference between the actual PSRR indicates how the output of the DAC is affected by changes VOUT and the ideal VOUT, expressed in millivolts in the linear in the supply voltage. PSRR is the ratio of the change in VOUT to region of the transfer function. Offset error is measured on the a change in VDD for full-scale output of the DAC. It is measured AD5678 with Code 512 loaded into the DAC register. It can be in decibels. VREF is held at 2 V, and VDD is varied ±10%. negative or positive and is expressed in millivolts. DC Crosstalk Zero-Code Error DC crosstalk is the dc change in the output level of one DAC in Zero-code error is a measure of the output error when zero response to a change in the output of another DAC. It is measured code (0x0000) is loaded into the DAC register. Ideally, the with a full-scale output change on one DAC (or soft power-down output should be 0 V. The zero-code error is always positive in and power-up) while monitoring another DAC. It is expressed the AD5678, because the output of the DAC cannot go below 0 V. in microvolts. It is due to a combination of the offset errors in the DAC and DC crosstalk due to load current change is a measure of the output amplifier. Zero-code error is expressed in millivolts. impact that a change in load current on one DAC has to another Figure 18 shows a plot of typical zero-code error vs. DAC kept at midscale. It is expressed in microvolts per milliamp. temperature. Reference Feedthrough Gain Error Reference feedthrough is the ratio of the amplitude of the signal Gain error is a measure of the span error of the DAC. It is the at the DAC output to the reference input when the DAC output deviation in slope of the DAC transfer characteristic from the is not being updated (that is, is high). It is expressed in LDAC ideal, expressed as a percentage of the full-scale range. decibels. Zero-Code Error Drift Channel-to-Channel Isolation Zero-code error drift is a measure of the change in zero-code Channel-to-channel isolation is the ratio of the amplitude of the error with a change in temperature. It is expressed in μV/°C. signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels. Gain Error Drift Digital Feedthrough Gain error drift is a measure of the change in gain error with Digital feedthrough is a measure of the impulse injected into changes in temperature. It is expressed in (ppm of full-scale the analog output of a DAC from the digital input pins of the range)/°C. device, but is measured when the DAC is not being written to ( held high). It is specified in nV-s and measured with a SYNC full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Rev. C | Page 18 of 28 AD5678 Digital Crosstalk Multiplying Bandwidth Digital crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC at midscale in response to a full-scale code change multiplying bandwidth is a measure of this. A sine wave on the (all 0s to all 1s or vice versa) in the input register of another reference (with full-scale code loaded to the DAC) appears on DAC. It is measured in standalone mode and is expressed in the output. The multiplying bandwidth is the frequency at nV-s. which the output amplitude falls to 3 dB below the input. Analog Crosstalk Total Harmonic Distortion (THD) Analog crosstalk is the glitch impulse transferred to the output Total harmonic distortion is the difference between an ideal of one DAC due to a change in the output of another DAC. It is sine wave and its attenuated version using the DAC. The sine measured by loading one of the input registers with a full-scale wave is used as the reference for the DAC, and the THD is a code change (all 0s to all 1s or vice versa) while keeping measure of the harmonics present on the DAC output. It is LDAC measured in decibels. high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with low and monitoring the output of another DAC. The LDAC energy of the glitch is expressed in nV-s. Rev. C | Page 19 of 28 AD5678 THEORY OF OPERATION D/A SECTION R The AD5678 DAC is fabricated on a CMOS process. The archi- tecture consists of a string of DACs followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C R reference with an internal gain of 2. Figure 45 shows a block diagram of the DAC architecture. TO OUTPUT R AMPLIFIER V DD REF (+) RESISTOR V DAC REGISTER OUT STRING REF (–) OUTPUT R AMPLIFIER (GAIN = +2) GND R Figure 45. DAC Architecture Because the input coding to the DAC is straight binary, the ideal Figure 46. Resistor String output voltage when using an external reference is given by INTERNAL REFERENCE D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN N The AD5678 has an on-chip reference with an internal gain of ⎝ 2 ⎠ 2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full- the ideal output voltage when using an internal reference is scale output of 2.5 V. The AD5678-2 has a 2.5 V 5 ppm/°C given by reference, giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external D ⎛ ⎞ = × × V2 V ⎜ ⎟ OUT REFOUT N reference. The internal reference is enabled via a write to a ⎝ 2 ⎠ control register. See Table 7. where: The internal reference associated with each part is available at D = decimal equivalent of the binary code that is loaded to the the V pin. A buffer is required if the reference output is REFOUT DAC register. used to drive external loads. When using the internal reference, 0 to 4,095 for AD5678 DAC C, D, E, F (12 bits). it is recommended that a 100 nF capacitor be placed between 0 to 65,535 for AD5678 DAC A, B, G, H (16 bits). the reference output and GND for reference stability. N = the DAC resolution. Individual channel power-down is not supported while using RESISTOR STRING the internal reference. The resistor string section is shown in Figure 46. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. C | Page 20 of 28 05299-005 05299-006 AD5678 Table 7. Command Definitions OUTPUT AMPLIFIER Command The output buffer amplifier can generate rail-to-rail voltages on C3 C2 C1 C0 Description its output, which gives an output range of 0 V to VDD. The 0 0 0 0 Write to Input Register n amplifier is capable of driving a load of 2 kΩ in parallel with 0 0 0 1 Update DAC Register n 1,000 pF to GND. The source and sink capabilities of the output 0 0 1 0 Write to Input Register n, update all amplifier can be seen in Figure 24 and Figure 25. The slew rate (software LDAC) is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs. 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC SERIAL INTERFACE 0 1 0 1 Load clear code register The AD5678 has a 3-wire serial interface ( , SCLK, and SYNC 0 1 1 0 Load LDAC register DIN) that is compatible with SPI, QSPI, and MICROWIRE 0 1 1 1 Reset (power-on reset) interface standards as well as most DSPs. See Figure 2 for a 1 0 0 0 Set up internal REF register timing diagram of a typical write sequence. 1 0 0 1 Reserved – – – – Reserved The write sequence begins by bringing the SYNC line low. Data 1 1 1 1 Reserved from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5678 compatible with high speed Table 8. Address Commands nd DSPs. On the 32 falling clock edge, the last data bit is clocked Address (n) Selected DAC in and the programmed function is executed, that is, a change A3 A2 A1 A0 Channel in DAC register contents and/or a change in the mode of 0 0 0 0 DAC A (16 bits) operation. At this stage, the line can be kept low or be SYNC 0 0 0 1 DAC B (16 bits) brought high. In either case, it must be brought high for a 0 0 1 0 DAC C (12 bits) minimum of 15 ns before the next write sequence so that a 0 0 1 1 DAC D (12 bits) falling edge of SYNC can initiate the next write sequence. 0 1 0 0 DAC E (12 bits) Because the buffer draws more current when V = 2 V SYNC IN 0 1 0 1 DAC F (12 bits) than it does when VIN = 0.8 V, SYNC should be idled low 0 1 1 0 DAC G (16 bits) between write sequences for even lower power operation of the 0 1 1 1 DAC H (16 bits) part. As is mentioned previously, however, SYNC must be 1 1 1 1 All DACs brought high again just before the next write sequence. Rev. C | Page 21 of 28 AD5678 INTERRUPT SYNC INPUT SHIFT REGISTER In a normal write sequence, the SYNC line is kept low for The input shift register is 32 bits wide. The first four bits are nd don’t cares. The next four bits are the command bits, C3 to C0 32 falling edges of SCLK, and the DAC is updated on the 32 (see Table 7), followed by the 4-bit DAC address bits, A3 to A0 falling edge and rising edge of . However, if is SYNC SYNC nd (see Table 8), and finally the 16-/12-bit data-word. The data- brought high before the 32 falling edge, this acts as an word comprises the 16-/12-bit input code followed by four or interrupt to the write sequence. The shift register is reset, and eight don’t care bits for the AD5678 DAC A, B, G, H and the write sequence is seen as invalid. Neither an update of the AD5678 DAC C, D, E, F, respectively (See Figure 47 and DAC register contents nor a change in the operating mode Figure 48). These data bits are transferred to the DAC register occurs—see Figure 49. nd on the 32 falling edge of SCLK. DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 47. AD5678 Input Register Content for DAC A, B, G , H DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX XXXX X DATA BITS COMMAND BITS ADDRESS BITS Figure 48. AD5678 Input Register Content for DAC C, D, E, F SCLK SYNC DB31 DB0 DB31 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES SYNC HIGH BEFORE 32ND FALLING EDGE ON THE 32ND FALLING EDGE SYNC Figure 49. Interrupt Facility Rev. C | Page 22 of 28 05299-009 05299-008 05299-007 AD5678 the part is in power-down mode. There are three different INTERNAL REFERENCE REGISTER options. The output is connected internally to GND through The on-board reference is off at power-up by default. This either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited allows the use of an external reference if the application requires (three-state). The output stage is illustrated in Figure 50. it. The on-board reference can be turned on/off by a user- programmable internal REF register by setting Bit DB0 high or The bias generator of the selected DAC(s), output amplifier, low (see Table 9). Command 1000 is reserved for this internal resistor string, and other associated linear circuitry are shut REF set-up command (see Table 7). Table 11 shows the state of down when the power-down mode is activated. However, the the bits in the input shift register corresponds to the mode of contents of the DAC register are unaffected when in power- operation of the device. down. The time to exit power-down is typically 5 μs for V = 5 V and for V = 3 V, see Figure 33. DD DD POWER-ON RESET Any combination of DACs can be powered up by setting PD1 The AD5678 contains a power-on reset circuit that controls the and PD0 to 0 (normal operation). The output powers up to the output voltage during power-up. The AD5678 output powers up value in the input register (LDAC low) or to the value in the to 0 V, and the output remains powered up at this level until a DAC register before powering down ( high). LDAC valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the CLEAR CODE REGISTER output of the DAC while it is in the process of powering up. The AD5678 has a hardware pin that is an asynchronous There is also a software executable reset function that resets the CLR DAC to the power-on reset code. Command 0111 is reserved clear input. The CLR input is falling edge sensitive . Bringing for this reset function—see Table 7. Any events on or LDAC the line low clears the contents of the input register and the CLR CLR during power-on reset are ignored. DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly. This POWER-DOWN MODES function can be used in system calibration to load zero scale, The AD5678 contains four separate modes of operation. midscale, or full scale to all channels together. These clear code Command 0100 is reserved for the power-down function. See values are user-programmable by setting two bits, Bit DB1 and Bit Table 7. These modes are software-programmable by setting DB0, in the CLR control register. See Table 13. The default two bits, Bit DB9 and Bit DB8, in the control register. setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register, see Table 7. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC H to nd The part exits clear code mode on the 32 falling edge of the DAC A) can be powered down to the selected mode by setting next write to the part. If CLR is activated during a write the corresponding eight bits (DB7 to DB0) to 1. See Table 12 for sequence, the write is aborted. the contents of the input shift register during power-down/power- up operation. When using the internal reference, only all channel The pulse activation time—the falling edge of to when CLR CLR power-down to the selected modes is supported. the output starts to change—is typically 280 ns. However, if the value is outside the linear region, it typically takes 520 ns after When both bits are set to 0, the part works normally with its executing CLR for the output to start changing. See Figure 43. normal power consumption of 1.3 mA at 5 V. However, for the three power-down modes, the supply current falls to 400 nA at See Table 14 for contents of the input shift register during the 5 V (200 nA at 3 V). Not only does the supply current fall, but loading clear code register operation. the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while Rev. C | Page 23 of 28 AD5678 Table 9. Internal Reference Register Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0 X 1 0 0 0 X X X X X 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Internal REF register Table 11. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 12. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Power- Power-down/power-up channel selection—set bit to 1 to select cares don’t cares cares down mode V FB AMPLIFIER V OUT RESISTOR STRING DAC POWER-DOWN RESISTOR CIRCUITRY NETWORK Figure 50. Output Stage During Power-Down Table 13. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation Table 14. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X CR1 CR0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register Rev. C | Page 24 of 28 05299-010 AD5678 FUNCTION POWER SUPPLY BYPASSING AND GROUNDING LDAC When accuracy is important in a circuit, it is helpful to carefully The outputs of all DACs can be updated simultaneously using consider the power supply and ground return layout on the the hardware LDAC pin. board. The printed circuit board containing the AD5678 should Synchronous : After new data is read, the DAC registers LDAC have separate analog and digital sections. If the AD5678 is in a nd system where other devices require an AGND-to-DGND are updated on the falling edge of the 32 SCLK pulse. LDAC connection, the connection should be made at one point only. can be permanently low or pulsed as in Figure 2. This ground point should be as close as possible to the AD5678. Asynchronous : The outputs are not updated at the same LDAC The power supply to the AD5678 should be bypassed with 10 μF time that the input registers are written to. When LDAC goes low, and 0.1 μF capacitors. The capacitors should physically be as the DAC registers are updated with the contents of the input register. close as possible to the device, with the 0.1 μF capacitor ideally Alternatively, the outputs of all DACs can be updated simulta- right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective neously using the software LDAC function by writing to Input series resistance (ESR) and low effective series inductance (ESI), Register n and updating all DAC registers. Command 0011 is such as is typical of common ceramic types of capacitors. This reserved for this software function. LDAC 0.1 μF capacitor provides a low impedance path to ground for An LDAC register gives the user extra flexibility and control high frequencies caused by transient currents due to internal over the hardware pin. This register allows the user to logic switching. LDAC select which combination of channels to simultaneously update The power supply line should have as large a trace as possible to when the hardware LDAC pin is executed. Setting the LDAC bit provide a low impedance path and reduce glitch effects on the register to 0 for a DAC channel means that this channel’s update supply line. Clocks and other fast switching digital signals should is controlled by the pin. If this bit is set to 1, this channel LDAC be shielded from other parts of the board by digital ground. Avoid updates synchronously; that is, the DAC register is updated crossover of digital and analog signals if possible. When traces after new data is read, regardless of the state of the LDAC pin. It cross on opposite sides of the board, ensure that they run at right effectively sees the LDAC pin as being tied low. (See Table 15 angles to each other to reduce feedthrough effects through the for the LDAC register mode of operation.) This flexibility is board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground useful in applications where the user wants to simultaneously plane only and the signal traces are placed on the solder side. update select channels while the rest of the channels are However, this is not always possible with a 2-layer board. synchronously updating. Writing to the DAC using command 0110 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC pin. See Table 16 for the contents of the input shift register during the load LDAC register mode of operation. Table 15. Register LDAC Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation 0 1/0 Determined by LDAC pin 1 X—don’t care DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0. Table 16. 32-Bit Input Shift Register Contents for LDAC Overwrite Function MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Setting LDAC bit to 1 overrides LDAC pin cares don’t cares cares Rev. C | Page 25 of 28 AD5678 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 51. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Package Power-On Internal 1 Model Temperature Range Package Description Option Reset to Code Accuracy Reference AD5678BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±16 LSB INL 1.25 V AD5678BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±16 LSB INL 1.25 V AD5678BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5678BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5678ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V AD5678ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V 1 Z = RoHS Compliant Part. Rev. C | Page 26 of 28 061908-A AD5678 NOTES Rev. C | Page 27 of 28 AD5678 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05299–0–2/11(C) Rev. C | Page 28 of 28