ANALOG DEVICES AD5664

2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output, ® Quad, 12-/16-Bit nanoDACs AD5624/AD5664 FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF Low power, quad nanoDACs AD5624/AD5664 AD5664: 16 bits AD5624: 12 bits INPUT DAC STRING V A BUFFER OUT REGISTER REGISTER DAC A Relative accuracy: ±12 LSBs max SCLK Guaranteed monotonic by design INPUT DAC STRING BUFFER V B INTERFACE OUT REGISTER REGISTER DAC B LOGIC 10-lead MSOP and 3 mm × 3 mm LFCSP_WD SYNC INPUT DAC STRING 2.7 V to 5.5 V power supply BUFFER V C OUT REGISTER REGISTER DAC C DIN Power-on reset to zero INPUT DAC STRING Per channel power-down BUFFER V D OUT REGISTER REGISTER DAC D Serial interface, up to 50 MHz POWER-ON POWER-DOWN RESET LOGIC APPLICATIONS Figure 1. Process control Table 1. Related Devices Data acquisition systems Part No. Description Portable battery-powered instruments AD5624R/AD5644R/AD5664R 2.7 V to 5.5 V quad, 12-, 14-, Digital gain and offset adjustment 16-bit DACs with internal Programmable voltage and current sources reference Programmable attenuators GENERAL DESCRIPTION The AD5624/AD5664, members of the nanoDAC family, are The AD5624/AD5664 use a versatile 3-wire serial interface that low power, quad, 12-, 16-bit buffered voltage-out DACs that operates at clock rates up to 50 MHz, and are compatible with operate from a single 2.7 V to 5.5 V supply and are guaranteed standard SPI®, QSPI™, MICROWIRE™, and DSP interface monotonic by design. standards. PRODUCT HIGHLIGHTS The AD5624/AD5664 require an external reference voltage to set the output range of the DAC. The part incorporates a power- 1. Relative accuracy: ±12 LSBs maximum. on reset circuit that ensures the DAC output powers up to 0 V 2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm, and remains there until a valid write takes place. The parts LFCSP_WD. contain a power-down feature that reduces the current 3. Low power, typically consumes 1.32 mW at 3 V and consumption of the device to 480 nA at 5 V and provides 2.25 mW at 5 V. software-selectable output loads while in power-down mode. 4. Maximum settling time of 4.5 μs (AD5624) and 7 μs The low power consumption of these parts in normal operation (AD5664). makes them ideally suited to portable battery-operated equipment. The power consumption is 2.25 mW at 5 V, going down to 2.4 μW in power-down mode. The AD5624/AD5664 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05943-001 AD5624/AD5664 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 15 Applications....................................................................................... 1 Input Shift Register .................................................................... 16 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 16 General Description ......................................................................... 1 Power-On Reset.......................................................................... 16 Product Highlights ........................................................................... 1 Software Reset............................................................................. 17 Specifications..................................................................................... 3 Power-Down Modes .................................................................. 17 AC Characteristics........................................................................ 4 LDAC Function .......................................................................... 18 Timing Characteristics ................................................................ 5 Microprocessor Interfacing....................................................... 19 Timing Diagram ........................................................................... 5 Applications..................................................................................... 20 Absolute Maximum Ratings............................................................ 6 Choosing a Reference for the AD5624/AD5664.................... 20 ESD Caution.................................................................................. 6 Using a Reference as a Power Supply for the AD5624/AD5664........................................................................ 20 Pin Configuration and Function Descriptions............................. 7 Bipolar Operation Using the AD5624/AD5664..................... 21 Typical Performance Characteristics ............................................. 8 Using AD5624/AD5664 with a Galvanically Isolated Terminology .................................................................................... 13 Interface....................................................................................... 21 Theory of Operation ...................................................................... 15 Power Supply Bypassing and Grounding................................ 21 D/A Section................................................................................. 15 Outline Dimensions....................................................................... 22 Resistor String............................................................................. 15 Ordering Guide .......................................................................... 22 Output Amplifier........................................................................ 15 REVISION HISTORY 6/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD5624/AD5664 SPECIFICATIONS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5664 Resolution 16 16 Bits Relative Accuracy ±8 ±16 ±6 ±12 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5624 Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 2 10 mV All zeroes loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.1 ±1 −0.1 ±1 % of FSR All ones loaded to DAC register Gain Error ±1.5 ±1.5 % of FSR Zero-Code Error Drift ±2 ±2 μV/°C Gain Temperature ±2.5 ±2.5 ppm of FSR/°C Coefficient DC Power Supply Rejection −100 −100 dB DAC code = midscale ; VDD ± Ratio 10% DC Crosstalk 10 10 μV Due to full-scale output change RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change 5 5 μV Due to powering down (per channel) 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 5 V DD Power-Up Time 4 4 Coming out of power-down μs mode; VDD = 5 V REFERENCE INPUTS Reference Current 170 200 170 200 μA V = V = 5.5 V REF DD Reference Input Range 0.75 VDD 0.75 VDD V Reference Input Impedance 26 26 kΩ 3 LOGIC INPUTS Input Current ±2 ±2 μA All digital inputs VINL, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V VINH, Input High Voltage 2 2 V VDD = 5 V, 3 V Pin Capacitance 3 3 pF Rev. 0 | Page 3 of 24 AD5624/AD5664 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS VDD 2.7 5.5 2.7 5.5 V 4 IDD (Normal Mode) VIH = VDD, VIL = GND VDD = 4.5 V to 5.5 V 0.45 0.9 0.45 0.9 mA V = 2.7 V to 3.6 V 0.44 0.85 0.44 0.85 mA DD I (All Power-Down V = V , V = GND DD IH DD IL 5 Modes) VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 μA VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 μA 1 Temperature range: A grade and B grade: −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. AC CHARACTERISTICS 1 VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 2, 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time AD5664 4 7 μs ¼ to ¾ scale settling to ±2 LSB AD5624 3 4.5 μs ¼ to ¾ scale settling to ±0.5 LSB Slew Rate 1.8 V/μs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dBs VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 1 nV-s Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 0.1 Hz to 10 Hz μV p-p 1 Guaranteed by design and characterization, not production tested. 2 Temperature range: −40°C to +105°C; typical at 25°C. 3 See the Terminology section. Rev. 0 | Page 4 of 24 AD5624/AD5664 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX 1 Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD 2 t1 20 ns min SCLK cycle time t 9 ns min SCLK high time 2 t 9 ns min SCLK low time 3 t 13 ns min SYNC to SCLK falling edge setup time 4 t5 5 ns min Data setup time t6 5 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t 15 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t10 0 ns min SCLK falling edge to SYNC fall ignore 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t t 10 1 t 9 SCLK t 2 t t 8 3 t 7 t 4 SYNC t 6 t 5 DB23 DB0 DIN Figure 2. Serial Write Operation Rev. 0 | Page 5 of 24 05943-002 AD5624/AD5664 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any V to GND −0.3 V to V + 0.3 V OUT DD other conditions above those indicated in the operational VREF to GND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability. Industrial (A Grade, B Grade) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (TJ max − TA)/θJA LFCSP_WD Package (4-Layer Board) θJA Thermal Impedance 61°C/W MSOP Package (4-Layer Board) θ Thermal Impedance 142°C/W JA θJC Thermal Impedance 43.7°C/W Reflow Soldering Peak Temperature Pb-Free 260°C ± 5°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD5624/AD5664 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V A 1 10 V OUT REF V B 2 AD5624/ 9 V OUT DD AD5664 GND 3 8 DIN TOP VIEW 4 7 V C (Not to Scale) SCLK OUT V D 5 6 SYNC OUT Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 3 GND Ground Reference Point for All Circuitry on the Part. 4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges th of the next 24 clocks. If SYNC is taken high before the 24 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 DIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF DD capacitor in parallel with a 0.1 μF capacitor to GND. 10 VREF Reference Voltage Input. Rev. 0 | Page 7 of 24 05943-003 AD5624/AD5664 TYPICAL PERFORMANCE CHARACTERISTICS 10 0.20 V = V = 5V DD REF V = V = 5V DD REF T = 25°C A 8 T = 25°C A 0.15 6 0.10 4 0.05 2 0 0 –2 –0.05 –4 –0.10 –6 –0.15 –8 –10 –0.20 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 7. DNL AD5624 Figure 4. INL AD5664 8 1.0 V = V = 5V DD REF T = 25°C 0.8 A 6 MAX INL V = V = 5V DD REF 0.6 4 0.4 2 0.2 MAX DNL 0 0 MIN DNL –0.2 –2 –0.4 –4 –0.6 MIN INL –6 –0.8 –8 –1.0 –40 –20 0 20 40 60 80 100 0 500 1000 1500 2000 2500 3000 3500 4000 CODE TEMPERATURE (°C) Figure 5. INL AD5624 Figure 8. INL Error and DNL Error vs. Temperature 1.0 10 V = V = 5V DD REF 0.8 T = 25°C MAX INL A 8 0.6 6 V = 5V DD 0.4 4 T = 25°C A 0.2 2 MAX DNL 0 0 MIN DNL –0.2 –2 –0.4 –4 –0.6 –6 MIN INL –0.8 –8 –1.0 –10 0 10k 20k 30k 40k 50k 60k 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 CODE V (V) REF Figure 9. INL and DNL Error vs. V REF Figure 6. DNL AD5664 Rev. 0 | Page 8 of 24 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 05943-006 05943-005 05943-004 ERROR (LSB) ERROR (LSB) DNL ERROR (LSB) 05943-009 05856-022 05943-007 AD5624/AD5664 8 1.0 6 MAX INL 0.5 T = 25°C A 4 GAIN ERROR 0 2 MAX DNL FULL-SCALE ERROR 0 –0.5 MIN DNL –2 –1.0 –4 MIN INL –1.5 –6 –8 –2.0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 V (V) V (V) DD DD Figure 10. INL and DNL Error vs. Supply Figure 13. Gain Error and Full-Scale Error vs. Supply 0 1.0 V = 5V T = 25°C DD A –0.02 0.5 ZERO-SCALE ERROR –0.04 GAIN ERROR 0 –0.06 –0.08 –0.5 –0.10 –1.0 –0.12 –0.14 –1.5 FULL-SCALE ERROR –0.16 –2.0 OFFSET ERROR –0.18 –0.20 –2.5 –40 –20 0 20 40 60 80 100 2.7 3.2 3.7 4.2 4.7 5.2 V (V) TEMPERATURE (°C) DD Figure 11. Gain Error and Full-Scale Error vs. Temperature Figure 14. Zero-Scale Error and Offset Error vs. Supply 1.5 V = 5.5V DD 6 T = 25°C A 1.0 ZERO-SCALE ERROR 5 0.5 0 4 –0.5 3 –1.0 2 –1.5 OFFSET ERROR 1 –2.0 0 –2.5 0.41 0.42 0.43 0.44 0.45 –40 –2008 20 40 600 100 I (mA) TEMPERATURE (°C) DD Figure 15. I Histogram with V = 5.5 V Figure 12. Zero-Scale Error and Offset Error vs. Temperature DD DD Rev. 0 | Page 9 of 24 ERROR (mV) ERROR (% FSR) ERROR (LSB) 05943-012 05943-011 05943-010 FREQUENCY ERROR (mV) ERROR (% FSR) 05943-017 05943-014 05943-013 AD5624/AD5664 8 V = 3.6V DD T = 25°C A 7 6 V = V = 5V DD REF T = 25°C A 5 FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ 4 AND 200pF TO GND 3 V = 909mV/DIV OUT 2 1 1 0 0.39 0.40 0.41 0.42 0.43 TIME BASE = 4µs/DIV I (mA) DD Figure 16. I Histogram with V = 3.6 V Figure 19. Full-Scale Settling Time, 5 V DD DD 0.20 V = V = 5V, 3V DAC LOADED WITH V = V = 5V DD REF DD REF ZERO SCALE – T = 25°C T = 25°C 0.15 A A SINKING CURRENT 0.10 0.05 0 V –0.05 DD 1 –0.10 MAX(C2) –0.15 420.0mV DAC LOADED WITH 2 FULL SCALE – –0.20 V OUT SOURCING CURRENT –0.25 CH1 2.0V CH2 500mV M100µs 125MS/s 8.0ns/pt –5 –4 –3 –2 –1 0 1 235 4 A CH1 1.28V I (mA) Figure 17. Headroom at Rails vs. Source and Sink Current Figure 20. Power-On Reset to 0 V 0.50 V = V = 5V DD REFIN SYNC 0.45 0.40 1 V = V = 3V DD REFIN SLCK 0.35 3 0.30 0.25 0.20 0.15 V 0.10 OUT V = 5V DD 0.05 2 T = 25°C A 0 –40 –20 0 20 40 60 80 100 CH1 5.0V CH2 500mV M400ns A CH1 1.4V TEMPERATURE (°C) CH3 5.0V Figure 18. Supply Current vs. Temperature Figure 21. Exiting Power-Down to Midscale Rev. 0 | Page 10 of 24 I (mA) DD ERROR VOLTAGE (V) FREQUENCY 05943-016 05943-018 05943-026 05943-023 05943-022 05943-021 AD5624/AD5664 16 2.538 V = V = 5V DD REF 2.537 V = V REF DD T = 25°C A T = 25°C A 2.536 5ns/SAMPLE NUMBER 14 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGE AROUND V = 3V MIDSCALE (0x8000 TO 0x7FFF) DD 2.533 12 2.532 2.531 2.530 10 2.529 2.528 2.527 V = 5V DD 8 2.526 2.525 2.524 6 2.523 2.522 4 2.521 0 50 100 150 200 250 300 350 400 450 512 01 2 3 4 5 6 781 9 0 SAMPLE NUMBER CAPACITANCE (nF) Figure 22. Digital-to-Analog Glitch Impulse (Negative) Figure 25. Settling Time vs. Capacitive Load 2.498 V = V = 5V DD REF T = 25°C A 5ns/SAMPLE NUMBER 2.497 V = V = 5V DD REF ANALOG CROSSTALK = 0.424nV T = 25°C A DAC LOADED WITH MIDSCALE 2.496 2.495 2.494 1 2.493 2.492 2.491 Y AXIS = 2µV/DIV 0 50 100 150 200 250 300 350 400 450 512 X AXIS = 4s/DIV SAMPLE NUMBER Figure 23. Analog Crosstalk Figure 26. 0.1 Hz to 10 Hz Output Noise Plot –20 800 V = 5V V = V = 5V DD DD REF T = 25°C T = 25°C A A –30 700 DAC LOADED WITH FULL SCALE V = 2V ± 0.3V p-p REF –40 600 –50 500 –60 400 –70 300 –80 200 –90 100 –100 0 2k 4k 6k 8k 10k 10 100 1k 10k 100k 1M (Hz) FREQUENCY (Hz) Figure 24. Total Harmonic Distortion Figure 27. Noise Spectral Density Rev. 0 | Page 11 of 24 (dB) V (V) V (V) OUT OUT 05943-027 05943-025 05943-024 OUTPUT NOISE (nV/√Hz) TIME (µs) 05943-029 05943-030 05943-028 AD5624/AD5664 5 V = 5V DD T = 25°C A 0 –5 –10 –15 –20 –25 –30 –35 –40 10k 100k 1M 10M FREQUENCY (Hz) Figure 28. Multiplying Bandwidth Rev. 0 | Page 12 of 24 (dB) 05943-031 AD5624/AD5664 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) DC Power Supply Rejection Ratio (PSRR) For the DAC, relative accuracy or integral nonlinearity is a This indicates how the output of the DAC is affected by changes measurement of the maximum deviation, in LSBs, from a in the supply voltage. PSRR is the ratio of the change in VOUT to straight line passing through the endpoints of the DAC transfer a change in VDD for full-scale output of the DAC. It is measured function. A typical INL vs. code plot can be seen in Figure 4 in dB. VREF is held at 2 V, and VDD is varied by ±10%. and Figure 5. Output Voltage Settling Time Differential Nonlinearity (DNL) This is the amount of time it takes for the output of a DAC to Differential nonlinearity is the difference between the measured settle to a specified level for a ¼ to ¾ full-scale input change th change and the ideal 1 LSB change between any two adjacent and is measured from the 24 falling edge of SCLK. codes. A specified differential nonlinearity of ±1 LSB maximum Digital-to-Analog Glitch Impulse ensures monotonicity. This DAC is guaranteed monotonic by Digital-to-analog glitch impulse is the impulse injected into the design. A typical DNL vs. code plot can be seen in Figure 6 and analog output when the input code in the DAC register changes Figure 7. state. It is normally specified as the area of the glitch in nV-s, Zero-Scale Error and is measured when the digital input code is changed by Zero-scale error is a measurement of the output error when 1 LSB at the major carry transition (0x7FFF to 0x8000) as shown in Figure 22. zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in Digital Feedthrough the AD5624/AD5664 because the output of the DAC cannot go Digital feedthrough is a measure of the impulse injected into below 0 V. It is due to a combination of the offset errors in the the analog output of the DAC from the digital inputs of the DAC and the output amplifier. Zero-code error is expressed in DAC, but is measured when the DAC output is not updated. It mV. A plot of zero-code error vs. temperature can be seen in is specified in nV-s, and measured with a full-scale code change Figure 12. on the data bus, that is, from all 0s to all 1s and vice versa. Full-Scale Error Total Harmonic Distortion (THD) Full-scale error is a measurement of the output error when full- This is the difference between an ideal sine wave and its scale code (0xFFFF) is loaded to the DAC register. Ideally, the attenuated version using the DAC. The sine wave is used as the output should be VDD − 1 LSB. Full-scale error is expressed in % reference for the DAC, and the THD is a measurement of the of FSR. A plot of full-scale error vs. temperature can be seen in harmonics present on the DAC output. It is measured in dB. Figure 11. Noise Spectral Density Gain Error This is a measurement of the internally generated random This is a measure of the span error of the DAC. It is the noise. Random noise is characterized as a spectral density deviation in slope of the DAC transfer characteristic from ideal (nV/√Hz). It is measured by loading the DAC to midscale and expressed as a % of FSR. measuring noise at the output. It is measured in nV/√Hz. A plot Zero-Code Error Drift of noise spectral density can be seen in Figure 27. This is a measurement of the change in zero-code error with a DC Crosstalk change in temperature. It is expressed in μV/°C. DC crosstalk is the dc change in the output level of one DAC in Gain Temperature Coefficient response to a change in the output of another DAC. It is This is a measurement of the change in gain error with changes measured with a full-scale output change on one DAC (or soft in temperature. It is expressed in ppm of FSR/°C. power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. Offset Error DC crosstalk due to load current change is a measure of the Offset error is a measure of the difference between VOUT (actual) impact that a change in load current on one DAC has to and VOUT (ideal) expressed in mV in the linear region of the another DAC kept at midscale. It is expressed in μV/mA. transfer function. Offset error is measured on the AD5624/ AD5664 with code 512 loaded in the DAC register. It can be negative or positive. Rev. 0 | Page 13 of 24 AD5624/AD5664 Digital Crosstalk DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all due to a digital code change and subsequent analog output 1s and vice versa) in the input register of another DAC. It is change of another DAC. It is measured by loading the attack measured in standalone mode and is expressed in nV-s. channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while Analog Crosstalk monitoring the output of the victim channel that is at midscale. This is the glitch impulse transferred to the output of one DAC The energy of the glitch is expressed in nV-s. due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change Multiplying Bandwidth (all 0s to all 1s and vice versa). Then execute a software LDAC The amplifiers within the DAC have a finite bandwidth. The and monitor the output of the DAC whose digital code was multiplying bandwidth is a measure of this. A sine wave on the not changed. The area of the glitch is expressed in nV-s (see reference (with full-scale code loaded to the DAC) appears on Figure 23). the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. 0 | Page 14 of 24 AD5624/AD5664 THEORY OF OPERATION D/A SECTION R The AD5624/AD5664 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output R buffer amplifier. Figure 29 shows a block diagram of the DAC architecture. TO OUTPUT R AMPLIFIER V DD OUTPUT AMPLIFIER (GAIN = +2) REF (+) DAC RESISTOR V OUT REGISTER STRING REF (–) R GND Figure 29. DAC Architecture R Since the input coding to the DAC is straight binary, the ideal Figure 30. Resistor String output voltage is given by SERIAL INTERFACE D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN N The AD5624/AD5664 have a 3-wire serial interface (SYNC, ⎝ 2 ⎠ SCLK, and DIN) that is compatible with SPI, QSPI, and where: MICROWIRE interface standards as well as with most DSPs. D is the decimal equivalent of the binary code that is loaded to See Figure 2 for a timing diagram of a typical write sequence. the DAC register: The write sequence begins by bringing the line low. Data SYNC 0 to 4095 for AD5624 (12 bit). from the DIN line is clocked into the 24-bit shift register on the 0 to 65535 for AD5664 (16 bit). falling edge of SCLK. The serial clock frequency can be as high N is the DAC resolution. as 50 MHz, making the AD5624/AD5664 compatible with high th speed DSPs. On the 24 falling clock edge, the last data bit is RESISTOR STRING clocked in and the programmed function is executed, that is, a The resistor string is shown in Figure 30. It is simply a string of change in DAC register contents and/or a change in the mode resistors, each of value R. The code loaded to the DAC register of operation. At this stage, the SYNC line can be kept low or be determines at which node on the string the voltage is tapped off brought high. In either case, it must be brought high for a to be fed into the output amplifier. The voltage is tapped off by minimum of 15 ns before the next write sequence so that a closing one of the switches connecting the string to the falling edge of can initiate the next write sequence. Since SYNC amplifier. Because it is a string of resistors, it is guaranteed the SYNC buffer draws more current when VIN = 2.0 V than it monotonic. does when V = 0.8 V, should be idled low between IN SYNC OUTPUT AMPLIFIER write sequences for even lower power operation. It must, however, be brought high again just before the next write The output buffer amplifier can generate rail-to-rail voltages on sequence. its output, which gives an output range of 0 V to VDD. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 17. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale settling time of 7 μs. Rev. 0 | Page 15 of 24 05943-032 05943-033 AD5624/AD5664 INPUT SHIFT REGISTER SYNC INTERRUPT The input shift register is 24 bits wide The first two bits are In a normal write sequence, the SYNC line is kept low for at least th don’t care bits. The next three bits are the Command bits, C2 to 24 falling edges of SCLK, and the DAC is updated on the 24 th C0 (see Table 7), followed by the 3-bit DAC address, A2 to A0 falling edge. However, if is brought high before the 24 SYNC (see Table 8), and then the 16-, 12-bit data-word. The data-word falling edge, then this acts as an interrupt to the write sequence. comprises the 16-, 12- bit input code followed by 0 or 4 don’t The input shift register is reset and the write sequence is seen as care bits for the AD5664 and AD5624 respectively (see Figure invalid. Neither an update of the DAC register contents nor a 31 and Figure 32). These data bits are transferred to the DAC change in the operating mode occurs (see Figure 33). th register on the 24 falling edge of SCLK. POWER-ON RESET Table 7. Command Definition The AD5624/AD5664 family contains a power-on reset circuit C2 C1 C0 Command that controls the output voltage during power-up. The AD5624/ 0 0 0 Write to input register n AD5664 DAC outputs power up to 0 V and the output remains 0 0 1 Update DAC register n there until a valid write sequence is made to the DAC. This is 0 1 0 Write to input register n, update all (software LDAC) useful in applications where it is important to know the state of 0 1 1 Write to and update DAC channel n the output of the DAC while it is in the process of powering up. 1 0 0 Power down DAC (power-up) 1 0 1 Reset 1 1 0 Load LDAC register 1 1 1 Reserved Table 8. Address Command A2 A1 A0 ADDRESS (n) 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 1 1 All DACs DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS COMMAND BITS ADDRESS BITS Figure 31. AD5664 Input Shift Register Contents DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX X DATA BITS COMMAND BITS ADDRESS BITS Figure 32. AD5624 Input Shift Register Contents SCLK SYNC DB23 DB0 DB23 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH SYNC HIGH BEFORE 24 FALLING EDGE ON THE 24 FALLING EDGE Figure 33. SYNC Interrupt Facility Rev. 0 | Page 16 of 24 05943-035 05943-034 05943-036 AD5624/AD5664 Table 10. Modes of Operation for the AD5624/AD5664 SOFTWARE RESET DB5 DB4 Operating Mode The AD5624/AD5664 contain a software reset function. 0 0 Normal operation Command 110 is reserved for the software reset function (see Power-down modes Table 7). The software reset command contains two reset modes 0 1 1 kΩ to GND that are software programmable by setting Bit DB0 in the 1 0 100 kΩ to GND control register. Table 9 shows how the state of the bit 1 1 Three-state corresponds to the software reset modes of operation of the devices. When both bits are set to 0, the parts work normally with their Table 9. Software Reset Modes for the AD5624/AD5664 normal power consumption of 450 μA at 5 V. However, for the DB0 Registers Reset to Zero three power-down modes, the supply current falls to 480 nA at 0 DAC register 5 V (200 nA at 3 V). Not only does the supply current fall, but Input shift register the output stage is also internally switched from the output of 1 (Power-On Reset) DAC register the amplifier to a resistor network of known values. This allows Input shift register the output impedance of the part to be known while the part is LDAC register in power-down mode. Power-down register The outputs can either be connected internally to GND through a 1 kΩ or 100 kΩ resistor, or left open-circuited (three-state) POWER-DOWN MODES (see Figure 34). The AD5624/AD5664 contain four separate modes of operation. Command 100 is reserved for the power-down function (see Table 7). These modes are software programmable by setting two RESISTOR AMPLIFIER V OUT STRING DAC bits (DB5 and DB4) in the control register. Table 10 shows how the state of the bits corresponds to the mode of operation of the device. All DACs (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, POWER-DOWN RESISTOR CIRCUITRY NETWORK DB2, DB1, and DB0) to 1. By executing the same Command 100, any combination of DACs is powered up by setting Bit DB5 and Bit DB4 to normal operation mode. To select which combination Figure 34. Output Stage During Power-Down of DAC channels to power-up, set the corresponding four bits The bias generator, the output amplifier, the resistor string, and (DB3, DB2, DB1, and DB0) to 1. See Table 11 for contents of the other associated linear circuitry are shut down when power- input shift register during the power-down/power-up operation. down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V (see Figure 21). Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation DB23 to DB15 DB0 DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 to DB6 DB5 DB4 DB3 DB2 DB1 (LSB) x 1 0 0 x x x x PD1 PD0 DAC D DAC C DAC B DAC A Don’t care Command bits (C2 to C0) Address bits (A2 to A0); don’t Don’t Power- Power-down/power-up channel care care down mode selection, set bit to 1 to select channel Rev. 0 | Page 17 of 24 05943-037 AD5624/AD5664 DAC registers. When the LDAC bit register is set high, LDAC FUNCTION however, the DAC registers become transparent and the The AD5624/AD5664 DACs have double-buffered interfaces contents of the input registers are transferred to them on the consisting of two banks of registers: input registers and DAC th falling edge of the 24 SCLK pulse. This is equivalent to having registers. The input registers are connected directly to the input an LDAC hardware pin tied permanently low for the selected shift register and the digital code is transferred to the relevant DAC channel, that is, synchronous update mode. See Table 12 input register on completion of a valid write sequence. The for the LDAC register mode of operation. See Table 13 for DAC registers contain the digital code used by the resistor contents of the input shift register during the LDAC register set- strings. up command. The double-buffered interface is useful if the user requires This flexibility is useful in applications where the user wants to simultaneous updating of all DAC outputs. The user can write update select channels simultaneously, while the rest of the to three of the input registers individually and then write to the channels update synchronously. remaining input register and update all DAC registers, the outputs update simultaneously. Command 010 is reserved for this software LDAC. Table 12. LDAC Register Mode of Operation Load DAC Register Access to the DAC registers is controlled by the LDAC LDAC Bits function. The LDAC registers contain two modes of operation (DB3 to DB0) LDAC Mode of Operation for each DAC channel. The DAC channels are selected by 0 Normal operation (default), DAC register setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and update is controlled by write command. DB0). Command 110 is reserved for setting up the LDAC 1 The DAC registers are updated after new register. When the LDAC bit register is set low, the data is read in on the falling edge of the th corresponding DAC registers are latched and the input 24 SCLK pulse. registers can change state without affecting the contents of the Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664 DB23 to DB22 DB15 to DB0 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB4 DB3 DB2 DB1 (LSB) x 1 1 0 x x x x DacD DacC DacB DacA Don’t Care Command bits (C2 to C0) Address bits (A3 to A0); don’t care Don’t Set bit to 0 or 1 for required mode of cares operation on respective channel Rev. 0 | Page 18 of 24 AD5624/AD5664 AD5624/AD5664 to 80C51/80L51 Interface MICROPROCESSOR INTERFACING AD5624/AD5664 to Blackfin® ADSP-BF53x Interface Figure 37 shows a serial interface between the AD5624/AD5664 and the 80C51/80L51 microcontroller. The setup for the interface Figure 35 shows a serial interface between the AD5624/AD5664 and is as follows. TxD of the 80C51/80L51 drives SCLK of the the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x AD5624/AD5664, while RxD drives the serial data line of the processor family incorporates two dual-channel synchronous serial part. The SYNC signal is derived from a bit-programmable pin ports, SPORT1 and SPORT0, for serial and multiprocessor commu- nications. Using SPORT0 to connect to the AD5624/AD5664, the on the port. In this case, port line P3.3 is used. When data is setup for the interface is as follows. DTOPRI drives the DIN pin of transmitted to the AD5624/AD5664, P3.3 is taken low. The the AD5624/AD5664, while TSCLK0 drives the SCLK of the part. 80C51/80L51 transmits data in 10-bit bytes only; thus only eight The SYNC is driven from TFS0. falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and 1 AD5624/ ADSP-BF53x a second write cycle is initiated to transmit the second byte of 1 AD5664 data. P3.3 is taken high following the completion of this cycle. TFS0 SYNC The 80C51/80L51 output the serial data in a format that has the DTOPRI DIN LSB first. The AD5624/AD5664 must receive data with the MSB TSCLK0 SCLK first. The 80C51/80L51 transmit routine should take this into account. 1 ADDITIONAL PINS OMITTED FOR CLARITY. 1 Figure 35. Blackfin ADSP-BF53x Interface to AD5624/AD5664 AD5624/ 80C51/80L51 1 AD5664 AD5624/AD5664 to 68HC11/68L11 Interface P3.3 SYNC Figure 36 shows a serial interface between the AD5624/AD5664 TxD SCLK and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ RxD DIN 68L11 drives the SCLK of the AD5624/AD5664, while the MOSI output drives the serial data line of the DAC. 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. 80C51/80L51 Interface to AD5624/AD5664 The SYNC signal is derived from a port line (PC7). The setup AD5624/AD5664 to MICROWIRE Interface conditions for correct operation of this interface are as follows. Figure 38 shows an interface between the AD5624/AD5664 and The 68HC11/68L11 is configured with its CPOL bit as a 0 and any MICROWIRE-compatible device. Serial data is shifted out its CPHA bit as a 1. When data is being transmitted to the DAC, on the falling edge of the serial clock and is clocked into the the SYNC line is taken low (PC7). When the 68HC11/68L11 is AD5624/AD5664 on the rising edge of the SK. configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 1 AD5624/ MICROWIRE 1 68HC11/68L11 is transmitted in 10-bit bytes with only eight AD5664 falling clock edges occurring in the transmit cycle. Data is CS SYNC transmitted MSB first. To load data to the AD5624/AD5664, SK SCLK PC7 is left low after the first eight bits are transferred, and a SO DIN second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. 1 ADDITIONAL PINS OMITTED FOR CLARITY. 1 Figure 38. MICROWIRE Interface to AD5624/AD5664 AD5624/ 68HC11/68L11 1 AD5664 PC7 SYNC SCK SCLK MOSI DIN 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. 68HC11/68L11 Interface to AD5624/AD5664 Rev. 0 | Page 19 of 24 05943-038 05943-039 05943-041 05943-040 AD5624/AD5664 APPLICATIONS CHOOSING A REFERENCE FOR THE USING A REFERENCE AS A POWER SUPPLY FOR AD5624/AD5664 THE AD5624/AD5664 To achieve the optimum performance from the AD5624/ Because the supply current required by the AD5624/AD5664 is AD5664, thought should be given to the choice of a precision extremely low, an alternative option is to use a voltage reference voltage reference. The AD5624/AD5664 have only one to supply the required voltage to the part (see Figure 39). This is reference input, V . The voltage on the reference input is used especially useful if the power supply is quite noisy, or if the REF to supply the positive input to the DAC. Therefore, any error in system supply voltages are at some value other than 5 V or 3 V, the reference is reflected in the DAC. for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5624/AD5664 (see Table 14 for a suitable When choosing a voltage reference for high accuracy applica- reference). If the low dropout REF195 is used, it must supply tions, the sources of error are initial accuracy, ppm drift, long- 450 μA of current to the AD5624/AD5664, with no load on the term drift, and output voltage noise. Initial accuracy on the output of the DAC. When the DAC output is loaded, the output voltage of the DAC leads to a full-scale error in the DAC. REF195 also needs to supply the current to the load. The total To minimize these errors, a reference with high initial accuracy current required (with a 5 kΩ load on the DAC output) is is preferred. Choosing a reference with an output trim 450 μA + (5 V/5 kΩ) = 1.45 mA adjustment, such as the ADR423, allows a system designer to trim out system errors by setting a reference voltage to a voltage The load regulation of the REF195 is typically 2 ppm/mA, other than the nominal. The trim adjustment can also be used which results in a 2.9 ppm (14.5 μV) error for the 1.45 mA at temperature to trim out any error. current drawn from it. This corresponds to a 0.191 LSB error. 15V Long-term drift is a measurement of how much the reference drifts over time. A reference with a tight long-term drift 5V REF195 500mA specification ensures that the overall solution remains relatively stable during its entire lifetime. V V DD REF SYNC 3-WIRE The temperature coefficient of a reference’s output voltage AD5624/ V = 0V TO 5V OUT SERIAL SCLK AD5664 INTERFACE affects INL, DNL, and TUE. A reference with a tight temperature DIN coefficient specification should be chosen to reduce temperature dependence of the DAC output voltage in ambient conditions. Figure 39. REF195 as Power Supply to the AD5624/AD5664 In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references such as the ADR425 produce low output noise in the 0.1 Hz to10 Hz range. Examples of recom- mended precision references for use as supply to the AD5624/AD5664 are shown in the Table 14. Table 14. Partial List of Precision References for Use with the AD5624/AD5664 o Part No. Initial Accuracy (mV max) Temp Drift (ppm C max) 0.1 Hz to 10 Hz Noise (μV p-p typ) V (V) OUT ADR425±2 3 3.4 5 ADR395±6 25 5 5 REF195±2 5 50 5 AD780±2 3 4 2.5/3 ADR423±2 3 3.4 3 Rev. 0 | Page 20 of 24 05943-042 AD5624/AD5664 5V BIPOLAR OPERATION USING THE REGULATOR 10µF 0.1µF POWER AD5624/AD5664 The AD5624/AD5664 have been designed for single-supply operation, but a bipolar output range is also possible using the V DD circuit in Figure 40. The circuit gives an output voltage range of SCLK VOA V1A SCLK ±5 V. Rail-to-rail operation at the amplifier output is achievable AD5624/ ADuM1300 using an AD820 or an OP295 as the output amplifier. AD5664 V SDI V1B VOB SYNC OUT The output voltage for any input code can be calculated as follows: VOC DATA V1C DIN GND ⎡ ⎤ ⎛ D ⎞ R1+ R2 R2 ⎛ ⎞ ⎛ ⎞ V V = × ⎜ ⎟× −V × ⎜ ⎟ ⎜ ⎟ O ⎢ DD DD ⎥ 65,536 ⎝ R1 ⎠ ⎝ R1 ⎠ ⎝ ⎠ ⎣ ⎦ Figure 41. AD5624/AD5664 with a Galvanically Isolated Interface where D represents the input code in decimal (0 to 65536). POWER SUPPLY BYPASSING AND GROUNDING With V = 5 V, R1 = R2 = 10 kΩ, DD When accuracy is important in a circuit, it is helpful to consider ⎛ 10× D ⎞ carefully the power supply and ground return layout on the V = ⎜ ⎟ − 5 V O 65,536 ⎝ ⎠ board. The printed circuit board containing the AD5624/ AD5664 should have separate analog and digital sections, each This is an output voltage range of ±5 V, with 0x0000 corre- having its own area of the board. If the AD5624/AD5664 is in a sponding to a −5 V output, and 0xFFFF corresponding to a system where other devices require an AGND-to-DGND +5 V output. connection, the connection should be made at one point only. R2 = 10kΩ This ground point should be as close as possible to the AD5624/AD5664. +5V +5V R1 = 10kΩ The power supply to the AD5624/AD5664 should be bypassed AD820/ ±5V OP295 with 10 μF and 0.1 μF capacitors. The capacitors should be V V DD OUT located as close as possible to the device, with the 0.1 μF capacitor 10µF 0.1µF AD5624/ –5V ideally right up against the device. The 10 μF capacitor is the AD5664 tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and effective series 3-WIRE inductance (ESI), for example, common ceramic types of SERIAL INTERFACE capacitors. This 0.1 μF capacitor provides a low impedance path Figure 40. Bipolar Operation with the AD5624/AD5664 to ground for high frequencies caused by transient currents due to internal logic switching. USING AD5624/AD5664 WITH A The power supply line itself should have as large a trace as GALVANICALLY ISOLATED INTERFACE possible to provide a low impedance path and to reduce glitch In process control applications in industrial environments, it is effects on the supply line. Clocks and other fast switching often necessary to use a galvanically isolated interface to protect digital signals should be shielded from other parts of the board and isolate the controlling circuitry from any hazardous by digital ground. Avoid crossover of digital and analog signals common-mode voltages that might occur in the area where the if possible. When traces cross on opposite sides of the board, DAC is functioning. Isocouplers provide isolation in excess of ensure that they run at right angles to each other to reduce 3 kV. The AD5624/AD5664 use a 3-wire serial logic interface, feedthrough effects through the board. The best board layout so the ADuM130x 3-channel digital isolator provides the technique is the microstrip technique where the component required isolation (see Figure 41). The power supply to the part side of the board is dedicated to the ground plane only and the also needs to be isolated, which is done by using a transformer. signal traces are placed on the solder side. However, this is not On the DAC side of the transformer, a 5 V regulator provides always possible with a 2-layer board. the 5 V supply required for the AD5624/AD5664. Rev. 0 | Page 21 of 24 05943-043 05943-044 AD5624/AD5664 OUTLINE DIMENSIONS INDEX AREA 3.00 PIN 1 BSC SQ INDICATOR 10 1 1.50 BCS SQ 0.50 2.48 EXPOSED BSC 2.38 PAD TOP VIEW (BOTTOM VIEW) 2.23 6 5 0.50 1.74 0.40 1.64 0.80 MAX 0.30 0.80 1.49 0.55 TYP 0.75 0.05 MAX SIDE VIEW 0.70 0.02 NOM SEATING 0.30 0.20 REF PLANE 0.23 0.18 Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.17 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 43. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Package Package Model Temperature Range Accuracy Description Option Branding AD5624BRMZ −40°C to +105°C ±1 LSB INL 10-Lead MSOP RM-10 D5J AD5624BRMZ-REEL7 −40°C to +105°C ±1 LSB INL 10-Lead MSOP RM-10 D5J AD5624BCPZ-250RL7 −40°C to +105°C ±1 LSB INL 10-Lead LFCSP_WD CP-10-9 D5J AD5624BCPZ-REEL7 −40°C to +105°C ±1 LSB INL 10-Lead LFCSP_WD CP-10-9 D5J AD5664ARMZ −40°C to +105°C ±16 LSB INL 10-Lead MSOP RM-10 D7C AD5664ARMZ-REEL7 −40°C to +105°C ±16 LSB INL 10-Lead MSOP RM-10 D7C AD5664BRMZ −40°C to +105°C ±12 LSB INL 10-Lead MSOP RM-10 D78 AD5664BRMZ-REEL7 −40°C to +105°C ±12 LSB INL 10-Lead MSOP RM-10 D78 AD5664BCPZ-250RL7 −40°C to +105°C ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D78 AD5664BCPZ-REEL7 −40°C to +105°C ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D78 Rev. 0 | Page 22 of 24 AD5624/AD5664 NOTES Rev. 0 | Page 23 of 24 AD5624/AD5664 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05943-0-6/06(0) Rev. 0 | Page 24 of 24