ANALOG DEVICES AD5663

2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output, ® Dual 16-Bit nanoDAC AD5663 FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD REF Low power, dual 16-bit nanoDAC Relative accuracy: ±12 LSBs maximum LDAC Guaranteed monotonic by design INPUT DAC STRING SCLK BUFFER V A OUT REGISTER REGISTER DAC A 10-lead MSOP and 3 mm × 3 mm LFCSP_WD INTERFACE SYNC LOGIC 2.7 V to 5.5 V power supply INPUT DAC STRING BUFFER V B OUT DIN REGISTER REGISTER DAC B Per channel power-down Power-on reset to zero scale or midscale AD5663 LDAC CLR Hardware and functions POWER-ON POWER-DOWN RESET LOGIC Serial interface; up to 50 MHz LDAC CLR GND Figure 1. APPLICATIONS Process control Data acquisition systems Table 1. Related Devices Portable battery-powered instruments Part No. Description Digital gain and offset adjustment AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-/14-/16-bit Programmable voltage and current sources DACs with internal reference Programmable attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. Dual 16-bit DAC; relative accuracy of ±12 LSBs maximum. The AD5663, a member of the nanoDAC family, is a low power, dual, 16-bit buffered voltage-out DAC that operates from a single 2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm 2.7 V to 5.5 V supply and is guaranteed monotonic by design. LFCSP_WD packages. The AD5663 requires an external reference voltage to set the 3. Low power; typically consumes 0.6 mW at 3 V and output range of the DAC. The part incorporates a power-on 1.25 mW at 5 V. reset circuit that ensures the DAC output powers up to 0 V or 4. 7 μs maximum settling time. midscale (AD5663-1) and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. The power consumption is 1.25 mW at 5 V, going down to 2.4 μW in power-down mode. The on-chip precision output amplifier of the AD5663 allows rail-to-rail output swing to be achieved. The AD5663 uses a versatile, 3-wire serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05855-001 AD5663 TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier........................................................................ 14 Applications....................................................................................... 1 Serial Interface ............................................................................ 14 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 14 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 15 Product Highlights ........................................................................... 1 Power-On Reset.......................................................................... 15 Revision History ............................................................................... 2 Software Reset............................................................................. 15 Specifications..................................................................................... 3 Power-Down Modes .................................................................. 16 AC Characteristics........................................................................ 4 LDAC Function .......................................................................... 16 Timing Characteristics ................................................................ 5 Microprocessor Interfacing....................................................... 18 Timing Diagram ........................................................................... 5 Applications..................................................................................... 19 Absolute Maximum Ratings............................................................ 6 Choosing a Reference for the AD5663.................................... 19 ESD Caution.................................................................................. 6 Using a Reference as a Power Supply for the AD5663 .......... 19 Pin Configuration and Function Description .............................. 7 Bipolar Operation Using the AD5663 ..................................... 20 Typical Performance Characteristics ............................................. 8 Using the AD5663 with a Galvanically Isolated Interface .... 20 Terminology .................................................................................... 12 Power Supply Bypassing and Grounding................................ 20 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 21 D/A Section................................................................................. 14 Ordering Guide .......................................................................... 21 Resistor String............................................................................. 14 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD5663 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5663 Resolution 16 16 Bits Relative Accuracy ±8 ±16 ±6 ±12 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.15 ±1 −0.15 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 ±1.5 % of FSR 3 Zero-Scale Error Drift ±2 ±2 μV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale, VDD ± 10% DC Crosstalk 10 10 μV Due to full-scale output change RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change 5 5 μV Due to powering down (per channel) 2 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS Reference Current 170 200 170 200 μA VREF = VDD = 5.5 V, 3.6 V Reference Input Range 0.75 V 0.75 V V DD DD Reference Input Impedance 26 26 kΩ 3 LOGIC INPUTS Input Current ±2 ±2 μA All digital inputs V , Input Low Voltage 0.8 0.8 V V = 5 V, 3 V INL DD V , Input High Voltage 2 2 V V = 5 V, 3 V INH DD Pin Capacitance 3 3 pF DIN, SCLK, and SYNC 19 19 pF LDAC and CLR POWER REQUIREMENTS VDD 2.7 5.5 2.7 5.5 V 4 IDD (Normal Mode) VIH = VDD and VIL = GND V = 4.5 V to 5.5 V 250 450 250 450 μA DD V = 2.7 V to 3.6 V 200 425 200 425 μA DD I (All Power-Down V = V , V = GND DD IH DD IL 5 Modes) VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 μA VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 μA 1 Temperature range: A grade and B grade are both equal to −40°C to +105°C. 2 Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. Rev. 0 | Page 3 of 24 AD5663 AC CHARACTERISTICS 1 VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 4 7 μs 1/4 to 3/4 scale settling to ±2 LSB Slew Rate 1.8 V/μs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dBs V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 1 nV-s Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p; frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 0.1 Hz to 10 Hz μV p-p 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. Rev. 0 | Page 4 of 24 AD5663 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 1 VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments 2 t 20 ns min SCLK cycle time 1 t2 9 ns min SCLK high time t3 9 ns min SCLK low time SYNC to SCLK falling edge setup time t4 13 ns min t 5 ns min Data setup time 5 t6 5 ns min Data hold time t 0 ns min SCLK falling edge to SYNC rising edge 7 t 15 ns min Minimum SYNC high time 8 SYNC rising edge to SCLK fall ignore t9 13 ns min t10 0 ns min SCLK falling edge to SYNC fall ignore LDAC pulse width low t11 10 ns min t 15 ns min SCLK falling edge to LDAC rising edge 12 t 5 ns min CLR pulse width low 13 LDAC falling edge t14 0 ns min SCLK falling edge to CLR pulse activation time t15 300 ns max 1 Guaranteed by design and characterization; not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t 10 t 1 t 9 SCLK t 2 t 8 t t 7 t 3 4 SYNC t 6 t 5 DIN DB23 DB0 t 11 t 14 1 LDAC t 12 2 LDAC t 13 CLR t V 15 OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. 0 | Page 5 of 24 05855-002 AD5663 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any V to GND −0.3 V to V + 0.3 V OUT DD other conditions above those indicated in the operational VREF to GND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability. Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (Tmax) 150°C J Power Dissipation (TJ max − TA)/θJA LFCSP_WD Package (4-Layer Board) θJA Thermal Impedance 61°C/W MSOP Package (4-Layer Board) θ Thermal Impedance 142°C/W JA θJC Thermal Impedance 43.7°C/W Reflow Soldering Peak Temperature Pb-Free 260(+0/−5)°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD5663 PIN CONFIGURATION AND FUNCTION DESCRIPTION V A 1 10 V OUT REF 2 9 V B V OUT DD AD5663 GND 3 8 DIN TOP VIEW (Not to Scale) 4 7 LDAC SCLK CLR 5 6 SYNC Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 3 GND Ground Reference Point for All Circuitry on the Part. 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 5 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device. 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 10 VREF Reference Voltage Input. Rev. 0 | Page 7 of 24 05855-003 AD5663 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 8 MAX INL V = V = 5V DD REF 8 T = 25°C A 6 V = 5V DD 6 4 T = 25°C A 4 2 MAX DNL 2 0 0 MIN DNL –2 –2 –4 –4 –6 MIN INL –6 –8 –8 –10 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 –10 V (V) REF 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE Figure 4. INL Figure 7. INL and DNL Error vs. VREF 8 1.0 MAX INL V = V = 5V 6 DD REF 0.8 T = 25°C A T = 25°C A 4 0.6 0.4 2 MAX DNL 0.2 0 0 MIN DNL –2 –0.2 –4 –0.4 MIN INL –0.6 –6 –0.8 –8 2.7 3.2 3.7 4.2 4.7 5.2 –1.0 V (V) 0 10k 20k 30k 40k 50k 60k DD CODE Figure 5. DNL Figure 8. INL and DNL Error vs. Supply 8 0 V = 5V DD 6 MAX INL –0.02 V = V = 5V DD REF –0.04 4 GAIN ERROR –0.06 2 –0.08 MAX DNL 0 –0.10 MIN DNL –2 –0.12 –4 –0.14 FULL-SCALE ERROR MIN INL –0.16 –6 –0.18 –8 –0.20 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. INL Error and DNL Error vs. Temperature Figure 9. Gain Error and Full-Scale Error vs. Temperature Rev. 0 | Page 8 of 24 ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 05855-006 05855-005 05855-004 ERROR (% FSR) ERROR (LSB) ERROR (LSB) 05855-009 05855-008 05855-007 AD5663 1.5 V = 5.5V DD T = 25°C A 8 1.0 ZERO-SCALE ERROR 0.5 6 0 –0.5 4 –1.0 2 –1.5 OFFSET ERROR –2.0 0 –2.5 0.230 0.235 0.240 0.245 0.250 0.255 –40 –2008 20 40 600 100 I (mA) DD TEMPERATURE (°C) Figure 10. Zero-Scale and Offset Error vs. Temperature Figure 13. IDD Histogram with VDD = 5.5 V 0.20 1.0 DAC LOADED WITH V = V = 5V, 3V DD REF T = 25°C ZERO SCALE – 0.15 A SINKING CURRENT 0.5 0.10 GAIN ERROR 0.05 0 0 FULL-SCALE ERROR –0.5 –0.05 –0.10 –1.0 –0.15 DAC LOADED WITH –1.5 FULL SCALE – –0.20 SOURCING CURRENT –0.25 –2.0 –5 –4 –3 –2 –1 0 1 235 4 2.7 3.2 3.7 4.2 4.7 5.2 I (mA) V (V) DD Figure 11. Gain Error and Full-Scale Error vs. Supply Figure 14. Headroom at Rails vs. Source and Sink Current 0.30 1.0 T = 25°C T = 25°C A A V = V = 5V DD REFIN 0.25 0.5 ZERO-SCALE ERROR 0 0.20 V = V = 3V DD REFIN –0.5 0.15 –1.0 0.10 –1.5 0.05 –2.0 OFFSET ERROR 0 –2.5 –40 –20 0 20 40 60 80 100 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) V (V) DD Figure 12. Zero-Scale and Offset Error vs. Supply Figure 15. Supply Current vs. Temperature Rev. 0 | Page 9 of 24 ERROR (mV) ERROR (% FSR) ERROR (mV) 05855-012 05855-011 05855-010 I (mA) DD NUMBER OF UNITS ERROR VOLTAGE (V) 05855-014 05858-090 05855-044 AD5663 2.538 V = V = 5V DD REF 2.537 T = 25°C A 2.536 5ns/SAMPLE NUMBER 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 2.533 2.532 V = V = 5V DD REF 2.531 T = 25°C A 2.530 FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF 2.529 OUTPUT LOADED WITH 2kΩ 2.528 AND 200pF TO GND 2.527 2.526 2.525 V = 909mV/DIV OUT 2.524 2.523 1 2.522 2.521 0 50 100 150 200 250 300 350 400 450 512 SAMPLE NUMBER TIME BASE = 4µs/DIV Figure 16. Full-Scale Settling Time, 5 V Figure 19. Digital-to-Analog Glitch Impulse (Negative) 2.498 V = V = 5V DD REF V = V = 5V T = 25°C A DD REF T = 25°C 5ns/SAMPLE NUMBER 2.497 A ANALOG CROSSTALK = 0.424nV 2.496 2.495 2.494 V DD 1 2.493 MAX(C2)* 420.0mV 2.492 2 V OUT 2.491 0 50 100 150 200 250 300 350 400 450 512 CH1 2.0V CH2 500mV M100µs 125MS/s 8.0ns/pt SAMPLE NUMBER A CH1 1.28V Figure 17. Power-On Reset to 0 V Figure 20. Analog Crosstalk –20 V = 5V DD SYNC T = 25°C A –30 DAC LOADED WITH FULL SCALE V = 2V ± 0.3V p-p REF 1 –40 SLCK 3 –50 –60 –70 –80 V OUT V = 5V DD –90 2 –100 2k 4k 6k 8k 10k CH1 5.0V CH2 500mV M400ns A CH1 1.4V FREQUENCY (Hz) CH3 5.0V Figure 18. Exiting Power-Down to Midscale Figure 21. Total Harmonic Distortion Rev. 0 | Page 10 of 24 05855-021 05855-020 05855-019 (dB) V (V) V (V) OUT OUT 05855-025 05855-059 05855-058 AD5663 16 5 V = 5V DD V = V REF DD T = 25°C A T = 25°C 0 A 14 –5 V = 3V DD –10 12 –15 10 –20 V = 5V DD –25 8 –30 6 –35 4 –40 01 2 3 4 5 6781 9 0 10k 100k 1M 10M CAPACITANCE (nF) FREQUENCY (Hz) Figure 22. Settling Time vs. Capacitive Load Figure 25. Multiplying Bandwidth V = V = 5V DD REF T = 25°C CLR A 3 DAC LOADED WITH MIDSCALE V A OUT 1 V B OUT 4 4 Y AXIS = 2µV/DIV 2 X AXIS = 4s/DIV CH2 1.0V M200ns A CH3 1.10V CH3 5.0V CH4 1.0V Figure 23. 0.1 Hz to 10 Hz Output Noise Plot CLR Figure 26. Pulse Activation Time 800 V = V = 5V DD REF T = 25°C A 700 600 500 400 300 200 100 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 24. Noise Spectral Density Rev. 0 | Page 11 of 24 OUTPUT NOISE (nV/ Hz) TIME (µs) 05855-027 05855-028 05855-026 (dB) 05855-050 05855-029 AD5663 TERMINOLOGY Output Voltage Settling Time Relative Accuracy or Integral Nonlinearity (INL) Output voltage settling time is the amount of time it takes for the For the DAC, relative accuracy or integral nonlinearity is a output of a DAC to settle to a specified level for a 1/4 to 3/4 full- measurement of the maximum deviation, in LSBs, from a scale input change and is measured from the 24th falling edge of straight line passing through the endpoints of the DAC transfer SCLK. function. A typical INL vs. code plot is shown in Figure 4. Digital-to-Analog Glitch Impulse Differential Nonlinearity (DNL) Digital-to-analog glitch impulse is the impulse injected into the Differential nonlinearity is the difference between the measured analog output when the input code in the DAC register changes change and the ideal 1 LSB change between any two adjacent state. It is normally specified as the area of the glitch in nV-s, codes. A specified differential nonlinearity of ±1 LSB maximum and is measured when the digital input code is changed by ensures monotonicity. This DAC is guaranteed monotonic by 1 LSB at the major carry transition (0x7FFF to 0x8000). See design. A typical DNL vs. code plot is shown in Figure 5. Figure 19. Zero-Scale Error Digital Feedthrough Zero-scale error is a measurement of the output error when Digital feedthrough is a measure of the impulse injected into zero code (0x0000) is loaded to the DAC register. Ideally, the the analog output of the DAC from the digital inputs of the output should be 0 V. The zero-scale error is always positive in DAC, but it is measured when the DAC output is not updated. the AD5663 because the output of the DAC cannot go below It is specified in nV-s and measured with a full-scale code change 0 V. It is due to a combination of the offset errors in the DAC on the data bus, that is, from all 0s to all 1s and vice versa. and the output amplifier. Zero-scale error is expressed in mV. A plot of zero-scale error vs. temperature is shown in Figure 10. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal Full-Scale Error sine wave and its attenuated version using the DAC. The sine Full-scale error is a measurement of the output error when full- wave is used as the reference for the DAC, and the THD is a scale code (0xFFFF) is loaded to the DAC register. Ideally, the measurement of the harmonics present on the DAC output. output should be VDD − 1 LSB. Full-scale error is expressed in It is measured in dB. percent of full-scale range. A plot of full-scale error vs. tempera- ture is shown in Figure 9. Noise Spectral Density Noise spectral density is a measurement of the internally Gain Error generated random noise. Random noise is characterized as a Gain error is a measure of the span error of the DAC. It is the spectral density (voltage per √Hz). It is measured by loading the deviation in slope of the DAC transfer characteristic from ideal DAC to midscale and measuring noise at the output. It is expressed as a percent of the full-scale range. measured in nV/√Hz. Figure 24 shows a plot of noise spectral Zero-Scale Error Drift density. Zero-scale error drift is a measurement of the change in zero- DC Crosstalk scale error with a change in temperature. It is expressed in μV/°C. DC crosstalk is the dc change in the output level of one DAC in Gain Temperature Coefficient response to a change in the output of another DAC. It is measured Gain temperature coefficient is a measurement of the change in with a full-scale output change on one DAC (or soft power-down gain error with changes in temperature. It is expressed in (ppm and power-up) while monitoring another DAC kept at midscale. of full-scale range)/°C. It is expressed in μV. DC crosstalk due to load current change is a measure of the Offset Error impact that a change in load current on one DAC has to another Offset error is a measure of the difference between VOUT (actual) DAC kept at midscale. It is expressed in μV/mA. and VOUT (ideal) expressed in mV in the linear region of the trans- fer function. Offset error is measured on the AD5663 with Digital Crosstalk Code 512 loaded in the DAC register. It can be negative or Digital crosstalk is the glitch impulse transferred to the output positive. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DC Power Supply Rejection Ratio (PSRR) DAC. It is measured in standalone mode and is expressed PSRR indicates how the output of the DAC is affected by changes in nV-s. in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. V is held at 2 V, and V is varied by ±10%. REF DD Rev. 0 | Page 12 of 24 AD5663 Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC due to a change in the output of another DAC. It is multiplying bandwidth is a measure of this. A sine wave on the measured by loading one of the input registers with a full-scale reference (with full-scale code loaded to the DAC) appears on code change (all 0s to all 1s and vice versa) while keeping the output. The multiplying bandwidth is the frequency at LDAC high. Then pulse LDAC low and monitor the output of which the output amplitude falls to 3 dB below the input. the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Rev. 0 | Page 13 of 24 AD5663 THEORY OF OPERATION D/A SECTION OUTPUT AMPLIFIER The AD5663 DAC is fabricated on a CMOS process. The The output buffer amplifier can generate rail-to-rail voltages on architecture consists of a string DAC followed by an output its output, which gives an output range of 0 V to V . It can drive DD buffer amplifier. Figure 27 shows a block diagram of the DAC a load of 2 kΩ in parallel with 1000 pF to GND. architecture. The source and sink capabilities of the output amplifier can be V DD OUTPUT seen in Figure 14. The slew rate is 1.8 V/μs with a 1/4 to 3/4 AMPLIFIER (GAIN = +2) full-scale settling time of 10 μs. REF (+) DAC RESISTOR V OUT REGISTER STRING SERIAL INTERFACE REF (–) The AD5663 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE GND interface standards, as well as with most DSPs. See Figure 2 for Figure 27. DAC Architecture a timing diagram of a typical write sequence. Because the input coding to the DAC is straight binary, the ideal SYNC The write sequence begins by bringing the line low. Data output voltage is given by from the DIN line is clocked into the 24-bit shift register on the ⎛ D ⎞ falling edge of SCLK. The serial clock frequency can be as high V = V × ⎜ ⎟ OUT REF as 50 MHz, making the AD5663 compatible with high speed 65,536 ⎝ ⎠ DSPs. On the 24th falling clock edge, the last data bit is clocked where D is the decimal equivalent of the binary code that is in and the programmed function is executed; that is, there is a loaded to the DAC register. It can range from 0 to 65,535. change in DAC register contents and/or a change in the mode SYNC of operation. At this stage, the line can be kept low or be RESISTOR STRING brought high. In either case, it must be brought high for a mini- The resistor string section is shown in Figure 28. It is a string of mum of 15 ns before the next write sequence so that a falling edge resistors, each of Value R. The code loaded to the DAC register SYNC SYNC of can initiate the next write sequence. Because the determines at which node on the string the voltage is tapped off buffer draws more current when VIN = 2.0 V than it does when to be fed into the output amplifier. The voltage is tapped off by V = 0.10 V, SYNC should be idled low between write sequences IN closing one of the switches connecting the string to the amplifier. for even lower power operation. As mentioned previously, Because it is a string of resistors, it is guaranteed monotonic. however, it must be brought high again just before the next write sequence. R INPUT SHIFT REGISTER R The input shift register is 24 bits wide (see Figure 29). The first two bits are don’t cares. The next three are the Command Bit C2 TO OUTPUT to Command Bit C0 (see Table 7), followed by the 3-bit DAC R AMPLIFIER Address A2 to DAC Address A0 (see Table 8), and, finally, the 16-bit data-word. These are transferred to the DAC register on the 24th falling edge of SCLK. Table 7. Command Definition R C2 C1 C0 Command 0 0 0 Write to input register n 0 0 1 Update DAC register n R 0 1 0 Write to input register n, update all (software LDAC) Figure 28. Resistor String 0 1 1 Write to and update DAC channel n 1 0 0 Power down DAC (power up) 1 0 1 Reset 1 1 0 LDAC register setup 1 1 1 Reserved Rev. 0 | Page 14 of 24 05855-033 05855-032 AD5663 Table 8. Address Command SOFTWARE RESET A2 A1 A0 ADDRESS (n) The AD5663 contains a software reset function. Command 101 0 0 0 DAC A is reserved for the software reset function (see Table 7). The 0 0 1 DAC B software reset command contains two reset modes that are 0 1 0 Reserved software-programmable by setting Bit DB0 in the control 0 1 1 Reserved register. 1 1 1 All DACs Table 9 shows how the state of the bit corresponds to the mode SYNC INTERRUPT of operation of the device. Table 10 shows the contents of the input shift register during the software reset mode of operation. SYNC In a normal write sequence, the line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the Table 9. Software Reset Modes for the AD5663 24th falling edge. However, if SYNC is brought high before the DB0 Registers Reset to 0 24th falling edge, this acts as an interrupt to the write sequence. 0 DAC register The shift register is reset and the write sequence is seen as Input register invalid. Neither an update of the DAC register contents nor a 1 (Power-On Reset) DAC register change in the operating mode occurs (see Figure 30). Input register LDAC register POWER-ON RESET Power-down register The AD5663 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5663 DAC outputs power up to 0 V, the AD5663-1 powers up to midscale, and the output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. Any events on LDAC or CLR during power-on reset are ignored. Table 10. 24-Bit Input Shift Register Contents for Software Reset Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 x 1 0 1 x x x x 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS COMMAND BITS ADDRESS BITS Figure 29. Input Register Contents SCLK SYNC DB23 DB0 DB23 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH SYNC HIGH BEFORE 24 FALLING EDGE ON THE 24 FALLING EDGE Figure 30. SYNC Interrupt Facility Rev. 0 | Page 15 of 24 05855-034 05855-035 AD5663 The time required to exit power-down is typically 4 μs for POWER-DOWN MODES V = 5 V and for V = 3 V (see Figure 18). DD DD The AD5663 contains four separate modes of operation. Table 11. Power-Down Modes of Operation for the AD5663 Command 100 is reserved for the power-down function DB5 DB4 Operating Mode (see Table 7). These modes are software-programmable by 0 0 Normal operation setting Bit DB5 and Bit DB4 in the control register. Table 11 Power-Down Modes shows how the state of the bits corresponds to the mode of 0 1 1 kΩ to GND operation of the device. Any or all DACs (DAC B and DAC A) 1 0 100 kΩ to GND can be powered down to the selected mode by setting the 1 1 Three-state corresponding two bits (Bit DB1 and Bit DB0) to 1. By executing the same Command 100, any combination of DACs can be powered up by setting Bit DB5 and Bit DB4 to normal LDAC FUNCTION operation mode. Again, to select which combination of DAC The AD5663 DAC has double-buffered interfaces consisting of channels to power up, set the corresponding two bits (Bit DB1 two banks of registers: input registers and DAC registers. The and Bit DB0) to 1. See Table 12 for contents of the input shift input registers are connected directly to the input shift register register during power-down/power-up operation. and the digital code is transferred to the relevant input register The DAC output powers up to the value in the input register on completion of a valid write sequence. The DAC registers while LDAC is low. If LDAC is high, the DAC output powers up contain the digital code used by the resistor strings. to the value held in the DAC register before power-down. LDAC pin. Access to the DAC registers is controlled by the When both bits are set to 0, the part works normally with its LDAC When the pin is high, the DAC registers are latched and normal power consumption of 500 μA at 5 V. However, for the the input registers can change state without affecting the three power-down modes, the supply current falls to 480 nA at LDAC contents of the DAC registers. When is brought low, 5 V (100 nA at 3 V). Not only does the supply current fall, but however, the DAC registers become transparent and the the output stage is also internally switched from the output of contents of the input registers are transferred to them. The the amplifier to a resistor network of known values. This has the double-buffered interface is useful if the user requires advantage that the output impedance of the part is known while simultaneous updating of all DAC outputs. The user can write the part is in power-down mode. The outputs can either be to one of the input registers individually and then, by bringing connected internally to GND through a 1 kΩ or 100 kΩ register LDAC low when writing to the other DAC input register, all or left open-circuited (three-state) (see Figure 31). outputs update simultaneously. These parts each contain an extra feature whereby a DAC register is not updated unless its input register has been RESISTOR AMPLIFIER V OUT STRING DAC updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5663, POWER-DOWN the DAC register updates only if the input register has changed RESISTOR CIRCUITRY NETWORK since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Figure 31. Output Stage During Power-Down The outputs of all DACs can be updated simultaneously using The bias generator, the output amplifier, the resistor string, and the hardware LDAC pin. other associated linear circuitry are shut down when power- down mode is activated. However, the contents of the DAC register are unaffected when in power-down. Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function MSB LSB DB23 to DB15 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x 1 0 0 x x x x PD1 PD0 x x DAC B DAC A Don’t Command bits (C2 to C0) Address bits (A2 to A0); Don’t Power-down Don’t care Power down/Power up care care mode channel selection; don’t care set bit to 1 to select channel Rev. 0 | Page 16 of 24 05855-036 AD5663 This flexibility is useful in applications where the user wants to LDAC Synchronous : The DAC registers are updated after new simultaneously update select channels while the rest of the data is read in on the falling edge of the 24th SCLK pulse. channels are synchronously updating LDAC can be permanently low or pulsed, as shown in Figure 2. Writing to the DAC using Command 110 loads the 2-bit LDAC Asynchronous LDAC: The outputs are not updated at the same register [DB1:DB0]. The default for each channel is 0; that is, time that the input registers are written to. When LDAC goes the LDAC pin works normally. Setting the bits to 1 means the low, the DAC registers are updated with the contents of the DAC register is updated regardless of the state of the LDAC pin. input register. See Table 14 for contents of the input shift register during the LDAC LDAC register setup command. The register gives the user full flexibility and control LDAC over the hardware pin. This register allows the user to LDAC Table 13. Register Mode of Operation select which combination of channels to simultaneously update LDAC Bits LDAC LDAC when the hardware pin is executed. Setting the bit LDAC Pin LDAC Operation (DB1 to DB0) register to 0 for a DAC channel means that the update of this 0 1/0 Determined by LDAC pin channel is controlled by the LDAC pin. If this bit is set to 1, this 1 x = don’t care The DAC registers are updated channel synchronously updates; that is, the DAC register is after new data is read in on the updated after new data is read in, regardless of the state of the falling edge of the 24th SCLK LDAC LDAC pin. It effectively sees the pin as being pulled low. pulse LDAC See Table 13 for the register mode of operation. Table 14. 24-Bit Input Shift Register Contents for LDAC Register Setup Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0 x 1 1 0 x x x x DAC B DAC A Set DAC to 0 or 1 for required mode of Don’t care Command bits (C2 to C0) Address bits (A3 to A0); Don’t care operation Don’t care Rev. 0 | Page 17 of 24 AD5663 1 1 68HC11/68L11 AD5663 MICROPROCESSOR INTERFACING PC7 SYNC AD5663 to Blackfin® ADSP BF53x Interface SCK SCLK Figure 32 shows a serial interface between the AD5663 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor MOSI DIN family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor 1 ADDITIONAL PINS OMITTED FOR CLARITY. communications. Using SPORT0 to connect to the AD5663, the Figure 33. AD5663 to 68HC11/68L11 Interface setup for the interface is as follows: AD5663 to 80C51/80L51 Interface • DT0PRI drives the DIN pin of the AD5663. Figure 34 shows a serial interface between the AD5663 and the 80C51/80L51 microcontroller. The setup for the interface is as • TSCLK0 drives the SCLK of the part. follows: SYNC • The pin is driven from TFS0. • TxD of the 80C51/80L51 drives SCLK of the AD5663. 1 1 ADSP-BF53x AD5663 • RxD drives the serial data line of the part. TFS0 SYNC SYNC The signal is again derived from a bit-programmable pin DTOPRI DIN on the port. In this case, Port Line P3.3 is used. When data is to be TSCLK0 SCLK transmitted to the AD5663, P3.3 is taken low. The 80C51/80L51 transmits data in 10-bit bytes only; thus only eight falling clock 1 ADDITIONAL PINS OMITTED FOR CLARITY. edges occur in the transmit cycle. To load data to the DAC, P3.3 Figure 32. AD5663 to Blackfin ADSP-BF53x Interface is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 AD5663 to 68HC11/68L11 Interface is taken high following the completion of this cycle. The 80C51/ Figure 33 shows a serial interface between the AD5663 and the 80L51 outputs the serial data in a format that has the LSB first. 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 The AD5663 must receive data with the MSB first. The 80C51/ drives the SCLK of the AD5663, and the MOSI output drives 80L51 transmit routine should take this into account. the serial data line of the DAC. 1 1 80C51/80L51 AD5663 The SYNC signal is derived from a port line (PC7). The setup P3.3 SYNC conditions for correct operation of this interface are as follows: TxD SCLK • The 68HC11/68L11 is configured with its CPOL bit as 0. RxD DIN • The 68HC11/68L11 is configured with its CPHA bit as 1. 1 ADDITIONAL PINS OMITTED FOR CLARITY. SYNC line is When data is being transmitted to the DAC, the Figure 34. AD5663 to 80C51/80L51 Interface taken low (PC7). When the 68HC11/68L11 is configured as AD5663 to MICROWIRE Interface previously described, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the Figure 35 shows an interface between the AD5663 and any 68HC11/68L11 is transmitted in 10-bit bytes with only eight MICROWIRE-compatible device. Serial data is shifted out on falling clock edges occurring in the transmit cycle. Data is the falling edge of the serial clock and is clocked into the AD5663 transmitted MSB first. To load data to the AD5663, PC7 is left on the rising edge of the SK. low after the first eight bits are transferred, and a second serial 1 1 MICROWIRE AD5663 write operation is performed to the DAC. PC7 is taken high at the end of this procedure. CS SYNC SK SCLK SO DIN 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5663 to MICROWIRE Interface Rev. 0 | Page 18 of 24 05855-037 05855-040 05855-039 05855-038 AD5663 APPLICATIONS CHOOSING A REFERENCE FOR THE AD5663 USING A REFERENCE AS A POWER SUPPLY FOR THE AD5663 To achieve the optimum performance from the AD5663, thought should be given to the choice of a precision voltage Because the supply current required by the AD5663 is extremely reference. The AD5663 has only one reference input, V . REF low, an alternative option is to use a voltage reference to supply The voltage on the reference input is used to supply the positive the required voltage to the part (see Figure 36). This is especially input to the DAC. Therefore, any error in the reference is useful if the power supply is quite noisy, or if the system supply reflected in the DAC. voltages are at some value other than 5 V or 3 V (for example, 15 V). The voltage reference outputs a steady supply voltage for When choosing a voltage reference for high accuracy applica- the AD5663; see Table 15 for a suitable reference. If the low drop- tions, the sources of error are initial accuracy, ppm drift, long- out REF195 is used, it must supply 250 μA of current to the term drift, and output voltage noise. Initial accuracy on the AD5663, with no load on the output of the DAC. When the output voltage of the DAC leads to a full-scale error in the DAC output is loaded, the REF195 also needs to supply the DAC. To minimize these errors, a reference with high initial current to the load. The total current required (with a 5 kΩ accuracy is preferred. Also, choosing a reference with an output load on the DAC output) is trim adjustment, such as the ADR423, allows a system designer to trim system errors out by setting a reference voltage to a 250 μA + (5 V/5 kΩ) = 1.25 mA voltage other than the nominal. The trim adjustment can also The load regulation of the REF195 is typically 2 ppm/mA, be used at temperature to trim out any error. which results in a 2.5 ppm (12.5 μV) error for the 1.25 mA Long-term drift is a measurement of how much the reference current drawn from it. This corresponds to a 0.164 LSB error. drifts over time. A reference with a tight long-term drift specifi- 15V cation ensures that the overall solution remains relatively stable 5V REF195 during its entire lifetime. 500µA The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature SYNC V V DD REF V = 0V TO 5V THREE-WIRE OUT coefficient specification should be chosen to reduce temperature SERIAL SCLK AD5663 INTERFACE DIN dependence of the DAC output voltage in ambient conditions. In high accuracy applications, which have a relatively low noise Figure 36. REF195 as Power Supply to the AD5663 budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references, such as the ADR425, produce low output noise in the 0.1 Hz to 10 Hz range. Examples of recom- mended precision references for use as supplies to the AD5663 are shown in the Table 15. Table 15. Partial List of Precision References for Use with the AD5663 o Part No. Initial Accuracy (mV Max) Temperature Drift (ppm C Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ) V (V) OUT ADR425 ±2 3 3.4 5 ADR395±6 25 5 5 REF195 ±2 5 50 5 AD780±2 3 4 2.5/3 ADR423 ±2 3 3.4 3 Rev. 0 | Page 19 of 24 05855-041 AD5663 5V BIPOLAR OPERATION USING THE AD5663 REGULATOR 10µF 0.1µF POWER The AD5663 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 37. The circuit gives an output voltage range of ±5 V. V Rail-to-rail operation at the amplifier output is achievable using DD SCLK V V SCLK IA OA an AD820 or an OP295 as the output amplifier. ADuM1300 AD5663 The output voltage for any input code can be calculated as V SDI V V SYNC OUT IB OB ⎡ ⎤ ⎛ D ⎞ R1+ R2 R2 ⎛ ⎞ ⎛ ⎞ V = V × ⎜ ⎟× −V × ⎜ ⎟ ⎜ ⎟ O ⎢ DD DD ⎥ V DATA V OC DIN IC 65,536 ⎝ R1 ⎠ ⎝ R1 ⎠ ⎝ ⎠ ⎣ ⎦ GND where D represents the input code in decimal (0 to 65,535). Figure 38. AD5663 with a Galvanically Isolated Interface With VDD = 5 V, R1 = R2 = 10 kΩ POWER SUPPLY BYPASSING AND GROUNDING 10× D ⎛ ⎞ V = ⎜ ⎟ − 5 V O When accuracy is important in a circuit, it is helpful to carefully 65,536 ⎝ ⎠ consider the power supply and ground return layout on the board. The printed circuit board containing the AD5663 should This is an output voltage range of ±5 V, with 0x0000 corre- have separate analog and digital sections, each having its own sponding to a −5 V output, and 0xFFFF corresponding to a area of the board. If the AD5663 is in a system where other +5 V output. devices require an AGND-to-DGND connection, the connection R2 = 10kΩ should be made at one point only. This ground point should be +5V as close as possible to the AD5663. +5V R1 = 10kΩ AD820/ The power supply to the AD5663 should be bypassed with 10 μF ±5V OP295 and 0.1 μF capacitors. The capacitors should be located as close V V DD OUT 10µF 0.1µF as possible to the device, with the 0.1 μF capacitor ideally right AD5663 –5V up against the device. The 10 μF capacitors are of the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and effective series inductance THREE-WIRE SERIAL (ESI) as in, for example, common ceramic types of capacitors. INTERFACE This 0.1 μF capacitor provides a low impedance path to ground Figure 37. Bipolar Operation with the AD5663 for high frequencies caused by transient currents due to internal USING THE AD5663 WITH logic switching. A GALVANICALLY ISOLATED INTERFACE The power supply line itself should have as large a trace as In process control applications in industrial environments, it possible to provide a low impedance path and to reduce glitch is often necessary to use a galvanically isolated interface to effects on the supply line. Clocks and other fast switching protect and isolate the controlling circuitry from any hazardous digital signals should be shielded from other parts of the board common-mode voltages that can occur in the area where the by digital ground. Avoid crossover of digital and analog signals DAC is functioning. iCoupler® provides isolation in excess of if possible. When traces cross on opposite sides of the board, 2.5 kV. The AD5663 use a 3-wire serial logic interface, so the ensure that they run at right angles to each other to reduce ADuM1300 three-channel digital isolator provides the required feedthrough effects through the board. The best board layout isolation (see Figure 38). The power supply to the part also technique is the microstrip technique, where the component needs to be isolated, which is done by using a transformer. On side of the board is dedicated to the ground plane only, and the the DAC side of the transformer, a 5 V regulator provides the signal traces are placed on the solder side. However, this is not 5 V supply required for the AD5663. always possible with a 2-layer board. Rev. 0 | Page 20 of 24 05855-042 05855-043 AD5663 OUTLINE DIMENSIONS INDEX AREA 3.00 PIN 1 BSC SQ INDICATOR 10 1 1.50 BCS SQ 0.50 2.48 EXPOSED BSC 2.38 PAD TOP VIEW (BOTTOM VIEW) 2.23 6 5 0.50 1.74 0.40 1.64 0.80 MAX 0.30 0.80 1.49 0.55 TYP 0.75 0.05 MAX SIDE VIEW 0.70 0.02 NOM SEATING 0.30 0.20 REF PLANE 0.23 0.18 Figure 39. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.33 0.60 SEATING 0.23 0° 0.05 PLANE 0.17 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 40. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Power-On Package Package Model Range Reset Code Accuracy Description Option Branding 1 AD5663ARMZ −40°C to +105°C Zero ±16 LSB INL 10-lead MSOP RM-10 D80 1 −40°C to +105°C Zero ±16 LSB INL 10-lead MSOP RM-10 D80 AD5663ARMZ-REEL7 1 −40°C to +105°C Zero ±12 LSB INL 10-lead MSOP RM-10 D8C AD5663BRMZ 1 −40°C to +105°C Zero ±12 LSB INL 10-lead MSOP RM-10 D8C AD5663BRMZ-REEL7 1 −40°C to +105°C Midscale ±12 LSB INL 10-lead MSOP RM-10 D7J AD5663BRMZ-1 1 AD5663BRMZ-1REEL7 −40°C to +105°C Midscale ±12 LSB INL 10-lead MSOP RM-10 D7J 1 AD5663BCPZ-250RL7 −40°C to +105°C Zero ±12 LSB INL 10-lead LFCSP_WD CP-10-9 D8C 1 −40°C to +105°C Zero ±12 LSB INL 10-lead LFCSP_WD CP-10-9 D8C AD5663BCPZ-REEL7 1 Z = Pb-free part. Rev. 0 | Page 21 of 24 AD5663 NOTES Rev. 0 | Page 22 of 24 AD5663 NOTES Rev. 0 | Page 23 of 24 AD5663 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05855-0-4/06(0) TTTT Rev. 0 | Page 24 of 24