ANALOG DEVICES AD5662

2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output TM 16-Bit nanoDAC in a SOT-23 AD5662 FEATURES FUNCTIONAL BLOCK DIAGRAM V V Low power (250 μA @ 5 V) single 16-bit nanoDAC REF GND DD 12-bit accuracy guaranteed POWER-ON Tiny 8-lead SOT-23/MSOP package AD5662 RESET V FB Power-down to 480 nA @ 5 V, 100 nA @ 3 V Power-on reset to zero scale/midscale REF(+) DAC OUTPUT V 2.7 V to 5.5 V power supply 16-BIT OUT REGISTER BUFFER DAC Guaranteed 16-bit monotonic by design 3 power-down functions Serial interface with Schmitt-triggered inputs INPUT POWER-DOWN CONTROL RESISTOR CONTROL LOGIC Rail-to-rail operation LOGIC NETWORK SYNC interrupt facility Temperature range −40°C to +125°C Qualified for automotive applications SYNC SCLK DIN APPLICATIONS Process control Figure 1. Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5662, a member of the nanoDAC family, is a low power, The AD5662 uses a versatile 3-wire serial interface that operates single, 16-bit buffered voltage-out DAC that operates from a at clock rates up to 30 MHz, and is compatible with standard single 2.7 V to 5.5 V supply and is guaranteed monotonic by SPI®, QSPI™, MICROWIRE™, and DSP interface standards. design. PRODUCT HIGHLIGHTS The AD5662 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on 1. 16-bit DAC—12-bit accuracy guaranteed. reset circuit that ensures the DAC output powers up to 0 V 2. Available in 8-lead SOT-23 and 8-lead MSOP packages. (AD5662x-1) or to midscale (AD5662x-2), and remains there until a valid write takes place. The part contains a power-down 3. Low power. Typically consumes 0.42 mW at 3 V and feature that reduces the current consumption of the device to 0.75 mW at 5 V. 480 nA at 5 V and provides software-selectable output loads while in power-down mode. 4. Power-on reset to zero scale or to midscale. The low power consumption of this part in normal operation 5. 10 μs max settling time. makes it ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V, going down to RELATED DEVICES 2.4 μW in power-down mode. Part No. Description The AD5662’s on-chip precision output amplifier allows rail-to- AD5620/AD5640/AD5660 3 V/5 V 12-/14-/16-bit DAC with rail output swing to be achieved. For remote sensing applications, internal reference in SOT-23 the output amplifier’s inverting input is available to the user. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 ©2005–2010 Analog Devices, Inc. All rights reserved. 04777-001 AD5662 TABLE OF CONTENTS Specifications..................................................................................... 3  Power-On Reset.......................................................................... 15  Timing Characteristics..................................................................... 5  Power-Down Modes .................................................................. 16  Absolute Maximum Ratings............................................................ 6  Microprocessor Interfacing ...................................................... 16  ESD Caution.................................................................................. 6  Applications..................................................................................... 18  Pin Configuration and Function Description .............................. 7  Choosing a Reference for the AD5662.................................... 18  Typical Performance Characteristics ............................................. 8  Using a Reference as a Power Supply for the AD5662 .......... 18  Terminology .................................................................................... 13  Bipolar Operation Using the AD5662..................................... 19  Theory of Operation ...................................................................... 14  Using the AD5662 as an Isolated, Programmable, 4-20 mA Process Controller...................................................................... 19  DAC Section................................................................................ 14  Using AD5662 with a Galvanically Isolated Interface........... 20  Resistor String............................................................................. 14  Power Supply Bypassing and Grounding................................ 20  Output Amplifier........................................................................ 14  Outline Dimensions ....................................................................... 21  Serial Interface ............................................................................ 14  Ordering Guide .......................................................................... 22  Input Shift Register .................................................................... 15  Automotive Products................................................................. 22  SYNC Interrupt .......................................................................... 15  REVISION HISTORY 12/10—Rev. 0 to Rev. A Changes to Features Section.............................................................1 Changes to Ordering Guide ...........................................................22 Added Automotive Products Section ...........................................22 1/05—Revision 0: Initial Version Rev. A | Page 2 of 24 AD5662 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 A Grade B Grade Y Version Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 4 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design See Figure 5 Zero Code Error 2 10 2 10 mV All 0s loaded to DAC register Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register Offset Error ±10 ±10 mV Gain Error ±1.5 ±1.5 % FSR 3 Zero Code Error Drift ±2 ±2 μV/°C 3 Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C 3 DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale; VDD = 5 V/3 V ±10% 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Output Voltage Settling Time 8 10 8 10 μs ¼ to ¾ scale change settling to ±2 LSB RL = 2 kΩ; 0 pF < CL < 200 pF Slew Rate 1.5 1.5 V/μs ¼ to ¾ scale Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L 4 Output Noise Spectral Density 100 100 nV/√Hz DAC code = midscale,10 kHz 4 Output Noise (0.1 Hz to 10 Hz) 10 10 μV p-p DAC code = midscale 4 Total Harmonic Distortion (THD) −80 −80 dB VREF = 2 V ± 300 mV p-p, f = 5 kHz Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 0.1 nV-s DC Output Impedance 0.5 0.5 Ω 4 Short-Circuit Current 30 30 mA VDD = 5 V, 3 V Power-Up Time 4 4 μs Coming out of power-down mode VDD = 5 V, 3 V 3 REFERENCE INPUT Reference Current 40 75 40 75 μA VREF = VDD = 5 V 30 50 30 50 μA VREF = VDD = 3.6 V 5 Reference Input Range 0.75 V 0.75 V V DD DD Reference Input Impedance 125 125 kΩ 3 LOGIC INPUTS Input Current ±2 ±2 μA All digital inputs V , Input Low Voltage 0.8 0.8 V V = 5 V, 3 V INL DD V , Input High Voltage 2 2 V V = 5 V, 3 V INH DD Pin Capacitance 3 3 pF Rev. A | Page 3 of 24 AD5662 1 A Grade B Grade Y Version Parameter Min Typ Max Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V DD DD I (Normal Mode) DAC active and excluding load current DD V = 4.5 V to 5.5 V 150 250 150 250 μA V = V and V = GND DD IH DD IL VDD = 2.7 V to 3.6 V 140 225 140 225 μA VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD and VIL = GND V = 2.7 V to 3.6 V 0.1 0.375 0.1 0.375 μA V = V and V = GND DD IH DD IL POWER EFFICIENCY IOUT/IDD 90 90 % ILOAD = 2 mA. VDD = 5 V 1 Temperature range is as follows: Y version: −40°C to +125°C, typical at +25°C. 2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024. 3 Guaranteed by design and characterization; not production tested. 4 Output unloaded. 5 Reference input range at ambient where ±1 LSB max DNL specification is achievable. Rev. A | Page 4 of 24 AD5662 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments 1 t 50 33 ns min SCLK cycle time 1 t 13 13 ns min SCLK high time 2 t3 13 13 ns min SCLK low time t4 13 13 ns min SYNC to SCLK falling edge setup time t5 5 5 ns min Data setup time t 4.5 4.5 ns min Data hold time 6 t 0 0 ns min SCLK falling edge to SYNC rising edge 7 t 50 33 ns min 8 Minimum SYNC high time t9 13 13 ns min SYNC rising edge to SCLK fall ignore t10 0 0 ns min SCLK falling edge to SYNC fall ignore 1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V. t 10 t 1 t 9 SCLK t 2 t 8 t t t 3 7 4 SYNC t 6 t 5 DB23 DIN DB0 Figure 2. Serial Write Operation Rev. A | Page 5 of 24 04777-002 AD5662 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating Stresses above those listed under Absolute Maximum Ratings V to GND −0.3 V to +7 V DD may cause permanent damage to the device. This is a stress V to GND −0.3 V to V + 0.3 V OUT DD rating only; functional operation of the device at these or any VFB to GND −0.3 V to VDD + 0.3 V other conditions above those listed in the operational sections VREF to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability. Industrial (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θJA SOT-23 Package (4-Layer Board) θ Thermal Impedance 119°C/W JA MSOP Package (4-Layer Board) θJA Thermal Impedance 141°C/W θJC Thermal Impedance 44°C/W Reflow Soldering Peak Temperature SnPb 240°C Pb-free 260°C ESD 2 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 AD5662 PIN CONFIGURATION AND FUNCTION DESCRIPTION V 1 8 GND DD AD5662 V 2 7 DIN REF TOP VIEW V 3 6 SCLK (Not to Scale) FB V 4 5 SYNC OUT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. 2 VREF Reference Voltage Input. 3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. 4 V Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. OUT 5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. th The DAC is updated following the 24 clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 7 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 8 GND Ground Reference Point for All Circuitry on the Part. Rev. A | Page 7 of 24 04777-003 AD5662 TYPICAL PERFORMANCE CHARACTERISTICS 10 8 V = V = 5V DD REF 8 T = 25°C A 6 MAX INL V = V = 5V DD REF 6 4 4 2 2 MAX DNL 0 0 MIN DNL –2 –2 –4 –4 –6 MIN INL –6 –8 –10 –8 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k –40 –20 0 20 40 60 80 100 120 CODE TEMPERATURE (°C) Figure 7. INL Error and DNL Error vs. Temperature Figure 4. Typical INL Plot 10 MAX INL 8 6 V = 5V DD 4 T = 25°C A 2 MAX DNL 0 MIN DNL –2 –4 –6 MIN INL –8 –10 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 V (V) REF Figure 5. Typical DNL Plot Figure 8. INL and DNL Error vs. VREF 90 8 V = V = 5V DD REF T = 25°C 80 A 6 MAX INL T = 25°C A 70 4 60 2 50 MAX DNL 0 40 MIN DNL –2 30 –4 20 MIN INL 10 –6 0 –8 511 10511 20511 30511 40511 50511 60511 2.7 3.2 3.7 4.2 4.7 5.2 CODES V (V) DD Figure 6. Typical Total Unadjusted Error Plot Figure 9. INL and DNL Error vs. Supply Rev. A | Page 8 of 24 ERROR (LSB) INL ERROR (LSB) 04777-019 04777-011 ERROR (LSB) ERROR (LSB) ERROR (LSB) 04777-041 04777-045 04777-036 AD5662 1.0 0 V = 5V T = 25°C DD A –0.22 0.5 ZERO-SCALE ERROR –0.04 GAIN ERROR 0 –0.06 –0.08 –0.5 –0.01 –1.0 –0.12 –0.14 –1.5 FULL-SCALE ERROR –0.16 –2.0 OFFSET ERROR –0.18 –0.20 –2.5 –40 –20 0 20 40 60 80 100 120 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) V (V) DD Figure 10. Gain Error and Full-Scale Error vs. Temperature Figure 13. Zero-Scale and Offset Error vs. Supply 1.5 20 V = V = 5.5V DD REF 1.0 18 T = 25°C ZERO-SCALE ERROR A 16 0.5 14 0 12 –0.5 10 –1.0 8 6 –1.5 OFFSET ERROR 4 –2.0 2 –2.5 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) I (μA) DD Figure 11. Zero-Scale and Offset Error vs. Temperature Figure 14. IDD Histogram with VDD = 5.5 V 1.0 0.20 V = V = 5V, 3V DAC LOADED WITH DD REF T = 25°C ZERO SCALE – 0.15 A 0.5 SINKING CURRENT 0.10 GAIN ERROR 0 0.05 FULL-SCALE ERROR 0 –0.5 –0.05 –1.0 –0.10 –0.15 –1.5 DAC LOADED WITH FULL SCALE – –0.20 SOURCING CURRENT –2.0 –0.25 2.7 3.2 3.7 4.2 4.7 5.2 –5 –4 –3 –2 –1 0 1 235 4 V (V) DD I (mA) Figure 12. Gain Error and Full-Scale Error vs. Supply Figure 15. Headroom at Rails vs. Source and Sink Current Rev. A | Page 9 of 24 ERROR (% FSR) ERROR (mV) ERROR (% FSR) 04777-042 04777-035 04777-038 ERROR VOLTAGE (V) NUMBER OF DEVICES ERROR (mV) 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 MORE 04777-013 04777-046 04777-039 AD5662 250 1000 T = 25°C T = 25°C V = V = 5V A A DD REF 900 V = 5V DD 200 800 700 V = V = 3V DD REF 150 600 500 100 400 300 50 200 V = 3V DD 100 0 0 512 10512 20512 30512 40512 50512 60512 01 2 3 4 5 CODE V (V) LOGIC Figure 16. Supply Current vs. Code Figure 19. Supply Current vs. Logic Input Voltage 160 V =5V DD 140 V = V = 3V DD REF T = 25°C A 120 V = 3V DD FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ 100 AND 200pF TO GND 80 V = 455mV/DIV OUT 60 40 20 0 TIME BASE = 4μs/DIV –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 20. Full-Scale Settling Time, 3 V Figure 17. Supply Current vs. Temperature 160 T = 25°C A 140 120 V = V = 5V DD REF T = 25°C A 100 FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ 80 AND 200pF TO GND 60 V = 909mV/DIV OUT 40 1 20 0 TIME BASE = 4μs/DIV 2.7 3.2 3.7 4.2 4.7 5.2 V (V) DD Figure 21. Full-Scale Settling Time, 5 V Figure 18. Supply Current vs. Supply Voltage Rev. A | Page 10 of 24 I (μA) I (μA) I (μA) DD DD DD 04777-040 04777-037 04777-043 I (μA) DD 04777-014 04777-015 04777-044 AD5662 2.502500 V = V = 5V V = V = 5V DD REF DD REF 2.502250 T = 25°C T = 25°C A A 2.502000 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND 2.501750 MIDSCALE (0x8000 TO 0x7FFF) 2.501500 GLITCH IMPULSE = 2.723nV.s 2.501250 2.501000 2.500750 2.500500 V DD 1 2.500250 2.500000 2.499750 MAX(C2)* 420.0mV 2.499500 2 2.499250 V OUT 2.499000 2.498750 CH1 2.0V CH2 500mV M100μs 125MS/s 8.0ns/pt 0 50 100 150 200 250 300 350 400 450 500 550 A CH1 1.28V SAMPLE NUMBER Figure 22. Power-On Reset to 0 V Figure 25. Digital-to-Analog Glitch Impulse (Negative) 2.500400 V = V = 5V DD REF T = 25°C A 2.500300 2.500200 2.500100 2.500000 V DD 2.499900 1 2.499800 2.499700 2.499600 2.499500 V = V = 5V DD REF 2.499400 T = 25°C A 13nS/SAMPLE NUMBER 2 2.499300 1 LSB CHANGE AROUND V OUT MIDSCALE (0x7FFF TO 0x8000) 2.499200 GLITCH IMPULSE = 1.271nV.s CH1 2.0V CH2 1.0V M100μs 125MS/s 8.0ns/pt 2.499100 A CH1 1.28V 0 50 100 150 200 250 300 350 400 450 500 550 SAMPLE NUMBER Figure 23. Power-On Reset to Midscale Figure 26. Digital-to-Analog Glitch Impulse (Positive) 2.500250 V = V = 5V DD REF 2.500200 T = 25°C A 20nS/SAMPLE NUMBER 2.500150 DAC LOADED WITH MIDSCALE 2.500100 DIGITAL FEEDTHROUGH = 0.06nV.s 2.500050 2.500000 SCLK 2.499950 1 2.499900 2.499850 2.499800 2.499750 2 2.499700 V OUT 2.499650 2.499600 CH1 2.0V CH2 1.0V M1.0μs 5.0gS/s 200ps/pt 0 50 100 150 200 250 300 350 400 450 500 550 A CH2 2.16V SAMPLE NUMBER Figure 24. Exiting Power-Down to Midscale Figure 27. Digital Feedthrough Rev. A | Page 11 of 24 04777-018 04777-017 04777-016 AMPLITUDE AMPLITUDE AMPLITUDE 04777-007 04777-006 04777-005 AD5662 –20 V = 5V DD V = V = 5V DD REF T = 25°C A T = 25°C –30 A DAC LOADED WITH FULL SCALE DAC LOADED WITH MIDSCALE V = 2V± 0.3Vp-p REF –40 –50 –60 1 –70 –80 –90 Y AXIS = 2μV/DIV X AXIS = 4s/DIV –100 2k 4k 6k 8k 10k Hz Figure 30. 0.1 Hz to 10 Hz Output Noise Plot Figure 28. Total Harmonic Distortion 16 800 V = V V = V = 5V REF DD DD REF T = 25°C T = 25°C A A 700 14 600 V = 3V DD 12 500 10 400 300 V = 5V 8 DD 200 6 100 4 0 01 2 3 4 5 6781 9 0 10 100 1k 10k 100k 1M CAPACITANCE (nF) FREQUENCY (Hz) Figure 31. Noise Spectral Density Figure 29. Settling Time vs. Capacitive Load Rev. A | Page 12 of 24 TIME (μs) dB 04777-009 04777-008 OUTPUT NOISE (nV/√Hz) 04777-010 04777-020 AD5662 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Offset Error For the DAC, relative accuracy or integral nonlinearity is a Offset error is a measure of the difference between VOUT (actual) measurement of the maximum deviation, in LSBs, from a and VOUT (ideal) expressed in mV in the linear region of the straight line passing through the endpoints of the DAC transfer transfer function. Offset error is measured on the AD5662 with function. A typical INL vs. code plot can be seen in Figure 4. Code 512 loaded in the DAC register. It can be negative or positive. Differential Nonlinearity (DNL) DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes Differential nonlinearity is the difference between the measured in the supply voltage. PSRR is the ratio of the change in VOUT to a change and the ideal 1 LSB change between any two adjacent change in V for full-scale output of the DAC. It is measured in DD codes. A specified differential nonlinearity of ±1 LSB maximum dB. VREF is held at 2 V, and VDD is varied by ±10%. ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle Zero-Code Error to a specified level for a ¼ to ¾ full-scale input change and is Zero-code error is a measurement of the output error when th measured from the 24 falling edge of SCLK. zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in Digital-to-Analog Glitch Impulse the AD5662 because the output of the DAC cannot go below Digital-to-analog glitch impulse is the impulse injected into the 0 V. It is due to a combination of the offset errors in the DAC analog output when the input code in the DAC register changes and the output amplifier. Zero-code error is expressed in mV. A state. It is normally specified as the area of the glitch in nV-s, plot of zero-code error vs. temperature can be seen in Figure 11. and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Full-Scale Error Figure 25 and Figure 26. Full-scale error is a measurement of the output error when full- scale code (0xFFFF) is loaded to the DAC register. Ideally, the Digital Feedthrough output should be VDD − 1 LSB. Full-scale error is expressed in Digital feedthrough is a measure of the impulse injected into percent of full-scale range. A plot of full-scale error vs. the analog output of the DAC from the digital inputs of the temperature can be seen in Figure 10. DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change Gain Error on the data bus, that is, from all 0s to all 1s and vice versa. This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed Total Harmonic Distortion (THD) as a percent of the full-scale range. This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for Total Unadjusted Error (TUE) the DAC, and the THD is a measurement of the harmonics present Total unadjusted error is a measurement of the output error, on the DAC output. It is measured in dB. taking all the various errors into account. A typical TUE vs. Noise Spectral Density code plot can be seen in Figure 6. This is a measurement of the internally generated random noise. Zero-Code Error Drift Random noise is characterized as a spectral density (voltage per This is a measurement of the change in zero-code error with a √Hz). It is measured by loading the DAC to midscale and meas- change in temperature. It is expressed in μV/°C. uring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density can be seen in Figure 31. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Rev. A | Page 13 of 24 AD5662 THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5662 DAC is fabricated on a CMOS process. The The output buffer amplifier can generate rail-to-rail voltages on architecture consists of a string DAC followed by an output its output, which gives an output range of 0 V to V . This output DD buffer amplifier. Figure 32 shows a block diagram of the DAC buffer amplifier has a gain of 2 derived from a 50 kΩ resistor architecture. divider network in the feedback path. The output amplifier’s inverting input is available to the user, allowing for remote V DD R V sensing. This VFB pin must be connected to VOUT for normal FB R operation. It can drive a load of 2 kΩ in parallel with 1000 pF to REF (+) GND. The source and sink capabilities of the output amplifier can RESISTOR DAC REGISTER V OUT STRING be seen in Figure 15. The slew rate is 1.5 V/μs with a ¼ to ¾ REF (–
) OUTPUT full-scale settling time of 10 μs. AMPLIFIER GND SERIAL INTERFACE The AD5662 has a 3-wire serial interface (SYNC, SCLK, and Figure 32. DAC Architecture DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for Since the input coding to the DAC is straight binary, the ideal a timing diagram of a typical write sequence. output voltage is given by The write sequence begins by bringing the SYNC line low. Data ⎛ D ⎞ V = V ×⎜ ⎟ OUT REF from the DIN line is clocked into the 24-bit shift register on the 65,536 ⎝ ⎠ falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5662 compatible with high speed where D is the decimal equivalent of the binary code that is th DSPs. On the 24 falling clock edge, the last data bit is clocked loaded to the DAC register. It can range from 0 to 65,535. in and the programmed function is executed, that is, a change RESISTOR STRING in DAC register contents and/or a change in the mode of opera- tion. At this stage, the line can be kept low or be brought The resistor string section is shown in Figure 33. It is simply a SYNC string of resistors, each of value R. The code loaded to the DAC high. In either case, it must be brought high for a minimum of register determines at which node on the string the voltage is 33 ns before the next write sequence so that a falling edge of tapped off to be fed into the output amplifier. The voltage is SYNC can initiate the next write sequence. Since the SYNC tapped off by closing one of the switches connecting the string buffer draws more current when V = 2.4 V than it does when IN to the amplifier. Because it is a string of resistors, it is guaranteed VIN = 0.8 V, SYNC should be idled low between write sequences monotonic. for even lower power operation. As mentioned previously it must, however, be brought high again just before the next write sequence. R R TO OUTPUT R AMPLIFIER R R Figure 33. Resistor String Rev. A | Page 14 of 24 04777-023 04777-022 AD5662 th 24 falling edge, this acts as an interrupt to the write sequence. INPUT SHIFT REGISTER The shift register is reset and the write sequence is seen as The input shift register is 24 bits wide (see Figure 34). The first invalid. Neither an update of the DAC register contents nor a six bits are don’t cares. The next two are control bits that control change in the operating mode occurs (see Figure 35). the part’s mode of operation (normal mode or any one of three power-down modes). See the Power-Down Modes section for a POWER-ON RESET more complete description of the various modes. The next 16 The AD5662 family contains a power-on reset circuit that bits are the data bits. These are transferred to the DAC register controls the output voltage during power-up. The AD5662x-1 th on the 24 falling edge of SCLK. DAC output powers up to 0 V, and the AD5662x-2 DAC output powers up to midscale. The output remains there until a valid SYNC INTERRUPT write sequence is made to the DAC. This is useful in In a normal write sequence, the line is kept low for at SYNC applications where it is important to know the state of the least 24 falling edges of SCLK, and the DAC is updated on the output of the DAC while it is in the process of powering up. th 24 falling edge. However, if SYNC is brought high before the DB23 (MSB) DBO (LSB) X X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 NORMAL OPERATION 0 1 1 kΩ TO GND 1 0 100 kΩ TO GND POWER-DOWN MODES THREE-STATE 1 1 Figure 34. Input Register Contents SCLK SYNC DB23 DB0 DB23 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH SYNC HIGH BEFORE 24 FALLING EDGE ON THE 24 FALLING EDGE Figure 35. SYNC Interrupt Facility Rev. A | Page 15 of 24 04777-024 04777-025 AD5662 MICROPROCESSOR INTERFACING POWER-DOWN MODES The AD5662 contains four separate modes of operation. These AD5662 to Blackfin® ADSP-BF53x Interface modes are software-programmable by setting two bits (DB17 Figure 37 shows a serial interface between the AD5662 and and DB16) in the control register. Table 5 shows how the state the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x of the bits corresponds to the device’s mode of operation. processor family incorporates two dual-channel synchronous Table 5. Modes of Operation for the AD5662 serial ports, SPORT1 and SPORT0, for serial and multiprocessor DB17 DB16 Operating Mode communications. Using SPORT0 to connect to the AD5662, the 0 0 Normal Operation setup for the interface is as follows. DT0PRI drives the DIN pin Power-Down Modes of the AD5662, while TSCLK0 drives the SCLK of the part. The 0 1 1 kΩ to GND SYNC is driven from TFS0. 1 0 100 kΩ to GND 1 1 Three-State ADSP-BF53x* AD5662* When both bits are set to 0, the part works normally with its TFS0 SYNC normal power consumption of 250 μA at 5 V. However, for the DTOPRI DIN three power-down modes, the supply current falls to 480 nA at TSCLK0 SCLK 5 V (100 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of *ADDITIONAL PINS OMITTED FOR CLARITY the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while Figure 37. AD5662 to Blackfin ADSP-BF53x Interface the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ or 100 kΩ AD5662 to 68HC11/68L11 Interface resistor, or left open-circuited (three-state) (see Figure 36). Figure 38 shows a serial interface between the AD5662 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 RESISTOR drives the SCLK of the AD5662, while the MOSI output drives AMPLIFIER V OUT STRING DAC the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup POWER-DOWN conditions for correct operation of this interface are as follows. RESISTOR CIRCUITRY NETWORK The 68HC11/68L11 is configured with its CPOL bit as a 0 and its CPHA bit as a 1. When data is being transmitted to the DAC, the line is taken low (PC7). When the 68HC11/ 68L11 is SYNC Figure 36. Output Stage During Power-Down configured as described above, data appearing on the MOSI The bias generator, the output amplifier, the resistor string, and output is valid on the falling edge of SCK. Serial data from the other associated linear circuitry are shut down when power- 68HC11/68L11 is transmitted in 8-bit bytes with only eight down mode is activated. However, the contents of the DAC falling clock edges occurring in the transmit cycle. Data is register are unaffected when in power-down. The time to exit transmitted MSB first. In order to load data to the AD5662, PC7 power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V is left low after the first eight bits are transferred, and a second (see Figure 24). serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. 68HC11/68L11* AD5662* PC7 SYNC SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. AD5662 to 68HC11/68L11 Interface Rev. A | Page 16 of 24 04777-026 04777-027 04777-028 AD5662 AD5662 to 80C51/80L51 Interface AD5662 to MICROWIRE Interface Figure 40 shows an interface between the AD5662 and any Figure 39 shows a serial interface between the AD5662 and the 80C51/80L51 microcontroller. The setup for the interface is as MICROWIRE-compatible device. Serial data is shifted out on follows. TxD of the 80C51/80L51 drives SCLK of the AD5662, the falling edge of the serial clock and is clocked into the AD5662 while RxD drives the serial data line of the part. The SYNC on the rising edge of the SK. signal is again derived from a bit-programmable pin on the port. MICROWIRE* AD5662* In this case, port line P3.3 is used. When data is to be transmitted to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus only eight falling clock edges occur CS SYNC in the transmit cycle. To load data to the DAC, P3.3 is left low SK SCLK after the first eight bits are transmitted, and a second write cycle SO DIN is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 *ADDITIONAL PINS OMITTED FOR CLARITY outputs the serial data in a format that has the LSB first. The Figure 40. AD5662 to MICROWIRE Interface AD5662 must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. 80C51/80L51* AD5662* P3.3 SYNC TxD SCLK RxD DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 39. AD5662 to 80C51/80L51 Interface Rev. A | Page 17 of 24 04777-029 04777-030 AD5662 APPLICATIONS USING A REFERENCE AS A CHOOSING A REFERENCE FOR THE AD5662 POWER SUPPLY FOR THE AD5662 To achieve the optimum performance from the AD5662, Because the supply current required by the AD5662 is extremely thought should be given to the choice of a precision voltage low, an alternative option is to use a voltage reference to supply reference. The AD5662 has only one reference input, V . The REF the required voltage to the part (see Figure 41). This is especially voltage on the reference input is used to supply the positive useful if the power supply is quite noisy, or if the system supply input to the DAC. Therefore any error in the reference is voltages are at some value other than 5 V or 3 V, for example, reflected in the DAC. 15 V. The voltage reference outputs a steady supply voltage for When choosing a voltage reference for high accuracy applica- the AD5662; see Table 6 for a suitable reference. If the low drop- tions, the sources of error are initial accuracy, ppm drift, long- out REF195 is used, it must supply 250 μA of current to the term drift, and output voltage noise. Initial accuracy on the AD5662, with no load on the output of the DAC. When the output voltage of the DAC leads to a full-scale error in the DAC output is loaded, the REF195 also needs to supply the DAC. To minimize these errors, a reference with high initial current to the load. The total current required (with a 5 kΩ accuracy is preferred. Also, choosing a reference with an output load on the DAC output) is trim adjustment, such as the ADR423, allows a system designer to trim system errors out by setting a reference voltage to a 250 μA + (5 V/5 kΩ) = 1.25 mA voltage other than the nominal. The trim adjustment can also The load regulation of the REF195 is typically 2 ppm/mA, be used at temperature to trim out any error. which results in a 2.5 ppm (12.5 μV) error for the 1.25 mA Long-term drift is a measurement of how much the reference current drawn from it. This corresponds to a 0.164 LSB error. drifts over time. A reference with a tight long-term drift +15V specification ensures that the overall solution remains relatively stable during its entire lifetime. +5V REF195 250μA The temperature coefficient of a reference’s output voltage effect INL, DNL, and TUE. A reference with a tight temperature V V coefficient specification should be chosen to reduce temperature SYNC DD REF 3-WIRE V = 0V TO 5V OUT SERIAL SCLK AD5662 dependence of the DAC output voltage in ambient conditions. INTERFACE DIN In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. It Figure 41. REF195 as Power Supply to the AD5662 is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references such as the ADR425 produce low output noise in the 0.1 Hz to10 Hz range. Examples of recom- mended precision references for use as supply to the AD5662 are shown in the Table 6. Table 6. Partial List of Precision References for Use with the AD5662 o Part No. Initial Accuracy (mV max) Temp Drift (ppm C max) 0.1 Hz to 10 Hz Noise (μV p-p typ) V (V) OUT ADR425 ±2 3 3.4 5 ADR395 ±6 25 5 5 REF195 ±2 5 50 5 AD780 ±2 3 4 2.5/3 ADR423 ±2 3 3.4 3 Rev. A | Page 18 of 24 04777-031 AD5662 USING THE AD5662 AS AN ISOLATED, BIPOLAR OPERATION USING THE AD5662 PROGRAMMABLE, 4-20 mA PROCESS The AD5662 has been designed for single-supply operation, CONTROLLER but a bipolar output range is also possible using the circuit in In many process control system applications, 2-wire current Figure 42. The circuit gives an output voltage range of ±5 V. transmitters are used to transmit analog signals through noisy Rail-to-rail operation at the amplifier output is achievable using environments. These current transmitters use a zero-scale an AD820 or an OP295 as the output amplifier. signal current of 4 mA that can power the transmitter’s signal The output voltage for any input code can be calculated as conditioning circuitry. The full-scale output signal in these follows: transmitters is 20 mA. The converse approach to process control can also be used; a low-power, programmable current ⎡ ⎤ ⎛ D ⎞ R1+ R2 R2 ⎛ ⎞ ⎛ ⎞ source can be used to control remotely located sensors or V = V ×⎜ ⎟× −V × ⎜ ⎟ ⎜ ⎟ O ⎢ DD DD ⎥ 65,536 ⎝ R1 ⎠ ⎝ R1⎠ ⎝ ⎠ ⎣ ⎦ devices in the loop. A circuit that performs this function is shown in Figure 43. where D represents the input code in decimal (0 to 65,535). Using the AD5662 as the controller, the circuit provides a With VDD = 5 V, R1 = R2 = 10 kΩ, programmable output current of 4 mA to 20 mA, proportional ⎛ 10× D⎞ to the DAC’s digital code. Biasing for the controller is provided V = − 5 V ⎜ ⎟ O 65,536 by the ADR02 and requires no external trim for two reasons: ⎝ ⎠ (1) the ADR02’s tight initial output voltage tolerance and (2) This is an output voltage range of ±5 V, with 0x0000 corre- the low supply current consumption of both the AD8627 and sponding to a −5 V output, and 0xFFFF corresponding to a the AD5662. The entire circuit, including opto-couplers, +5 V output. consumes less than 3 mA from the total budget of 4 mA. The AD8627 regulates the output current to satisfy the current R2 = 10kΩ summation at the noninverting node of the AD8627. +5V +5V R1 = 10kΩ IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2) AD820/ ±5V OP295 V FB For the values shown in Figure 43, V V REF OUT 10μF 0.1μF IOUT = 0.2435 μA × D + 4 mA AD5662 –5V where D = 0 ≤ D ≤ 65535, giving a full-scale output current of 20 mA when the AD5662’s digital code equals 0xFFFF. Offset THREE-WIRE SERIAL trim at 4 mA is provided by P2, and P1 provides the circuit’s INTERFACE gain trim at 20 mA. These two trims do not interact because Figure 42. Bipolar Operation with the AD5662 the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the AD8627 more than 300 mV below its inverting input. Without this diode, such transients could cause phase reversal of the AD8627 and possible latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maxi- mum applied input voltage to the ADR02 and is from 12 V to 40 V. ADR02 V LOOP R2 12V TO 36V 18.5kΩ P2 4mA ADJUST SERIAL R1 Q1 P1 AD5662 AD8627 LOAD 4.7kΩ 2N3904 20mA R6 ADJUST 3.3kΩ D1 4mA TO 20mA R3 1.5kΩ RL R7 100Ω Figure 43. Programmable 4–20 mA Process Controller Rev. A | Page 19 of 24 04777-032 04777-034 AD5662 USING AD5662 WITH A POWER SUPPLY BYPASSING AND GROUNDING GALVANICALLY ISOLATED INTERFACE When accuracy is important in a circuit, it is helpful to carefully In process-control applications in industrial environments, it is consider the power supply and ground return layout on the board. The printed circuit board containing the AD5662 should often necessary to use a galvanically isolated interface to protect have separate analog and digital sections, each having its own and isolate the controlling circuitry from any hazardous area of the board. If the AD5662 is in a system where other common-mode voltages that might occur in the area where the devices require an AGND-to-DGND connection, the connection DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5662 uses a 3-wire serial logic interface, so the should be made at one point only. This ground point should be ADuM130x 3-channel digital isolator provides the required as close as possible to the AD5662. isolation (see Figure 44). The power supply to the part also The power supply to the AD5662 should be bypassed with 10 μF needs to be isolated, which is done by using a transformer. On and 0.1 μF capacitors. The capacitors should be located as close the DAC side of the transformer, a 5 V regulator provides the as possible to the device, with the 0.1 μF capacitor ideally right 5 V supply required for the AD5662. up against the device. The 10 μF capacitors are the tantalum +5V bead type. It is important that the 0.1 μF capacitor has low REGULATOR effective series resistance (ESR) and effective series inductance 10μF 0.1μF POWER (ESI), for example, common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal V DD logic switching. SCLK V1A SCLK ADMu103x AD5662 The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch VOB V SDI V1B SYNC OUT effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, V1C VOC DIN DATA ensure that they run at right angles to each other to reduce GND feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the Figure 44. AD5662 with a Galvanically Isolated Interface signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. A | Page 20 of 24 04777-033 AD5662 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 1 2 3 4 PIN 1 INDICATOR 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.60 8° 0.38 0.45 0.15 MAX 4° 0.22 SEATING 0.30 0° PLANE COMPLIANT TO JEDEC STANDARDS MO-178BA Figure 45. 8-Lead SOT-23 (RJ-8) Dimensions shown in millimeters 3.00 BSC 85 3.00 4.90 BSC BSC 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.80 8° 0.38 0.60 0.23 0° 0.22 0.40 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. A | Page 21 of 24 AD5662 ORDERING GUIDE Package Package Power-On 1, 2 Model Temperature Range Description Option Branding Reset to Code Acurracy AD5662ARJ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D38 Zero ±32 LSB INL AD5662ARJZ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9P Zero ±32 LSB INL AD5662ARJ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D38 Zero ±32 LSB INL AD5662ARJZ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9P Zero ±32 LSB INL AD5662ARJ-2500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D39 Midscale ±32 LSB INL AD5662ARJ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D39 Midscale ±32 LSB INL AD5662ARJZ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9Q Midscale ±32 LSB INL AD5662ARM-1 −40°C to +125°C 8-lead MSOP RM-8 D38 Zero ±32 LSB INL AD5662ARMZ-1 −40°C to +125°C 8-lead MSOP RM-8 D9P Zero ±32 LSB INL AD5662ARM-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D38 Zero ±32 LSB INL AD5662ARMZ-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D9P Zero ±32 LSB INL AD5662BRJ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D36 Zero ±16 LSB INL AD5662BRJZ-1500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9T Zero ±16 LSB INL AD5662BRJ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D36 Zero ±16 LSB INL AD5662BRJZ-1REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9T Zero ±16 LSB INL AD5662BRJ-2500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D37 Midscale ±16 LSB INL AD5662BRJZ-2500RL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9R Midscale ±16 LSB INL AD5662BRJ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D37 Midscale ±16 LSB INL AD5662BRJZ-2REEL7 −40°C to +125°C 8-lead SOT-23 RJ-8 D9R Midscale ±16 LSB INL AD5662BRM-1 −40°C to +125°C 8-lead MSOP RM-8 D36 Zero ±16 LSB INL AD5662BRMZ-1 −40°C to +125°C 8-lead MSOP RM-8 D9T Zero ±16 LSB INL AD5662BRM-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D36 Zero ±16 LSB INL AD5662BRMZ-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D9T Zero ±16 LSB INL AD5662WARMZ-1REEL7 −40°C to +125°C 8-lead MSOP RM-8 D9P Zero ±32 LSB INL EVAL-AD5662EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5662WARMZ-1REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model. Rev. A | Page 22 of 24 AD5662 NOTES Rev. A | Page 23 of 24 AD5662 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04777–0–12/10(A) Rev. A | Page 24 of 24