ANALOG DEVICES AD5648

Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/°C On-Chip Reference Data Sheet AD5628/AD5648/AD5668 FEATURES FUNCTIONAL BLOCK DIAGRAM V /V V REFIN REFOUT DD Low power, small footprint, pin-compatible octal DACs AD5628/AD5648/AD5668 1.25V/2.5V AD5668: 16 bits REF BUFFER AD5648: 14 bits INPUT DAC STRING LDAC V A OUT REGISTER REGISTER DAC A AD5628: 12 bits BUFFER INPUT DAC STRING V B OUT REGISTER REGISTER DAC B 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP BUFFER INPUT DAC STRING SCLK V C OUT On-chip 1.25 V/2.5 V, 5 ppm/°C reference REGISTER REGISTER DAC C INTERFACE BUFFER DAC Power down to 400 nA @ 5 V, 200 nA @ 3 V INPUT STRING SYNC V D LOGIC OUT REGISTER REGISTER DAC D 2.7 V to 5.5 V power supply BUFFER INPUT DAC STRING DIN V E OUT REGISTER REGISTER DAC E Guaranteed monotonic by design BUFFER INPUT DAC STRING V F OUT REGISTER REGISTER DAC F Power-on reset to zero scale or midscale BUFFER INPUT DAC STRING 3 power-down functions V G REGISTER REGISTER DAC G OUT Hardware LDAC and LDAC override function BUFFER DAC STRING INPUT V H REGISTER OUT REGISTER DAC H CLR function to programmable code POWER-DOWN POWER-ON LOGIC RESET Rail-to-rail operation 1 1 GND LDAC CLR 1 RU-16 PACKAGE ONLY APPLICATIONS Figure 1. Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION selectable output loads while in power-down mode for any or all The AD5628/AD5648/AD5668 devices are low power, octal, DAC channels. The outputs of all DACs can be updated simul- 12-/14-/16-bit, buffered voltage-output DACs. All devices taneously using the LDAC function, with the added functionality operate from a single 2.7 V to 5.5 V supply and are guaranteed of user-selectable DAC channels to simultaneously update. There monotonic by design. The AD5668 and AD5628 are available in is also an asynchronous CLR that updates all DACs to a user- both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the programmable code—zero scale, midscale, or full scale. AD5648 is available in both a 14-lead and 16-lead TSSOP. The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial The AD5628/AD5648/AD5668 have an on-chip reference with interface that operates at clock rates of up to 50 MHz and is an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have compatible with standard SPI®, QSPI™, MICROWIRE™, and a 1.25 V 5 ppm/°C reference, giving a full-scale output range DSP interface standards. The on-chip precision output amplifier of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have enables rail-to-rail output swing. a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use PRODUCT HIGHLIGHTS of an external reference. The internal reference is enabled via a 1. Octal, 12-/14-/16-bit DAC. software write. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. 3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and The part incorporates a power-on reset circuit that ensures that the 16-lead WLCSP. DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1, 4. Power-on reset to 0 V or midscale. AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and 5. Power-down capability. When powered down, the DAC remains powered up at this level until a valid write takes place. typically consumes 200 nA at 3 V and 400 nA at 5 V. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software- Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05302-001 AD5628/AD5648/AD5668 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 D/A Section................................................................................. 21 Applications....................................................................................... 1 Resistor String............................................................................. 21 Functional Block Diagram .............................................................. 1 Internal Reference ...................................................................... 21 General Description ......................................................................... 1 Output Amplifier........................................................................ 22 Product Highlights ........................................................................... 1 Serial Interface ............................................................................ 22 Revision History ............................................................................... 2 Input Shift Register .................................................................... 23 Specifications..................................................................................... 3 Interrupt .......................................................................... 23 SYNC AC Characteristics........................................................................ 6 Internal Reference Register....................................................... 24 Timing Characteristics ................................................................ 7 Power-On Reset.......................................................................... 24 Absolute Maximum Ratings............................................................ 8 Power-Down Modes .................................................................. 24 ESD Caution.................................................................................. 8 Clear Code Register ................................................................... 24 Pin Configurations and Function Descriptions ........................... 9 Function .......................................................................... 26 LDAC Typical Performance Characteristics ........................................... 11 Power Supply Bypassing and Grounding................................ 26 Terminology .................................................................................... 19 Outline Dimensions....................................................................... 27 Theory of Operation ...................................................................... 21 Ordering Guide .......................................................................... 29 REVISION HISTORY Changes to Table 4.............................................................................7 8/11—Rev. E to Rev. F Deleted SnPb from Table 5...............................................................8 Added 16-Lead WLCSP.....................................................Universal Added Figure 5; Renumbered Sequentially ...................................9 Added Figure 6 and Table 7; Renumbered Sequentially ........... 10 Changes to Table 6.............................................................................9 Changes to Figure 32 and Figure 33............................................. 15 Replaced Typical Performance Characteristics Section ............ 10 Updated Outline Dimensions ....................................................... 26 Changes to Power-On Reset Section ........................................... 23 Changes to Ordering Guide .......................................................... 28 Updated Outline Dimensions....................................................... 26 1/11—Rev. D to Rev. E Changes to Ordering Guide .......................................................... 28 Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset 1/10—Rev. B to Rev. C Error, and Reference TC Parameters, Table 1............................... 3 Changes to Figure 3........................................................................ 10 Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Changes to Ordering Guide .......................................................... 28 Error, and Reference TC Parameters, Table 2............................... 5 Changes to Output Voltage Settling Time, Table 3 ...................... 6 2/09—Rev. A to Rev. B Added Figure 53; Renumbered Sequentially .............................. 17 Changes to Reference Current Parameter, Table 1........................3 Change to Output Amplifier Section........................................... 21 Changes to I (Normal Mode) Parameter, Table 1......................4 DD Changes to Ordering Guide .......................................................... 28 Changes to Reference Current Parameter, Table 2........................5 Changes to IDD (Normal Mode) Parameter, Table 2......................6 9/10—Rev. C to Rev. D Change to Title.................................................................................. 1 11/05—Rev. 0 to Rev. A Added 16-Lead LFCSP Throughout ................................Universal Change to Specifications ..................................................................3 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 10/05—Revision 0: Initial Version Changes to Table 3............................................................................ 6 Rev. F | Page 2 of 32 Data Sheet AD5628/AD5648/AD5668 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection Ratio –80 –80 dB VDD ± 10% DC Crosstalk 10 10 μV Due to full-scale output change, (External Reference) R = 2 kΩ to GND or V L DD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode, VDD = 5 V REFERENCE INPUTS Reference Current 40 55 40 55 μA VREF = VDD = 5.5 V (per DAC channel) Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD56x8-2, AD56x8-3 2.495 2.505 2.495 2.505 V At ambient 3 Reference TC 5 10 5 10 ppm/°C TSSOP 15 5 10 ppm/°C LFCSP Reference Output Impedance 7.5 7.5 kΩ Rev. F | Page 3 of 32 AD5628/AD5648/AD5668 Data Sheet 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 5 V INL DD Input High Voltage, V 2 2 V V = 5 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DD All digital inputs at 0 or VDD, DAC active, excludes load current 4 IDD (Normal Mode) VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1.0 1.5 1.0 1.5 mA Internal reference off V = 4.5 V to 5.5 V 1.8 2.25 1.7 2.25 mA Internal reference on DD 5 I (All Power-Down Modes) DD VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 μA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. Rev. F | Page 4 of 32 Data Sheet AD5628/AD5648/AD5668 V = 2.7 V to 3.6 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection –80 –80 dB V ± 10% DD 3 Ratio 3 10 10 μV DC Crosstalk Due to full-scale output change, (External Reference) RL = 2 kΩ to GND or VDD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) 3 DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) R = 2 kΩ to GND or V L DD 10 10 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 3 V DD Power-Up Time 4 4 μs Coming out of power-down mode, V = 3 V DD REFERENCE INPUTS Reference Current 40 55 40 55 μA V = V = 5.5 V (per DAC channel) REF DD Reference Input Range 0 V 0 V DD DD Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5628/AD5648/AD5668-1 1.247 1.253 1.247 1.253 V At ambient 3 Reference TC 5 15 5 15 ppm/°C TSSOP 15 5 15 ppm/°C LFCSP Reference Output 7.5 7.5 kΩ Impedance Rev. F | Page 5 of 32 AD5628/AD5648/AD5668 Data Sheet 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 3 V INL DD Input High Voltage, V 2 2 V V = 3 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 2.7 3.6 2.7 3.6 V DD All digital inputs at 0 or VDD, DAC active, excludes load current 4 IDD (Normal Mode) VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off V = 2.7 V to 3.6 V 1.8 2.25 1.7 2.25 mA Internal reference on DD 5 I (All Power-Down Modes) DD VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 μA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. AC CHARACTERISTICS V = 2.7 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. 1, 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 2.5 7 μs ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) Slew Rate 1.2 V/μs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB(16-bit resolution) change around major carry (see Figure 42) 19 nV-s From code 0xEA00 to code 0xE9FF (16-bit resolution) Digital Feedthrough 0.1 nV-s Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz VREF = 2 V ± 0.2 V p-p Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400(16-bit resolution), 1 kHz 100 nV/√Hz DAC code = 0x8400(16-bit resolution), 10 kHz Output Noise 12 μV p-p 0.1 Hz to 10 Hz, DAC code = 0x0000 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. F | Page 6 of 32 Data Sheet AD5628/AD5648/AD5668 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD 1 t1 20 ns min SCLK cycle time t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 13 ns min to SCLK falling edge set-up time 4 SYNC t5 4 ns min Data set-up time t6 4 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t 15 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t10 0 ns min SCLK falling edge to SYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min SCLK falling edge to LDAC rising edge t 5 ns min CLR pulse width low 13 t 0 ns min SCLK falling edge to LDAC falling edge 14 t 300 ns typ CLR pulse activation time 15 1 Maximum SCLK frequency is 50 MHz at V = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. DD t 10 t 1 t 9 SCLK t 2 t 8 t t 7 t 3 4 SYNC t 6 t 5 DIN DB31 DB0 t 11 t 14 1 LDAC t 12 2 LDAC t 13 CLR t V 15 OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. F | Page 7 of 32 05302-002 AD5628/AD5648/AD5668 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect VOUT to GND −0.3 V to VDD + 0.3 V device reliability. VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range ESD CAUTION Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T ) 150°C J MAX TSSOP Package Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 150.4°C/W Reflow Soldering Peak Temperature Pb Free 260°C Rev. F | Page 8 of 32 Data Sheet AD5628/AD5648/AD5668 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5628/AD5668 V 1 12 GND DD V A 2 11 V B OUT OUT TOP VIEW 1 16 LDAC SCLK (Not to Scale) 3 10 V D V C OUT OUT SYNC 2 15 DIN 1 SYNC 14 SCLK V E 4 9 V F OUT OUT V 3 14 GND 2 13 V DIN DD DD AD5628/ AD5628/ 4 AD5648/ 13 3 12 V A V B V A GND OUT OUT OUT AD5648/ AD5668 5 12 4 11 V C V D V C V B OUT OUT OUT OUT TOP VIEW TOP VIEW V E 5 10 V D V E 6 11 V F (Not to Scale) OUT OUT OUT OUT (Not to Scale) V G 6 9 V F V G 7 10 V H OUT OUT OUT OUT V /V 7 8 V H 8 9 V /V CLR NOTES REFIN REFOUT OUT REFIN REFOUT 1. EXPOSED PAD MUST BE TIED TO GND. Figure 3. 14-Lead TSSOP (RU-14) Figure 4. 16-Lead TSSOP (RU-16) Figure 5. 16-Lead LFCSP(CP-16-17) Table 6. Pin Function Descriptions Pin No. 14-Lead 16-Lead 16-Lead TSSOP TSSOP LFCSP Mnemonic Description 15 N/A 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. 1 2 16 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken nd high before the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 2 3 1 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply DD should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 3 4 2 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 11 13 11 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 5 3 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 10 12 10 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 7 8 6 V / The AD5628/AD5648/AD5668 have a common pin for reference input and reference REFIN VREFOUT output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. N/A 9 7 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 5 6 4 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 9 11 9 V F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. OUT 6 7 5 V G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. OUT 8 10 8 V H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. OUT 12 14 12 GND Ground Reference Point for All Circuitry on the Part. 13 15 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 16 14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. EPAD EPAD It is recommended that the exposed paddle be soldered to the ground plane. Rev. F | Page 9 of 32 05302-003 05302-004 05302-005 V G 5 16 SYNC OUT V /V 6 15 LDAC REFIN REFOUT CLR 7 14 SCLK V H 8 13 DIN OUT AD5628/AD5648/AD5668 Data Sheet BALL A1 INDICATOR 1 23 4 GND SCL DIN SYNC A V B LDAC V V A OUT DD OUT B V F V D V E V C OUT OUT OUT OUT C V H CLR V V G OUT REF OUT D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 6. 16-Lead WLCSP Table 7. 16-Lead WLCSP Pin Function Descriptions Pin. No. Mnemonic Description B2 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. A4 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges nd of the next 32 clocks. If SYNC is taken high before the 32 falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. B3 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. B4 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT B1 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. C4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. C2 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. D3 V /V The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the REFIN REFOUT internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. D2 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. C3 V E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. OUT C1 V F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. OUT D4 V G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. OUT D1 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. A1 GND Ground Reference Point for All Circuitry on the Part. A3 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. A4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. F | Page 10 of 32 05302-006 Data Sheet AD5628/AD5648/AD5668 TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 V = 5V V = 5V DD DD EXT REF = 5V EXT REF = 5V 8 0.8 T = 25°C T = 25°C A A 6 0.6 4 0.4 2 0.2 0 0 –2 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 0 10k 20k 30k 40k 50k 60k 65535 0 10k 20k 30k 40k 50k 60k 65535 CODES CODES Figure 7. INL AD5668—External Reference Figure 10. DNL AD5668—External Reference 4 0.5 V = 5V DD V = 5V DD EXT REF = 5V EXT REF = 5V 0.4 3 T = 25°C A T = 25°C A 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 5k 10k 15k 16384 0 5k 10k 15k 16384 CODES CODES Figure 11. DNL AD5648—External Reference Figure 8. INL AD5648—External Reference 1.0 0.20 V = 5V V = 5V DD DD EXT REF = 5V EXT REF = 5V 0.8 0.15 T = 25°C T = 25°C A A 0.6 0.10 0.4 0.05 0.2 0 0 –0.2 –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –1.0 –0.20 0 500 1000 1500 2000 2500 3000 3500 4095 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 9. INL AD5628—External Reference Figure 12. DNL AD5628—External Reference Rev. F | Page 11 of 32 INL (LSB) INL (LSB) INL (LSB) 05302-108 05302-107 05302-106 DNL (LSB) DNL (LSB) INL (LSB) 05302-111 05302-110 05302-109 AD5628/AD5648/AD5668 Data Sheet 10 1.0 V = 5V V = 5V DD DD INT REF = 2.5V INT REF = 2.5V T = 25°C T = 25°C A A 0.5 5 0 0 –5 –0.5 –10 –1.0 0 10k 20k 30k 40k 50k 60k 65535 0 10k 20k 30k 40k 50k 60k 65535 CODES CODES Figure 13. INL AD5668-2/AD5668-3 Figure 16. DNL AD5668-2/AD5668-3 4 0.5 V = 5V V = 5V DD DD EXT REF = 5V EXT REF = 2.5V 0.4 3 T = 25°C T = 25°C A A 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 5k 10k 15k 16383 0 5k 10k 15k 16383 CODES CODES Figure 14. INL AD5648-2 Figure 17. DNL AD5648-2 0.20 1.0 V = 5V V = 5V DD DD INT REF = 2.5V INT REF = 2.5V 0.15 T = 25°C T = 25°C A A 0.5 0.10 0.05 0 0 –0.05 –0.10 –0.5 –0.15 –0.20 –1.0 0 500 1000 1500 2000 2500 3000 3500 4095 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 18. DNL AD5628-2 Figure 15. INL AD5628-2 Rev. F | Page 12 of 32 INL (LSB) INL (LSB) INL (LSB) 05302-114 05302-113 05302-112 DNL (LSB) DNL (LSB) DNL (LSB) 05302-117 05302-116 05302-115 Data Sheet AD5628/AD5648/AD5668 10 1.0 V = 3V DD V = 3V DD INT REF = 1.25V INT REF = 1.25V 8 T = 25°C A T = 25°C A 6 0.5 4 2 0 0 –2 –4 –0.5 –6 –8 –10 –1.0 0 10k 20k 30k 40k 50k 60k 65535 0 10k 20k 30k 40k 50k 60k 65535 CODES CODES Figure 19. INL AD5668-1 Figure 22. DNL AD5668-1 4 0.5 V = 3V DD V = 3V DD EXT REF = 1.25V EXT REF = 1.25V 0.4 3 T = 25°C A T = 25°C A 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 5k 10k 15k 16383 0 5k 10k 15k 16383 CODES CODES Figure 20. INL AD5648-1 Figure 23. DNL AD5648-1 1.0 0.20 V = 3V V = 3V DD DD INT REF = 1.25V INT REF = 1.25V 0.15 T = 25°C T = 25°C A A 0.5 0.10 0.05 0 0 –0.05 –0.5 –0.10 –0.15 –1.0 –0.20 0 500 1000 1500 2000 2500 3000 3500 4095 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 21. INL AD5628-1 Figure 24. DNL AD5628-1 Rev. F | Page 13 of 32 INL (LSB) INL (LSB) INL (LSB) 05302-120 05302-119 05302-118 DNL (LSB) DNL (LSB) DNL (LSB) 05302-123 05302-122 05302-121 AD5628/AD5648/AD5668 Data Sheet 0 1.95 V = 5V T = 25°C DD A 1.90 –0.05 OFFSET ERROR 1.85 –0.10 1.80 FULL-SCALE ERROR –0.15 1.75 1.70 ZERO-SCALE ERROR –0.20 GAIN ERROR 1.65 –0.25 1.60 –0.30 1.55 –40 –25 –10 5 20 35 50 65 80 95 110 125 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TEMPERATURE (°C) V (V) DD Figure 25. Gain Error and Full-Scale Error vs. Temperature Figure 28. Zero-Scale Error and Offset Error vs. Supply Voltage 6 21 V = 5V DD 18 5 OFFSET ERROR 15 4 ZERO-SCALE ERROR 12 3 9 2 6 1 3 0 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 0.85 0.90 0.95 1.00 1.05 TEMPERATURE (°C) I WITH EXTERNAL REFERENCE (mA) DD Figure 26. Zero-Scale Error and Offset Error vs. Temperature Figure 29. I Histogram with External Reference DD 18 –0.16 T = 25°C A FULL-SCALE ERROR –0.17 16 –0.18 14 –0.19 12 –0.20 10 –0.21 8 –0.22 6 –0.23 4 –0.24 GAIN ERROR 2 –0.25 0 –0.26 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 1.65 1.70 1.75 1.80 1.85 1.190 I WITH INTERNAL REFERENCE (mA) V (V) DD DD Figure 30. IDD Histogram with Internal Reference Figure 27. Gain Error and Full-Scale Error vs. Supply Voltage Rev. F | Page 14 of 32 ERROR (% FSR) ERROR (mV) ERROR (% FSR) 05302-126 05302-125 05302-124 NUMBER OF HITS NUMBER OF HITS ERROR (mV) 05302-127 05302-129 05302-128 Data Sheet AD5628/AD5648/AD5668 0.4 1.8 T = 25°C A T = 25°C A 1.7 0.3 1.6 0.2 V = 5V DD 1.5 0.1 V = 3V, INT REF = 1.25V 1.4 DD 0 V = 3V DD 1.3 –0.1 1.2 –0.2 1.1 –0.3 1.0 V = 5V, INT REF = 2.5V DD –0.4 0.9 0.8 –0.5 –10 –8 –6 –4 –2 0246 8 10 0 10k 20k 30k 40k 50k 60k DIGITAL CODES (Decimal) SOURCE/SINK CURRENT (mA) Figure 31. Headroom at Rails vs. Source and Sink Figure 34. Supply Current vs. Code 6 2.0 V = 5V DD INT REF = 2.5V FULL SCALE 1.9 T = 25°C 5 A 1.8 4 3/4 SCALE 1.7 V = 5.5V 1.6 DD 3 MIDSCALE 1.5 V = 3.6V DD 2 1.4 1/4 SCALE 1.3 1 1.2 0 1.1 ZERO SCALE 1.0 –1 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 –40 –25 –10 5 20 35 50 65 80 95 110 125 CURRENT (A) TEMPERATURE (°C) Figure 32. AD5668-2/AD5668-3 Source and Sink Capability Figure 35. Supply Current vs. Temperature 1.48 4.0 T = 25°C A V = 3V DD INT REF = 1.25V 3.5 1.46 T = 25°C A 3.0 FULL SCALE 1.44 2.5 3/4 SCALE 2.0 1.42 1.5 MIDSCALE 1.40 1.0 1/4 SCALE 0.5 1.38 ZERO SCALE 0 1.36 –0.5 1.34 –1.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 V (V) DD CURRENT (A) Figure 36. Supply Current vs. Supply Voltage Figure 33. AD5668-1 Source and Sink Capability Rev. F | Page 15 of 32 V (V) V (V) OUT OUT ERROR VOLTAGE (V) 05302-130 05302-132 05302-131 I (mA) I (mA) DD DD I (mA) DD 05302-133 05302-135 05302-134 AD5628/AD5648/AD5668 Data Sheet 2.3 5.5 T = 25°C A V = 5V DD 5.0 EXT REF = 5V 2.1 T = 25°C A 4.5 1.9 4.0 V DD 3.5 1.7 3.0 V =5V DD 1.5 2.5 V A OUT 2.0 1.3 1.5 1.1 1.0 V =3V DD 0.5 0.9 0 0.7 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –0.0010 –0.0006 –0.0002 0.0002 0.0006 0.0010 V (V) LOGIC TIME (s) Figure 37. Supply Current vs. Logic Input Voltage Figure 40. Power-On Reset to Midscale 6 5.5 V = 5V TH DD V = 5V 24 CLK RISING EDGE DD EXT REF = 5V 5.0 EXT REF = 5V T = 25°C A T = 25°C A 5 4.5 4.0 4 3.5 3.0 3 2.5 V A OUT 2.0 2 1.5 1.0 1 0.5 0 0 –0.5 –2 0 2 4 6 8 –10 –5 0 5 10 TIME (µs) TIME (µs) Figure 38. Full-Scale Settling Time, 5 V Figure 41. Exiting Power-Down to Midscale 5.5 V = 5V DD T V = 5V DD 5.0 EXT REF = 5V EXT REF = 5V T = 25°C A T = 25°C A 4.5 4.0 V DD 3.5 3.0 V A OUT 2.5 3 2.0 1.5 1.0 TH 24 CLK RISING EDGE 0.5 V A OUT 0 4 –0.5 –0.0010 –0.0006 –0.0002 0.0002 0.0006 0.0010 M400ns A CH4 1.50V B CH3 10.0mV CH4 5.0V T 17.0% TIME (s) W Figure 39. Power-On Reset to 0 V Figure 42. Digital-to-Analog Glitch Impulse (Negative) Rev. F | Page 16 of 32 VOLTAGE (V) I (mA) V (V) DD OUT 05302-137 05302-136 05302-138 VOLTAGE (V) VOLTAGE (V) 05302-141 05302-140 05302-139 Data Sheet AD5628/AD5648/AD5668 0.0010 0.20 V = 5V EXT REF = 2.5V DD EXT REF = 5V 0.15 T = 25°C A 0.0005 0.10 0.05 0 0 –0.0005 –0.05 –0.10 –0.0010 –0.15 –0.0015 –0.20 09 1 2 3 4 5 6 7 8 01 1 2 3 4 5 6 7 890 TIME (µs) TIME (s) Figure 43. Analog Crosstalk Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 0.0020 0.20 V = 5V INT REF = 1.25V DD EXT REF = 5V 0.15 T = 25°C 0.0015 A 0.10 0.0010 0.05 0.0005 0 0 –0.05 –0.0005 –0.10 –0.0010 –0.15 –0.0015 –0.20 08 1 2 3 4 5 6 7 01 1 2 3 4 5 6 7 890 TIME (µs) TIME (s) Figure 44. DAC-to-DAC Crosstalk Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 0.06 800 EXT REF = 5V 700 0.04 600 0.02 500 0 400 V = 2.5V REF –0.02 300 –0.04 200 –0.06 100 V = 1.25V REF –0.08 0 01 1 2 3 4 5 6 7 890 100 1k 10k 100k 1M TIME (s) FREQUENCY (Hz) Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 48. Noise Spectral Density, Internal Reference Rev. F | Page 17 of 32 OUTPUT VOLTAGE (V) GLITCH AMPLITUDE (V) GLITCH AMPLITUDE (V) 05302-144 05302-143 05302-142 OUTPUT NOISE (V) OUTPUT NOISE (V) OUTPUT NOISE (nV/ Hz) 05302-147 05302-146 05302-145 AD5628/AD5648/AD5668 Data Sheet 0 10 V = 5.5V DD EXT REF = 5V 0 T = 25°C –20 A V = 2V ± 0.1V p-p REF –10 FREQUENCY = 10kHz –40 –20 –60 –30 –40 –80 CH A –50 CH B –100 CH C CH D –60 CH E V = 5.5V DD CH F –120 EXT REF = 5V CH G –70 T = 25°C CH H A V = 2V ± 0.2V p-p –3dB REF –80 –140 0 2000 4000 6000 8000 10,000 10 100 1k 1k0 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 49. Total Harmonic Distortion Figure 52. Multiplying Bandwidth 1.2510 V = 5.5V DD 9 T = 25°C 1.2508 A 8 1.2506 V = EXTERNAL REFERENCE = 5V DD 7 1.2504 6 1.2502 5 1.2500 1.2498 4 1.2496 3 V = EXTERNAL REFERENCE = 3V DD 1.2494 2 1.2492 1 1.2490 –40 25 105 0 01 1 2 3 4 5 6 7 8 90 TEMPERATURE (°C) CAPACITIVE LOAD (nF) Figure 53. 1.25 V Reference Temperature Coefficient vs. Temperature Figure 50. Settling Time vs. Capacitive Load 2.503 5.5 EXT REF = 5V 5.0 2.502 4.5 2.501 4.0 3.5 2.500 3.0 V A OUT 2.499 2.5 2.0 2.498 1.5 CLR PULSE 2.497 1.0 0.5 2.496 0 2.495 –0.5 105 25 –40 –10 –5 0 5 10 TEMPERATURE (°C) TIME (µs) CLR Figure 54. 2.5 V Reference Temperature Coefficient vs. Temperature Figure 51. Hardware Rev. F | Page 18 of 32 THD (dB) VOLTAGE (V) SETTLING TIME (µs) 05302-150 05302-149 05302-148 REFERENCE (ppm/°C) V (dBm) OUT REFERENCE (ppm/°C) 05302-154 05302-151 05302-152 Data Sheet AD5628/AD5648/AD5668 TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse For the DAC, relative accuracy, or integral nonlinearity (INL), is Digital-to-analog glitch impulse is the impulse injected into the a measure of the maximum deviation in LSBs from a straight line analog output when the input code in the DAC register changes passing through the endpoints of the DAC transfer function. state. It is normally specified as the area of the glitch in nV-s and Figure 7 to Figure 9, Figure 13 to Figure 15, and Figure 19 to is measured when the digital input code is changed by 1 LSB at Figure 21 show plots of typical INL vs. code. the major carry transition (0x7FFF to 0x8000). See Figure 42. Differential Nonlinearity DC Power Supply Rejection Ratio (PSRR) Differential nonlinearity (DNL) is the difference between the PSRR indicates how the output of the DAC is affected by changes measured change and the ideal 1 LSB change between any two in the supply voltage. PSRR is the ratio of the change in VOUT to adjacent codes. A specified differential nonlinearity of ±1 LSB a change in VDD for full-scale output of the DAC. It is measured maximum ensures monotonicity. This DAC is guaranteed mono- in decibels. VREF is held at 2 V, and VDD is varied ±10%. tonic by design. Figure 10 to Figure 12, Figure 16 to Figure 18, and Figure 22 to Figure 24 show plots of typical DNL vs. code. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in Offset Error response to a change in the output of another DAC. It is measured Offset error is a measure of the difference between the actual with a full-scale output change on one DAC (or soft power-down VOUT and the ideal VOUT, expressed in millivolts in the linear and power-up) while monitoring another DAC kept at midscale. region of the transfer function. Offset error is measured on the It is expressed in microvolts. AD5668 with Code 512 loaded into the DAC register. It can be DC crosstalk due to load current change is a measure of the negative or positive and is expressed in millivolts. impact that a change in load current on one DAC has to another Zero-Code Error DAC kept at midscale. It is expressed in microvolts per milliamp. Zero-code error is a measure of the output error when zero Reference Feedthrough code (0x0000) is loaded into the DAC register. Ideally, the Reference feedthrough is the ratio of the amplitude of the signal output should be 0 V. The zero-code error is always positive in at the DAC output to the reference input when the DAC output the AD5628/AD5648/AD5668, because the output of the DAC is not being updated (that is, is high). It is expressed in LDAC cannot go below 0 V. It is due to a combination of the offset decibels. errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. Figure 28 shows a plot of typical zero- Digital Feedthrough code error vs. temperature. Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the Gain Error device, but is measured when the DAC is not being written to Gain error is a measure of the span error of the DAC. It is the (SYNC held high). It is specified in nV-s and measured with a deviation in slope of the DAC transfer characteristic from the full-scale change on the digital input pins, that is, from all 0s to ideal, expressed as a percentage of the full-scale range. all 1s or vice versa. Zero-Code Error Drift Digital Crosstalk Zero-code error drift is a measure of the change in zero-code Digital crosstalk is the glitch impulse transferred to the output error with a change in temperature. It is expressed in μV/°C. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. Gain Error Drift It is measured in standalone mode and is expressed in nV-s. Gain error drift is a measure of the change in gain error with Analog Crosstalk changes in temperature. It is expressed in (ppm of full-scale Analog crosstalk is the glitch impulse transferred to the output range)/°C. of one DAC due to a change in the output of another DAC. It is Full-Scale Error measured by loading one of the input registers with a full-scale Full-scale error is a measure of the output error when full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC code (0xFFFF) is loaded into the DAC register. Ideally, the high, and then pulsing low and monitoring the output of LDAC output should be V – 1 LSB. Full-scale error is expressed as a DD the DAC whose digital code has not changed. The area of the percentage of the full-scale range. Figure 25 shows a plot of glitch is expressed in nV-s. typical full-scale error vs. temperature. Rev. F | Page 19 of 32 AD5628/AD5648/AD5668 Data Sheet DAC-to-DAC Crosstalk Total Harmonic Distortion (THD) DAC-to-DAC crosstalk is the glitch impulse transferred to the Total harmonic distortion is the difference between an ideal output of one DAC due to a digital code change and subsequent sine wave and its attenuated version using the DAC. The sine output change of another DAC. This includes both digital and wave is used as the reference for the DAC, and the THD is a analog crosstalk. It is measured by loading one of the DACs measure of the harmonics present on the DAC output. It is with a full-scale code change (all 0s to all 1s or vice versa) with measured in decibels. LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. F | Page 20 of 32 Data Sheet AD5628/AD5648/AD5668 THEORY OF OPERATION D/A SECTION R The AD5628/AD5648/AD5668 DACs are fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. Each part includes an R internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 55 shows a block diagram of the DAC architecture. TO OUTPUT R AMPLIFIER V DD V REFIN OUTPUT AMPLIFIER (GAIN = ×2) REF DAC V OUT REGISTER R RESISTOR STRING R GND Figure 55. DAC Architecture Because the input coding to the DAC is straight binary, the ideal Figure 56. Resistor String output voltage when using an external reference is given by INTERNAL REFERENCE D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN The AD5628/AD5648/AD5668 have an on-chip reference with N ⎝ 2 ⎠ an internal gain of 2. The AD5628/AD5648/AD5668-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V; The ideal output voltage when using the internal reference is the AD5628/AD5648/AD5668-2, -3 have a 2.5 V, 5 ppm/°C given by reference, giving a full-scale output of 5 V. The on-board D ⎛ ⎞ reference is off at power-up, allowing the use of an external V = 2×V × ⎜ ⎟ OUT REFOUT N ⎝ 2 ⎠ reference. The internal reference is enabled via a write to the control register (see Table 8). where: D = decimal equivalent of the binary code that is loaded to the The internal reference associated with each part is available at DAC register. the VREFOUT pin. A buffer is required if the reference output is 0 to 4095 for AD5628 (12 bits). used to drive external loads. When using the internal reference, 0 to 16,383 for AD5648 (14 bits). it is recommended that a 100 nF capacitor be placed between 0 to 65,535 for AD5668 (16 bits). the reference output and GND for reference stability. N = the DAC resolution. Individual channel power-down is not supported while using RESISTOR STRING the internal reference. The resistor string section is shown in Figure 56. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. F | Page 21 of 32 05302-153 05302-053 AD5628/AD5648/AD5668 Data Sheet Table 8. Command Definitions OUTPUT AMPLIFIER Command The output buffer amplifier can generate rail-to-rail voltages on C3 C2 C1 C0 Description its output, which gives an output range of 0 V to VDD. The 0 0 0 0 Write to Input Register n amplifier is capable of driving a load of 2 kΩ in parallel with 0 0 0 1 Update DAC Register n 200 pF to GND. The source and sink capabilities of the output 0 0 1 0 Write to Input Register n, update all amplifier can be seen in Figure 32 and Figure 33. The slew rate (software LDAC) is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs. 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC SERIAL INTERFACE 0 1 0 1 Load clear code register The AD5628/AD5648/AD5668 have a 3-wire serial interface 0 1 1 0 Load LDAC register SYNC ( , SCLK, and DIN) that is compatible with SPI, QSPI, and 0 1 1 1 Reset (power-on reset) MICROWIRE interface standards as well as most DSPs. See 1 0 0 0 Set up internal REF register Figure 2 for a timing diagram of a typical write sequence. 1 0 0 1 Reserved – – – – Reserved The write sequence begins by bringing the SYNC line low. Data 1 1 1 1 Reserved from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5628/AD5648/AD5668 compatible Table 9. Address Commands nd with high speed DSPs. On the 32 falling clock edge, the last Address (n) data bit is clocked in and the programmed function is executed, A3 A2 A1 A0 Selected DAC Channel that is, a change in DAC register contents and/or a change in 0 0 0 0 DAC A the mode of operation. At this stage, the SYNC line can be kept 0 0 0 1 DAC B low or be brought high. In either case, it must be brought high 0 0 1 0 DAC C for a minimum of 15 ns before the next write sequence so that a 0 0 1 1 DAC D SYNC SYNC falling edge of can initiate the next write sequence. 0 1 0 0 DAC E should be idled low between write sequences for even lower 0 1 0 1 DAC F power operation of the part. As is mentioned previously, 0 1 1 0 DAC G SYNC however, must be brought high again just before the next 0 1 1 1 DAC H write sequence. 1 1 1 1 All DACs Rev. F | Page 22 of 32 Data Sheet AD5628/AD5648/AD5668 INTERRUPT SYNC INPUT SHIFT REGISTER In a normal write sequence, the SYNC line is kept low for The input shift register is 32 bits wide. The first four bits are nd don’t cares. The next four bits are the command bits, C3 to C0 32 falling edges of SCLK, and the DAC is updated on the 32 (see Table 8), followed by the 4-bit DAC address, A3 to A0 (see SYNC. However, if SYNC is brought falling edge and rising edge of nd Table 9) and finally the 16-/14-/12-bit data-word. The data- high before the 32 falling edge, this acts as an interrupt to the word comprises the 16-/14-/12-bit input code followed by four, write sequence. The shift register is reset, and the write sequence six, or eight don’t care bits for the AD5668, AD5648, and is seen as invalid. Neither an update of the DAC register contents AD5628, respectively (see Figure 57 through Figure 59). These nor a change in the operating mode occurs (see Figure 60). nd data bits are transferred to the DAC register on the 32 falling edge of SCLK. DB31 (MSB) DB0 (LSB) X XXX C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 57. AD5668 Input Register Contents DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 58. AD5648 Input Register Contents DB31 (MSB) DB0 (LSB) X XX X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DATA BITS COMMAND BITS ADDRESS BITS Figure 59. AD5628 Input Register Contents SCLK SYNC DB31 DB0 DB31 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES SYNC HIGH BEFORE 32ND FALLING EDGE ON THE 32ND FALLING EDGE SYNC Figure 60. Interrupt Facility Rev. F | Page 23 of 32 05302-057 05302-056 05302-055 05302-054 AD5628/AD5648/AD5668 Data Sheet the part is in power-down mode. There are three different INTERNAL REFERENCE REGISTER options. The output is connected internally to GND through The on-board reference is off at power-up by default. This allows either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited the use of an external reference if the application requires it. The (three-state). The output stage is illustrated in Figure 61. on-board reference can be turned on or off by a user-program- mable internal REF register by setting Bit DB0 high or low (see The bias generator of the selected DAC(s), output amplifier, Table 10). Command 1000 is reserved for setting the internal resistor string, and other associated linear circuitry are shut REF register (see Table 8). Table 12 shows how the state of the down when the power-down mode is activated. The internal bits in the input shift register corresponds to the mode of reference is powered down only when all channels are powered operation of the device. down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically POWER-ON RESET 4 μs for V = 5 V and for V = 3 V. See Figure 41 for a plot. DD DD The AD5628/AD5648/AD5668 family contains a power-on reset circuit that controls the output voltage during power-up. Any combination of DACs can be powered up by setting PD1 The AD5628/AD5648/AD5668-1, -2 DAC output powers up to and PD0 to 0 (normal operation). The output powers up to the 0 V, and the AD5668-3 DAC output powers up to midscale. The value in the input register (LDAC low) or to the value in the output remains powered up at this level until a valid write DAC register before powering down ( high). LDAC sequence is made to the DAC. This is useful in applications CLEAR CODE REGISTER where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software The AD5628/AD5648/AD5668 have a hardware pin that CLR executable reset function that resets the DAC to the power-on is an asynchronous clear input. The CLR input is falling edge reset code. Command 0111 is reserved for this reset function sensitive. Bringing the line low clears the contents of the CLR (see Table 8). Any events on LDAC or CLR during power-on input register and the DAC registers to the data contained in reset are ignored. the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load POWER-DOWN MODES zero scale, midscale, or full scale to all channels together. These The AD5628/AD5648/AD5668 contain four separate modes clear code values are user-programmable by setting two bits, of operation. Command 0100 is reserved for the power-down Bit DB1 and Bit DB0, in the CLR control register (see Table 14). function (see Table 8). These modes are software-programmable The default setting clears the outputs to 0 V. Command 0101 is by setting two bits, Bit DB9 and Bit DB8, in the control register. reserved for loading the clear code register (see Table 8). Table 12 shows how the state of the bits corresponds to the nd The part exits clear code mode on the 32 falling edge of the next mode of operation of the device. Any or all DACs (DAC H to write to the part. If CLR is activated during a write sequence, the DAC A) can be powered down to the selected mode by setting write is aborted. the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for the contents of the input shift register during power-down/power- The pulse activation time—the falling edge of to CLR CLR up operation. When using the internal reference, only all channel when the output starts to change—is typically 280 ns. However, if power-down to the selected modes is supported. outside the DAC linear region, it typically takes 520 ns after executing for the output to start changing (see Figure 51). When both bits are set to 0, the part works normally with its CLR normal power consumption of 1.3 mA at 5 V. However, for the See Table 15 for contents of the input shift register during the three power-down modes, the supply current falls to 0.4 μA at loading clear code register operation. 5 V (0.2 μA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while Rev. F | Page 24 of 32 Data Sheet AD5628/AD5648/AD5668 Table 10. Internal Reference Register Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0 X 1 0 0 0 X X X X X 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF register Table 12. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Power- Power-down/power-up channel selection—set bit to 1 to select cares don’t cares cares down mode RESISTOR AMPLIFIER V OUT STRING DAC POWER-DOWN RESISTOR CIRCUITRY NETWORK Figure 61. Output Stage During Power-Down Table 14. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation Table 15. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X CR1 CR0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register Rev. F | Page 25 of 32 05302-058 AD5628/AD5648/AD5668 Data Sheet POWER SUPPLY BYPASSING AND GROUNDING FUNCTION LDAC When accuracy is important in a circuit, it is helpful to carefully The outputs of all DACs can be updated simultaneously using consider the power supply and ground return layout on the board. the hardware LDAC pin. The printed circuit board containing the AD5628/AD5648/ AD5668 should have separate analog and digital sections. If the Synchronous : After new data is read, the DAC registers LDAC nd AD5628/AD5648/AD5668 are in a system where other devices are updated on the falling edge of the 32 SCLK pulse. LDAC require an AGND-to-DGND connection, the connection should can be permanently low or pulsed as in Figure 2. be made at one point only. This ground point should be as close Asynchronous : The outputs are not updated at the same as possible to the AD5628/AD5648/AD5668. LDAC time that the input registers are written to. When LDAC goes The power supply to the AD5628/AD5648/AD5668 should be low, the DAC registers are updated with the contents of the bypassed with 10 μF and 0.1 μF capacitors. The capacitors input register. should physically be as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF Alternatively, the outputs of all DACs can be updated simulta- capacitors are the tantalum bead type. It is important that the neously using the software LDAC function by writing to Input 0.1 μF capacitor has low effective series resistance (ESR) and Register n and updating all DAC registers. Command 0011 is low effective series inductance (ESI), such as is typical of reserved for this software function. LDAC common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies An LDAC register gives the user extra flexibility and control caused by transient currents due to internal logic switching. over the hardware pin. This register allows the user to LDAC select which combination of channels to simultaneously update The power supply line should have as large a trace as possible to when the hardware LDAC pin is executed. Setting the LDAC bit provide a low impedance path and reduce glitch effects on the register to 0 for a DAC channel means that this channel’s update supply line. Clocks and other fast switching digital signals should is controlled by the LDAC pin. If this bit is set to 1, this channel be shielded from other parts of the board by digital ground. Avoid updates synchronously; that is, the DAC register is updated crossover of digital and analog signals if possible. When traces after new data is read, regardless of the state of the pin. It LDAC cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the effectively sees the LDAC pin as being tied low. (See Table 16 board. The best board layout technique is the microstrip technique, for the register mode of operation.) This flexibility is LDAC where the component side of the board is dedicated to the ground useful in applications where the user wants to simultaneously plane only and the signal traces are placed on the solder side. update select channels while the rest of the channels are However, this is not always possible with a 2-layer board. synchronously updating. Writing to the DAC using command 0110 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC pin. See Table 17 for the contents of the input shift register during the load LDAC register mode of operation. Table 16. LDAC Register Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation 0 1/0 Determined by LDAC pin. 1 X—don’t care DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0. Table 17. 32-Bit Input Shift Register Contents for Register Function LDAC MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t LDAC LDAC Setting bit to 1 overrides pin cares don’t cares cares Rev. F | Page 26 of 32 Data Sheet AD5628/AD5648/AD5668 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 8° 0.15 0.60 SEATING 0° 0.05 0.45 0.30 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. F | Page 27 of 32 061908-A AD5628/AD5648/AD5668 Data Sheet 4.10 0.35 4.00 SQ 0.30 3.90 0.25 PIN 1 INDICATOR 13 16 0.65 12 BSC 1 EXPOSED 2.70 PAD 2.60 SQ 2.50 4 9 8 5 0.45 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.35 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters 2.645 2.605 SQ 2.565 4 3 2 1 A BALL A1 IDENTIFIER B 1.50 REF C D 0.50 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.650 SIDE VIEW 0.595 0.540 COPLANARITY 0.05 0.340 SEATING 0.270 PLANE 0.320 0.240 0.300 0.210 Figure 65. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-16) Dimensions shown in millimeters Rev. F | Page 28 of 32 PIN 1 INDICATOR 08-16-2011-A 08-16-2010-C Data Sheet AD5628/AD5648/AD5668 ORDERING GUIDE Package Power-On Internal 1 Model Temperature Range Package Description Option Reset to Code Accuracy Reference AD5628BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V AD5628BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V AD5628BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5628BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5628ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V AD5628ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V AD5628ACPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 1.25 V AD5628ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 2.5 V AD5628BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 2.5 V AD5628BCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V AD5648BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V AD5648BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V AD5648BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V AD5648BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V AD5648ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V AD5648ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V AD5668BRUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V AD5668BRUZ-1REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V AD5668BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5668BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5668BRUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V AD5668BRUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V AD5668ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V AD5668ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V AD5668ARUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V AD5668ARUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V AD5668BCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5668BCPZ-1500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5668BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5668BCPZ-2500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5668ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±32 LSB INL 2.5 V AD5668ACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±32 LSB INL 2.5 V AD5668BCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V EVAL-AD5668SDCZ LFCSP Evaluation Board EVAL-AD5668SDRZ TSSOP Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 29 of 32 AD5628/AD5648/AD5668 Data Sheet NOTES Rev. F | Page 30 of 32 Data Sheet AD5628/AD5648/AD5668 NOTES Rev. F | Page 31 of 32 AD5628/AD5648/AD5668 Data Sheet NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05302-0-8/11(F) Rev. F | Page 32 of 32