ANALOG DEVICES AD5601

2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70 Data Sheet AD5601/AD5611/AD5621 FEATURES FUNCTIONAL BLOCK DIAGRAM V 6-lead SC70 and LFCSP packages DD GND Micropower operation: 100 µA maximum at 5 V Power-down typically to 0.2 µA at 3 V POWER-ON AD5601/AD5611/AD5621 RESET 2.7 V to 5.5 V power supply Guaranteed monotonic by design REF(+) DAC OUTPUT Power-on reset to 0 V with brownout detection 12-/10-/8-BIT V OUT REGISTER BUFFER DAC 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation INPUT POWER-DOWN CONTROL SYNC interrupt facility RESISTOR CONTROL LOGIC LOGIC NETWORK Minimized zero-code error AD5601 buffered 8-bit DAC B version: ±0.5 LSB INL AD5611 buffered 10-bit DAC SYNC SCLK SDIN B version: ±0.5 LSB INL Figure 1. A version: ±4 LSB INL Table 1. Related Devices AD5621 buffered 12-bit DAC Part Number Description B version: ±1 LSB INL AD5641 2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in A version: ±6 LSB INL SC70 and LFCSP packages APPLICATIONS They also provide software-selectable output loads while in Voltage level setting power-down mode. The parts are put into power-down mode Portable battery-powered instruments over the serial interface. Digital gain and offset adjustment The low power consumption of these parts in normal operation Programmable voltage and current sources makes them ideally suited to portable battery-operated equip- Programmable attenuators ment. The combination of small package and low power makes GENERAL DESCRIPTION these nanoDAC devices ideal for level-setting requirements, such as generating bias or control voltages in space-constrained The AD5601/AD5611/AD5621, members of the nanoDAC® and power-sensitive applications. family, are single, 8-/10-/12-bit, buffered voltage output DACs that operate from a single 2.7 V to 5.5 V supply, consuming PRODUCT HIGHLIGHTS typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70 1. Available in 6-lead LFCSP and SC70 packages. packages. Their on-chip precision output amplifier allows rail- 2. Low power, single-supply operation. The AD5601/ to-rail output swing to be achieved. The AD5601/AD5611/ AD5611/AD5621 operate from a single 2.7 V to 5.5 V AD5621 utilize a versatile 3-wire serial interface that operates at supply with a maximum current consumption of 100 µA, clock rates up to 30 MHz and is compatible with SPI, QSPI™, making them ideal for battery-powered applications. MICROWIRE™, and DSP interface standards. 3. The on-chip output buffer amplifier allows the output of The reference for the AD5601/AD5611/AD5621 is derived the DAC to swing rail-to-rail with a typical slew rate of from the power supply inputs and, therefore, gives the widest 0.5 V/µs. dynamic output range. The parts incorporate a power-on reset 4. Reference is derived from the power supply. circuit, which ensures that the DAC output powers up to 0 V 5. High speed serial interface with clock speeds up to and remains there until a valid write to the device takes place. 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. The AD5601/AD5611/AD5621 contain a power-down feature 6. Power-down capability. When powered down, the DAC that reduces current consumption to typically 0.2 µA at 3 V. typically consumes 0.2 µA at 3 V. Power-on reset with brownout detection. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved. 06853-001 AD5601/AD5611/AD5621 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier ........................................................................ 14 Applications ....................................................................................... 1 Serial Interface ............................................................................ 14 General Description ......................................................................... 1 Input Shift Register .................................................................... 14 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 14 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 16 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 16 Specifications ..................................................................................... 3 Microprocessor Interfacing ....................................................... 16 Timing Characteristics ................................................................ 4 Applications ..................................................................................... 18 Absolute Maximum Ratings ............................................................ 5 Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 ....................................................... 18 ESD Caution .................................................................................. 5 Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18 Pin Configuration and Function Descriptions ............................. 6 Using the AD5601/AD5611/AD5621 with a Galvanically Typical Performance Characteristics ............................................. 7 Isolated Interface ........................................................................ 19 Terminology .................................................................................... 13 Power Supply Bypassing and Grounding ................................ 19 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 20 DAC Section ................................................................................ 14 Ordering Guide .......................................................................... 21 Resistor String ............................................................................. 14 REVISION HISTORY 2/12—Rev. E to Rev. F 12/07—Rev. B to Rev. C Added 6-Lead LFCSP ......................................................... Universal Changes to Features .......................................................................... 1 Changes to Features Section, General Description Section, Changes to Table 2 ............................................................................. 3 Table 1, and Product Highlights Section ....................................... 1 Changes to AD5601/AD5611/AD5621 to ADSP-2101 Interface Section ............................................................................. 16 Changes to Table 4 ............................................................................ 5 Added Figure 4; Renumbered Sequentially .................................. 6 Updated Outline Dimensions ....................................................... 20 Changes to Table 5 ............................................................................ 6 Changes to Ordering Guide .......................................................... 20 Changes to Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 Section .............................................. 18 7/05—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 20 Changes to Figure 48...................................................................... 17 Changes to Ordering Guide .......................................................... 21 Changes to Galvanically Isolated Interface Section ................... 19 Changes to Figure 52...................................................................... 19 7/10—Rev. D to Rev. E Changes to Figure 1 .......................................................................... 1 3/05—Rev. 0 to Rev. A Changes to Timing Characteristics ................................................. 4 5/08—Rev. C to Rev. D Changes to Absolute Maximum Ratings ........................................ 5 Changes to General Description Section ...................................... 1 Changes to Full Scale Error Section ................................................ 7 Changes to Table 2 ............................................................................ 3 Changes to Figure 20...................................................................... 10 Changes to Choosing a Reference as Power Supply for the Changes to Theory of Operation .................................................. 14 AD5601/AD5611/AD5621 Section .............................................. 18 Changes to Power Down Modes .................................................. 15 Changes to Ordering Guide .......................................................... 20 1/05—Revision 0: Initial Version Rev. F | Page 2 of 24 Data Sheet AD5601/AD5611/AD5621 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Temperature range for A/B grades is −40°C to +125°C, typical at 25°C. Table 2. A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5601 Resolution 8 Bits 1 Relative Accuracy (INL) ±0.5 LSB Differential Nonlinearity (DNL) ±0.5 LSB Guaranteed monotonic by design AD5611 Resolution 10 Bits 1 Relative Accuracy (INL) ±4 ±0.5 LSB Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design AD5621 Resolution 12 Bits 1 Relative Accuracy (INL) ±6 ±1 LSB Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register Offset Error ±0.063 ±10 ±0.063 ±10 mV Gain Error ±0.0004 ±0.037 ±0.0004 ±0.037 %FSR Zero-Code Error Drift 5.0 5.0 µV/°C Gain Temperature Coefficient 2.0 2.0 ppm FSR/°C 2 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale Slew Rate 0.5 0.5 V/µs Capacitive Load Stability 470 470 pF RL = ∞ 1000 1000 pF RL = 2 kΩ Output Noise Spectral Density 120 120 DAC code = midscale,1 kHz nV/√Hz Noise 2 2 µV DAC code = midscale, 0.1 Hz to 10 kHz bandwidth Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry Digital Feedthrough 0.2 0.2 nV-s Short-Circuit Current 15 15 mA V = 3 V/5 V DD DC Output Impedance 0.5 0.5 Ω LOGIC INPUTS 3 Input Current ±2 ±2 µA Input High Voltage, V 1.8 1.8 V V = 4.7 V to 5.5 V INH DD 1.4 1.4 V VDD = 2.7 V to 3.6 V Input Low Voltage, VINL 0.8 0.8 V VDD = 4.7 V to 5.5 V 0.6 0.6 V V = 2.7 V to 3.6 V DD Pin Input Capacitance 3 3 pF Rev. F | Page 3 of 24 AD5601/AD5611/AD5621 Data Sheet A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V DD DD I for Normal Mode DAC active and excluding load DD current VDD = ±4.5 V to ±5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND VDD = ±2.7 V to ±3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND I for All Power-Down Modes V = V and V = GND DD IH DD IL V = ±4.5 V to ±5.5 V 0.5 0.5 µA V = V and V = GND DD IH DD IL V = ±2.7 V to ±3.6 V 0.2 0.2 µA V = V and V = GND DD IH DD IL POWER EFFICIENCY I /I 96 96 % I = 2 mA and V = ±5 V OUT DD LOAD DD 1 Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252. 2 Guaranteed by design and characterization, not production tested. 3 Total current flowing into all pins. TIMING CHARACTERISTICS V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted. See Figure 2. DD MIN MAX Table 3. 1 Parameter Limit Unit Test Conditions/Comments 2 t 33 ns min SCLK cycle time 1 t 5 ns min SCLK high time 2 t3 5 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 5 ns min Data setup time t 4.5 ns min Data hold time 6 t 0 ns min SCLK falling edge to SYNC rising edge 7 t 20 ns min Minimum high time 8 SYNC t9 13 ns min SYNC rising edge to next SCLK falling edge ignored 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH 2 Maximum SCLK frequency is 30 MHz. t t t t 4 2 1 9 SCLK t 8 t 3 t 7 SYNC t 6 t 5 D15 D14 D2 D1 D0 D15 D14 SDIN Figure 2. Timing Diagram Rev. F | Page 4 of 24 06853-002 Data Sheet AD5601/AD5611/AD5621 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7.0 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect VOUT to GND −0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range Industrial (A/B Grades) −40°C to +125°C Storage Temperature Range −65°C to +160°C ESD CAUTION Maximum Junction Temperature 150°C SC70 Package θJA Thermal Impedance 433.34°C/W θJC Thermal Impedance 149.47°C/W LFCSP Package θ Thermal Impedance 95°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD (Human Body Model) 2.0 kV Rev. F | Page 5 of 24 AD5601/AD5611/AD5621 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 AD5601/ 6V DD OUT V SYNC16 OUT AD5601/ AD5611/ SCLK 2 5GND AD5621 AD5611/ SCLK25 GND TOP VIEW AD5621 (Not to Scale) 4SYNC SDIN 3 TOP VIEW 34 V SDIN DD (Not to Scale) NOTES: 1. CONNECT THE EXPOSED PAD TO GND. Figure 3. 6-Lead SC70 Pin Configuration Figure 4. 6-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SC70 LFCSP Pin No. Pin No. Mnemonic Description 1 4 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling th edges of the clocks that follow. The DAC is updated following the 16 clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 3 3 SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 1 VDD Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. 5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. 6 6 V Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. OUT EP Exposed Pad. Connect to GND. Rev. F | Page 6 of 24 06853-003 06853-053 Data Sheet AD5601/AD5611/AD5621 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 2.5 V = V = 5V DD REF V = V = 5V DD REF T = 25°C T = 25°C A 2.0 A 1.5 0.5 1.0 0.5 0 0 –0.5 –1.0 –0.5 –1.5 –2.0 –1.0 –2.5 64 564 1064 1564 2064 2564 3064 3564 4064 64 564 1064 1564 2064 2564 3064 3564 4064 DAC CODE DAC CODE Figure 5. Typical AD5621 INL Figure 8. AD5621 Total Unadjusted Error (TUE) 0.5 0.6 V = V = 5V V = V = 5V DD REF DD REF T = 25°C T = 25°C 0.4 A A 0.4 0.3 0.2 0.2 0.1 0 0 –0.1 –0.2 –0.2 –0.3 –0.4 –0.4 –0.5 –0.6 16 116 216 316 416 516 616 716 816 916 16 116 216 316 416 516 616 716 816 916 DAC CODE DAC CODE Figure 6. Typical AD5611 INL Figure 9. AD5611 Total Unadjusted Error (TUE) 0.100 0.20 V = V = 5V V = V = 5V DD REF DD REF T = 25°C T = 25°C A A 0.075 0.15 0.050 0.10 0.025 0.05 0 0 –0.05 –0.025 –0.10 –0.050 –0.15 –0.075 –0.20 –0.100 4 54 104 154 204 4 54 104 154 204 DAC CODE DAC CODE Figure 7. Typical AD5601 INL Figure 10. AD5601 Total Unadjusted Error (TUE) Rev. F | Page 7 of 24 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 06853-005 06853-006 06853-004 TOTAL UNADJUSTED ERROR (LSB) TOTAL UNADJUSTED ERROR (LSB) TOTAL UNADJUSTED ERROR (LSB) 06853-008 06853-009 06853-007 0.05 0.04 0.03 0.02 0.01 –0.01 –0.02 –0.03 –0.04 –0.05 AD5601/AD5611/AD5621 Data Sheet 0.20 12 V = 3V V = 5V V = 5V DD DD DD V = DV V = DV IH DD IH DD T = 25°C A 0.15 V = GND V = GND IL IL 10 T = 25°C T = 25°C A A 0.10 8 0.05 0 6 0 –0.05 4 –0.10 2 –0.15 –0.20 0 64 564 1064 1564 2064 2564 3064 3564 DAC CODE I (mA) DD Figure 11. Typical AD5621 DNL Figure 14. I Histogram (3 V/5 V) DD V = 5V T = 25°C DD A T = 25°C V = 5V A DD CH1 = SCLK 0 CH2 = V OUT 16 116 216 316 416 516 616 716 816 916 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV DAC CODE Figure 12. Typical AD5611 DNL Figure 15. Full-Scale Settling Time 0.010 T = 25°C A V = 5V DD V = 5V 0.008 DD T = 25°C A CH1 = SCLK 0.006 0.004 0.002 0 CH2 = V OUT –0.002 –0.004 –0.006 –0.008 –0.010 4 54 104 154 204 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV DAC CODE Figure 13. Typical AD5601 DNL Figure 16. Half-Scale Settling Time Rev. F | Page 8 of 24 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 06853-011 06853-010 06853-012 NUMBER OF DEVICES 0.05456 0.05527 0.05599 0.05671 0.05742 0.05814 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 06853-015 06853-014 0.07334 06853-013 Data Sheet AD5601/AD5611/AD5621 V = 5V DD V DD V = 5V DD T = 25°C A T = 25°C A MIDSCALE LOADED CH1 CH1 V = 70mV OUT CH2 CH1 5µV/DIV CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV Figure 17. Power-On Reset to 0 V Figure 20. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth CH1 V = 5V DD V DD V = 5V DD T = 25°C CH1 A T = 25°C A V OUT CH2 CH2 V OUT CH1 5V, CH2 1V, TIME BASE = 2µs/DIV CH1 1V, CH2 5V, TIME BASE = 50µs/DIV Figure 18. V vs. V Figure 21. Exiting Power-Down Mode DD OUT 140 2.458 3/4 SCALE 2.456 FULL SCALE 120 2.454 MIDSCALE 2.452 100 1/4 SCALE 2.450 80 2.448 2.446 60 ZERO SCALE 2.444 40 2.442 T = 25°C A V = 5V DD 2.440 LOAD = 2kΩ AND 220pF 20 CODE 0x2000 TO 0x1FFF 2.438 10ns/SAMPLE NUMBER 2.436 0 0 100 200 300 400 500 0 5 10 15 20 25 SAMPLE NUMBER FREQUENCY (MHz) Figure 19. Digital-to-Analog Glitch Energy Figure 22. IDD vs. SCLK vs. Code Rev. F | Page 9 of 24 AMPLITUDE (V) 06853-017 06853-016 06853-018 I (µA) DD 06853-019 06853-020 06853-021 AD5601/AD5611/AD5621 Data Sheet 700 0.3 V = 5V V = 5V DD DD AD5621 MAX INL ERROR T = 25°C A 0.2 600 UNLOADED OUTPUT AD5601 MAX INL ERROR 0.1 AD5611 MAX INL ERROR 500 0 400 AD5611 MIN INL ERROR –0.1 –0.2 AD5601 MIN INL ERROR 300 –0.3 MIDSCALE 200 FULL SCALE –0.4 AD5621 MIN INL ERROR 100 –0.5 ZERO SCALE 0 –0.6 100 1k 10k 100k –40 –20 0 20 40 60 80 100 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 23. Noise Spectral Density Figure 26. INL vs. Temperature (5 V) 70 0.08 T = 25°C V = 5V A 0.07 DD V = 5V DD 0.06 60 AD5621 MAX DNL ERROR 0.05 0.04 50 0.03 V = 3V DD AD5611 MAX DNL ERROR 0.02 40 0.01 0 –0.01 30 –0.02 AD5601 MAX DNL ERROR AD5611 MIN DNL ERROR –0.03 AD5601 MIN DNL ERROR 20 –0.04 –0.05 10 –0.06 AD5621 MIN DNL ERROR –0.07 –0.08 0 –40 10 60 110 160 0 2000 4000 6000 8000 10000 12000 14000 16000 DIGITAL INPUT CODE TEMPERATURE (°C) Figure 24. Supply Current vs. Digital Input Code Figure 27. DNL vs. Temperature (5 V) 0.8 0.00149 V = 5V V = 5V DD DD AD5621 ZERO-CODE ERROR T = 25°C A 0.6 DAC LOADED WITH ZERO-SCALE CODE 0.00099 0.4 AD5611 ZERO-CODE ERROR 0.2 AD5601 ZERO-CODE ERROR 0.00049 AD5601 FULL-SCALE ERROR 0.0 –0.2 –0.00001 DAC LOADED WITH FULL-SCALE CODE –0.4 AD5611 FULL-SCALE ERROR AD5621 FULL-SCALE ERROR –0.6 –0.00051 –15 –10 –5 0 5 10 15 –40 –20 0 –20 40 60 80 100 120 140 TEMPERATURE (°C) I (mA) Figure 25. Sink and Source Capability Figure 28. Zero-Code Error and Full-Scale Error vs. Temperature Rev. F | Page 10 of 24 ΔV (V) OUT OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz) I (µA) DD 06853-023 06853-022 06853-024 ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 06853-026 06853-025 06853-027 Data Sheet AD5601/AD5611/AD5621 1.5 0.10 1.3 AD5621 MAX TUE 0.09 1.1 0.08 0.07 V = 5V 0.9 DD 0.7 0.06 0.5 0.05 AD5601 MAX TUE AD5611 MAX TUE V = 3V DD 0.3 0.04 0.03 0.1 –0.1 0.02 AD5601 MIN TUE AD5611 MIN TUE –0.3 0.01 AD5621 MIN TUE –0.5 0 –40 –20 0 20 40 60 80 100 120 140 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 29. Total Unadjusted Error (TUE) vs. Temperature (5 V) Figure 32. Supply Current vs. Temperature (3 V/5 V Supply) 1.5 T = 25°C A 1.4 0.4 1.3 1.2 AD5621 MAX INL ERROR 0.2 1.1 AD5601 MAX INL ERROR 1.0 V = 5V DD AD5611 MAX INL ERROR 0.9 0 0.8 AD5601 MIN INL ERROR 0.7 V = 3V DD AD5611 MIN INL ERROR 0.6 –0.2 0.5 0.4 0.3 –0.4 0.2 AD5621 MIN INL ERROR 0.1 –0.6 0 2.7 3.2 3.7 4.2 4.7 5.2 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 30. Offset Error vs. Temperature (3 V/5 V Supply) Figure 33. INL vs. Supply Voltage at 25°C 0 0.10 0.09 T = 25°C A 0.08 –0.002 0.07 V = 5V DD 0.06 –0.004 0.05 0.04 AD5621 MAX DNL ERROR 0.03 –0.006 0.02 AD5611 MAX DNL ERROR 0.01 –0.008 0 –0.01 –0.02 AD5611 MIN DNL ERROR –0.010 –0.03 V = 3V AD5601 MAX DNL ERROR DD –0.04 AD5601 MIN DNL ERROR –0.012 –0.05 –0.06 –0.07 –0.014 AD5621 MIN DNL ERROR –0.08 –0.09 –0.016 –0.10 –40 –20 0 20 40 60 80 100 120 140 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 31. Gain Error vs. Temperature (3 V/5 V Supply) Figure 34. DNL vs. Supply Voltage at 25°C Rev. F | Page 11 of 24 GAIN ERROR (%FSR) TOTAL UNADJUSTED ERROR (LSB) OFFSET ERROR (mV) 06853-029 06853-028 06853-030 DNL ERROR (LSB) I (mA) DD INL ERROR (LSB) 06853-032 06853-031 06853-033 AD5601/AD5611/AD5621 Data Sheet 0.10 1.5 T = 25°C T = 25°C A A 0.09 1.3 AD5621 MAX TUE 0.08 1.1 0.07 0.9 0.06 0.7 0.05 0.5 0.04 AD5611 MAX TUE 0.3 0.03 AD5621 MIN TUE 0.1 0.02 AD5601 MAX TUE –0.1 0.01 AD5611 MIN TUE AD5601 MIN TUE –0.3 0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 37. Supply Current vs. Supply Voltage at 25°C Figure 35. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C 450 0.0010 T = 25°C T = 25°C A A SCLK/SDIN AD5621 ZERO-CODE ERROR INCREASING 400 SCLK/SDIN 0.0008 V = 5V DD DECREASING 350 V = 5V DD 0.0006 300 SCLK/SDIN 0.0004 250 INCREASING AD5601 FULL-SCALE ERROR V = 3V DD AD5611 ZERO-CODE ERROR 200 0.0002 AD5601 ZERO-CODE ERROR 150 0 100 AD5611 FULL-SCALE ERROR –0.0002 AD5621 FULL-SCALE ERROR 50 SCLK/SDIN DECREASING V = 3V DD 0 –0.0004 0 1 2 3 4 5 6 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 SUPPLY VOLTAGE (V) V (V) LOGIC Figure 38. SCLK/SDIN vs. Logic Voltage Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C Rev. F | Page 12 of 24 ERROR (LSB) TOTAL UNADJUSTED ERROR (LSB) 06853-034 06853-035 I (mA) I (µA) DD DD 06853-037 06853-036 Data Sheet AD5601/AD5611/AD5621 TERMINOLOGY Relative Accuracy Total Unadjusted Error For the DAC, relative accuracy or integral nonlinearity (INL) is Total unadjusted error (TUE) is a measure of the output error, a measure of the maximum deviation, in LSBs, from a straight taking all the various errors into account. See Figure 8 to line passing through the endpoints of the DAC transfer func- Figure 10 for plots of typical TUE vs. code. tion. See Figure 5 to Figure 7 for plots of typical INL vs. code. Zero-Code Error Drift Differential Nonlinearity Zero-code error drift is a measure of the change in zero-code Differential nonlinearity (DNL) is the difference between the error with a change in temperature. It is expressed in µV/°C. measured change and the ideal 1 LSB change between any two Gain Temperature Coefficient adjacent codes. A specified differential nonlinearity of ±1 LSB Gain temperature coefficient is a measure of the change in gain maximum ensures monotonicity. This DAC is guaranteed error with changes in temperature. It is expressed in (ppm of monotonic by design. See Figure 11 to Figure 13 for plots of full-scale range)/°C. typical DNL vs. code. Digital-to-Analog Glitch Impulse Zero-Code Error Digital-to-analog glitch impulse is the impulse injected into the Zero-code error is a measure of the output error when zero analog output when the input code in the DAC register changes code (0x0000) is loaded to the DAC register. Ideally, the output state. It is normally specified as the area of the glitch in nV-s should be 0 V. The zero-code error is always positive in the and is measured when the digital input code is changed by AD5601/AD5611/AD5621 because the output of the DAC cannot 1 LSB at the major carry transition (0x2000 to 0x1FFF). See go below 0 V. Zero-code error is due to a combination of the Figure 19. offset errors in the DAC and output amplifier. Zero-code error Digital Feedthrough is expressed in mV. See Figure 28 for a plot of zero-code error Digital feedthrough is a measure of the impulse injected into vs. temperature. the analog output of the DAC from the digital inputs of the Full-Scale Error DAC, but is measured when the DAC output is not updated. Full-scale error is a measure of the output error when full-scale It is specified in nV-s and is measured with a full-scale code code (0xFFFF) is loaded to the DAC register. Ideally, the output change on the data bus—from all 0s to all 1s and vice versa. should be VDD − 1 LSB. Full-scale error is expressed in mV. See Figure 28 for a plot of full-scale error vs. temperature. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percent of the full-scale range. Rev. F | Page 13 of 24 AD5601/AD5611/AD5621 Data Sheet THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5601/AD5611/AD5621 DACs are fabricated on a The output buffer amplifier is capable of generating rail-to-rail CMOS process. The architecture consists of a string DAC voltages on its output, giving an output range of 0 V to V . It is DD followed by an output buffer amplifier. Figure 39 is a block capable of driving a load of 2 kΩ in parallel with 1000 pF to diagram of the DAC architecture. GND. The source and sink capabilities of the output amplifier V are shown in Figure 25. The slew rate is 0.5 V/µs, with a half- DD scale settling time of 8 µs with the output loaded. REF (+) SERIAL INTERFACE RESISTOR DAC REGISTER V OUT NETWORK The AD5601/AD5611/AD5621 have a 3-wire serial interface REF (–) OUTPUT (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, AMPLIFIER and MICROWIRE interface standards as well as most DSPs. See GND Figure 2 for a timing diagram of a typical write sequence. Figure 39. DAC Architecture SYNC The write sequence begins by bringing the line low. Data from the SDIN line is clocked into the 16-bit shift register on Because the input coding to the DAC is straight binary, the ideal the falling edge of SCLK. The serial clock frequency can be as output voltage is given by high as 30 MHz, making the AD5601/AD5611/AD5621 com- th D   patible with high speed DSPs. On the 16 falling clock edge, V = V ×   OUT DD n the last data bit is clocked in and the programmed function is  2  executed (a change in DAC register contents and/or a change where: SYNC in the mode of operation). At this stage, the line may be D is the decimal equivalent of the binary code that is loaded to kept low or brought high. In either case, it must be brought high the DAC register. for a minimum of 33 ns before the next write sequence so that a n is the bit resolution of the DAC. falling edge of SYNC can initiate the next write sequence. RESISTOR STRING Because the SYNC buffer draws more current when V = 1.8 V IN The resistor string structure is shown in Figure 40. It is simply a than it does when V = 0.8 V, SYNC should be idled low IN string of resistors, each of Value R. The code loaded to the DAC between write sequences for even lower power operation of the register determines at which node on the string the voltage is part, as mentioned previously. However, it must be brought tapped off to be fed into the output amplifier. The voltage is high again just before the next write sequence. tapped off by closing one of the switches connecting the string INPUT SHIFT REGISTER to the amplifier. Because it is a string of resistors, it is guaran- teed monotonic. The input shift register is 16 bits wide (see Figure 41). The first two bits are control bits, which control the operating mode of the part (normal mode or any one of three power-down R modes). For a complete description of the various modes, see the Power-Down Modes section. For the AD5621, the next R 12 bits are the data bits, which are transferred to the DAC th register on the 16 falling edge of SCLK. The information in TO OUTPUT R the last two bits is ignored by the AD5621. See Figure 42 and AMPLIFIER Figure 43 for the AD5611 and AD5601 input shift register map. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the th SYNC 16 falling edge. However, if is brought high before the th R 16 falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a R change in the operating mode occurs (see Figure 44). Figure 40. Resistor String Structure Rev. F | Page 14 of 24 06853-039 06853-038 Data Sheet AD5601/AD5611/AD5621 DB15 (MSB) DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND POWER-DOWN MODES 1 0 100kΩ TO GND 1 1 THREE-STATE Figure 41. AD5621 Input Register Contents DB15 (MSB) DB0 (LSB) X PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND POWER-DOWN MODES 1 0 100kΩ TO GND 1 1 THREE-STATE Figure 42. AD5611 Input Register Contents DB15 (MSB) DB0 (LSB) PD1 PD0 D8 D7 D6 D5 D4 D3 D2 D1 X X X X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND POWER-DOWN MODES 1 0 100kΩ TO GND 1 1 THREE-STATE Figure 43. AD5601 Input Register Contents SCLK SYNC SDIN DB15 DB0 DB15 DB0 INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH SYNC HIGH BEFORE 16 FALLING EDGE ON THE 16 FALLING EDGE Figure 44. SYNC Interrupt Facility Rev. F | Page 15 of 24 06853-042 06853-041 06853-040 06853-043 AD5601/AD5611/AD5621 Data Sheet POWER-ON RESET MICROPROCESSOR INTERFACING AD5601/AD5611/AD5621 to ADSP-2101 Interface The AD5601/AD5611/AD5621 contain a power-on reset circuit that controls the output voltage during power-up. The DAC Figure 46 shows a serial interface between the AD5601/ register is filled with 0s and the output voltage is 0 V. It remains AD5611/AD5621 and the ADSP-2101. The ADSP-2101 should there until a valid write sequence is made to the DAC. This is be set up to operate in SPORT transmit alternate framing mode. useful in applications in which it is important to know the state The ADSP-2101 SPORT is programmed through the SPORT of the DAC output while it is in the process of powering up. control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. POWER-DOWN MODES Transmission is initiated by writing a word to the Tx register The AD5601/AD5611/AD5621 have four separate modes of after the SPORT is enabled. operation. These modes are software-programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows ADSP-2101* AD5601/AD5611/ AD5621* how the state of the bits corresponds to the operating mode of the device. TFS SYNC DT SDIN Table 6. Operating Modes of the AD5601/AD5611/AD5621 SCLK SCLK DB15 DB14 Operating Mode 0 0 Normal operation *ADDITIONAL PINS OMITTED FOR CLARITY Power-down modes: Figure 46. AD5601/AD5611/AD5621 to ADSP-2101 Interface 0 1 1 kΩ to GND 1 0 100 kΩ to GND AD5601/AD5611/AD5621 to 68HC11/68L11 Interface 1 1 Three-state Figure 47 shows a serial interface between the AD5601/AD5611/ AD5621 and the 68HC11/68L11 microcontroller. SCK of the When both bits are set to 0, the part has normal power 68HC11/68L11 drives the SCLK of the AD5601/AD5611/ consumption of 100 µA maximum at 5 V. However, for the AD5621, while the MOSI output drives the serial data line of three power-down modes, the supply current falls to typically SYNC the DAC. The signal is derived from a port line (PC7). 0.2 µA at 3 V. The setup conditions for correct operation of this interface are Not only does the supply current fall, but the output stage is as follows: the 68HC11/68L11 should be configured so that the also internally switched from the output of the amplifier to a CPOL bit is 0 and the CPHA bit is 1. When data is being trans- resistor network of known values. This has the advantage that mitted to the DAC, the SYNC line is taken low (PC7). When the the output impedance of the part is known while the part is in 68HC11/68L11 are configured as indicated, data appearing on power-down mode. the MOSI output is valid on the falling edge of SCK. Serial data There are three different options: the output is connected from the 68HC11/68L11 is transmitted in 8-bit bytes with only internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, eight falling clock edges occurring in the transmit cycle. Data is or the output is left open-circuited (three-stated). Figure 45 transmitted MSB first. To load data to the AD5601/AD5611/ shows the output stage. AD5621, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. RESISTOR AMPLIFIER V STRING DAC OUT 68HC11/ AD5601/AD5611/ 68L11* AD5621* PC7 SYNC POWER-DOWN RESISTOR CIRCUITRY SCK SCLK NETWORK MOSI SDIN Figure 45. Output Stage During Power-Down *ADDITIONAL PINS OMITTED FOR CLARITY The bias generator, output amplifier, resistor string, and other Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power- down is typically 13 µs for VDD = 5 V and 16 µs for VDD = 3 V. See Figure 21 for a plot. Rev. F | Page 16 of 24 06853-044 06853-046 06853-045 Data Sheet AD5601/AD5611/AD5621 AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x and a second write cycle is initiated to transmit the second byte Interface of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first. The Figure 48 shows a serial interface between the AD5601/AD5611/ AD5601/AD5611/AD5621 require data with the MSB as the AD5621 and the Blackfin ADSP-BF53x microprocessor. The first bit received. The 80C51/80L51 transmit routine should ADSP-BF53x processor family incorporates two dual-channel take this into account. synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to 80C51/80L51* AD5601/AD5611/ the AD5601/AD5611/AD5621, the setup for the interface is as AD5621* follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/ P3.3 SYNC AD5621, while TSCLK0 drives the SCLK of the part. The SYNC TxD SCLK is driven from TFS0. RxD SDIN ADSP-BF53x* AD5601/AD5611/ AD5621* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface DT0PRI SDIN TSCLK0 SCLK AD5601/AD5611/AD5621 to MICROWIRE Interface TFS0 SYNC Figure 50 shows an interface between the AD5601/AD5611/ AD5621 and any MICROWIRE-compatible device. Serial data *ADDITIONAL PINS OMITTED FOR CLARITY is shifted out on the falling edge of the serial clock and is Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface clocked into the AD5601/AD5611/AD5621 on the rising edge AD5601/AD5611/AD5621 to 80C51/80L51 Interface of the SK. Figure 49 shows a serial interface between the AD5601/ MICROWIRE* AD5601/AD5611/ AD5611/AD5621 and the 80C51/80L51 microcontroller. The AD5621* setup for the interface is as follows: TxD of the 80C51/80L51 CS SYNC drives SCLK of the AD5601/AD5611/AD5621, while RxD SK SCLK SYNC drives the serial data line of the part. The signal is again SO SDIN derived from a bit programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the *ADDITIONAL PINS OMITTED FOR CLARITY AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, Rev. F | Page 17 of 24 06853-047 06853-049 06853-048 AD5601/AD5611/AD5621 Data Sheet APPLICATIONS CHOOSING A REFERENCE AS POWER SUPPLY FOR BIPOLAR OPERATION USING THE THE AD5601/AD5611/AD5621 AD5601/AD5611/AD5621 The AD5601/AD5611/AD5621 come in tiny LFCSP and SC70 The AD5601/AD5611/AD5621 have been designed for single- packages with less than a 100 µA supply current. Because of supply operation, but a bipolar output range is also possible this, the choice of reference depends on the application using the circuit shown in Figure 52. The circuit in Figure 52 requirements. For applications with space-saving requirements, gives an output voltage range of ±5 V. Rail-to-rail operation at the ADR02 is recommended. It is available in an SC70 package the amplifier output is achievable using an AD820 or OP295 as and has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package) the output amplifier. and provides very good noise performance at 3.4 µV p-p in the 0.1 R2 = 10kΩ Hz to 10 Hz range. +5V +5V R1 = 10kΩ Because the supply current required by the AD5601/AD5611/ AD5621 is extremely low, the parts are ideal for low supply AD820/ +5V OP295 applications. The ADR395 voltage reference is recommended in V V OUT DD this case. It requires less than 100 µA of quiescent current and 10µF 0.1µF AD5601/AD5611/ –5V can, therefore, drive multiple DACs in one system, if required. It AD5621 also provides very good noise performance at 8 µV p-p in the 0.1 Hz to 10 Hz range. 3-WIRE SERIAL 7V INTERFACE 5V Figure 52. Bipolar Operation with the AD5601/AD5611/AD5621 ADR395 The output voltage for any input code can be calculated as D R1+R2 R2         SYNC 3-WIRE V = V × × −V × V = 0V TO 5V OUT       OUT DD DD  N  AD5601/AD5611/ SERIAL SCLK  2   R1  R1   AD5621 INTERFACE SDIN N where D represents the input code in decimal (0 – 2 ). With VDD = 5 V, R1 = R2 = 10 kΩ Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621 10×D Some recommended precision references for use as supplies to   V = − 5 V OUT N the AD5601/AD5611/AD5621 are listed in Table 7. 2   This is an output voltage range of ±5 V, with 0x0000 corre- Table 7. Precision References for the AD5601/AD5611/AD5621 sponding to a −5 V output and 0x3FFF corresponding to a Initial Accuracy Temp Drift 0.1 Hz to 10 Hz +5 V output. Part No. (mV max) (ppm/°C max) Noise (µV p-p typ) ADR435 ±2 3 (R-8) 8 ADR425 ±2 3 (R-8) 3.4 ADR02 ±3 3 (R-8) 10 ADR02 ±3 3 (SC70) 10 ADR395 ±5 9 (TSOT-23) 8 Rev. F | Page 18 of 24 06853-050 06853-051 Data Sheet AD5601/AD5611/AD5621 USING THE AD5601/AD5611/AD5621 WITH A POWER SUPPLY BYPASSING AND GROUNDING GALVANICALLY ISOLATED INTERFACE When accuracy is important in a circuit, it is helpful to carefully In process control applications in industrial environments, consider the power supply and ground return layout on the board. The PCB containing the AD5601/AD5611/AD5621 it is often necessary to use a galvanically isolated interface to should have separate analog and digital sections, each having its protect and isolate the controlling circuitry from any hazardous own area of the board. If the AD5601/AD5611/AD5621 are in a common-mode voltages that might occur in the area where the system where other devices require an AGND-to-DGND DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial connection, the connection should be made at one point only. logic interface, the ADuM1300 3-channel digital isolator This ground point should be as close as possible to the provides the required isolation (see Figure 53). The power AD5601/AD5611/AD5621. supply to the part also needs to be isolated, which is done by The power supply to the AD5601/AD5611/AD5621 should be using a transformer. On the DAC side of the transformer, a 5 V bypassed with 10 µF and 0.1 µF capacitors. The capacitors regulator provides the 5 V supply required for the AD5601/ should be physically as close as possible to the device, with the AD5611/AD5621. 0.1 µF capacitor ideally right up against the device. The 10 µF 5V capacitors are the tantalum bead type. It is important that the REGULATOR POWER 10µF 0.1µF 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 µF capacitor provides a low imped- ance path to ground for high frequencies caused by transient V DD currents due to internal logic switching. SCLK V V SCLK IA OA The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch ADuM1300 AD5601/ AD5611/ effects on the supply line. Clocks and other fast switching V SDI V V SYNC OUT IB OB AD5621 digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, DATA V V SDIN IC OC ensure that they run at right angles to each other to reduce GND feedthrough effects on the board. The best board layout tech- nique is the microstrip technique, where the component side of Figure 53. AD5601/AD5611/AD5621 with a Galvanically Isolated Interface the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a two-layer board. Rev. F | Page 19 of 24 06853-052 AD5601/AD5611/AD5621 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 6 5 4 2.40 1.25 2.10 1 2 3 1.80 1.15 0.65 BSC 1.30 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.22 SEATING 0.10 MAX 0.36 0.30 0.08 PLANE COPLANARITY 0.26 0.15 0.10 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 2.10 1.30 2.00 1.90 0.65 REF 0.20 MIN 4 6 3.10 EXPOSED 1.70 PAD 3.00 1.60 2.90 1.50 PIN 1 INDEX 0.45 AREA 0.40 0.35 3 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 0.05 MAX 0.203 REF THE EXPOSED PAD, REFER TO 0.75 0.00 MIN THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.35 COPLANARITY PLANE 0.30 0.08 0.25 COMPLIANT TOJEDEC STANDARDS MO-229 Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2.00 × 3.00 mm Body, Very Very Thin, Dual Lead (CP-6-5) Dimensions shown in millimeters Rev. F | Page 20 of 24 PIN 1 INDICATOR (R 0.15) 072809-A 10-18-2010-A Data Sheet AD5601/AD5611/AD5621 ORDERING GUIDE Temperature Package 1 Model Range INL Package Description Option Branding AD5601BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V AD5601BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V AD5601BCPZ-RL7 –40°C to +125°C ±0.5 LSB 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-6-5 89 AD5611AKSZ-500RL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U AD5611AKSZ-REEL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U AD5611ACPZ-RL7 –40°C to +125°C ±4.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 8B AD5611BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T AD5611BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T AD5621AKSZ-500RL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S AD5621AKSZ-REEL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S AD5621ACPZ-RL7 –40°C to +125°C ±6.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 88 AD5621BKSZ-500RL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R AD5621BKSZ-REEL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R EVAL-AD5621EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 21 of 24 AD5601/AD5611/AD5621 Data Sheet NOTES Rev. F | Page 22 of 24 Data Sheet AD5601/AD5611/AD5621 NOTES Rev. F | Page 23 of 24 AD5601/AD5611/AD5621 Data Sheet NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06853-0-2/12(F) Rev. F | Page 24 of 24