ANALOG DEVICES AD5582

Quad, Parallel Input, Voltage Output, a 12-/10-Bit Digital-to-Analog Converters AD5582/AD5583 FEATURES AD5582 FUNCTIONAL BLOCK DIAGRAM 12-Bit Linearity and Monotonic AD5582 V V V V V V DD3 SS3 REFLA REFHA REFLB REFHB 10-Bit Linearity and Monotonic AD5583 38 37 10 9 7 8 Wide Operating Range: Single 5 V to 15 V or 3 V DD1 Dual �5 V Supply 33 AD5582 A1 ADDR 4 DECODE V SS1 Unipolar or Bipolar Operation 32 A0 + 5 VOA Double Buffered Registers Enable Independent or – 31 DB11 Simultaneous Multichannel Update DB10 30 4 Independent Rail-to-Rail Reference Inputs 2 VOB DB9 29 20 mA High Current Output Drive 28 DB8 I Parallel Interface N 26 D DB7 11 R1 T O DAC Data Readback Capability IN E 20k� DB6 25 REG REG R 5 �s Settling Time D 12 I RCT F DB5 24 A 20k� Built-In Matching Resistor Simplifies C 23 DB4 13 R2 E Negative Reference 21 DB3 Unconditionally Stable Under Any Capacitive Loading 1 AGND1 20 DB2 4 4 Compact Footprint: TSSOP-48 DB1 19 48 AGND2 Extended Temperature Range: �40�C to �125�C OE 18 DB0 47 VOC APPLICATIONS 34 CS Process Control Equipment 35 R/W CONTROL Closed-Loop Servo Control LOGIC DV 14 DD – Data Acquisition Systems 44 VOD 17 MSB + Digitally Controlled Calibration 46 V DD2 Optical Network Control Loops RS 16 45 V 4 m to 20 mA Current Transmitter 15 SS2 LDAC 22 27 36 40 39 41 42 GENERAL DESCRIPTION DGND1 DGND2 DGND3 V V V V REFHD REFLD REFHC REFLC The AD5582/AD5583 family of quad, 12-/10-bit, voltage output digital-to-analog converters is designed to operate from a single 5 V to 15 V or dual ±5 V supply. It offers the user ease of use in �2.5V AD5582/AD5583 single- or dual-supply systems. Built using an advance BiCMOS ADR421 V REFHA REF �2.5V DAC A process, this high performance DAC is dynamically stable, capable V REFHB of high current drive, and in small form factor. V REFHC V �2.5V REFHD DAC B The applied external reference V determines the full-scale out- REF R1 put voltage ranges from V to V , resulting in a wide selection SS DD R2 RCT of full-scale outputs. For multiplying and wide dynamic appli- �2.5V DAC C cations, ac reference inputs can be as high as |V – V |. Two V DD SS REFLA – V REFLB built-in precision trimmed resistors are available and can be V + �2.5V REFLC DAC D configured easily to provide four-quadrant multiplications. �2.5V V REFLD A doubled-buffered parallel interface offers a fast settling time. A common level sensitive load DAC strobe (LDAC) input allows DIGITAL CIRCUITRY OMITTED FOR CLARITY additional simultaneous update of all DAC outputs. An external Figure 1. Using Built-In Matching Resistors asynchronous reset (RS) forces all registers to the zero code state to Generate a Negative Voltage Reference when the MSB = 0 or to midscale when the MSB = 1. Both parts are offered in the same pinout and package to allow The AD5582 is well suited for DAC8412 replacement in medium users to select the appropriate resolution for a given application voltage applications in new designs, as well as any other general without PCB layout changes. purpose multichannel 10- to 12-bit applications. The AD5582/AD5583 are specified over the extended industrial (–40∞C to +125∞C) temperature range and offered in a thin and REV. A compact 1.1 mm TSSOP-48 package. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD5582/AD5583–SPECIFICATIONS (V = +5 V, V = –5 V, DV = +5 V � 10%, V = +2.5 V, V = –2.5 V, DD SS DD REFH REFL ELECTRICAL CHARACTERISTICS –40�C < T < +125�C, unless otherwise noted.) A 1 Parameter Symbol Condition Min Typ Max Unit STATIC PERFORMANCE 2 Resolution N AD5582 12 Bits AD5583 10 Bits 3 Relative Accuracy INL –1 +1 LSB 3 Differential Nonlinearity DNL Monotonic –1 LSB Zero-Scale Error V Data = 000 for AD5582 –2 +2 LSB ZSE H and AD5583 Gain Error V Data = 0xFFF for AD5582 –2 +2 LSB GE H V Data = 0x3FF for AD5583 –4 +4 LSB GE H Gain Error V V = 2.7 V to 4.5 V –4 +4 LSB GE DD 4 Full-Scale Tempco TCV 1.5 ppm/∞C FS REFERENCE INPUT V Input Range V V + 0.5 V V REFH REFH REFL DD 5 V Input Range V V V – 0.5 V REFL REFL SS REFH 1 Input Resistance R Data = 555 (Minimum R)12 20 kW REF H REF for AD5582 and 155 for AD5583 H 4 Input Capacitance C 80 pF REF REF Input Current I Data = 555 for AD5582 500 mA REF H REF Multiplying Bandwidth BW Code = Full Scale 1.3 MHz REF R1–R2 Matching R1/R2 AD5582 ±0.025 % AD5583 ±0.100 % ANALOG OUTPUT 6 Output Current I Data = 800 for AD5582 and ±2mA OUT H 200 for AD5583, �V £ 2 mV H OUT 6 Output Current I Data = 800 for AD5582 and OUT H 200 for AD5583, �V £ |–8 mV| +20 mA H OUT �V £ ±15 mV –20 mA OUT 4, 7 Capacitive Load C No Oscillation Note 7 pF L LOGIC INPUTS Logic Input Low Voltage V DV = 5 V ± 10% 0.8 V IL DD DV = 3 V ± 10% 0.4 V DD Logic Input High Voltage V DV = 5 V ± 10% 2.4 V IH DD DV = 3 V ± 10% 2.1 V DD Input Leakage Current I 0.01 1 mA IL 4 Input Capacitance C 5pF IL Output Voltage High V I = –0.8 mA 2.4 V OH OH Output Voltage Low V I = 1.2 mA, T = 85∞C, 0.4 V OL OL A I = 0.6 mA, DV = 3 V OL DD I = 1.0 mA, T = 125∞C, 0.4 V OL A I = 0.5 mA, DV = 3 V OL DD AC CHARACTERISTICS Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms to Zero Scale 8 Settling Time t To ±0.1% of Full Scale 5 ms S DAC Glitch Q Code 7FF to 800 to 7FF 100 nV-s H H H for AD5582 and 1FF to 200 H H to 1FF for AD5583 H Digital Feedthrough V /t Data = Midscale, CS Toggles at 5 nV-s OUT CS f = 16 MHz Analog Crosstalk V /V V = 1.5 V dc + 1 V p-p, –80 dB OUT REF REF Data = 000 , f = 100 kHz H Output Noise e f = 1 kHz 33 nV/÷Hz N –2– REV. A AD5582/AD5583 1 Parameter Symbol Condition Min Typ Max Unit SUPPLY CHARACTERISTICS Single-Supply Voltage Range V V = 0 V 3 18 V DD SS Dual-Supply Voltage Range V /V V = +2.7 V to +6.5 V, –9 +9 V DD SS DD V = –6.5 V to –2.7 V SS Digital Logic Supply DV 2.7 8 V DD 6 Positive Supply Current I V = 0 V, No Load 1.7 3 mA DD IL Negative Supply Current I V = 0 V, No Load 1.5 3 mA SS IL Power Dissipation P V = 0 V, No Load 16 30 mW DISS IL Power Supply Sensitivity P �V = ±5% 30 ppm/V SS DD NOTES 1 Typical specifications represent average readings measured at 25∞C. 2 N DAC Output Equation: V = V + [(V – V ) � D/2 ], where D = data loaded in corresponding DAC Register A, B, C, D, and N equals the number of bits; OUT REFL REFH REFL AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V – V )/4096 V and (V – V )/1024 V for AD5582 and AD5583, respectively. REFH REFL REFH REFL 3 The first two codes (000 , 001 ) of the AD5583 and the first four codes (000 , 001 , 002 , 003 ) of the AD5582 are excluded from the linearity error measurement H H H H H H in single-supply operation. 4 These parameters are guaranteed by design and not subject to production testing. 5 Dual-supply operation, V = V , exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors. REFL SS 6 Short circuit output and supply currents are 24 mA and 25 mA, respectively. 7 Part is stable under any capacitive loading conditions. 8 The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation. Specifications subject to change without notice. (V = 15 V, V = 0 V, DV = 5 V � 10%, V = 10 V, V = 0 V, DD SS DD REFH REFL ELECTRICAL CHARACTERISTICS –40�C < T < +125�C, unless otherwise noted.) A 1 Parameter Symbol Condition Min Typ Max Unit STATIC PERFORMANCE 2 Resolution N AD5582 12 Bits AD5583 10 Bits 3 Relative Accuracy INL –1 +1 LSB 3 Differential Nonlinearity DNL Monotonic –1 LSB Zero-Scale Error V Data = 000 for AD5582 –2 +2 LSB ZSE H and AD5583 Gain Error V Data = 0xFFF for AD5582 –2 +2 LSB GE H V Data = 0x3FF for AD5583 –4 +4 LSB GE H 4 Full-Scale Tempco TCV 1.5 ppm/∞C FS REFERENCE INPUT V Input Range V V + 0.5 V V REFH REFH REFL DD 5 V Input Range V V V – 0.5 V REFL REFL SS REFH 1 Input Resistance R Data = 555 (Minimum R)12 20 kW REF H REF for AD5582 and 155 for AD5583 H 4 Input Capacitance C 80 pF REF REF Input Current I Data = 555 for AD5582 1000 mA REF H REF Multiplying Bandwidth BW Code = Full Scale 1.3 MHz REF R1–R2 Matching R1/R2 AD5582 ±0.025 % AD5583 ±0.100 % ANALOG OUTPUT 6 Output Current I Data = 800 for AD5582 and 2 mA OUT H 200 for AD5583, �V £ 2 mV H OUT 6 Output Current I Data = 800 for AD5582 and OUT H 200 for AD5583, �V £ |–8 mV| +20 mA H OUT �V £ 15 mV –20 mA OUT 4, 7 Capacitive Load C No Oscillation Note 7 pF L REV. A –3– AD5582/AD5583 ELECTRICAL CHARACTERISTICS (continued) 1 Parameter Symbol Condition Min Typ Max Unit LOGIC INPUTS/OUTPUTS Logic Input Low Voltage V 0.8 V IL DV = 3 V ± 10% 0.4 V DD Logic Input High Voltage V 2.4 V IH DV = 3 V ± 10% 2.1 V DD Input Leakage Current I mA IL 4 Input Capacitance C pF IL Output Voltage High V I = –0.8 mA 2.4 V OH OH Output Voltage Low V I = 1.2 mA, T = 85�C, 0.4 V OL OL A I = 0.6 mA, DV = 3 V OL DD V I = 1.0 mA, T = 125�C, 0.4 V OL OL A I = 0.5 mA, DV = 3 V OL DD AC CHARACTERISTICS Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms to Zero Scale 8 Settling Time t To ±0.1% of Full Scale 14 ms S DAC Glitch Q Code 7FF to 800 to 7FF for 100 nV-s H H H AD5582 and 1FF to 200 to H H 1FF for AD5583 H Digital Feedthrough V /t Data = Midscale, CS Toggles at 5 nV-s OUT CS f = 16 MHz Analog Crosstalk V /V V = 1.5 V dc + 1 V p-p, –80 dB OUT REF REF Data = 000 , f = 100 kHz H Output Noise e f = 1 kHz 33 nV/÷Hz N SUPPLY CHARACTERISTICS Single-Supply Voltage Range V V = 0 V 3 16.5 V DD SS Dual-Supply Voltage Range V /V V = +2.7 V to +6.5 V, –6.5 +6.5 V DD SS DD V = –6.5 V to –2.7 V SS Digital Logic Supply DV 2.7 6.5 V DD 6 Positive Supply Current I V = 0 V, No Load 2.3 3.5 mA DD IL Power Dissipation P V = 0 V, No Load 34.5 52.5 mW DISS IL Power Supply Sensitivity PSS �V = ±5% 30 ppm/V DD NOTES 1 Typical specifications represent average readings measured at 25∞C. 2 N DAC Output Equation: V = V + [(V – V ) � D/2 ], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of OUT REFL REFH REFL bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V – V )/4096 V and = (V – V )/1024 V for AD5582 and AD5583, respectively. REFH REFL REFH REFL 3 The first two codes (000 , 001 ) of the AD5583 and the first four codes (000 , 001 , 002 , 003 ) of the AD5582 are excluded from the linearity error measurement H H H H H H in single-supply operation. 4 These parameters are guaranteed by design and not subject to production testing. 5 Dual-supply operation, V = V , exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors. REFL SS 6 Short circuit output and supply currents are 24 mA and 25 mA, respectively. 7 Part is stable under any capacitive loading conditions. 8 The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation. Specifications subject to change without notice. –4– REV. A AD5582/AD5583 (V = 15 V or 5 V, V = 0 V, DV = 5 V � 10%, V = 10 V, V = 0 V, –40�C < T < +125�C, DD SS DD REFH REFL A TIMING CHARACTERISTICS unless otherwise noted.) Parameter Symbol Condition Min Typ Max Unit INTERFACE TIMING* Chip Select Write Pulse Width t 20 ns WCS Chip Select Read Pulse Width t 130 ns RCS Write Setup t 35 ns WS Write Hold t 0ns WH Address Setup t 35 ns AS Address Hold t 0ns AH Load Setup t 0ns LS Load Hold t 0ns LH Write Data Setup t 35 ns WDS Write Data Hold t 0ns WDH Load Data Pulse Width t 20 ns LDW Reset Pulse Width t 20 ns RESET Read Data Hold t 0ns RDH Read Data Setup t 0ns RDS Data to Hi-Z t C = 10 pF 100 ns DZ L Chip Select to Data t C = 10 pF 100 ns CSD L Chip Select Repetitive Pulse Width t 10 ns CSP Load Setup in Double Buffer Mode t 20 ns LDS Load Data Hold t 0ns LDH *All input control signals are specified with t = t = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F Specifications subject to change without notice. (V = 15 V or 5 V, V = 0 V, DV = 3 V � 10%, V = 10 V, V = 0 V, –40�C < T < +125�C, DD SS DD REFH REFL A TIMING CHARACTERISTICS unless otherwise noted.) Parameter Symbol Condition Min Typ Max Unit INTERFACE TIMING* Chip Select Write Pulse Width t 35 ns WCS Chip Select Read Pulse Width t 130 ns RCS Write Setup t 50 ns WS Write Hold t 0ns WH Address Setup t 50 ns AS Address Hold t 0ns AH Load Setup t 0ns LS Load Hold t 0ns LH Write Data Setup t 50 ns WDS Write Data Hold t 0ns WDH Load Data Pulse Width t 35 ns LDW Reset Pulse Width t 35 ns RESET Read Data Hold t 0ns RDH Read Data Setup t 0ns RDS Data to Hi-Z t C = 10 pF 80 100 ns DZ L Chip Select to Data t C = 10 pF 80 100 ns CSD L Chip Select Repetitive Pulse Width t 20 ns CSP Load Setup in Double Buffer Mode t 35 ns LDS Load Data Hold t 0ns LDH *All input control signals are specified with t = t = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F Specifications subject to change without notice. REV. A –5– AD5582/AD5583 ABSOLUTE MAXIMUM RATINGS* Thermal Resistance Junction to Case, � . . . . . . . . . . 42∞C/W JC V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V Maximum Junction Temperature (T Max) . . . . . . . . . . 150∞C DD SS J V to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V Package Power Dissipation = (T Max – T )/� DD J A JA V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –9 V Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C SS V to V . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C DD REF+ V to V . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V Lead Temperature REF– SS V to V . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V RV-48 (Soldering, 60 secs) . . . . . . . . . . . . . . . . . . . . 300∞C REFH REFL DV to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V DD *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the Logic Inputs to GND . . . . . . . . . . . V – 0.3 V, V + 0.3 V SS DD device at these or any other conditions above those indicated in the operational V to GND . . . . . . . . . . . . . . . . . V – 0.3 V, V + 0.3 V OUT SS DD sections of this specification is not implied. Exposure to absolute maximum rating I Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 24 mA OUT conditions for extended periods may affect device reliability. Thermal Resistance Junction to Ambient, � . . . . . . 115∞C/W JA 1 ORDERING GUIDE Resolution Temperature Package Package Container Top 2 Model (Bits) Range Description Option Quantity Marking 1 AD5582YRV-REEL 12 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5582Y AD5583YRV-REEL 10 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5583Y 1 AD5582YRV 12 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5582Y AD5583YRV 10 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5583Y NOTES 1 The AD5582 contains 4116 transistors. The die size measures 108 mil � 144 mil. 2 First row marking is shown in the table above. Second row marking contains date code in YYWW format. Third row marking contains the lot number. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. –6– REV. A AD5582/AD5583 AD5582 PIN CONFIGURATION AGND1 1 48 AGND2 2 47 VOB VOC V 3 46 V DD1 DD2 V 4 45 V SS1 SS2 VOA 5 44 VOD NC 6 43 NC V 7 42 V REFLB REFLC V 8 41 V REFHB REFHC V 9 40 V REFHA REFHD V 10 39 V REFLA REFLD AD5582 R1 11 38 V TOP VIEW DD3 (Not to Scale) RCT 12 37 V SS3 R2 13 36 DGND3 DV 14 35 R/W DD 15 34 LDAC CS 16 33 A1 RS MSB 17 32 A0 DB0 18 31 DB11 DB1 19 30 DB10 DB2 20 29 DB9 21 28 DB3 DB8 DGND1 22 27 DGND2 DB4 23 26 DB7 DB5 24 25 DB6 NC = NO CONNECT AD5582 PIN FUNCTION DESCRIPTIONS* Pin Pin No. Mnemonic Description No. Mnemonic Description 1 AGND1 Analog Ground for DAC A and B 25 DB6 Data Bit 6 2 VOB DAC B Output 26 DB7 Data Bit 7 3V Positive Power Supply for DAC A and B 27 DGND2 Digital Ground 2 DD1 4V Negative Power Supply for DAC A and B 28 DB8 Data Bit 8 SS1 5 VOA DAC A Output 29 DB9 Data Bit 9 6NCNo Connect 30 DB10 Data Bit 10 7V DAC B Voltage Reference Low Terminal 31 DB11 Data Bit 11 REFLB 8V DAC B Voltage Reference High Terminal 32 A0 Address Input 0 REFHB 9V DAC A Voltage Reference High Terminal 33 A1 Address Input 1 REFHA 10 V DAC A Voltage Reference Low Terminal 34 CS Chip Select, Active Low REFLA 11 R1 R1 Terminal (for Negative Reference) 35 R/W Read/Write Mode Select 12 RCT Center Tap Terminal (for Negative Reference) 36 DGND3 Digital Ground 3 13 R2 R2 Terminal (for Negative Reference) 37 V Negative Power Supply for Analog Switches SS3 14 DV Power Supply for Digital Circuits 38 V Positive Power Supply for Analog Switches DD DD3 15 LDAC DAC Register Load, Active Low Level Sensitive 39 V DAC D Voltage Reference Low Terminal REFLD 16 RS Reset Strobe 40 V DAC D Voltage Reference High Terminal REFHD 17 MSB MSB = 0, Reset to 000 . 41 V DAC C Voltage Reference High Terminal H REFHC MSB = 1, Reset to 800 . H 42 V DAC C Voltage Reference Low Terminal REFLC 18 DB0 Data Bit 0 43 NC No Connect 19 DB1 Data Bit 1 44 VOD DAC D Output 20 DB2 Data Bit 2 45 V Negative Power Supply for DAC C and D SS2 21 DB3 Data Bit 3 46 V Positive Power Supply for DAC C and D DD2 22 DGND1 Digital Ground 1 47 VOC DAC C Output 23 DB4 Data Bit 4 48 AGND2 Analog Ground for DAC C and D 24 DB5 Data Bit 5 *AD5582 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5. REV. A –7– AD5582/AD5583 AD5583 PIN CONFIGURATION AGND1 1 48 AGND2 2 47 VOB VOC V 3 46 V DD1 DD2 V 4 45 V SS2 SS1 VOA 5 44 VOD NC 6 43 NC V 7 42 V REFLB REFLC V 8 41 V REFHB REFHC V 9 40 VREFHD REFHA V 10 39 V REFLA REFLD AD5583 11 38 R1 V TOP VIEW DD3 (Not to Scale) RCT 12 37 V SS3 R2 13 36 DGND3 DV 14 35 R/W DD 15 34 LDAC CS 16 33 A1 RS MSB 17 32 A0 NC 18 31 DB9 NC 19 30 DB8 DB0 20 29 DB7 21 28 DB1 DB6 DGND1 22 27 DGND2 DB2 23 26 DB5 DB3 24 25 DB4 NC = NO CONNECT AD5583 PIN FUNCTION DESCRIPTIONS* Pin Pin No. Mnemonic Description No. Mnemonic Description 1 AGND1 Analog Ground for DAC A and B 25 DB4 Data Bit 4 2 VOB DAC B Output 26 DB5 Data Bit 5 3V Positive Power Supply for DAC A and B 27 DGND2 Digital Ground 2 DD1 4V Negative Power Supply for DAC A and B 28 DB6 Data Bit 6 SS1 5 VOA DAC A Output 29 DB7 Data Bit 7 6NCNo Connect (Do Not Connect Anything 30 DB8 Data Bit 8 other than Dummy Pad) 31 DB9 Data Bit 9 7V DAC B Voltage Reference Low Terminal 32 A0 Address Input 0 REFLB 8V DAC B Voltage Reference High Terminal 33 A1 Address Input 1 REFHB 9V DAC A Voltage Reference High Terminal 34 CS Chip Select, Active Low REFHA 10 V DAC A Voltage Reference Low Terminal 35 R/W Read/Write Mode Select REFLA 11 R1 R1 Terminal (for Negative Reference) 36 DGND3 Digital Ground 3 12 RCT Center Tap Terminal (for Negative Reference) 37 V Negative Power Supply for Analog Switches SS3 13 R2 R2 Terminal (for Negative Reference) 38 V Positive Power Supply for Analog Switches DD3 14 DV Power Supply for Digital Circuits 39 V DAC D Voltage Reference Low Terminal DD REFLD 15 LDAC DAC Register Load, Active Low Level Sensitive 40 V DAC D Voltage Reference High Terminal REFHD 16 RS Reset Strobe 41 V DAC C Voltage Reference High Terminal REFHC 17 MSB MSB = 0, Reset to 000 . 42 V DAC C Voltage Reference Low Terminal H REFLC MSB = 1, Reset to 200 . 43 NC No Connect (Do Not Connect Anything H 18 NC No Connect (Do Not Connect Anything other than Dummy Pad) other than Dummy Pad) 44 VOD DAC D Output 19 NC No Connect (Do Not Connect Anything 45 V Negative Power Supply for DAC C and D SS2 other than Dummy Pad) 46 V Positive Power Supply for DAC C and D DD2 20 DB0 Data Bit 0 47 VOC DAC C Output 21 DB1 Data Bit 1 48 AGND2 Analog Ground for DAC C and D 22 DGND1 Digital Ground 1 23 DB2 Data Bit 2 24 DB3 Data Bit 3 *AD5583 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5. –8– REV. A AD5582/AD5583 TIMING DIAGRAMS t = 10ns CSP t = 20ns WCS CS t = 0ns t = 35ns WS WH R/W t = 35ns AS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ONE TWO THREE FOUR t = 0ns t = 0ns LS LH LDAC t = 0ns WDH t = 35ns WDS DATA1 DATA2 DATA3 DATA4 DATA IN VALID VALID VALID VALID Figure 2a. Single Buffer Mode, Output Updated Individually, DV = 5 V DD t = 10ns CSP t = 20ns WCS CS t = 35ns t = 0ns WH WS R/W t = 35ns AS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ONE TWO THREE FOUR t = 0ns LDH t = 0ns LDS LDAC t = 20ns LDW t = 35ns t = 0ns WDS WDH DATA1 DATA2 DATA3 DATA4 DATA IN VALID VALID VALID VALID Figure 2b. Double Buffer Mode, Output Updated Simultaneously, DV = 5 V DD REV. A –9– AD5582/AD5583 t = 20ns WCS CS t = 35ns WS t = 0ns WH R/W t = 0ns AH t = 35ns AS A0/A1 t = 20ns LDW t = 0ns t = 0ns LH LS LDAC t = 35ns t = 0ns WDS WDH DATA IN t = 20ns RESET RS Figure 2c. Data Write (Input and Output Registers) Timing t = 130ns RCS CS t = 35ns t = 0ns RDS RDH R/W t = 35ns AS t = 0ns AH A0/A1 t = 100ns MAX t = 100ns MAX CSD DZ DATA OUT HI-Z DATA VALID HI-Z Figure 2d. Data Output (Read Timing) –10– REV. A Typical Performance Characteristics–AD5582/AD5583 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0512 1024 1536 2048 2560 3072 3584 4096 0128 2565 38412 640768 896 1024 CODE (Decimal) CODE (Decimal) TPC 1. AD5582 Integral Nonlinearity Error TPC 4. AD5583 Differential Nonlinearity Error 1.0 6 V = 5V DD 0.8 V = 0V SS V = 0V 4 REFL 0.6 NO LOAD 0.4 2 INL 0.2 ZSE 0 0 –0.2 DNL GE –2 –0.4 –0.6 –4 –0.8 –1.0 –6 0 512 1024 1536 2048 2560 3072 3584 4096 05 10 15 20 25 30 CODE (Decimal) V – V (mV) DD REFH TPC 2. AD5582 Differential Nonlinearity Error TPC 5. AD5582 INL, DNL, ZSE, and GE at Positive Rail-to-Rail Operation 1.0 4 V = +5V DD 0.8 V = –5V SS 3 V = +4V REFH ZSE 0.6 NO LOAD 2 0.4 1 0.2 DNL DAC-A DAC-B 0 0 –0.2 –1 INL –0.4 DAC-C –2 DAC-D GE –0.6 –3 –0.8 –1.0 –4 0128 256 384 512 640 768 896 1024 05 10 15 20 25 30 35 CODE (Decimal) V – V (mV) REFL SS TPC 3. AD5583 Integral Nonlinearity Error TPC 6. AD5582 INL, DNL, GE, and ZSE at Negative Rail-to-Rail Operation REV. A –11– INL (LSB) DNL ( LSB) INL (LSB) DNL (LSB) ERROR (LSB) ERROR (LSB) AD5582/AD5583 1.0 40 V = �5V DD ZERO ZERO 0.8 V = �5V SS 30 SCALE SCALE V = �4V REFH ERROR ERROR 0.6 V = 0V REFL 20 R = NO LOAD L 0.4 V > V V = V REFL SS REFL SS R = 260� L 10 0.2 0 0 –0.2 –10 R = 790� L –0.4 R = 390� –20 L GAIN GAIN –0.6 ERROR ERROR –30 RESISTIVE LOAD R IS BETWEEN L PULL-UP RESISTIVE LOAD R –0.8 L V AND GND OUT IS BETWEEN V AND V DD OUT –40 –1.0 100 1k 10k 100k 1M 0 512 1024 1536 2048 2560 3072 3584 4096 R _PU (�) L CODE (Decimal) TPC 7. AD5582 INL at Various Resistive Loads TPC 10. AD5582 Gain and Zero-Scale Error vs. Pull-Up Resistive Loads 0.5 5.0 V = �5V DD 0.4 V = �5V SS 4.5 V = �4V REFH 0.3 V = 0V REFL 4.0 0.2 3.5 R = NO LOAD L 0.1 3.0 0 2.5 –0.1 2.0 R = 260� L –0.2 1.5 INL –0.3 1.0 RESISTIVE LOAD R IS BETWEEN L DNL –0.4 V AND GND 0.5 OUT –0.5 0 512 1024 1536 2048 2560 3072 3584 4096 0 02 4 6 8 10 12 CODE (Decimal) V – V (V) REFH REFL TPC 8. AD5582 DNL at Various Resistive Loads TPC 11. AD5582 Linearity Errors vs. Differential Reference Ranges 0 2.00 1.95 –2 V = +5V OR +15V DD 1.90 V = –5V OR 0V SS –4 V = 0V SS V = +4V REFH 1.85 V = +4V REFH V = 0V REFL V = 0V REFL –6 1.80 V = +5V DD –8 1.75 V = –5V SS V = +15V DD V = +4V REFH V = 0V SS 1.70 –10 V = +10V REFH V = 0V 1.65 REFL –12 1.60 –14 RESISTIVE LOAD R IS BETWEEN L 1.55 V AND GND OUT –16 1.50 100 1k 10k 100k 02 4 6 8 10 12 14 16 R (�) L V (V) DD TPC 9. AD5582 Gain Error vs. Resistive Load TPC 12. AD5582 Supply Current vs. Supply Voltage –12– REV. A DNL (LSB) INL (LSB) GAIN ERROR (LSB) I (mA) LINEARITY ERROR (LSB) DD ERROR (LSB) AD5582/AD5583 3.5 300 V = 5V DD V = 0V SS 3.0 250 V = 4V REFH V = 0V REFL 2.5 200 V = +15V DD V = +5V DD 2.0 V = 0V SS V = –5V SS V = 0V 150 REFL V = –5V REFL 1.5 V = +5V 100 DD V = 0V 1.0 SS V = 0V REFL 50 0.5 0 0 0 512 1024 1536 2048 2560 3072 3584 4096 –10 –5 0 5 10 15 20 CODE (Decimal) V (V) REFH TPC 13. AD5582 Supply Current vs. Reference Voltage TPC 16. AD5582 Reference Current 4.0 140 V = �15V DD V = 0V SS 3.5 120 V = �10V REFH V = 0V REFL 3.0 100 2.5 80 2.0 60 1.5 V = �5V DD V = �5V SS 40 V = �4V 1.0 REFH V = 0V REFL 20 0.5 0 0 –60 –40 –2004 200 6080 100 120 140 0 512 1024 1536 2048 2560 3072 3584 4096 TEMPERATURE (�C) CODE (Decimal) TPC 14. AD5582 Supply Current vs. Temperature TPC 17. AD5582 Referenced Input Resistance 20 6 V = 5V OR 15V DD V = 5V 0.5V DD 18 DV = 3V DD V = 0V SS V = 0V SS 5 V = 4V REF 16 DATA = 800 H V = 5V OR 15V DD 14 DV = 5V DD 4 V = 0V SS 12 10 3 8 2 6 4 1 2 0 0 01 2 3 4 5 10k 100k 1M 10M 100M V (V) CLOCK FREQUENCY (Hz) IH TPC 15. AD5582 Supply Current vs. Logic Input Voltage TPC 18. AD5582 Supply Current vs. Clock Frequency REV. A –13– I (mA) I (mA) DD DD I (mA) DD SUPPLY CURRENT (mA) R (k�) REFERENCE CURRENT (�A) REF AD5582/AD5583 –100 V = �5V � 0.5V DD –90 V = 0V DATA 5V/DIV SS V = �4V REF 100 –80 DATA = 800 90 H –70 V = 5V DD V = 0V –60 SS V = 2.5V REFH –50 10 –40 0 –30 –20 –10 5�s/DIV V 0.5V/DIV OUT 0 110 100 1k 10k 100k 1M GRAPH <1> : C = 0 L FREQUENCY (Hz) GRAPH <2> w/RINGING : C = 10nF L TPC 19. AD5582 PSRR vs. Frequency TPC 22. Large Signal Settling When Loaded (See Test Circuit 1) V 200mV/DIV OUT V 200mV/DIV 2�s/DIV V 0.1V/DIV 5�s/DIV REF OUT TPC 20. Small Signal Response Operating TPC 23. Midscale Transition Glitch at Near Rail, C = 2 nF (See Test Circuit 1) L – 3980 V = 15V R = 30Hz DD BW – 1260 V = 0V 33nV/ Hz @ 1kHz SS 100 V = 10V – REFH 398 90 126 23004 V 2V/DIV OUT 7285 39.90 12.60 2300 10 4.00 730 0 1.26 230 0.40 73 0.13 23 5�s/DIV DATA 5V/DIV 0.04 7.3 1Hz 2kHz TPC 21. Large Signal Settling TPC 24. AD5582 Output Noise Density –14– REV. A PSRR (dB) AMPLITUDE (�V) NOISE DENSITY (nV/ Hz) AD5582/AD5583 FFF 0 0.8 H 800 H V = +5V DD 400 H V = –5V SS 0.6 200 H V = +4V REFH 100 –24 H V = –4V REFL 080 0.4 H 040 H ZSE DRIFT 020 H 0.2 010 –48 +3� H 008 H 004 H 0 –3� 002 H 001 –72 H –0.2 +3� –0.4 000 –96 –3� GE DRIFT H –0.6 –0.8 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 FREQUENCY (Hz) HOURS OF OPERATION AT 150�C TPC 25. AD5582 Multiplying Bandwidth TPC 26. AD5582 Long-Term Drift Test Circuit V DD 1k� V OUT DAC C 1k� L Test Circuit 1 THEORY OF OPERATION These DACs feature double buffers, which allow both synchro- The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel nous and asynchronous channels update with additional data input DACs in compact TSSOP-48 packages. readback capability. These parts can be reset to zero scale or mid- scale controlled by the RS and MSB pins. When RS is activated, Each DAC is a voltage switching, high impedance (R = 20 kW), the MSB of 0 resets the DACs to zero scale and the MSB of 1 R-2R ladder configuration with segmentation to optimize die resets the DACs to midscale. The ability to operate from wide area and precision. Figure 3 shows a simplified R-2R structure supply voltages, +5 V to +15 V or ±5 V, with multiplying bipolar without the segmentation. The 2R resistances are switched references is another key feature of these DACs. between V and V , and the output is obtained from REFH REFL the rightmost ladder node. As the code is sequenced through R R R + all possible states, the voltage of this node changes in steps of V – O N (2/3 V – V )/(2 – 1) starting from the lowest V and 2R 2R 2R 2R 2R 2R R REFH REFL REFL going to the highest V – DUTLSB. Buffering it with an REFH 2R amplifier with a gain of 1.5 brings the output to: SW0 SW1 SW2 SWn–3 SWn–1 D V = VV – +V (1) ()() OUT REFH REFL REFL N 21 – V REFL + + V REFH where D is the decimal equivalent of the data bits and N is the b0 b1 b2 bn–2 bn–1 – – numbers of bits. If –V is equal to V as V , V is simplified to: REFL REFH REF OUT Figure 3. Simplified R-2R Architecture (Segmentation Not Shown) Ê 2D ˆ V = – 1 V Power Supplies Á ˜ OUT REF (For AD5582) (2) Ë 4095 ¯ There are three separate power supplies needed for the opera- tion of the DACs. For dual supply, V can be set from –6.5 V SS to –2.7 V and V can be set from +2.7 V to +6.5 V. For single DD Ê 2D ˆ V = – 1 V Á ˜ supply, V should be set at 0 V while V is set from 3 V to OUT REF (For AD5583) (3) SS DD Ë 1023 ¯ 16.5 V. However, setting the single supply of V below 4.5 V DD can impact the overall accuracy of the device. The advantage of this scheme is that it allows the DAC to inter- polate between two voltages for differential references or single-ended reference. REV. A –15– ATTENUATION (dB) ERROR (LSB) AD5582/AD5583 Since these DACs can be operated at high voltages, the digital Reset signal levels are therefore controlled separately by the provision The RS function can be used either at power-up or at any time of DV . DV can be set as low as 2.7 V but no greater than during operation. The RS function has priority over any other DD DD 6.5 V. This allows the DAC to be operable from low level digital digital inputs. This pin is active low and sets the DAC output signals generated from a wide range of microcontrollers, FPGA, registers to either zero scale or midscale, determined by the state and signal processors. of the MSB. The reset to midscale is useful when the DAC is configured for bipolar references and the output will be reset to 0 V. Reference Input All four channels of DACs allow independent and differential Output Amplifiers reference voltages. The flexibility of independent references Unlike many voltage output DACs, the AD5582/AD5583 feature allows users to apply a unique reference voltage to each channel. buffered voltage outputs with high output current driving capa- Similarly, bipolar references can be applied across the differential bility. Each output is capable of both sourcing and sinking ±20 mA, references. To maintain optimum accuracy, the difference between eliminating the need for external buffers when driving any capaci- V and V should be greater than 1 V. See TPC 11. tive loads without oscillation. These amplifiers also have short REFH REFL circuit protection. The voltages applied to these reference inputs set the output voltage limits of all four channels of the DACs, and V must Glitch REFH always be higher than V . V can be set at any voltage from The worst-case glitch of the AD5582 occurs at the transitions REFL REFH V + 0.5 V to V , while V can be set at any voltage from between midscale (1000 0000 0000 ) to midscale minus 1 REFL DD REFL B V to V – 0.5 V. In addition, a symmetrical negative reference (0111 1111 1111 ), or vice versa. The glitch energy is mea- SS REFH B can be generated easily by an external op amp in an inverting sured as 100 mV � 1 ms or equivalent to 100 nV-s. Such glitch mode with a pair of built-in precision resistors, R1 and R2. These occurs in a shorter duration than the settling time and therefore resistors are matched within ±0.025% for the AD5582 and 0.1% most applications will be immune to such an effect without a for the AD5583, which is equivalent to less than 1 LSB mis- deglitcher. match. Figure 4 shows a simple configuration. Layout and Power Supply Bypassing Common reference or references can be applied to all four chan- It is a good practice to employ compact, minimum lead length nels, but each reference pin should be decoupled with a 0.1 mF PCB layout design. The leads to the input should be as short as ceramic capacitor mounted close to the pin. possible to minimize IR drop and stray inductance. It is also essential to bypass the power supplies with quality capaci- +2.5V AD5582 tors for optimum stability. Supply leads to the device should be ADR421 V REFHA REF �2.5V bypassed with 0.01 mF to 0.1 mF disc or chip ceramics capacitors. DAC A V REFHB Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors should V REFHC V �2.5V also be applied at the supplies to minimize transient disturbance. REFHD DAC B R1 The AD5582/AD5583 optimize internal layout design to reduce die area so that all analog supply pins are required to be con- R2 RCT nected externally. See Figure 5. �2.5V DAC C V REFLA – V REFLB V AD5582/ + �2.5V REFLC DAC D –2.5V AD5583 V REFLD V V DD DD1 + V C1 C2 DD2 Figure 4. Using On-Board Matching Resistors 10�F 0.1�F V DD3 to Generate a Negative Voltage REF AGND1 + C3 C4 AGND2 10�F 0.1�F Digital I/O V V SS SS1 Digital I/O consists of a 12-/10-bit bidirectional data bus, two V SS2 register select inputs, A0 and A1, an R/W input, a Reset (RS), a V SS3 DV DD Chip Select (CS), and a Load DAC (LDAC) input. Control of C5 DGND the DACs and the bus direction is determined by these inputs 0.1�F as shown in Table I. All digital pins are TTL/CMOS compat- ible and all internal registers are level triggered. Figure 5. Power Supply Configurations The register selects inputs A0 and A1. Decoding of the registers is enabled by the CS input. When CS is high, no decoding is APPLICATIONS taking place and neither the writing nor the reading of the input Programmable Current Source registers is enabled. The loading of the second bank of registers AD5582/AD5583 high current capability allow them to be used is controlled by the asynchronous LDAC input. By taking LDAC directly in programmable current source applications, such as low while CS is enabled, the individual channel is updated as 4 m to 20 mA current transmitter and other general purpose single buffer mode, Figure 2a. If CS is enabled sequentially to applications. For higher compliance voltage that is higher than load data into all input registers, then a subsequent LDAC pulse 15 V, Figure 6 shows a versatile V-I conversion circuit using an will allow all channels to be updated simultaneously as double improved Howland Current Pump. In addition to the precision buffer mode, Figure 2b. current conversion it provides, this circuit enables a bidirec- R/W controls the writing to and reading from the input register. tional current flow and high voltage compliance. The voltage –16– REV. A AD5582/AD5583 Table I. AD5582/AD5583 Logic Table INPUT DAC OPERATION SELECTED A1 A0 R/WCS LDAC RS REGISTER REGISTER MODE DAC 00 00 01 Write Transparent Transparent A 01 00 01 Write Transparent Transparent B 10 00 01 Write Transparent Transparent C 11 00 01 Write Transparent Transparent D 00 00 11 Write Hold Write Input A 01 00 11 Write Hold Write Input B 10 00 11 Write Hold Write Input C 11 00 11 Write Hold Write Input D 00 10 11 Read Hold Readback to D0 to DN A 01 10 11 Read Hold Readback to D0 to DN B 10 10 11 Read Hold Readback to D0 to DN C 11 10 11 Read Hold Readback to D0 to DN D XX X1 01 Hold Update All Registers Update All Registers All XX X 1 1 1 Hold Hold Hold All XX XX X0 All registers reset to midscale or zero scale. All XX X 1 X ≠ All registers latched to midscale or zero scale. All MSB = 0 resets to zero scale, MSB = 1 resets to midscale. X: Don’t Care. Input and output registers are transparent when asserted. compliance is mainly limited by the op amp supply voltages. This circuit is versatile, but users must pay attention to the This circuit can be used in 4 to 20 mA current transmitters with compensation. Without C1, it can be shown that the output up to 500 W of load. impedance becomes: RR 13 '() R1 +R2 R1' R2' Z = O (5) 150k� 15k� RR 12'' +R3 –R1'R2 +R3 () () C1 10pF If the resistors are perfectly matched, Z is infinite, which is O highly desirable. On the other hand, if they are not matched, Z O +15V can either be positive or negative. The latter, because of the R3' 50� pole in the right S-plane, can cause oscillation. As a result, C1 – U4 in the range of a few pF is needed to prevent the oscillation. For U1 +2.5V +5V AD8510 +5V ADR421 critical applications, C1 should be found empirically without + V R3 DAC overcompensating. 50� V V REFH DD –15V R1 Boosted Programmable Voltage Source U2 RCT VL AD5582 For users who need higher than 20 mA current driving capabil- R2 R1 R2 150k� 15k� V V REFL SS ity, they can add an external op amp and power transistors. The +5V capacitive loading capability will change, but it can still drive LOAD IL 100 nF capacitive load without oscillation in this circuit. Figure 7 –5V – shows a programmable power supply with 200 mA capability. OP1177 –2.5V FDV30IN + V V DD O DECOUPLING CAPS ARE OMITTED FOR CLARITY +5V –5V N1 +4.096V U1 REF198 +15V Figure 6. Programmable Current Source with Bidirectional V V REFH DD LOAD Current Control and High Voltage Compliance Capabilities C1 U2 + 1�F AD5582 U3 Figure 6 shows that if the resistor network is matched, the load OP1177 V V REFL SS current is: – RR 23 + /R1 () I = V (4) L DAC DECOUPLING CAPS ARE OMITTED FOR CLARITY R3 Figure 7. Boosted Programmable Voltage Source R3 in theory can be made small to achieve the current needed within the U4 output current driving capability. In this circuit, the AD8510 can deliver ±20 mA in both directions and the voltage compliance approaches ±15 V. REV. A –17– AD5582/AD5583 V V DD DD +10V +10V FDBK FDBK G+ G+ V+ V+ C1 C2 C3 V V DD IN VINP OUT VINP OUT U5 U6 V O AD603 AD603 0.1�F 0.1�F 0.1�F R3 R1 G– G– V– V– 50k� 100� COMM COMM + U4 R4 AD8565 50k� – V DD V DD VOA VOB V 1-TO-3 VOC VOD DD R2 R1 V REFHA 10k� 10k� DV DD 2.0V V REFHB V REFHC +IN V REFHD U1 U2 AD5582 ADR510 V REFLA –IN 1.0V V REFLB V REFLC +IN V REFLD V 1-TO-3 SS U3 ADR510 –IN DECOUPLING CAPS ARE OMITTED FOR CLARITY Figure 8. Programmable PGA In this circuit, the inverting input of the op amp forces the V to O The decibel gain is linear in dB, accurately calibrated, and stable be equal to the DAC output. The load current is then delivered by over temperature and supply. The gain is controlled at a high the supply via the N-Ch FET N1. U3 needs to be a rail-to-rail impedance (50 MW), low bias (200 nA) differential input; the input type. With a V of 5 V, this circuit can source a maximum DD scaling is 25 mV/dB, requiring a gain control voltage of only 1 V of 200 mA at 4.096 V full scale, 100 mA at midscale, and 50 mA to span the central 40 dB of the gain range. An overrange and near zero-scale outputs. Higher current can be achieved with N1 underrange of 1 dB is provided whatever the selected range. The in a larger package mounted on a heat sink. gain control response time is less than 1 ms for a 40 dB change. Programmable PGA The differential gain control interface allows the use of either The AD603 is a low noise, voltage controlled amplifier for use in differential or single-ended positive or negative control voltages, RF and IF AGC (automatic gain control) systems. It provides where the common-mode range is –1.2 V to +2.0 V. The accurate, pin selectable gains of –11 dB to +31 dB with a band- AD5582/AD5583 is ideally suited to provide the differential width of 90 MHz, or 9 dB to 51 dB with a bandwidth of 9 MHz. input range of 1 V within the common-mode range of 0 V to 2 V. Any intermediate gain range may be arranged using one external To accomplish this, place V at 2.0 V and V at 1.0 V, REFH REFL resistor between Pin 5 and Pin 7. The input referred noise spectral then all 4096 V levels of the AD5582 will fall within the gain density is only 1.3 nV/÷Hz and power consumption is 125 mW control range of the AD603. Please refer to the AD603 data at the recommended ±5 V supplies. sheet for further information regarding gain control, layout, and general operation. –18– REV. A AD5582/AD5583 OUTLINE DIMENSIONS 48-Lead Thin Shrink Small Outline Package [TSSOP] (RV-48) Dimensions shown in millimeters 12.60 12.50 12.40 48 25 6.20 6.10 6.00 8.10 BSC 1 24 PIN 1 1.20 MAX 0.15 0.05 0.75 8� 0.60 0.5 0� 0.27 SEATING 0.45 0.20 BSC PLANE 0.17 0.09 COMPLIANT TO JEDEC STANDARDS MO-153ED REV. A –19– AD5582/AD5583 Revision History Location Page 8/03—Data Sheet changed from REV. 0 to REV. A. Change to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to Figures 2a, 2b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 –20– REV. A C03040–0–8/03(A)