ANALOG DEVICES AD558

(@ T = +258C, V = +5 V to +15 V unless otherwise noted) A CC AD558–SPECIFICATIONS 1 1 Model AD558J AD558K AD558S AD558T Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 8 8 8 8 Bits 2 RELATIVE ACCURACY 0°C to +70°C ±1/2 ±1/4 ±1/2 ±1/4 LSB –55°C to +125°C ±3/4 ±3/8 LSB OUTPUT 3 Ranges 0 to +2.56 0 to +2.56 0 to +2.56 0 to +2.56 V 0 to +10 0 to +10 0 to +10 0 to +10 V Current Source +5 +5 +5 +5 mA Sink Internal Passive Internal Passive Internal Passive Internal Passive 4 Pull-Down to Ground Pull-Down to Ground Pull-Down to Ground Pull-Down to Ground 5 OUTPUT SETTLING TIME 0 to 2.56 Volt Range 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 μs 4 0 to 10 Volt Range 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 μs 6 FULL-SCALE ACCURACY @ 25°C 61.5 60.5 61.5 60.5 LSB T to T 62.5 61 62.5 61 LSB MIN MAX ZERO ERROR @ 25°C 61 61/2 61 61/2 LSB T to T 62 61 62 61 LSB MIN MAX 7 MONOTONICITY T to T Guaranteed Guaranteed Guaranteed Guaranteed MIN MAX DIGITAL INPUTS T to T MIN MAX Input Current ±100 ±100 ±100 100 μA Data Inputs, Voltage Bit On-Logic “1” 2.0 2.0 2.0 2.0 V Bit On-Logic “0” 0 0.8 0 0 0 V Control Inputs, Voltage On-Logic “1” 2.0 2.0 2.0 2.0 V On-Logic “0” 0 0.8 0 0.8 0 0.8 0 0.8 V Input Capacitance 4 4 4 4 pF 8 TIMING t , Strobe Pulse Width 200 200 200 200 ns W T to T 270 270 270 270 ns MIN MAX t Data Hold Time 10 10 10 10 ns DH T to T 10 10 10 10 ns MIN MAX t Data Set-Up Time 200 200 200 200 ns DS T to T 270 270 270 270 ns MIN MAX POWER SUPPLY Operating Voltage Range (V ) CC 2.56 Volt Range +4.5 +16.5 +4.5 +16.5 +4.5 +16.5 +4.5 +16.5 V 10 Volt Range +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 V Current (I)15 25 15 25 15 25 15 25 mA CC Rejection Ratio 0.03 0.03 0.03 0.03 %/% POWER DISSIPATION, V = 5 V 75 125 75 125 75 125 75 125 mW CC V = 15 V 225 375 225 375 225 375 225 375 mW CC OPERATING TEMPERATURE RANGE 0 +70 0 +70 –55 +125 –55 +125 °C NOTES 1 The AD558 S & T grades are available processed and screened lo MIL-STD-883 Class B. Consult Analog Devices’ Military Databook for details. 2 Relative Accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device. See “Measuring Offset Error”. 3 Operation of the 0 volt to 10 volt output range requires a minimum supply voltage of +11.4 volts. 4 Passive pull-down resistance is 2 kΩ for 2.56 volt range, 10 kΩ for 10 volt range. 5 Settling time is specified for a positive-going full-scale step to ±1/2 LSB. Negative-going steps to zero are slower, but can be improved with an external pull-down. 6 The full range output voltage for the 2.56 range is 2.55 V and is guaranteed with a +5 V supply, for the 10 V range, it is 9.960 V guaranteed with a +15 V supply. 7 A monotonic converter has a maximum differential linearity error of ±1 LSB. 8 See Figure 7. Specifications shown in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. –2– REV. A AD558 ABSOLUTE MAXIMUM RATINGS* V (LSB) DB0 1 16 OUT V to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V CC V SENSE DB1 2 15 OUT Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . 0 V to +7.0 V V SELECT DB2 3 14 OUT V . . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground OUT AD558 DB3 4 13 GND Momentary Short to V CC TOP VIEW DB4 5 12 GND (Not to Scale) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW +V DB5 6 11 CC Storage Temperature Range CS DB6 7 10 N/P (Plastic) Packages . . . . . . . . . . . . . . . . –25°C to +100°C (MSB) DB7 8 9 CE D (Ceramic) Package . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (soldering, 10 sec) . . . . . . . . . . . . . +300°C Figure 1a. AD558 Pin Configuration (DIP) Thermal Resistance Junction to Ambient/Junction to Case D (Ceramic) Package . . . . . . . . . . . . . . 100°C/W/30°C/W N/P (Plastic) Packages . . . . . . . . . . . . . 140°C/W/55°C/W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause 3 2 1 20 19 permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute V SELECT DB2 4 18 OUT maximum rating conditions for extended periods may affect device reliability. DB3 5 17 GND AD558 6 16 NC NC TOP VIEW (Not to Scale) AD558 METALIZATION PHOTOGRAPH DB4 7 15 GND +V 8 14 DB5 CC Dimensions shown in inches and (mm). 9 10 11 12 13 NC = NO CONNECT Figure 1a. AD558 Pin Configuration (DIP) Figure 1b. AD558 Pin Configuration (PLCC and LCC) ORDERING GUIDE Relative Accuracy Full-Scale Error Max Error, Max Package 1 2 Model Temperature T to T T to T Option MIN MAX MIN MAX AD558JN 0°C to +70°C ±1/2 LSB ±2.5 LSB Plastic (N-16) AD558JP 0°C to +70°C ±1/2 LSB ±2.5 LSB PLCC (P-20A) AD558JD 0°C to +70°C ±1/2 LSB ±2.5 LSB TO-116 (D-16) AD558KN 0°C to +70°C ±1/4 LSB ±1 LSB Plastic (N-16) AD558KP 0°C to +70°C ±1/4 LSB ±1 LSB PLCC (P-20A) AD558KD 0°C to +70°C ±1/4 LSB ±1 LSB TO-116 (D-16) AD558SD –55°C to +125°C ±3/4 LSB ±2.5 LSB TO-116 (D-16) AD558TD –55°C to +125°C ±3/8 LSB ±1 LSB TO-116 (D-16) NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD558/883B data sheet. 2 D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier. REV. A –3– DB6 DB1 DB0 (LSB) (MSB) DB7 NC NC V CE OUT CS V SENSE OUT AD558 CIRCUIT DESCRIPTION CHIP AVAILABILITY The AD558 consists of four major functional blocks, fabricated The AD558 is available in laser-trimmed, passivated chip form. on a single monolithic chip (see Figure 2). The main D-to-A AD558J and AD558T chips are available. Consult the factory for details. converter section uses eight equally-weighted laser-trimmed Input Logic Coding current sources switched into a silicon-chromium thin-film R/2R resistor ladder network to give a direct but unbuffered 0 Digital Input Code Output Voltage mV to 400 mV output range. The transistors that form the DAC switches are PNPs; this allows direct positive-voltage logic Binary Hexadecimal Decimal 2.56 V Range 10.000 V Range interface and a zero-based output range. 0000 0000 00 0 0 0 0000 0001 01 1 0.010 V 0.039 V DIGITAL INPUT DATA CONTROL 0000 0010 02 2 0.020 V 0.078 V INPUTS 0000 1111 0F 15 0.150 V 0.586 V LSB MSB 0001 0000 10 16 0.160 V 0.625 V CS CE +V GND GND CC 0111 1111 7F 127 1.270 V 4.961 V 1000 0000 80 128 1.280 V 5.000 V 2 I L 2 CONTROL I L LATCHES 1100 0000 C0 192 1.920 V 7.500 V LOGIC 1111 1111 FF 255 2.55 V 9.961 V BAND- OUTPUT GAP 8-BIT VOLTAGE-SWITCHING AMP REFERENCE CONNECTING THE AD558 D-TO-A CONVERTER V OUT CONTROL The AD558 has been configured for ease of application. All ref- AMP V SENSE OUT erence, output amplifier and logic connections are made inter- V SELECT nally. In addition, all calibration trims are performed at the OUT factory assuring specified accuracy without user trims. The only connection decision that must be made by the user is a single jumper to select output voltage range. Clean circuit board lay- Figure 2. AD558 Functional Block Diagram out is facilitated by isolating all digital bit inputs on one side of The high speed output buffer amplifier is operated in the non- the package; analog outputs are on the opposite side. inverting mode with gain determined by the user-connections Figure 3 shows the two alternative output range connections. at the output range select pin. The gain-setting application The 0 V to 2.56 V range may be selected for use with any power resistors are thin-film laser-trimmed to match and track the supply between +4.5 V and +16.5 V. The 0 V to 10 V range DAC resistors and to assure precise initial calibration of the two requires a power supply of +11.4 V to +16.5 V. output ranges, 0 V to 2.56 V and 0 V to 10 V. The amplifier output stage is an NPN transistor with passive pull-down for OUTPUT OUTPUT zero-based output capability with a single power supply. The AMP AMP internal precision voltage reference is of the patented bandgap 16 V 16 V OUT OUT type. This design produces a reference voltage of 1.2 volts and thus, unlike 6.3 volt temperature compensated Zeners, may be V SENSE V SENSE 15 15 OUT OUT operated from a single, low voltage logic power supply. The V SELECT V SELECT 14 14 microprocessor interface logic consists of an 8-bit data latch and OUT OUT control circuitry. Low power, small geometry and high speed 2 2 13 13 GND GND are advantages of the I L design as applied to this section. I L is bipolar process compatible so that the performance of the ana- log sections need not be compromised to provide on-chip logic a. 0 V to 2.56 V Output Range b. 0 V to 10 V Output Range capabilities. The control logic allows the latches to be operated Figure 3. Connection Diagrams from a decoded microprocessor address and write signal. If the Because of its precise factory calibration, the AD558 is intended application does not involve a μP or data bus, wiring CS and to be operated without user trims for gain and offset; therefore CE to ground renders the latches “transparent” for direct DAC no provisions have been made for such user trims. If a small in- access. crease in scale is required, however, it may be accomplished by slightly altering the effective gain of the output buffer. A MIL-STD-883 resistor in series with V SENSE will increase the output OUT The rigors of the military/aerospace environment, temperature range. extremes, humidity, mechanical stress, etc., demand the utmost in electronic circuits. The AD558, with the inherent reliability For example if a 0 V to 10.24 V output range is desired (40 mV = 1 LSB), a nominal resistance of 850 Ω is required. It must be of integrated circuit construction, was designed with these ap- remembered that, although the internal resistors all ratio- plications in mind. The hermetically-sealed, low profile DIP match and track, the absolute tolerance of these resistors is package takes up a fraction of the space required by equivalent modular designs and protects the chip from hazardous environ- typically ±20% and the absolute TC is typically –50 ppm/°C ments. To further ensure reliability, military temperature range (0 to –100 ppm/°C). That must be considered when rescaling is performed. Figure 4 shows the recommended circuitry for a AD558 grades S and T are available screened to MIL-STD-883. full-scale output range of 10.24 volts. Internal resistance values For more complete data sheet information consult the Analog shown are nominal. Devices’ Military Databook. –4– REV. A DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Applications–AD558 The only consideration in selecting a supply voltage is that, in OUTPUT AMP order to be able to use the 0 V to 10 V output range, the power supply voltage must be between +11.4 V and +16.5 V. If, how- 16 V OUT ever, the 0 V to 2.56 V range is to be used, power consumption 604Ω 500Ω will be minimized by utilizing the lowest available supply voltage 15 40kΩ (above +4.5 V). 14 14kΩ 2kΩ TIMING AND CONTROL 13 GND The AD558 has data input latches that simplify interface to 8- and 16-bit data buses. These latches are controlled by Chip Enable (CE) and Chip Select (CS) inputs. CE and CS are inter- Figure 4. 10.24 V Full-Scale Connection nally “NORed” so that the latches transmit input data to the NOTE: Decreasing the scale by putting a resistor in series with GND DAC section when both CE and CS are at Logic “0”. If the ap- will not work properly due to the code-dependent currents in GND. plication does not involve a data bus, a “00” condition allows Adjusting offset by injecting dc at GND is not recommended for the for direct operation of the DAC. When either CE or CS go to same reason. Logic “1”, the input data is latched into the registers and held until both CE and CS return to “0”. (Unused CE or CS inputs GROUNDING AND BYPASSING* should be tied to ground.) The truth table is given in Table I. All precision converter products require careful application of The logic function is also shown in Figure 6. good grounding practices to maintain full rated performance. Because the AD558 is intended for application in microcom- Table I. AD558 Control Logic Truth Table puter systems where digital noise is prevalent, special care must be taken to assure that its inherent precision is realized. Latch The AD558 has two ground (common) pins; this minimizes Input Data CE CS DAC Data Condition ground drops and noise in the analog signal path. Figure 5 0 0 0 0 “Transparent” shows how the ground connections should be made. 1 0 0 1 “Transparent” 0 g 0 0 Latching OUTPUT 1 g 0 1 Latching AMP 00g 0 Latching V OUT 16 10g 1 Latching V SENSE OUT X 1 X Previous Data Latched 15 X X 1 Previous Data Latched (SEE NEXT V SELECT OUT PAGE) 14 R L NOTES GND X = Does not matter. 13 g = Logic Threshold at Positive-Going Transition. TO SYSTEM GND TO SYSTEM GND 12 GND (SEE TEXT) 0.1μF TO SYSTEM V 11 CC +V CC Figure 5. Recommended Grounding and Bypassing It is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common in one place only. If the common tie-point is remote and acciden- tal disconnection of that one common tie-point occurs due to card removal with power on, a large differential voltage between the two commons could develop. To protect devices that inter- Figure 6. AD558 Control Logic Function face to both digital and analog parts of the system, such as the AD558, it is recommended that common ground tie-points In a level-triggered latch such as that in the AD558 there is an should be provided at each such device. If only one system interaction between data setup and hold times and the width of ground can be connected directly to the AD558, it is recom- the enable pulse. In an effort to reduce the time required to test mended that analog common be selected. all possible combinations in production, the AD558 is tested with t = t = 200 ns at 25°C and 270 ns at T and T , DS W MIN MAX POWER SUPPLY CONSIDERATIONS with t = 10 ns at all temperatures. Failure to comply with DH The AD558 is designed to operate from a single positive power these specifications may result in data not being latched properly. supply voltage. Specified performance is achieved for any supply Figure 7 shows the timing for the data and control signals; CE voltage between +4.5 V and +16.5 V. This makes the AD558 and CS are identical in timing as well as in function. ideal for battery-operated, portable, automotive or digital main- frame applications. *For additional insight, “An IC Amplifier Users’ Guide to Decoupling, Grounding and Making Things Go Right For A change,” is available at no charge from any Analog Devices Sales Office. REV. A –5– AD558 t DH V OUT DATA 16 2.0V t AD558 DS INPUTS V SENSE 0.8V OUT R L 15 2.0V CS OR CE R = 2x V P-D EE 0.8V NEGATIVE V (in kΩ) EE SUPPLY t W Figure 9. Improved Settling Time 1/2 LSB available, bipolar output ranges may be achieved by suitable DAC output offsetting and scaling. Figure 10 shows how a ±1.28 volt V OUTPUT output range may be achieved when a –5 volt power supply is t SETTLING available. The offset is provided by the AD589 precision 1.2 volt t reference which will operate from a +5 volt supply. The AD544 W = STORAGE PULSE WIDTH = 200ns MIN t = DATA HOLD TIME = 10ns MIN DH output amplifier can provide the necessary ±1.28 volt output t = DATA SETUP TIME = 200ns MIN DS swing from ±5 volt supplies. Coding is complementary offset t = DAC OUTPUT SETTLING TIME TO ±1/2 LSB SETTLING binary. Figure 7. AD558 Timing 5kΩ V = 0V TO +2.56V OUT +5V USE OF V SENSE OUT 0.01μF Separate access to the feedback resistor of the output amplifier 16 5kΩ allows additional application versatility. Figure 8a shows how AD558 15 I × R drops in long lines to remote loads may be cancelled by AD544 14 V 4.53kΩ O putting the drops “inside the loop.” Figure 8b shows how the 0.01μF 13 12 +1.28 TO 1.5kΩ separate sense may be used to provide a higher output current 500Ω –1.27 BIPOLAR by feeding back around a simple current booster. V –5V IN OFFSET AD589 ADJUST V OUT 16 INPUT CODE V OUT AD558 V –1.2V OUT V SENSE OUT 0V TO +10V 00000000 +128V 4.7kΩ 15 0.01μF 10000000 0V 12 14 11111111 –1.27V 13 R L GAIN GND –5V SELECT Figure 10. Bipolar Operation of AD558 from ±5 V Supplies a. Compensation for I × R Drops in Output Lines MEASURING OFFSET ERROR V CC One of the most commonly specified endpoint errors associated with real-world nonideal DACs is offset error. V OUT 16 2N2222 AD558 In most DAC testing, the offset error is measured by applying V OUT SENSE V OUT 15 the zero-scale code and measuring the output deviation from 0 0V TO +2.56V volts. There are some DACs, like the AD558 where offset errors 12 13 14 GAIN R may be present but not observable at the zero scale, because of L GND SELECT other circuit limitations (such as zero coinciding with single- supply ground) so that a nonzero output at zero code cannot be read as the offset error. Factors like this make testing the b. Output Current Booster AD558 a little more complicated. Figure 8. Use of V Sense OUT By adding a pulldown resistor from the output to a negative supply as shown in Figure 11, we can now read offset errors OPTIMIZING SETTLING TIME at zero code that may not have been observable due to circuit In order to provide single-supply operation and zero-based limitations. The value of the resistor should be such that, at zero output voltage ranges, the AD558 output stage has a passive voltage out, current through the resistor is 0.5 mA max. “pull-down” to ground. As a result, settling time for negative going output steps may be longer than for positive-going output steps. The relative difference depends on load resistance and OUTPUT capacitance. If a negative power supply is available, the AMP 0.5mA negative-going settling time may be improved by adding a pull- 16 V OUT down resistor from the output to the negative supply as shown –V 15 V SENSE in Figure 9. The value of the resistor should be such that, at OUT zero voltage out, current through that resistor is 0.5 mA max. 14 V SELECT OUT BIPOLAR OUTPUT RANGES 13 AGND The AD558 was designed for operation from a single power supply and is thus capable of providing only unipolar (0 V to a. 0 V to 2.56 V Output Range +2.56 V and 0 V to 10 V) output ranges. If a negative supply is –6– REV. A AD558 OUTPUT ADDRESS BUS AMP 0.5mA 16 16 V 16 OUT –V ADDRESS SELECT 15 V SENSE OUT PULSE LOGIC 8080A 14 V SELECT V CS OUT OUT AD558 MEMW CE 13 AGND DB0–DB7 b. 0 V to 10 V Output Range 8 8 Figure 11. Offset Connection Diagrams DATA BUS INTERFACING THE AD558 TO MICROPROCESSOR MEMW → CE DECODED ADDRESS SELECT PULSE → CS DATA BUSES The AD558 is configured to act like a “write only” location in b. 8080A/AD558 Interface memory that may be made to coincide with a read only memory location or with a RAM location. The latter case allows data 8 previously written into the DAC to be read back later via the ADDRESS BUS RAM. Address decoding is partially complete for either ROM or RAM. Figure 12 shows interfaces for three popular micropro- MA 0 – 7 8 cessor systems. ADDRESS CS TPA LATCH & V OUT 1802 AD558 ADDRESS BUS DECODE CE MWR 16 16 DB0–DB7 ADDRESS 6800 DECODER 8 8 VMA V OUT DATA BUS CS AD558 φ2 CDP 1802: MWR → CE DECODED ADDRESS SELECT PULSE → CS CE R/W DB0–DB7 c. 1802/AD558 Interface 8 Figure 12. Interfacing the AD558 to Microprocessors 8 DATA BUS R/W → CE GATED DECODED ADDRESS → CS a. 6800/AD558 Interface Performance (typical @ +258C, V 6 +5 V to +15 V unless otherwise noted) CC LSB 1.75 1.50 1.25 LSB ALL AD558 ALL AD558 1.00 1/2 AD558S, T AD558S, T ZERO 0.75 ERROR 0.50 1/4 0.25 FULL 0 0 SCALE o –0.25 C –55 –25 0 +25 +50 +75 +100 +125 ERROR –0.50 –1/4 –0.75 –1.00 1LSB = 0.39% OF FULL SCALE –1/2 o C –55 –25 0 +25 +50 +75 +100 +125 1LSB = 0.39% OF FULL SCALE Figure 13. Full-Scale Accuracy vs. Temperature Figure 14. Zero Drift vs. Temperature Performance Performance of AD558 of AD558 REV. A –7– AD558 mA OUTLINE DIMENSIONS 16 Dimensions shown in inches and (mm). 14 N (Plastic) Package I CC 12 10 4 6 8 1012141618 VOLTS V CC Figure 15. Quiescent Current vs. Power Supply Voltage for AD558 D (Ceramic) Package Figure 16. AD558 Settling Characteristics Detail 0 V to 2.56 V Output Range Full-Scale Step P (PLCC) Package Figure 17. AD558 Settling Characteristic Detail 0 V to 10 V Output Range Full-Scale Step Figure 18. AD558 Logic Timing –8– REV. A PRINTED IN U.S.A. C558f–21–8/87