ANALOG DEVICES AD5570

True Accuracy, 16-Bit ±12 V/±15 V, Serial Input Voltage Output DAC AD5570 FEATURES FUNCTIONAL BLOCK DIAGRAM V V SS DD DGND Full 16-bit performance 1 LSB maximum INL and DNL AD5570 POWER-ON RESET Output voltage range up to ±14 V REFGND On-board reference buffers, eliminating the need for a negative reference 2R 16-BIT Controlled output during power-on V OUT DAC Temperature ranges of −40°C to +85°C for A/B version/−40°C R AGND to +125°C for W/Y version AGNDS R Settling time of 10 μs to 0.003% DAC REGISTER REFIN Clear function to 0 V Asynchronous update of outputs (LDAC pin) POWER-DOWN CONTROL LOGIC PD SHIFT REGISTER Power-on reset LDAC Serial data output for daisy chaining Data readback facility SDIN SCLK SDO SYNC CLR 5 kV HBM ESD classification Figure 1. APPLICATIONS Industrial automation Automatic test equipment Process control Data acquisition systems General-purpose instrumentation GENERAL DESCRIPTION readback allows the user to read the contents of the DAC The AD5570 is a single 16-bit serial input, voltage output DAC register via the SDO pin. that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are Features on the AD5570 include LDAC which is used to update accurate to 1 LSB. During power-up, when the supply voltages the output of the DAC. The device also has a power-down pin are changing, V is clamped to 0 V via a low impedance path. OUT ( ), allowing the DAC to be put into a low power state, and a PD The AD5570 DAC comes complete with a set of reference CLR pin that allows the output to be cleared to 0 V. buffers. The reference buffers allow a single, positive reference The AD5570 is available in a 16-lead SSOP. to be used. The voltage on REFIN is gained up and inverted internally to give the positive and negative reference for the PRODUCT HIGHLIGHTS DAC core. Having the reference buffers on-chip eliminates the 1. 1 LSB maximum INL and DNL. need for external components such as inverters, precision 2. Buffered voltage output up to ±14 V. amplifiers, and resistors, thereby reducing the overall solution 3. Output controlled during power-up. size and cost. The AD5570 uses a versatile 3-wire interface that is compatible 4. On-board reference buffers. with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards. 5. Wide temperature range of −40°C to +125°C. Data is presented to the part as a 16-bit serial word. Serial data 6. 5 kV HBM ESD classification. is available on the SDO pin for daisy-chaining purposes. Data Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03760-001 AD5570 TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 16 Applications....................................................................................... 1 Reference Buffers........................................................................ 16 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 16 General Description ......................................................................... 1 Transfer Function....................................................................... 17 Product Highlights ........................................................................... 1 CLR Clear ( )................................................................................. 17 Revision History ............................................................................... 2 Power-Down ( ) ..................................................................... 17 PD Specifications..................................................................................... 3 Power-On Reset.......................................................................... 17 Timing Characteristics..................................................................... 5 Serial Data Output (SDO)......................................................... 17 Standalone ..................................................................................... 5 Applications Information .............................................................. 19 Timing Characteristics..................................................................... 6 Typical Operating Circuit ......................................................... 19 Daisy-Chaining and Readback ................................................... 6 Layout Guidelines....................................................................... 20 Absolute Maximum Ratings............................................................ 8 Opto-Isolators............................................................................. 20 ESD Caution.................................................................................. 8 Microprocessor Interfacing....................................................... 21 Pin Configuration and Function Descriptions............................. 9 Evaluation Board........................................................................ 22 Terminology .................................................................................... 10 Outline Dimensions....................................................................... 24 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 24 General Description ....................................................................... 16 REVISION HISTORY 11/10—Rev. B to Rev. C Added HBM ESD Classification to Features and Product Highlights Section ............................................................................ 1 Added ESD Parameter to Table 4 ................................................... 8 Changes to Ordering Guide .......................................................... 24 9/06—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 3............................................................................ 6 Changes to Figure 43...................................................................... 21 Changes to AD5570 to 8xC51 Interface Section ........................ 21 Changes to Ordering Guide .......................................................... 24 4/05—Rev. 0 to Rev. A Changes to Table 1............................................................................ 3 Changes to Table 4............................................................................ 8 Added Figure 16.............................................................................. 12 Revision 0: Initial Version Rev. C | Page 2 of 24 AD5570 SPECIFICATIONS VDD = +11.4 V to +16.5 V, VSS = −11.4 V to −16.5 V, VREF = 5 V, REFGND = AGND = DGND = 0 V, RL = 5 kΩ, CL = 200 pF to AGND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 1 Min Typ Max Parameter Unit Test Conditions/Comments ACCURACY Resolution 16 Bits Monotonicity 16 Bits Differential Nonlinearity (DNL) −1 ±0.3 +1 LSB Relative Accuracy (INL) B/Y Grade −1 ±0.4 +1 LSB A/W Grade −2 ±0.6 +2 LSB 3 Positive INL Drift Over Time See Figure 16 A/B Grades 2.5 ppm W/Y Grades 6.5 ppm Negative Full-Scale Error ±0.9 ±7.5 mV Full-Scale Error ±1.8 ±6 mV Bipolar Zero Error ±0.9 ±7.5 mV Gain Error ±1.8 ±7.5 mV 4 Gain Temperature Coefficient +0.25 ±1.5 ppm FSR/°C REFERENCE INPUT 4 Reference Input Range 4 5 5 V With ±11.4 V supplies 4 5 7 V With ±16.5 V supplies Input Current ±0.1 μA 4 OUTPUT CHARACTERISTICS Output Voltage Range VSS + 1.4 VDD − 1.4 V With ±11.4 V supplies V + 2.5 V − 2.5 V With ±16.5 V supplies SS DD Output Voltage Settling Time 12 16 μs At 16 bits to ±0.5 LSB 10 13 μs To 0.0003% 6 7 μs 512 LSB code change Slew Rate 6.5 V/μs Measured from 10% to 90% Digital-to-Analog Glitch Impulse 15 nV-s ±12 V supplies; 1 LSB change around the major carry Bandwidth 20 kHz Short Circuit Current 25 mA Output Noise Voltage Density 85 nV/Hz f = 1 kHz; midscale loaded DAC Output Impedance 0.35 0.5 Ω Digital Feedthrough 0.5 nV-s 5 WARMUP TIME 12 sec LOGIC INPUTS Input Currents ±0.1 μA VINH, Input High Voltage 2 V VINL, Input Low Voltage 0.8 V C , Input Capacitance 3 pF IN LOGIC OUTPUTS VOL, Output Low Voltage 0.4 V ISINK = 1 mA Floating-State Output 8 pF Rev. C | Page 3 of 24 AD5570 2 1 Min Typ Max Parameter Unit Test Conditions/Comments POWER REQUIREMENTS V /V ±11.4 ±16.5 V DD SS I 4 5 mA V unloaded DD OUT I 3.5 5 mA V unloaded SS OUT Power-Down Current 16 μA VOUT unloaded 6 Power-Supply Sensitivity 0.1 LSB/V ±15 supplies ±10%; full-scale loaded Power Dissipation 100 mW VOUT unloaded 1 Temperature ranges: A and B versions = − 40°C to +85°C; W and Y versions = −40°C to +125°C. 2 Typical specifications at ±12 V/±15 V, +25°C. 3 These numbers are generated from the life test of the part. 4 Guaranteed by design. 5 Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance. 6 Sensitivity of negative full-scale error and positive full-scale error to V , V variations. DD SS Rev. C | Page 4 of 24 AD5570 TIMING CHARACTERISTICS STANDALONE V = +12 V ± 5%, V = −12 V ± 5% or V = +15 V ± 10%, V = −15 V ± 10%, V = 5 V, REFGND = AGND = DGND = 0 V, R = 5 kΩ, DD SS DD SS REF L C = 200 pF to AGND; all specifications T to T , unless otherwise noted. L MIN MAX Table 2. 1, 2 Parameter Limit at T , T Unit Description MIN MAX fMAX 10 MHz max SCLK frequency t 100 ns min SCLK cycle time 1 t 35 ns min SCLK high time 2 t3 35 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 35 ns min Data setup time t 0 ns min Data hold time 6 t 45 ns min SCLK falling edge to SYNC rising edge 7 t 45 ns min high time 8 Minimum SYNC t9 0 ns min SYNC rising edge to LDAC falling edge t10 50 ns min LDAC pulse width t11 0 ns min LDAC falling edge to SYNC falling edge (no update) t 0 ns min LDAC rising edge to SYNC rising edge (no update) 12 t 20 ns min CLR pulse width 13 1 All parameters guaranteed by design and characterization. Not production tested. 2 All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. t 1 SCLK t t 2 3 t 8 t 4 t 7 SYNC t 6 t 5 SDIN DB15 DB0 t 9 t 10 1 LDAC t 11 t 12 2 LDAC t 13 CLR NOTES 1 ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC. 2 SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC. Figure 2. Serial Interface Timing Diagram Rev. C | Page 5 of 24 03760-002 AD5570 TIMING CHARACTERISTICS DAISY-CHAINING AND READBACK V = +12 V ± 5%, V = −12 V ± 5% or V = +15 V ± 10%, V = −15 V ± 10%, V = 5 V, REFGND = AGND = DGND = 0 V, R = 5 kΩ, DD SS DD SS REF L C = 200 pF to AGND; all specifications T to T , unless otherwise noted. L MIN MAX Table 3. 1, 2 Parameter Limit at T , T Unit Description MIN MAX fMAX 2 MHz max SCLK frequency t 500 ns min SCLK cycle time 1 t 200 ns min SCLK high time 2 t3 200 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 35 ns min Data setup time t 0 ns min Data hold time 6 t 45 ns min SCLK falling edge to SYNC rising edge 7 t 45 ns min high time 8 Minimum SYNC t9 0 ns min SYNC rising edge to LDAC falling edge t10 50 ns min LDAC pulse width 3 t14 200 ns max Data delay on SDO 1 All parameters guaranteed by design and characterization. Not production tested. 2 All input signals are measured with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of (V +V )/2. SDO; R = 5 kΩ, C = 15 pF. DD IL IH PULLUP L 3 With CL = 0 pF, t14 = 100 ns. t 1 SCLK t t t 3 2 4 t 7 t 8 SYNC t 10 1 LDAC t 9 2 LDAC t 6 t 5 DB0 DB15 DB15 (N) DB0 (N) SDIN (N + 1) (N + 1) t 14 DB15 SDO DB15 (N) DB0 (N) (N + 1) NOTES 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 3. Daisy-Chaining Timing Diagram Rev. C | Page 6 of 24 03760-003 AD5570 t 1 SCLK t 2 t 3 t 8 t t 4 7 SYNC t 6 t 5 DB15 DB0 SDIN DB15 (N) DB0 (N) (N + 1) (N + 1) t 10 LDAC t 9 t 14 DB15 (N) DB14 (N) DB0 (N) SDO Figure 4. Readback Timing Diagram Rev. C | Page 7 of 24 03760-004 AD5570 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND, AGNDS, DGND −0.3 V to +17 V DD rating only; functional operation of the device at these or any V to AGND, AGNDS, DGND +0.3 V to −17 V SS other conditions above those indicated in the operational AGND, AGNDS to DGND −0.3 V to +0.3 V section of this specification is not implied. Exposure to absolute REFGND to AGND, ADNDS −0.3 V to +0.3 V maximum rating conditions for extended periods may affect REFIN to AGND, AGNDS −0.3 V to +17 V device reliability. REFIN to REFGND −0.3 V to +17 V Digital Inputs to DGND −0.3 V to V + 0.3 V DD ESD CAUTION V to AGND, AGNDS OUT VSS − 0.3 V to VDD + 0.3 V SDO to DGND −0.3 V to +6.5 V Operating Temperature Range W/Y Grades −40°C to +125°C A/B Grades −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (TJ max) 150°C 16-Lead SSOP Package Power Dissipation (T max – T )/θ J A JA θ Thermal Impedance 139°C/W JA Lead Temperature (Soldering, 10 sec) 300°C IR Reflow, Peak Temperature 230°C 1 ESD 5 kV 1 HBM classification. Rev. C | Page 8 of 24 AD5570 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 16 REFGND SS V 2 15 REFIN DD CLR 3 14 REFGND AD5570 LDAC 4 13 V OUT TOP VIEW SYNC 5 12 AGNDS (Not to Scale) SCLK 6 11 AGND SDIN 7 10 PD SDO 8 9 DGND Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VSS Negative Analog Supply Voltage. −12 V ± 5% to −15 V ± 10% for specified performance. 2 V Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance. DD 3 CLR Level Sensitive, Active Low Input. A falling edge of CLR resets V to AGND. The contents of the registers OUT are untouched. 4 LDAC Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC. 5 SYNC Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. 6 SCLK Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 8 MHz. 7 SDIN Serial Data Input. Data is clocked into the 16-bit register on the falling edge of the serial clock input. 8 SDO Serial Data Output. Can be used for daisy-chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes. This is an open-drain output; it must be pulled to logic high with an external pull-up resistor of ~5 kΩ. 9 DGND Digital Ground. Ground reference for all digital circuitry. 10 PD Active Low Control Input. Allows the DAC to be put into a power-down state. 11 AGND Analog Ground. Ground reference for all analog circuitry. 12 AGNDS Analog Ground Sense. This is normally tied to AGND. 13 V Analog Output Voltage. OUT 14, 16 REFGND Reference Ground. Tie this pin to 0 V. 15 REFIN Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output range, REFIN is 5 V. Rev. C | Page 9 of 24 03760-005 AD5570 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time Relative accuracy or integral nonlinearity is a measure of Output voltage settling time is the amount of time it takes for the maximum deviation, in LSBs, from a straight line pass- the output to settle to a specified level for a full-scale input change. ing through the endpoints of the DAC transfer function. Slew Rate Monotonicity The slew rate of a device is a limitation in the rate of change of A DAC is monotonic if the output either increases or remains output voltage. The output slewing speed of a voltage-output constant for increasing digital inputs. The AD5570 is mono- DAC converter is usually limited by the slew rate of the ampli- tonic over its full operating temperature range. fier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/μs. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured Digital-to-Analog Glitch Impulse change and the ideal 1 LSB change between any two adjacent codes. Digital-to-analog glitch impulse is the amount of charge injected A specified differential nonlinearity of ±1 LSB maximum ensures into the analog output when the input codes in the DAC register monotonicity. change state. It is specified as the area of the glitch in nV-s and is measured when the digital input code changes by 1 LSB at the Gain Error major carry transition, that is, from code 0x7FFF to 0x8000. Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is Bandwidth the deviation in slope of the DAC transfer characteristic from The reference amplifiers within the DAC have a finite band- the ideal. width to optimize noise performance. To measure it, a sine wave is applied to the reference input (REFIN), with full-scale Gain Error Temperature Coefficient code loaded to the DAC. The bandwidth is the frequency at Gain error temperature coefficient is a measure of the change in which the output amplitude falls to 3 dB below the input. gain error with changes in temperature. It is expressed in ppm/°C. Digital Feedthrough Negative Full-Scale Error/Zero Scale Error Digital feedthrough is a measure of the impulse injected into Negative full-scale error is the error in the DAC output voltage the analog output of the DAC from the digital inputs of the when all 0s are loaded into the DAC latch. Ideally, the output DAC, but is measured when the DAC output is not updated. voltage, with all 0s in the DAC latch, is −2 VREF. SYNC is held high, while the SCLK and SDIN signals are tog- Full-Scale Error gled. Digital feedthrough is specified in nV-s and is measured Full-scale error is the error in the DAC output voltage when all with a full-scale code change on the data bus, that is, from all 1s are loaded to the DAC latch. Ideally, the output voltage with 0s to all 1s, and vice versa. all 1s loaded into the DAC latch is 2 V − 1 LSB. REF Power Supply Sensitivity Bipolar Zero Error Power supply sensitivity indicates how the output of the DAC is Bipolar zero error is the deviation of the analog input from the affected by changes in the power supply voltage. ideal half-scale output of 0.0000 V when the inputs are loaded with 0x8000. Rev. C | Page 10 of 24 AD5570 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 T = 25°C T = 25°C A A 0.8 V /V = ±15V 0.8 V /V = ±12V DD SS DD SS REFIN = +5V REFIN = +5V 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 10k 20k 30k 40k 50k 60k 0 10k 20k 30k 40k 50k 60k CODE CODE Figure 6. Integral Nonlinearity vs. Code, VDD/VSS = ±15 V Figure 9. Differential Nonlinearity vs. Code, VDD/VSS = ±12 V 1.0 1.0 T = 25°C V /V = ±15V A DD SS 0.8 V /V = ±15V 0.8 REFIN = +5V DD SS REFIN = +5V 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 10k 20k 30k 40k 50k 60k –40 –20 0 20 40 60 80 100 120 CODE TEMPERATURE (°C) Figure 7. Differential Nonlinearity vs. Code, V /V = ±15 V DD SS Figure 10. Integral Nonlinearity vs. Temperature, VDD/VSS = ±15 V 1.0 1.0 T = 25°C V /V = ±15V A DD SS 0.8 V /V = ±12V 0.8 REFIN = +5V DD SS REFIN = +5V 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 10k 20k 30k 40k 50k 60k –40 –20 0 20 40 60 80 100 120 CODE TEMPERATURE (°C) Figure 8. Integral Nonlinearity vs. Code, V /V = ±12 V Figure 11. Differential Nonlinearity vs. Temperature, V /V = ±15 V DD SS DD SS Rev. C | Page 11 of 24 INL (LSB) DNL (LSB) INL (LSB) 03760-008 03760-007 03760-006 DNL (LSB) INL (LSB) DNL (LSB) 03760-019 03760-018 03760-009 AD5570 1.0 1.0 V /V = ±12V DD SS T = 25°C A 0.8 REFIN = +5V 0.8 REFIN = 5V 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 –40 –20 0 20 40 60 80 100 120 11.4 12.0 13.0 14.0 15.0 16.0 16.5 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 12. Integral Nonlinearity vs. Temperature, V /V = ±12 V DD SS Figure 15. Differential Nonlinearity vs. Supply Voltage 1.0 1.0 V /V = ±12V DD SS V /V = ±16.5V DD SS 0.8 REFIN = +5V T = 125°C 0.8 A 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 –40 –20 0 20 40 60 80 100 120 0 100 200 300 400 500 600 700 800 900 1000 TEMPERATURE (°C) TIME (Hours) Figure 13. Differential Nonlinearity vs. Temperature, V /V = ±12 V DD SS Figure 16. INL Drift over Time 1.0 2.0 T = 25°C V /V = ±12V A DD SS 0.8 REFIN = 5V T = 25°C A 1.5 0.6 0.4 1.0 0.2 0 0.5 –0.2 0 –0.4 –0.6 –0.5 –0.8 –1.0 –1.0 11.4 12.0 13.0 14.0 15.0 16.0 16.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 14. Integral Nonlinearity vs. Supply Voltage Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±12 V Rev. C | Page 12 of 24 INL (LSB) DNL (LSB) INL (LSB) 03760-023 03760-021 03760-020 INL ERROR (LSB) DNL (LSB) INL (LSB) 03760-052 03760-026 03760-024 AD5570 0.5 1.0 V /V = ±12V DD SS V /V = ±15V DD SS 0.4 T = 25°C 0.8 A T = 25°C A 0.3 0.6 0.2 0.4 0.1 0.2 0 0 –0.1 –0.2 –0.2 –0.4 –0.3 –0.6 –0.4 –0.8 –0.5 –1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 18. Differential Nonlinearity Error vs. Reference Voltage, Figure 21. Integral Nonlinearity Error vs. Reference Voltage, V /V = ±12 V DD SS V /V = ±15 V DD SS 10.0 5.0 V /V = ±15V OR ±12V T = 25°C A DD SS T = 25°C REFIN = 5V A 4.5 7.5 |I | DD 5.0 4.0 2.5 3.5 |I | SS 3.0 0 2.5 –2.5 –5.0 2.0 11.4 12.4 13.4 14.4 15.4 16.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) V /V (V) DD SS Figure 19. TUE Error vs. Reference Voltage, V /V = ±15 V or ±12 V Figure 22. I /I vs. V /V DD SS DD SS DD SS 25 2.0 T = 25°C A V /V = ±15V DD SS REFIN = +5V T = 25°C A 1.5 20 |I | DD IN POWER-DOWN 1.0 0.5 15 0 10 –0.5 –1.0 5 |I | –1.5 SS IN POWER-DOWN 0 –2.0 11.4 12.4 13.4 14.4 15.4 16.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 SUPPLY VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 23. I /I in Power-Down vs. Supply Voltage Figure 20. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±15 V DD SS Rev. C | Page 13 of 24 TUE ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 03760-048 03760-028 03760-027 I /I POWER-DOWN CURRENT (µA) I /I (mA) INL ERROR (LSB) DD SS DD SS 03760-049 03760-030 03760-029 AD5570 4.15 0 T = 25°C A V /V = ±12V OR ±15V DD SS REFIN = 5V –1 REFIN = 5V 4.10 15V SUPPLIES DECREASING –2 4.05 –3 4.00 –4 INCREASING 3.95 DECREASING –5 –6 3.90 INCREASING –7 3.85 12V SUPPLIES –8 3.80 –9 3.75 –10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –40 –20 0 20 40 60 80 100 120 V (V) LOGIC TEMPERATURE (°C) Figure 24. Offset Error vs. Temperature SYNC Figure 27. Supply Current vs. Logic Input Current for SCLK, , SDIN, LDAC and Increasing and Decreasing 0 11 REFIN = +5V 10 –1 8 V /V = ±15V –2 DD SS 6 –3 4 –4 2 –5 V /V = ±12V DD SS 0 –6 –2 –7 –4 1µs/DIV –8 V = +15V –6 DD V = –15V SS –9 REFIN = +5V –8 T = 25°C A –10 –10 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TIME (µs) Figure 25. Bipolar Zero Error vs. Temperature Figure 28. Settling Time 40 10 REFIN = +5V T = 25°C A 8 REFIN = +5V 35 6 30 V /V = ±12V 4 DD SS 25 2 V /V = ±15V DD SS 20 0 V /V = ±15V DD SS –2 15 –4 10 V /V = ±12V DD SS –6 5 –8 0 –10 01 2 3 4 5 6 7 8 9 9.4 –40 –20 0 20 40 60 80 100 120 CAPACITANCE (nF) TEMPERATURE (°C) Figure 26. Gain Error vs. Temperature Figure 29.14-Bit Settling Time vs. Load Capacitance Rev. C | Page 14 of 24 OFFSET ERROR (LSB) GAIN ERROR (LSB) BIPOLAR ZERO ERROR (LSB) 03760-031 03760-034 03760-032 TIME (µs) I (mA) V (V) OUT DD 03760-035 03760-046 03760-037 AD5570 10.0000 –0.022 T = 25°C 9.9997 A REFIN = 5V 9.9994 –0.027 9.9991 9.9988 –0.032 9.9985 –0.037 9.9982 15V SUPPLIES 9.9979 –0.042 9.9976 –0.047 9.9973 9.9970 –0.052 12V SUPPLIES 9.9967 –0.057 9.9964 V = +12V DD 9.9961 V = –12V –0.062 SS 9.9958 REFIN = +5V 9.9955 T = 25°C –0.067 A 9.9952 8000 → 7FFFH –10 –8 –6 –4 –2 024 68 10 –0.072 SOURCE CURRENT (mA) SINK CURRENT (mA) 1µs/DIV Figure 30. Source and Sink Capability of Output Amplifier Figure 33. Major Code Transition Glitch Energy, V /V = ±12 V DD SS with Full-Scale Loaded –9.9973 T = 25°C A V = +15V REFIN = 5V DD –9.9976 V = –15V SS MIDSCALE LOADED –9.9979 20µV/DIV V = 0V 12V SUPPLIES REFIN –9.9982 –9.9985 –9.9988 15V SUPPLIES –9.9991 –9.9994 –9.9997 –10.0000 –10 –8 –6 –4 –2 024 68 10 CH1 20µV/DIV M 1.0Ωms 500kS/s 20µs/PT SOURCE CURRENT (mA) SINK CURRENT (mA) A CH1 0.0V Figure 31. Source and Sink Capability of Output Amplifier Figure 34. Peak-to-Peak Noise (100 kHz Bandwidth) with Zero-Scale Loaded –0.05 V = +15V DD V = –15V SS REFIN = +5V T = 25°C A –0.06 V DD RAMP TIME = 100µs –0.07 V SS –0.08 V OUT V = +15V DD –0.09 V = –15V SS REFIN = +5V T = 25°C A 7 FFF → 8000H –0.10 V /V = 10V/DIV DD SS V = 10mV/DIV OUT 100µs/DIV 1µs/DIV Figure 32. Major Code Transition Glitch Energy, VDD/VSS = ±15 V Figure 35. VOUT vs. VDD/VSS on Power-Up Rev. C | Page 15 of 24 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) V (V) OUT 03760-040 03760-038 03760-039 VOLTAGE (V) 03760-047 03760-042 03760-051 AD5570 GENERAL DESCRIPTION The AD5570 is a single 16-bit serial input, voltage output DAC. It On power-up, the input shift register and DAC register are operates from supply voltages of ±11.4 V to ±16.5 V, and has a loaded with midscale (0x8000). The DAC coding is straight buffered voltage output of up to ±13.6 V. Data is written to the binary; all 0s produce an output of −2 VREF; all 1s produce an AD5570 in a 16-bit word format, via a 3-wire serial interface. The output of +2 VREF − 1 LSB. device also offers an SDO pin, available for daisy-chaining or SYNC The input is a level-triggered input that acts as a frame readback. SYNC synchronization signal and chip enable. must frame the The AD5570 incorporates a power-on reset circuit to ensure the serial word being loaded into the device. Data can be transferred DAC output powers up to 0 V. The device also has a power-down SYNC into the device only while is low. To start the serial data pin to reduce the typical current consumption to 16 μA. transfer, SYNC is taken low, observing the minimum SYNC to SCLK falling edge setup time, t . After SYNC goes low, serial data DAC ARCHITECTURE 4 on SDIN is shifted into the device’s input shift register on the The DAC architecture of the AD5570 consists of a 16-bit, current- SYNC falling edges of SCLK. can be taken high after the falling mode, segmented R-2R DAC. The simplified circuit diagram for th edge of the 16 SCLK pulse, observing the minimum SCLK the DAC section is shown in Figure 36. SYNC falling edge to rising edge time, t7. The four MSBs of the 16-bit data word are decoded to drive After the end of the serial data transfer, data is automatically 15 switches, E1 to E15. Each of these switches connects one transferred from the input shift register to the input register of the 15 matched resistors to either AGND or IOUT. The of the DAC. remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network. When data has been transferred into the input register of the DAC, RR R the DAC register and DAC output can be updated by taking V REF LDAC SYNC low while is high. 2R 2R 2R 2R 2R 2R 2R LDAC Load DAC Input ( ) R/8 There are two ways that the DAC register and DAC output can E15 E14 E1 S11 S0 S10 be updated when data has been transferred into the input register IOUT of the DAC. Depending on the status of both SYNC and LDAC, V OUT one of two update modes is selected. AGND 4 MSBs DECODED INTO 12-BIT R-2R LADDER LDAC LDAC The first mode is synchronous . In this mode, is low 15 EQUAL SEGMENTS while data is being clocked into the input shift register. The DAC Figure 36. DAC Ladder Structure SYNC output is updated when is taken high. The update here REFERENCE BUFFERS SYNC occurs on the rising edge of . The AD5570 operates with an external reference. The reference The second mode is asynchronous LDAC. In this mode, LDAC input (REFIN) has an input range of up to 7 V. This input voltage is is high while data is being clocked in. The DAC output is updated then used to provide a buffered positive and negative reference by taking LDAC low any time after SYNC has been taken high. for the DAC core. The positive reference is given by LDAC The update now occurs on the falling edge of . +V =2 ×V REF REFIN Figure 37 shows a simplified block diagram of the input loading and the negative reference to the DAC core is given by circuitry. −V =2 ×V OUTPUT REF REFIN I/V AMPLIFIER These positive and negative reference voltages define the DAC V 16-BIT REFIN V OUT DAC output range. SERIAL INTERFACE LDAC DAC REGISTER The AD5570 is controlled over a versatile 3-wire serial interface SYNC that operates at clock rates up to 10 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. INPUT SHIFT SDIN SDO REGISTER Input Shift Register Figure 37. Simplified Serial Interface Showing Input Loading Circuitry The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. Rev. C | Page 16 of 24 03760-010 03760-012 AD5570 POWER-DOWN ( ) PD TRANSFER FUNCTION The power-down pin allows the user to place the AD5570 into Table 6 shows the ideal input code to the output voltage rela- a power-down mode. In power-down mode, power consump- tionship for the AD5570. tion is at a minimum; the device typically consumes only 16 μA. Table 6. Binary Code Table POWER-ON RESET Digital Input The AD5570 contains a power-on reset circuit that controls the MSB LSB Analog Output (VOUT) output during power-up and power-down. This is useful in appli- 1111 1111 1111 1111 +2 V × (32,767/32,768) REF cations where the known state of the output of the DAC during 1000 0000 0000 0001 +2 VREF × (1/32,768) power-up is important. On power-up and power-down, the output 1000 0000 0000 0000 0 V of the DAC and V , is held at AGND. OUT 0111 1111 1111 1111 −2 VREF × (1/32,768) SERIAL DATA OUTPUT (SDO) 0000 0000 0000 0000 −2 V REF The SDO is the internal shift registers output. For the AD5570, The output voltage expression is given by SDO is an internal pull-down only; an external pull-up resistor V =−2V + 4×V [D / 65536] OUT REFIN REFIN of ~5 kΩ to external logic high is required. SDO pull-down is disabled when the device is in power-down, thus saving current. where: D is the decimal equivalent of the code loaded to the DAC. The availability of SDO allows any number of AD5570s to be V is the reference voltage available at the REFIN pin. REFIN daisy-chained together. It also allows for the contents of the DAC register, or any number of DACs daisy-chained together, to be CLEAR (CLR) read back for diagnostic purposes. CLR is an active low digital input that allows the output to be Daisy Chaining CLR cleared to 0 V. When the signal is brought back high, the This mode of operation is designed for multi DAC systems, output stays at 0 V until LDAC is brought low. The relationship where several AD5570s can be connected in cascade as shown between and CLR is explained further in Table 7. LDAC in Figure 38. This is done by connecting the control inputs in parallel and then daisy-chaining the SDIN and SDO I/Os of Table 7. Relationships Among PD, CLR, and LDAC each device. An external pull-up resistor of ~5 kΩ on SDO is PD CLR LDAC Comments required when using the part in daisy-chain mode. 0 x x PD LDAC CLR has priority over and . The output remains at 0 V through an internal SYNC As described earlier, when goes low, serial data on SDIN 20 kΩ resistor. It is still possible to address is shifted into the input shift register on the falling edge of SCLK. both the input register and DAC register If more than 16 clock pulses are applied, the data ripples out of when the AD5570 is in power-down. the shift resister and appears on the SDO line. By connecting 1 0 0 Data is written to the input register and this line to the SDIN input on the next AD5570 in the chain, a CLR DAC register. has higher priority over multi DAC interface can be constructed. LDAC ; therefore, the output is at 0 V. 1 0 1 Data is written to the input register only. One data transfer cycle of 16 SCLK pulses is required for each The output is at 0 V and remains at 0 V DAC in the system. Therefore, the total number of clock cycles CLR when is taken back high. must equal 16 N, where N is the total number of devices in the 1 1 0 Data is written to the input register and the chain. The first data transfer cycle written into the chain appears at DAC register. The output is driven to the the last DAC in the system on the final data transfer cycle. DAC level. 1 1 1 Data is written to the input register only. When the serial transfer to all devices is complete, take SYNC high. The output of the DAC register is unchanged. This prevents any further data from being clocked into the devices. A continuous SCLK source can be used if SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used SYNC and is taken high some time later. The outputs of all the DACs in the system can be updated simultaneously using the LDAC signal. Rev. C | Page 17 of 24 AD5570 Readback To read back the contents of the DAC register without writing The AD5570 allows the data contained in the DAC register to SYNC LDAC to the part, take low while is held high. be read back, if required. As with daisy chaining, an external pull-up resistor of ~5 kΩ on SDO is required. The data in the Daisy-chaining readback is also possible through the SDO pin DAC register is available on SDO on the falling edges of SCLK of the last device in the DAC chain because the DAC data passes th SYNC when is low. On the 16 SCLK edge, SDO is updated to through the DAC chain with the appropriate latency. repeat SDIN with a delay of 16 clock cycles. 68HC11* AD5570* MOSI SDIN SCK SCLK PC7 SYNC V LDAC PC6 LOGIC SDO MISO R SDIN AD5570* SCLK SYNC LDAC SDO R SDIN AD5570* SCLK SYNC LDAC SDO R *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. Daisy-Chaining Using the AD5570 Rev. C | Page 18 of 24 03760-013 AD5570 APPLICATIONS INFORMATION 1 V REFGND 16 SS TYPICAL OPERATING CIRCUIT 2 V REFIN 15 DD Figure 39 shows the typical operating circuit for the AD5570. 3 CLR REFGND 14 The only external component needed for this precision 16-bit DAC is a single external positive reference. Because the device 4 LDAC V 13 OUT AD5570 incorporates reference buffers, it eliminates the need for a negative 5 SYNC AGNDS 12 2 reference, external inverters, precision amplifiers, and resistors. 6 6 SCLK AGND 11 3 This leads to an overall savings of both cost and board space. OP177* 7 SDIN PD 10 In the circuit shown in Figure 39, VDD and VSS are both connected 8 SDO DGND 9 to ±15 V, but V and V can operate supplies from 11.4 V to DD SS (OTHER CONNECTIONS OMITTED 16.5 V. AGNDS is connected to AGND, but the option of force/ FOR CLARITY) sense is included on this device if required by the user. *FOR OPTIMUM SETTLING TIME PERFORMANCE, THE AD845 IS RECOMMENDED. 0.1µF 10µF Figure 40. Driving AGND and AGNDS Using a Force/Sense Amplifier –15V 1 V REFGND 16 SS +15V 2 V REFIN 15 ADR435 The four possible sources of error to consider when choosing DD 0.1µF 10µF 3 CLR REFGND 14 a voltage reference for high accuracy applications are initial accuracy, long-term drift, temperature coefficient of the out- 4 LDAC V 13 V LDAC OUT OUT AD5570 put voltage, and output voltage noise. 5 SYNC AGNDS 12 SYNC 6 SCLK AGND 11 SCLK Initial accuracy on the output voltage of an external reference can 7 SDIN PD 10 lead to a full-scale error in the DAC. Therefore, to minimize SDIN 8 SDO DGND 9 these errors, a reference with low initial accuracy specification SDO 5kΩ is preferred. Also, choosing a reference with an output trim adjust- 5V ment, such as the ADR425, allows a system designer to trim out Figure 39. Typical Operating Circuit system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at tem- Force/Sense of AGND perature to trim out any error. Because of the extremely high accuracy of this device, system design issues (such as grounding and contact resistance) are Long-term drift (LTD) is a measure of how much the reference very important. The AD5570, with ±10 V output, has an LSB drifts over time. A reference with a tight long-term drift specifica- size of 305 μV. Therefore, series wiring and connector resistances tion ensures that the overall solution remains relatively stable of very small values can cause voltage drops of an LSB. For this over its entire lifetime. reason, the AD5570 offers a force/sense output configuration. The temperature coefficient of a references output voltage Figure 40 shows how to connect the AD5570 to the force/sense affects INL, DNL, and TUE. Choose a reference with a tight amplifier. Where accuracy of the output is important, an ampli- temperature coefficient specification to reduce the depend fier such as the OP177 is ideal. The OP177 is ultraprecise with ence of the DAC output voltage on ambient conditions. offset voltages of 10 μV maximum at room temperature, and off- In high accuracy applications that have a relatively low noise set drift of 0.1 μV/°C maximum. Alternative recommended budget, reference output voltage noise needs to be considered. amplifiers are the OP1177 and the OP77. For applications where It is important to choose a reference with as low an output noise optimization of the circuit for settling time is needed, the AD845 voltage as practical for the system resolution required. Precision is recommended. voltage references, such as the ADR435 (XFET® design), produce Precision Voltage Reference Selection low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference To achieve the optimum performance from the AD5570, give can be required to minimize the output noise. special attention to the selection of a precision voltage reference. The AD5570 has just one reference input, REFIN. This voltage on REFIN is used to provide a buffered positive and negative reference for the DAC core. Therefore, any error in the voltage reference is reflected in the output of the device. Rev. C | Page 19 of 24 03760-044 03760-045 AD5570 Avoid crossover of digital and analog signals. Traces on opposite Table 8. Partial List of Precision References Recommended sides of the board must run at right angles to each other. for Use with the AD5570 This reduces the effects of feed through the board. A micro- Initial Long-Term Temp Drift 0.1 Hz to strip technique is by far the best, but not always possible Accuracy Drift (ppm/ 10 Hz Noise Part No. (mV max) (ppm typ) °C max) (μV p-p typ) with a double-sided board. In this technique, the component ADR435 ±6 30 3 3.4 side of the board is dedicated to ground plane, while signal ADR425 ±6 50 3 3.4 traces are placed on the solder side. 1 ADR02 ±5 50 3 15 OPTO-ISOLATORS ADR395 50 25 5 ±6 In many process control applications, it is necessary to provide AD586 15 10 4 ±2.5 an isolation barrier between the controller and the unit being 1 Available in SC70 package. controlled. Opto-isolators provide voltage isolation in excess of LAYOUT GUIDELINES 3 kV. The serial loading structure of the AD5570 makes it ideal for opto-isolated interfaces, because the number of interface lines In any circuit where accuracy is important, careful considera- is kept to a minimum. Figure 41 shows a 4-channel isolated inter- tion of the power supply and ground return layout helps to face to the AD5570. To reduce the number of opto-isolators, the ensure the rated performance. The printed circuit board that LDAC pin can be tied permanently low if the simultaneous the AD5570 is mounted on is designed so the analog and dig- updating of the DAC is not required. The DAC can then be ital sections are separated and confined to certain areas of the updated on the rising edge of SYNC. board. If the AD5570 is in a system where multiple devices require an AGND-to-DGND connection, the connection is V CC made at one point only. The star ground point is established as close as possible to the device. µCONTROLLER The AD5570 has ample supply bypassing of 10 μF in parallel TO LDAC CONTROL OUT with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors TO SYNC SYNC OUT are the tantalum bead type. The 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI) such as the common ceramic types that provide a low imped- SERIAL CLOCK OUT TO SCLK ance path to ground at high frequencies to handle transient currents due to internal logic switching. TO SDIN SERIAL DATA OUT The power supply lines of the AD5570 use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as OPTO-COUPLER clocks are shielded with digital ground to avoid radiating noise Figure 41. Opto-Isolated Interface to other parts of the board, and are never be run near the refer- ence inputs. A ground line routed between the SDIN and SCLK lines reduces crosstalk between them; this is not required on a multilayer board that has a separate ground plane, but separating the lines helps. It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Rev. C | Page 20 of 24 03760-050 AD5570 LDAC is controlled by the PC6 port output. The DAC can be MICROPROCESSOR INTERFACING LDAC updated after each 2-byte transfer by bringing low. This Microprocessor interfacing to the AD5570 is via a serial bus CLR example does not show other serial lines for the DAC. If that uses standard protocol compatible with microcontrollers were used, control it by the Port Output PC5. and DSP processors. The communications channel is a 3-wire AD5570 to 8xC51 Interface (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5570 requires a 16-bit The AD5570 requires a clock synchronized to the serial data. For data word with data valid on the falling edge of SCLK. this reason, the 8xC51 must be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is For all the interfaces, the DAC output update can be done auto- output on TxD. matically when all the data is clocked in, or it can be done under the control of LDAC. The contents of the DAC register can be P3.3 and P3.4 are bit-programmable pins on the serial port and are used to drive SYNC and LDAC, respectively. read using the readback function. AD5570 to MC68HC11 Interface The 8xC51 provides the LSB of its SBUF register as the first bit in the data stream. The user must ensure that the data in the SBUF Figure 42 shows an example of a serial interface between the register is arranged correctly because the DAC expects MSB first. AD5570 and the MC68HC11 microcontroller. The serial periph- eral interface (SPI) on the MC68HC11 is configured for master AD5570* 8xC51* mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock phase bit (CPHA = 1). The SPI is configured by writing to the SPI control register (SPCR); see documentation on the MC68HC11. SCK of the MC68HC11 drives the SCLK of the AD5570, the RxD SDIN MOSI output drives the serial data line (SDIN) of the AD5570, TxD SCLK and the MISO input is driven from SDO. The SYNC is driven P3.3 SYNC from one of the port lines, in this case, PC7. P3.4 LDAC When data is being transmitted to the AD5570, the SYNC line *ADDITIONAL PINS OMITTED FOR CLARITY. (PC7) is taken low and data is transmitted MSB first. Data appear- Figure 43. AD5570 to 8xC51 Interface ing on the MOSI output is valid on the falling edge of SCK. Eight When data is to be transmitted to the DAC, P3.3 is taken low. Data falling clock edges occur in the transmit cycle; therefore, in order on RxD is clocked out of the microcontroller on the rising edge to load the required 16-bit word, PC7 is not brought high until of TxD and is valid on the falling edge. As a result, no glue logic the second 8-bit word has been transferred to the DACs input is required between this DAC and the microcontroller interface. shift register. The 8xC51 transmits data in 8-bit bytes with only eight falling MC68HC11* AD5570* clock edges occurring in the transmit cycle. Because the DAC expects a 16-bit word, SYNC (P3.3) must be left low after the first MISO SDO eight bits are transferred. After the second byte has been trans- MOSI SDIN ferred, the P3.3 line is taken high. The DAC can be updated using SCLK SCLK LDAC via P3.4 of the 8xC51. PC7 SYNC *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 42. AD5570 to MC68HC11 Interface Rev. C | Page 21 of 24 03760-014 03760-015 AD5570 AD5570 to ADSP21xx eight bits of data during each serial transfer operation; therefore, two consecutive write operations are needed. Figure 45 shows An interface between the AD5570 and the ADSP21xx family is the connection diagram. shown in Figure 44. The ADSP21xx must be set up to operate in the SPORT transmit alternate framing mode. The ADSP21xx is PIC16C6x/7x* AD5570* programmed through the SPORT control register and is con- figured as follows: internal clock operation, active low framing, SDI/RC4 SDO and 16-bit word length. SDO/RC5 SDIN Transmission is initiated by writing a word to the Tx register, after SCLK/RC3 SCLK the SPORT has been enabled. As the data is clocked out of the RA1 SYNC DSP on the rising edge of SCLK, no glue logic is required to inter- face the DSP to the DAC. In the interface shown, the DAC output *ADDITIONAL PINS OMITTED FOR CLARITY. is updated using the LDAC pin via the DSP. Alternatively, the Figure 45. AD5570 to PIC16C6x/7x Interface LDAC input can be tied permanently low, and then the update EVALUATION BOARD TFS is automatic when is taken high. The AD5570 comes with a full evaluation board to aid designers ADSP21xx AD5570* in evaluating the high performance of the part with minimal effort. The evaluation board requires a power supply, a PC, DR SDO and an oscilloscope. DT SDIN SCLK SCLK The AD5570 evaluation kit includes a populated and tested AD5570 printed circuit board. The evaluation board inter- TFS SYNC faces to the parallel interface of a PC. Software is available RFS FO LDAC with the evaluation board that allows the user to easily pro- gram the AD5570. A schematic of the evaluation board is *ADDITIONAL PINS OMITTED FOR CLARITY. shown in Figure 46. The software runs on any PC installed Figure 44. AD5570 to ADSP21xx Interface with Microsoft® Windows® 95/ Windows® 98/Windows® ME/ Windows® 2000/Windows® XP. AD5570 to PIC16C6x/7x An application note containing full details on operating the The PIC16C6x/7x synchronous serial port (SSP) is configured as evaluation board comes supplied with the AD5570 evalua- an SPI master with the clock polarity bit set to 0. This is done tion board. by writing to the synchronous serial port control register, SSPCON (see documentation on the PIC16/17 microcontroller). In this SYNC example, I/O port RA1 is being used to pulse and enable the serial port of the AD5570. This microcontroller transfers only Rev. C | Page 22 of 24 03760-016 03760-017 AD5570 Figure 46. Evaluation Board Schematic Rev. C | Page 23 of 24 DVDD TP4 J11 – CENTRONICS CONNECTOR R4 AVDD LK3 4.7kΩ 62 J2 V +V OUT IN C16 C34 TP8TP3TP9 TP2 TP1 TP7 TP10 U9–A 0.1µF ADR435 10µF DOUT 1 OE J11–13 U2 5 + TRIM AVDD PD 2 18 J11–3 A0 Y0 V 4 16 SS A1 Y1 GND DIN 6 14 J11–2 A2 Y2 C35 SCLK 8 12 4 J11–5 A3 Y3 0.1µF DVDD DVDD DVDD 12 15 U1 74ACT244 10 PD 8 WHITE PLASTIC SSOP CLAMP SDO J1 7 SDIN 13 6 AD5570 V SCLK V U9–B OUT OUT 5 SYNC 19 4 OE LDAC 3 CLR SYNC 11 9 J11–4 A0 Y0 TP5 13 7 C1 LDAC R1 J11–6 A1 Y1 LK1 CLR 15 5 912 11 16 14 J11–7 A2 Y2 CONVST 17 3 A3 Y3 J11–8 LK2 SDO PD DIN SCLK LDAC SYNC CLR 74ACT244 AVDD U3 J4 J5 J6 J7 J8 J9 J10 2 7 U4–A V+ 1 6 OE OP OP177 DATA 3 V– 18 2 J11–12 Y0 A0 16 4 4 Y1 A1 SDATA_ADC 14 6 J11–10 Y2 A2 REF 12 8 Y3 A3 C18 VSS C3 R2 10µF 74ACT244 SCLK_ADC 0.1µF 10kΩ REF/2 J11–9 + DGND AGND REF/2 REF/2 C17 + C5 U5 0.1µF 8 1 R3 10µF 4 10kΩ SCLK DVDD 5 SDATA DVDD 2 6 BUSY V IN 7 J13–1 CONVST J11–19 C36 + 3 J11–20 AVDD LM78L05ACM AD7895-10 0.1µF 8 1 C30 C31 C32 C33 J11–21 V V IN OUT 10µF 0.1µF 0.1µF 0.1µF 7 2 J11–22 0.33µF GND3 GND1 C4 DGND 20V C2 0.01µF 6 3 J11–23 J13–2 GND4 GND2 5 4 J11–24 U6 DGND AVDD J11–25 AVDD J11–26 J12–1 J11–27 ++ + + AVDD U4–B J11–28 C12 C11 C10 C9 C8 C7 C6 C14 19 OE 10µF 10µF 10µF 10µF 0.1µF 0.1µF 0.1µF 0.1µF J11–29 9 11 Y0 A0 J12–2 7 13 Y1 A1 J11–30 5 15 AGND Y2 A2 + + + 3 17 AGND Y3 A3 C13 C21 C22 C23 C24 C15 74ACT244 V SS 10µF 10µF 10µF 0.1µF 0.1µF 0.1µF J12–3 V SS LK4 R5 4.7kΩ R7 4.7kΩ R6 4.7kΩ V DD GND DGND V SS REFIN AGNDS V DD AGND REFGND REFGND REFIN REF LK5 03760-043 AD5570 OUTLINE DIMENSIONS 6.50 6.20 5.90 16 9 5.60 5.30 8.20 5.00 7.80 7.40 1 8 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AC Figure 47. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD5570ARS −40°C to +85°C 16-Lead SSOP RS-16 AD5570ARS-REEL −40°C to +85°C 16-Lead SSOP RS-16 AD5570ARS-REEL7 −40°C to +85°C 16-Lead SSOP RS-16 AD5570ARSZ −40°C to +85°C 16-Lead SSOP RS-16 AD5570ARSZ-REEL −40°C to +85°C 16-Lead SSOP RS-16 AD5570ARSZ-REEL7 −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRS −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRS-REEL −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRS-REEL7 −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRSZ −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRSZ-REEL −40°C to +85°C 16-Lead SSOP RS-16 AD5570BRSZ-REEL7 −40°C to +85°C 16-Lead SSOP RS-16 AD5570WRS −40°C to +125°C 16-Lead SSOP RS-16 AD5570WRSZ −40°C to +125°C 16-Lead SSOP RS-16 AD5570WRSZ-REEL −40°C to +125°C 16-Lead SSOP RS-16 AD5570WRSZ-REEL7 −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRS −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRS-REEL −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRS-REEL7 −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRSZ −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRSZ-REEL −40°C to +125°C 16-Lead SSOP RS-16 AD5570YRSZ-REEL7 −40°C to +125°C 16-Lead SSOP RS-16 EVAL-AD5570EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03760-0-11/10(C) Rev. C | Page 24 of 24 060106-A