ANALOG DEVICES AD557

(@ T = 25�C, V = 5 V unless otherwise noted) AD557–SPECIFICATIONS A CC Model Min Typ Max Unit ABSOLUTE MAXIMUM RATINGS* RESOLUTION 8 Bits V to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 18 V CC RELATIVE ACCURACY Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . . 0 V to 7.0 V 0°C to 70°C ±1/2 1 LSB V . . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground OUT OUTPUT Momentary Short to V Ranges 0 to 2.56 V CC Current Source 5 mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Sink Internal Passive Storage Temperature Range 2 Pull-Down to Ground N/P (Plastic) Packages . . . . . . . . . . . . . . . . –25°C to +100°C 3 OUTPUT SETTLING TIME 0.8 1.5 µs Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C 4 FULL-SCALE ACCURACY Thermal Resistance @ 25°C ±1.5 ±2.5 LSB Junction to Ambient/Junction to Case T to T ±2.5 ±4.0 LSB MIN MAX N/P (Plastic) Packages . . . . . . . . . . . . . . . . . . 140/55°C/W ZERO ERROR *Stresses above those listed under Absolute Maximum Ratings may cause perma- @ 25°C ±1 LSB nent damage to the device. This is a stress rating only; functional operation of the T to T ±3 LSB MIN MAX device at these or any other conditions above those indicated in the operational 5 MONOTONICITY section of this specification is not implied. Exposure to absolute maximum rating T to T Guaranteed But Not Tested MIN MAX conditions for extended periods may affect device reliability. DIGITAL INPUTS T to T MIN MAX Input Current �100 µA PIN CONFIGURATIONS Data Inputs, Voltage Bit On—Logic “1” 2.0 V DIP Bit On—Logic “0” 0 0.8 V Control Inputs, Voltage 1 16 V (LSB) BIT 8 OUT On—Logic “1” 2.0 V On—Logic “0” 0 0.8 V BIT 7 2 15 V SENSE A OUT Input Capacitance 4 pF BIT 6 3 14 V SENSE B OUT AD557 6 TIMING BIT 5 4 13 GND TOP VIEW t Strobe Pulsewidth 225 ns W (Not to Scale) BIT 4 5 12 GND T to T 300 ns MIN MAX t Data Hold Time 10 ns DH BIT 3 6 11 +V CC T to T 10 ns MIN MAX BIT 2 7 10 CS t Data Setup Time 225 ns DS T to T 300 ns (MSB) BIT 1 8 9 CE MIN MAX POWER SUPPLY Operating Voltage Range (V ) CC PLCC 2.56 Volt Range 4.5 5.5 V Current (I)1525mA CC Rejection Ratio 0.03 %/% POWER DISSIPATION, V = 5 V 75 125 mW CC OPERATING TEMPERATURE RANGE 0 70 °C NOTES 1 3 2 1 20 19 Relative Accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device. BIT 6 4 PIN 1 18 V SENSE B See “Measuring Offset Error” on the AD558 data sheet. OUT IDENTIFIER 2 Passive pull-down resistance is 2 kΩ. BIT 5 5 17 GND 3 Settling time is specified for a positive-going full-scale step to ±1/2 LSB. Negative- AD557 NC 6 16 NC going steps to zero are slower, but can be improved with an external pull-down. TOP VIEW 4 (Not to Scale) The full-scale output voltage is 2.55 V and is guaranteed with a 5 V supply. BIT 4 7 15 GND 5 A monotonic converter has a maximum differential linearity error of ±1 LSB. BIT 3 8 14 +V 6 CC See Figure 7. Specifications shown in boldface are tested on all production units at electrical test. 9 10 11 12 13 Specifications subject to change without notice. NC = NO CONNECT ORDERING GUIDE Temperature Package Package Model Range Description Option AD557JN 0°C to 70°C Plastic DIP N-16 AD557JP 0°C to 70°C Plastic Leaded Chip Carrier P-20A –2– REV. B BIT 2 BIT 7 (MSB) BIT 1 BIT 8 (LSB) NC NC V CE OUT CS V SENSE A OUT AD557 CIRCUIT DESCRIPTION CONNECTING THE AD557 The AD557 consists of four major functional blocks fabricated The AD557 has been configured for low cost and ease of appli- on a single monolithic chip (see Figure 1). The main D/A con- cation. All reference, output amplifier and logic connections are verter section uses eight equally weighted laser-trimmed current made internally. In addition, all calibration trims are performed sources switched into a silicon-chromium thin-film R/2R resistor at the factory assuring specified accuracy without user trims. ladder network to give a direct but unbuffered 0 mV to 400 mV The only connection decision to be made by the user is whether output range. The transistors that form the DAC switches are the output range desired is unipolar or bipolar. Clean circuit PNPs; this allows direct positive-voltage logic interface and a board layout is facilitated by isolating all digital bit inputs on zero-based output range. one side of the package; analog outputs are on the opposite side. DIGITAL INPUT DATA (BUS) CONTROL UNIPOLAR 0 V TO 2.56 V OUTPUT RANGE INPUTS BIT1 BIT8 Figure 2 shows the configuration for the 0 V to 2.56 V full- + V (MSB) (LSB) CS CE CC GND GND scale output range. Because of its precise factory calibration, the 2 AD557 is intended to be operated without user trims for gain l L 2 l L LATCHES CONTROL and offset; therefore, no provisions have been made for such user LOGIC trims. If a small increase in scale is required, however, it may be OUTPUT BAND-GAP accomplished by slightly altering the effective gain of the output AMP 8-BIT VOLTAGE-SWITCHING REFERENCE D-TO-A CONVERTER buffer. A resistor in series with V SENSE will increase the OUT V OUT output range. Note that decreasing the scale by putting a resistor CONTROL AMP in series with GND will not work properly due to the code- V SENSE A OUT dependent currents in GND. Adjusting offset by injecting dc at V SENSE B OUT GND is not recommended for the same reason. Figure 1. Functional Block Diagram OUTPUT AMP The high-speed output buffer amplifier is operated in the nonin- 16 V OUT verting mode with gain determined by the user-connections at the output range select pin. The gain-setting application 15 V SENSE A OUT resistors are thin film laser trimmed to match and track the 14 V SENSE B OUT DAC resistors and to assure precise initial calibration of the out- 13 GND put range, 0 V to 2.56 V. The amplifier output stage is an NPN transistor with passive pull-down for zero-based output capability with a single power supply. Figure 2. 0 V to 2.56 V Output Range The internal precision voltage reference is of the patented BIPOLAR –1.28 V TO +1.28 V OUTPUT RANGE band-gap type. This design produces a reference voltage of The AD557 was designed for operation from a single power 1.2 V and thus, unlike 6.3 V temperature-compensated Zeners, supply and is thus capable of providing only a unipolar 0 V to may be operated from a single, low-voltage logic power supply. 2.56 V output range. If a negative supply is available, bipolar The microprocessor interface logic consists of an 8-bit data output ranges may be achieved by suitable output offsetting and latch and control circuitry. Low power, small geometry and high 2 scaling. Figure 3 shows how a ±1.28 V output range may be speed are advantages of the I L design as applied to this section. 2 achieved when a –5 V power supply is available. The offset is I L is bipolar process compatible so that the performance of the provided by the AD589 precision 1.2 V reference which will analog sections need not be compromised to provide on-chip operate from a 5 V supply. The AD711 output amplifier can logic capabilities. The control logic allows the latches to be provide the necessary ±1.28 V output swing from ±5 V supplies. operated from a decoded microprocessor address and write sig- Coding is complementary offset binary. nal. If the application does not involve a µP or data bus, wiring CS and CE to ground renders the latches “transparent” for 5k� direct DAC access. V = 0V TO 2.56V +5V OUT Digital Input Code Output AD711 0.01�F Binary Hexadecimal Decimal Voltage 5k� AD557 V O 4.53k� 0000 0000 00 0 0 500� +1.28 TO 0.01�F BIPOLAR –1.27 0000 0001 01 1 0.010 V OFFSET 1.5k� 0000 0010 02 2 0.020 V ADJUST AD589 V IN 0000 1111 0F 15 0.150 V –5V –1.2V 0001 0000 10 16 0.160 V V INPUT CODE OUT 0.01�F 4.7k� 00000000 +1.28V 0111 1111 7F 127 1.270 V 10000000 0V 11111111 –1.27V 1000 0000 80 128 1.280 V –5V 1100 0000 C0 192 1.920 V 1111 1111 FF 255 2.55 V Figure 3. Bipolar Operation of AD557 from ±5 V Supplies REV. B –3– AD557 APPLICATIONS Timing and Control Grounding and Bypassing The AD557 has data input latches that simplify interface to 8- All precision converter products require careful application of and 16-bit data buses. These latches are controlled by Chip good grounding practices to maintain full rated performance. Enable (CE) and Chip Select (CS) inputs. CE and CS are inter- Because the AD557 is intended for application in microcom- nally “NORed” so that the latches transmit input data to the puter systems where digital noise is prevalent, special care must DAC section when both CE and CS are at Logic “0.” If the be taken to assure that its inherent precision is realized. application does not involve a data bus, a “00” condition allows for direct operation of the DAC. When either CE or CS go to The AD557 has two ground (common) pins; this minimizes Logic “1,” the input data is latched into the registers and held ground drops and noise in the analog signal path. Figure 4 until both CE and CS return to “0.” (Unused CE or CS inputs shows how the ground connections should be made. should be tied to ground.) The truth table is given in Table I. It is often advisable to maintain separate analog and digital The logic function is also shown in Figure 6. grounds throughout a complete system, tying them common in one place only. If the common tie-point is remote and acciden- V OUT 7.5 tal disconnection of that one common tie-point occurs due to card removal with power on, a large differential voltage between 5.0 the two commons could develop. To protect devices that inter- 2.5 face to both digital and analog parts of the system, such as the 00H 80H FFH AD557, it is recommended that common ground tie-points AD557 INPUT CODE should be provided at each such device. If only one system Figure 6. AD557 Input Code vs. Level Shifted Output in a ground can be connected directly to the AD557, it is recom- “False” Ground Configuration mended that analog common be selected. Table I. AD557 Control Logic Truth Table Latch OUTPUT AMP Input Data CE CS DAC Data Condition V OUT 16 0 0 0 0 “Transparent” V SENSE A OUT 15 1 0 0 1 “Transparent” V SENSE B 0 g 0 0 Latching OUT 14 R L 1 g 0 1 Latching GND 13 00 g 0 Latching TO SYSTEM GND 10 g 1 Latching 12 TO SYSTEM GND X 1 X Previous Data Latched GND 0.1�F (SEE TEXT) X X 1 Previous Data Latched 11 TO SYSTEM V CC +V CC NOTES X = Does not matter Figure 4. Recommended Grounding and Bypassing g = Logic Threshold at Positive-Going Transition In a level-triggered latch such as that used in the AD557, there Using a “False” Ground is an interaction between the data setup and hold times and Many applications, such as disk drives, require servo control the width of the enable pulse. In an effort to reduce the time voltages that swing on either side of a “false” ground. This required to test all possible combinations in production, the ground is usually created by dividing the 12 V supply equally AD557 is tested with t = t = 225 ns at 25°C and 300 ns at and calling the midpoint voltage “ground.” DS W T and T , with t = 10 ns at all temperatures. Failure to MIN MAX DH Figure 5 shows an easy and inexpensive way to implement this. comply with these specifications may result in data not being The AD586 is used to provide a stable 5 V reference from the latched properly. system’s 12 V supply. The op amp shown likewise operates from Figure 7 shows the timing for the data and control signals, CE a single (12 V) supply available in the system. The resulting out- and CS are identical in timing as well as in function. put at the V node is ±2.5 V around the “false” ground point OUT of 5 V. AD557 input code vs. V is shown in Figure 6. OUT t DH 2.0V DATA t DS 0.8V INPUTS 100k� 200k� AD557 2.0V 1/4 LM324 CS OR CE 0.8V t W V OUT 1/2 LSB DAC 12V 100k� V OUTPUT 6 2 AD586 5V V IN “FALSE” 100k� t 4 SETTLING GROUND t = STROBE PULSEWIDTH = 225ns min W t = DATA HOLD TIME = 10ns min DH Figure 5. Level Shifting the AD557 Output Around a t = DATA SETUP TIME = 225ns min DS t = DAC SETTLING TIME TO � 1/2 LSB SETTLING “False” Ground Figure 7. AD557 Timing –4– REV. B AD557 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-16 (Plastic) Package 0.87 (22.1) MAX 0.25 0.31 (6.35) (7.87) 0.035 0.18 (0.59) (4.57) MAX 0.18 0.125 0.011 (4.57) (3.18) MIN (0.28) 0.3 0.018 0.033 0.1 (7.62) (0.46) (0.84) (2.54) P-20A (PLCC) Package 0.173 � 0.008 (4.385 � 0.185) 0.390 � 0.005 SQ (9.906 � 0.125) 0.105 � 0.015 (2.665 � 0.375) 0.353 � 0.003 SQ (8.966 � 0.076) 0.020 (0.51) MIN 0.045 � 0.003 0.035 � 0.01 (1.143 � 0.076) (0.89 � 0.25) NO.1 PIN IDENTIFIER 0.029 � 0.003 (0.737 � 0.076) TOP VIEW 0.017 � 0.004 (0.432 � 0.101) 0.020 (0.51) MAX 0.025 (0.64) MIN 0.02 (0.51) 0.050 0.060 (1.53) MAX (1.27) MIN REV. B –5– AD557–Revision History Location Page Data sheet changed from REV. A to REV. B. Changes to MONOTONICITY section of spec. page . . . . . . . . . 2 –6– REV. B PRINTED IN U.S.A. C00512a–0–1/01 (rev. B)