ANALOG DEVICES AD5555

Dual, Current-Output, Serial-Input, 16-/14-Bit DACs Data Sheet AD5545/AD5555 FEATURES FUNCTIONAL BLOCK DIAGRAM V A V B REF REF 16-bit resolution AD5545 14-bit resolution AD5555 16 OR 14 V DD R A FB ±1 LSB DNL monotonic D0..DX INPUT DAC A SDI I A DAC A OUT ±1 LSB INL REGISTER REGISTER R R A A GND 2 mA full-scale current ±20%, with V = 10 V REF R B FB 0.5 µs settling time CS INPUT DAC B I B DAC B OUT EN REGISTER REGISTER R R 2Q multiplying reference-input 6.9 MHz BW CLK A B GND DAC A Zero or midscale power-up preset B ADDR POWER- Zero or midscale dynamic reset AD5545/ DECODE ON AD5555 RESET 3-wire interface Compact TSSOP-16 package 02918-0-001 DGND RS MSB LDAC Figure 1. APPLICATIONS Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs Programmable attenuator PRODUCT OVERVIEW The AD5545/AD5555 are 16-bit/14-bit, current-output, digital- to-analog converters designed to operate from a single 5 V supply with bipolar output up to ±15 V capability. An external reference is needed to establish the full-scale output-current. An internal feedback resistor (RFB) enhances the resistance and temperature tracking when combined with an external op amp to complete the I-to-V conversion. A serial data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and CS LDAC chip select ( ). Additional function allows simultaneous update operation. The internal reset logic allows power-on preset and dynamic reset at either zero or midscale, depending on the state of the MSB pin. The AD5545/AD5555 are packaged in the compact TSSOP-16 package and can be operated from –40°C to +85°C. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved. AD5545/AD5555 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Grounding ................................................................................... 11 Applications ....................................................................................... 1 Applications Information .............................................................. 12 Product Overview ............................................................................. 1 Stability ........................................................................................ 12 Functional Block Diagram .............................................................. 1 Positive Voltage Output ............................................................. 12 Revision History ............................................................................... 2 Bipolar Output ............................................................................ 12 Specifications ..................................................................................... 3 Programmable Current Source ................................................ 13 Electrical Characteristics ............................................................. 3 DAC with Programmable Input Reference Range ................ 14 Timing Diagrams .......................................................................... 4 Reference Selection .................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Amplifier Selection .................................................................... 15 ESD Caution .................................................................................. 5 Evaluation Board for the AD5545 ................................................ 17 Pin Configuration and Functional Descriptions .......................... 6 System Demonstration Platform .............................................. 17 Typical Performance Characteristics ............................................. 7 Operating the Evaluation Board .............................................. 17 Theory of Operation ........................................................................ 9 Evaluation Board Schematics ................................................... 18 Digital-to-Analog Converter ...................................................... 9 Evaluation Board Layout ........................................................... 21 Serial Data Interface ................................................................... 10 Outline Dimensions ....................................................................... 23 Power-Up Sequence ................................................................... 11 Ordering Guide .......................................................................... 23 Layout and Power Supply Bypassing ....................................... 11 REVISION HISTORY 12/11—Rev. D to Rev. E 4/10—Rev. A to Rev. B Added Figure 13; Renumbered Sequentially ................................ 8 Changes to 2Q Multiplying Reference Input ................................. 1 Changes to AC Characteristics and Endnote 3 in Table 1 ........... 4 5/11—Rev. C to Rev. D Changes to Figure 13 and Figure 15 ............................................... 8 Added Evaluation Board for the AD5545 Section, System Added Reference Selection Section, Amplifier Selection Section, Demonstration Platform Section, and Operating the Evaluation and Table 10 .................................................................................... 15 Board Section .................................................................................. 17 Added Table 11 and Table 12 ........................................................ 16 Added Figure 25 and Figure 26; Renumbered Sequentially ..... 17 Changes to Ordering Guide .......................................................... 17 Added Evaluation Board Schematics Section, Figure 27 .......... 18 9/09—Rev. 0 to Rev. A Added Figure 28 .............................................................................. 19 Added Figure 29 .............................................................................. 20 Changes to Features Section ............................................................ 1 Added Evaluation Board Layout Section, Figure 30, and Changes to Static Performance, Relative Accuracy, AD5545C Figure 31, ......................................................................................... 21 Parameter, Table 1 ............................................................................. 3 Added Figure 32 .............................................................................. 22 Moved ESD Caution.......................................................................... 5 Changes to Ordering Guide .......................................................... 23 Changes to Ordering Guide .......................................................... 16 3/11—Rev. B to Rev. C 7/03—Revision 0: Initial Version Change to Equation 4, Bipolar Output Section .......................... 12 Rev. E | Page 2 of 24 Data Sheet AD5545/AD5555 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5 V ± 10%, I = virtual GND, GND = 0 V, V = 10 V, T = full operating temperature range, unless otherwise noted. DD OUT REF A Table 1. Parameter Symbol Conditions Min Typ Max Unit 1 STATIC PERFORMANCE 16 Resolution N AD5545, 1 LSB = V /2 = 153 µV when V = 10 V 16 Bits REF REF 14 AD5555, 1 LSB = V /2 = 610 µV when V = 10 V 14 Bits REF REF Relative Accuracy INL AD5545B ±2 LSB AD5555C ±1 LSB AD5545C ±1 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current I Data = 0x0000, T = 25°C 10 nA OUT A Data = 0x0000, TA = TA Max 20 nA Full-Scale Gain Error G Data = full scale ±1 ±4 mV FSE 2 Full-Scale Temperature Coefficient TCVFS 1 ppm/°C REFERENCE INPUT VREF Range VREF –12 +12 V 3 Input Resistance R 5 kΩ REF 2 Input Capacitance CREF 5 pF ANALOG OUTPUT Output Current IOUT Data = full scale 2 mA 2 Output Capacitance C Code dependent 200 pF OUT LOGIC INPUTS AND OUTPUT Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage VIH 2.4 V Input Leakage Current I 10 µA IL 2 Input Capacitance CIL 10 pF 2, 4 INTERFACE TIMING 50 MHz 10 ns Clock Input Frequency fCLK ns Clock Width High tCH 10 Clock Width Low t 0 ns CL CS to Clock Setup ns tCSS 10 Clock to CS Hold ns tCSH 5 10 ns Data Setup tDS ns Data Hold tDH 5 ns LDAC Setup t 10 LDS Hold tLDH 10 ns LDAC Width 50 MHz tLDAC SUPPLY CHARACTERISTICS Power Supply Range V range 4.5 5.5 V DD Positive Supply Current IDD Logic inputs = 0 V 10 µA Power Dissipation P Logic inputs = 0 V 0.055 mW DISS Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/% Rev. E | Page 3 of 24 AD5545/AD5555 Data Sheet Parameter Symbol Conditions Min Typ Max Unit AC CHARACTERISTICS Output Voltage Setting Time t To ±0.1% full scale, data = zero scale to 0.5 µs S full scale to zero scale Reference Multiplying BW BW V = 100 mV rms, data = full scale, C1 = 5.6 pF 6.9 MHz REF DAC Glitch Impulse Q V = 0 V, data = midscale minus 1 to midscale –2 nV-s REF Feedthrough Error VOUT/VREF Data = zero scale, VREF = 100 mV rms, –81 dB f = 1 kHz, same channel Digital Feedthrough Q CS = logic high and f = 1 MHz 7 nV-s CLK Total Harmonic Distortion THD V = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz –104 dB REF Analog Crosstalk C V = 0 V, measure V with V = 5 V p-p –95 dB TA REFB OUTB REFA sine wave, data = full scale, f = 1 kHz to 10 kHz Output Spot Noise Voltage e f = 1 kHz, BW = 1 Hz 12 nV/√Hz N 1 All static performance tests (except I ) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 R terminal OUT FB is tied to the amplifier output. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification. 4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. TIMING DIAGRAMS SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 CLK INPUT REG LD t t t t DS DH CH CL CS t t CSS CSH LDAC t LDH t LDS t LDAC 02918-0-003 Figure 2. AD5545 18-Bit Data Word Timing Diagram SDI A1 A0 D13 D12 D11 D10 D09 D08 D1 D0 CLK INPUT REG LD t t t t DS DH CH CL CS t t CSS CSH LDAC t LDH t LDS t LDAC 02918-0-004 Figure 3. AD5555 16-Bit Data Word Timing Diagram Rev. E | Page 4 of 24 Data Sheet AD5545/AD5555 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only and functional operation of the device at these or V to GND –0.3 V to +8 V DD any other conditions above those indicated in the operational V to GND –18 V to +18 V REF section of this specification is not implied. Exposure to absolute Logic Inputs to GND –0.3 V to +8 V maximum rating conditions for extended periods may affect V(IOUT) to GND –0.3 V to VDD + 0.3 V device reliability. Input Current to Any Pin except ±50 mA Supplies ESD CAUTION Package Power Dissipation (T max – T )/θ J A JA Thermal Resistance θ JA 16-Lead TSSOP 150°C/W Maximum Junction Temperature 150°C (T max) J Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Lead Temperature RU-16 (Vapor Phase, 60 sec) 215°C RU-16 (Infrared, 15 sec) 220°C Rev. E | Page 5 of 24 AD5545/AD5555 Data Sheet PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS R A 1 16 CLK FB V A 15 LDAC 2 REF I A 3 14 MSB OUT AD5545/ A A 4 13 V GND DD AD5555 A B DGND 5 TOP VIEW 12 GND (Not to Scale) I B 6 11 CS OUT V B 10 RS 7 REF R B SDI 8 9 FB 02918-0-002 Figure 4. 16-Lead TSSOP Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 RFBA Establish voltage output for DAC A by connecting this pin to an external amplifier output. 2 V A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can REF be tied to the V pin. DD 3 I A DAC A Current Output. OUT 4 AGNDA DAC A Analog Ground. 5 AGNDB DAC B Analog Ground. 6 I B DAC B Current Output. OUT 7 V B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. REF This pin can be tied to the V pin. DD 8 RFBB Establish voltage output for DAC B by the RFBB pin connecting to an external amplifier output. 9 SDI Serial Data Input. Input data loads directly into the shift register. 10 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when MSB = 1. 11 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. This does not affect LDAC operation. 12 DGND Digital Ground Pin. 13 V Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%. DD 14 MSB MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied permanently to ground or VDD. 15 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 7 and Table 8 for operation. 16 CLK Clock Input. Positive edge clocks data into shift register. Rev. E | Page 6 of 24 Data Sheet AD5545/AD5555 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 0248 4096 6144 8192 10240 12288 14336 16384 CODE (Decimal) CODE (Decimal) 02918-0-009 02918-0-012 Figure 5. AD5545 Integral Nonlinearity Error Figure 8. AD5555 Differential Nonlinearity Error 1.0 1.5 V = 2.5V REF 0.8 T = 25°C A 1.0 0.6 0.4 0.5 0.2 INL 0 0 DNL –0.2 –0.5 –0.4 –0.6 –1.0 GE –0.8 –1.0 –1.5 0 8192 16384 24576 32768 40960 49152 57344 65536 2 4 6 8 10 CODE (Decimal) SUPPLY VOLTAGE V (V) DD 02918-0-010 02918-0-013 Figure 6. AD5545 Differential Nonlinearity Error Figure 9. Linearity Errors vs. V DD 1.0 5 V = 5V DD 0.8 T = 25°C A 0.6 4 0.4 0.2 3 0 –0.2 2 –0.4 –0.6 1 –0.8 –1.0 0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CODE (Decimal) LOGIC INPUT VOLTAGE V (V) IH 02918-0-014 02918-0-011 Figure 10. Supply Current vs. Logic Input Voltage Figure 7. AD5555 Integral Nonlinearity Error Rev. E | Page 7 of 24 INL (LSB) DNL (LSB) INL (LSB) DNL (LSB) SUPPLY CURRENT I (LSB) LINEARITY ERROR (LSB) DD AD5545/AD5555 Data Sheet 2 3.0 0 2.5 –2 2.0 –4 0x5555 –6 1.5 0x8000 –8 1.0 0xFFFF –10 0x0000 0.5 –12 –14 0 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M CLOCK FREQUENCY (Hz) FREQUENCY (Hz) 02918-0-117 02918-0-015 Figure 11. Supply Current vs. Clock Frequency Figure 14. Reference Multiplying Bandwidth 90 V = 5V ± 10% DD 80 V = 10V REF CS 70 60 50 40 30 20 V OUT 10 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 02918-0-016 02918-0-018 Figure 12. Power Supply Rejection Ration vs. Frequency Figure 15. Settling Time –3.70 20 –3.75 0 –20 –3.80 –40 –3.85 –60 –3.90 –80 –100 –3.95 –120 –4.00 –140 –4.05 –160 –200 –100 0 100 200 300 400 0 5 10 15 20 25 TIME (ns) 02918-0-119 FREQUENCY (Hz) 02918-0-113 Figure 13. AD5545/AD5555 Analog THD Figure 16. Midscale Transition and Digital Feedthrough Rev. E | Page 8 of 24 SUPPLY CURRENT (mA) POWER SPECTRUM (dB) PSSR (-dB) V (V) GAIN (dB) OUT Data Sheet AD5545/AD5555 THEORY OF OPERATION The AD5545/AD5555 contain a 16-/14-bit, current-output, These DACs are also designed to accommodate ac reference input digital-to-analog converter, a serial-input register, and a DAC signals. The AD5545/AD5555 accommodate input reference register. Both parts require a minimum of a 3-wire serial data voltages in the range of –12 V to +12 V. The reference voltage LDAC inputs exhibit a constant nominal input-resistance value of interface with an additional for dual channel simultaneous 5 kΩ, ±30%. The DAC output (I ) is code dependent, pro- update. OUT ducing various output resistances and capacitances. When DIGITAL-TO-ANALOG CONVERTER choosing an external amplifier, the user should take into The DAC architecture uses a current-steering R-2R ladder account the variation in impedance generated by the AD5545/ design. Figure 17 shows the typical equivalent DAC. The DAC AD5555 on the amplifiers inverting input node. The feedback contains a matching feedback resistor for use with an external resistance in parallel with the DAC ladder resistance dominates I-to-V converter amplifier. The R pin is connected to the FB output voltage noise. output of the external amplifier. The I terminal is connected OUT 5V V IN to the inverting input of the external amplifier. These DACs are V 2.500V OUT ADR03 designed to operate with both negative or positive reference voltages. The VDD power pin is used only by the logic to drive GND the DAC switches on and off. Note that a matching switch is V DD used in series with the internal 5 kΩ feedback resistor. If users R R R R A FB attempt to measure the R value, power must be applied to V V A FB DD REF 2R 2R 2R R 5kΩ +3V to achieve continuity. The V input voltage and the digital data REF S2 S1 I A OUT V CC (D) loaded into the corresponding DAC register, according to V OUT AD8628 Equation 1 and Equation 2, determine the DAC output voltage. V EE V = –V ×D /65,536 (1) AD5545/AD5555 LOAD REF OUT –3V A A GND V = –V ×D /16,384 (2) REF OUT DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED 02918-0-006 DD Note that the output full-scale polarity is the opposite of the Figure 18. Recommended System Connections VREF polarity for dc reference voltages. V DD R R R V REF R FB 2R 2R 2R R 5kΩ S2 S1 I OUT GND DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED DD 02918-0-005 Figure 17. Equivalent R-2R DAC Circuit Rev. E | Page 9 of 24 AD5545/AD5555 Data Sheet CS SERIAL DATA INTERFACE load DAC B data, pull low for an 18-bit duration and program CS DAC B with the proper address and data, then pull high to The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK) LDAC latch data to the DAC B register. Finally, pull low and then serial data interface for single channel update operation. With high to update both the DAC A and DAC B outputs LDAC Table 7 as an example (AD5545), users can tie low and simultaneously. RS CS high, then pull low for an 18-bit duration. New serial data is then clocked into the serial-input register in an 18-bit Table 6 shows that each DAC A and DAC B can be individually data-word format with the MSB bit loaded first. Table 8 defines loaded with a new data value. In addition, a common new data value can be loaded into both DACs simultaneously by setting Bit the truth table for the AD5555. Data is placed on the SDI pin A1 = A0 = high. This command enables the parallel combination and clocked into the register on the positive clock edge of CLK. of both DACs, with I A and I B tied together, to act as one For the AD5545, only the last 18-bits clocked into the serial OUT OUT DAC with significant improved noise performance. register are interrogated when the CS pin is strobed high, transferring the serial register data to the DAC register and ESD Protection Circuits updating the output. If the applied microcontroller outputs All logic input pins contain back-biased ESD protection Zeners serial data in different lengths than the AD5545, such as 8-bit connected to digital ground (DGND) and V as shown in DD bytes, three right justified data bytes can be written to the Figure 19. AD5545. The AD5545 ignores the six MSB and recognizes the V DD 18 LSB as valid data. After loading the serial register, the rising DIGITAL edge of CS transfers the serial register data to the DAC register INPUTS CS and updates the output; during the strobe, the CLK should 5k not be toggled. DGND If users want to program each channel separately but update them 02918-0-007 LDAC RS simultaneously, program and high initially, then pull Figure 19. Equivalent ESD Protection Circuits CS low for an 18-bit duration and program DAC A with the proper address and data bits. CS is then pulled high to latch data to the DAC A register. At this time, the output is not updated. To 1 Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB LSB Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in LDAC are used. If double-buffered data is not needed, the pin can be tied logic low to disable the DAC registers. 1 Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 CS Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 6. Address Decode A1 A0 DAC Decoded 0 0 None 0 1 DAC A 1 0 DAC B 1 1 DAC A and DAC B Rev. E | Page 10 of 24 Data Sheet AD5545/AD5555 1, 2 Table 7. AD5545 Control Logic Truth Table CS LDAC RS CLK MSB Serial Shift Register Function Input Register Function DAC Register H X H H X No effect Latched Latched L L H H X No effect Latched Latched L H H X Shift register data advanced one bit Latched Latched + L H H H X No effect Latched Latched L H H X No effect Selected DAC updated Latched + with current SR current H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X H X No effect Latched Latched + H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000 H X H L H No effect Latched data = 0x8000 Latched data = 0x8000 1 SR = shift register, + = positive logic transition, and X = don’t care. 2 At power-on, both the input register and the DAC register are loaded with all 0s. 1, 2 Table 8. AD5555 Control Logic Truth Table CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register H X H H X No effect Latched Latched L L H H X No effect Latched Latched L H H X Shift register data advanced one bit Latched Latched + L H H H X No effect Latched Latched L H H X No effect Selected DAC updated Latched + with current SR current H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X H X No effect Latched Latched + H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000 H X H L H No effect Latched data = 0x2000 Latched data = 0x2000 1 SR = shift register, + = positive logic transition, and X = don’t care. 2 At power-on, both the input register and the DAC register are loaded with all 0s. (see Figure 20). Users should not apply switching regulators for POWER-UP SEQUENCE V due to the power supply rejection ratio degradation over DD It is recommended to power-up VDD and ground prior to any frequency. reference voltages. The ideal power-up sequence is A x, GND AD5545/ DGND, V , V x, and digital inputs. A noncompliance DD REF AD5555 power-up sequence can elevate reference current, but the device V V DD DD will resume normal operation once V is powered. DD + C2 C1 10F 0.1F A X GND LAYOUT AND POWER SUPPLY BYPASSING It is a good practice to employ compact, minimum lead length DGND layout design. The input leads should be as direct as possible with a minimum conductor length. Ground paths should have 02918-0-008 low resistance and low inductance. Figure 20. Power Supply Bypassing and Grounding Connection Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to GROUNDING the device should be bypassed with 0.01 μF to 0.1 μF disc or The DGND and A x pins of the AD5545/AD5555 refer to the GND chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or digital and analog ground references. To minimize the digital electrolytic capacitors should also be applied at V to minimize DD ground bounce, the DGND terminal should be joined remotely any transient disturbance and to filter any low frequency ripple at a single point to the analog ground plane (see Figure 20). Rev. E | Page 11 of 24 AD5545/AD5555 Data Sheet APPLICATIONS INFORMATION STABILITY BIPOLAR OUTPUT V DD The AD5545/AD5555 is inherently a 2-quadrant multiplying U1 DAC. It can easily be set up for unipolar output operation. The C1 V R DD FB full-scale output polarity is the inverse of the reference input V V I REF REF OUT voltage. V O AD8628 In some applications, it may be necessary to generate the full GND 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished by using an additional external amplifier, AD5545/AD5555 U2 02918-0-020 U4, configured as a summing amplifier (see Figure 23). In this Figure 21. Operational Compensation Capacitor for Gain Peaking circuit, the second amplifier, U4, provides a gain of 2, which Prevention increases the output span magnitude to 5 V. Biasing the external In the I-to-V configuration, the IOUT of the DAC and the amplifier with a 2.5 V offset from the reference voltage results in a inverting node of the op amp must be connected as close as full 4-quadrant multiplying circuit. The transfer equation of this possible, and proper PCB layout techniques must be employed. circuit shows that both negative and positive output voltages are Because every code change corresponds to a step function, gain created because the input data (D) is incremented from code zero peaking may occur if the op amp has limited GBP, and if there (V = −2.5 V) to midscale (V = 0 V) to full scale (V = OUT OUT OUT is excessive parasitic capacitance at the inverting node. +2.5 V). An optional compensation capacitor, C1, can be added for V = (D/32,768 − 1) × V (AD5545) (3) OUT REF stability as shown in Figure 21. C1 should be found empirically, V = (D/8192 − 1) × V (AD5555) (4) OUT REF but 6 pF is generally more than adequate for the compensation. For the AD5545, the external resistance tolerance becomes the POSITIVE VOLTAGE OUTPUT dominant error that users should be aware of. To achieve the positive voltage output, an applied negative R1 R2 reference to the input of the DAC is preferred over the output 10kΩ±0.01% 10kΩ±0.01% inversion through an inverting amplifier because of the C2 resistors’ tolerance errors. To generate a negative reference, the U4 +5V reference can be level shifted by an op amp such that the V +5V OUT 5kΩ±0.01% V and GND pins of the reference become the virtual ground and 1/2 V+ O R3 ADR03 U1 AD8620 C1 −2.5 V, respectively (see Figure 22). V R V– DD FB 5V V V OUT IN V I +5V OUT REF –5V 1/2 ADR03 GND GND AD8620 –2.5 < V < +2.5 O U3 V V OUT IN U4 +5V U1 AD5545/AD5555 U2 02918-0-022 GND C1 V R DD FB 1/2 V+ U3 I Figure 23. Four-Quadrant Multiplying Application Circuit V OUT AD8620 REF V O –2.5V 1/2 V– GND AD8628 –5V AD5545/AD5555 0 < V < +2.5 U2 O 02918-0-021 Figure 22. Positive Voltage Output Configuration Rev. E | Page 12 of 24 Data Sheet AD5545/AD5555 If the resistors are perfectly matched, Z is infinite, which is PROGRAMMABLE CURRENT SOURCE O desirable, and the resistors behave as an ideal current source. Figure 24 shows a versatile V-to-I conversion circuit using On the other hand, if they are not matched, Z can be either O improved Howland Current Pump. In addition to the precision positive or negative. The latter can cause oscillation. As a result, current conversion it provides, this circuit enables a bidirec- C1 is needed to prevent the oscillation. For critical applications, tional current flow and high voltage compliance. This circuit C1 could be found empirically but typically falls in the range of can be used in a 4 mA to 20 mA current transmitter with up to a few picofarads. a 500 Ω of load. In Figure 24, it shows that if the resistor V DD network is matched, the load current is U1 (R2+R3) V R DD FB R1 I = ×V ×D (5) L REF V V I OUT R1' R2' REF REF R3 150kΩ 15kΩ GND AD8628 R3, in theory, can be made small to achieve the current needed C1 10pF within the U3 output current driving capability. This circuit is AD5545/AD5555 U2 versatile such that the AD8510 can deliver ±20 mA in both V DD R3' 50Ω directions, and the voltage compliance approaches 15 V, which U3 V+ is mainly limited by the supply voltages of U3. However, users AD8510 V– must pay attention to the compensation. Without C1, it can be R3 50Ω shown that the output impedance becomes V SS V L R1′R3(R1+R2) Z = (6) O R1 R2 R1(R2′+R3′)–R1′(R2+R3) 150kΩ 15kΩ I LOAD L 02918-0-023 Figure 24. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities Rev. E | Page 13 of 24 AD5545/AD5555 Data Sheet By putting Equations 7 through 10 together, the following DAC WITH PROGRAMMABLE INPUT results: REFERENCE RANGE Because high voltage references can be costly, users may   D C   1 consider using one of the DACs, a digital potentiometer, and a   128D C   V ABV  (11) low voltage reference to form a single-channel DAC with a REF REF D D A C 1  programmable input reference range. This approach optimizes N 2 128D C the programmable range as well as facilitates future system Table 9 shows a few examples of V AB of the 14-bit AD5555. REF upgrades with just software changes. Figure 25 shows this implementation. V AB is in the feedback network, therefore, REF AB vs. D and D of the AD5555 Table 9. VREF B C D D V AB     C A REF R D R WB A WB     V ABV  1 – –V   (7) REF REF REF_AB N     0 X V REF R 2 R WA WA     32 0 1.33 V REF where: 32 8192 1.6 V REF V AB = reference voltage of V A and V B REF REF REF 64 0 2 VREF VREF = external reference voltage 64 8192 4 VREF DA = DAC A digital code in decimal 96 0 4 VREF N = number of bits of DAC 96 8192 –8 V REF RWB and RWA are digital potentiometer 128-step programmable The output of DAC B is, therefore, resistances and are given by D B V V AB (12) D OB REF C N R  R (8) 2 WB AB 128 where DB is the DAC B digital code in decimal. 128D C R  R (9) WA AB The accuracy of V AB is affected by the matching of the input REF 128 and feedback resistors and, therefore, a digital potentiometer is R D WB C used for U4 because of its inherent resistance  (10) R 128D WA C matching. The AD7376 is a 30 V or ±15 V, 128-step digital where D = digital potentiometer digital code in decimal potentiometer. If 15 V or ±7.5 V is adequate for the application, C (0 ≤ D ≤ 127). a 256-step AD5260 digital potentiometer can be used instead. C +5V C1 +15V R A V DD FB I A OUT V+ U4 AB V A REF U1A OP4177 V– A A AD7376 W GND C2 +15V 2.2p –15V U2A 2 U3 V IN 3 5 OP4177 TEMP TRIM AD5555 6 V V REF REF_AB V OUT GND U2C 4 ADR03 C3 R B FB POT B I OUT V B O V B REF U1B OP4177 A B GND U2B 02918-0-024 Figure 25. DAC with Programmable Input Reference Range Rev. E | Page 14 of 24 Data Sheet AD5545/AD5555 The input bias current of an op amp also generates an offset at REFERENCE SELECTION the voltage output because of the bias current flowing in the When selecting a reference for use with the AD55xx series feedback resistor, R . FB of current output DACs, pay attention to the output voltage, temperature coefficient specification of the reference. Choosing Common-mode rejection of the op amp is important in voltage- a precision reference with a low output temperature coefficient switching circuits because it produces a code-dependent error minimizes error sources. Table 10 lists some of the references at the voltage output of the circuit. available from Analog Devices, Inc., that are suitable for use Provided that the DAC switches are driven from true wideband with this range of current output DACs. low impedance sources (V and AGND), they settle quickly. IN Consequently, the slew rate and settling time of a voltage-switching AMPLIFIER SELECTION DAC circuit is determined largely by the output op amp. To obtain The primary requirement for the current-steering mode is an minimum settling time in this configuration, minimize capacitance amplifier with low input bias currents and low input offset voltage. at the VREF node (the voltage output node in this application) of Because of the code-dependent output resistance of the DAC, the DAC. This is done by using low input capacitance buffer the input offset voltage of an op amp is multiplied by the variable amplifiers and careful board design. gain of the circuit. A change in this noise gain between two Analog Devices offers a wide range of amplifiers for both precision adjacent digital fractions produces a step change in the output dc and ac applications, as listed in Table 11 and Table 12. voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Table 10. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) I (mA) Output Noise (µV p-p) Package(s) SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Rev. E | Page 15 of 24 AD5545/AD5555 Data Sheet Table 11. Suitable Analog Devices Precision Op Amps V Maximum I Maximum 0.1 Hz to 10 Hz OS B Part No. Supply Voltage (V) (µV) (nA) Noise (µV p-p) Supply Current (µA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Table 12. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) V (Max) (µV) I (Max) (nA) Package(s) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Rev. E | Page 16 of 24 Data Sheet AD5545/AD5555 EVALUATION BOARD FOR THE AD5545 The EVAL-AD5545SDZ is used in conjunction with an SDP1Z system demonstration platform board available from Analog Devices, which is purchased separately from the evaluation board. The USB-to-SPI communication to the AD5545 is completed using this Blackfin®-based demonstration board. SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, see the system demonstration platform web page. OPERATING THE EVALUATION BOARD The evaluation board requires ±12 V and +5 V supplies. The +12 V V and −12 V V are used to power the output DD SS amplifier, and the +5 V is used to power the DAC (DVDD). Figure 27. Evaluation Board Software—AD5545 Dual DAC Figure 26. Evaluation Board Software – Device Selection Window Rev. E | Page 17 of 24 02918-0-025 02918-0-027 AD5545/AD5555 Data Sheet EVALUATION BOARD SCHEMATICS Figure 28. EVAL-AD5545SDZ Schematic Part A Rev. E | Page 18 of 24 02918-0-028 Data Sheet AD5545/AD5555 Figure 29. EVAL-AD5545SDZ Schematic Part B Rev. E | Page 19 of 24 02918-0-029 AD5545/AD5555 Data Sheet Figure 30. EVAL-AD5545SDZ Schematic Part B Rev. E | Page 20 of 24 02918-0-030 Data Sheet AD5545/AD5555 EVALUATION BOARD LAYOUT Figure 31. Silkscreen Figure 32. Component Side Rev. E | Page 21 of 24 02918-0-032 02918-0-031 AD5545/AD5555 Data Sheet Figure 33. Solder Side Rev. E | Page 22 of 24 02918-0-033 Data Sheet AD5545/AD5555 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE INL DNL Resolution Temperature Package Package Ordering 1, 2 Model LSB LSB (Bits) Range Description Option Qty AD5545BRU ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5545BRU-REEL7 ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5545BRUZ ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5545BRUZ-REEL7 ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5545CRUZ ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5545CRUZ-REEL7 ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5555CRU ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5555CRU-REEL7 ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5555CRUZ ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5555CRUZ-REEL7 ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 1000 EVAL-AD5545SDZ Evaluation Board 1 The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil. 2 Z = RoHS Compliant Part. Rev. E | Page 23 of 24 AD5545/AD5555 Data Sheet NOTES ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02918-0-12/11(E) Rev. E | Page 24 of 24