ANALOG DEVICES AD5554

Quad, Current-Output, Serial-Input 16-/14-Bit DACs Data Sheet AD5544/AD5554 FEATURES FUNCTIONAL BLOCK DIAGRAM V A B C D REF AD5544: 16-bit resolution V DD INL of ±1 LSB (B Grade) D0 R A FB D1 SDI D2 AD5554: 14-bit resolution INPUT DAC A DAC A I A D3 OUT REGISTER REGISTER R R D4 INL of ±0.5 LSB (B Grade) D5 A A GND D6 2 mA full-scale current ± 20%, with V = ±10 V REF D7 R B FB D8 0.9 µs settling time to ±0.1% D9 16 INPUT DAC B I B DAC B OUT REGISTER D10 R REGISTER R 12 MHz multiplying bandwidth D11 A B GND D12 Midscale glitch of −1 nV-sec D13 R C D14 FB Midscale or zero-scale reset D15 INPUT DAC C A0 DAC C I C OUT REGISTER R REGISTER SDO R 4 separate, 4-quadrant multiplying reference inputs A1 A C GND SPI-compatible, 3-wire interface CS R D FB CLK EN Double-buffered registers enable INPUT DAC D I D DAC D OUT REGISTER REGISTER Simultaneous multichannel change R R DAC A B A D GND Internal power-on reset C D 2:4 Temperature range: −40°C to +125°C AD5544 DECODE POWER-ON A F GND RESET Compact 28-lead SSOP and 32-lead LFCSP DGND RS MSB LDAC V SS APPLICATIONS Figure 1. Automatic test equipment Instrumentation Digitally controlled calibration The AD5544 is packaged in the compact 28-lead SSOP and 32- GENERAL DESCRIPTION lead LFCSP. The AD5554 is packed in the compact 28-lead SSOP. The AD5544/AD5554 quad, 16-/14-bit, current output, digital- 0.7 to-analog converters (DACs) are designed to operate from a 2.7 V to 5.5 V supply range. 0.6 The applied external reference input voltage (V x) determines 0.5 REF the full-scale output current. Integrated feedback resistors (R ) FB 0.4 provide temperature-tracking, full-scale voltage outputs when 0.3 combined with an external I-to-V precision amplifier. 0.2 A double-buffered serial data interface offers high speed, 3-wire, 0.1 SPI- and microcontroller-compatible inputs using serial data in (SDI), a chip select (CS), and clock (CLK) signals. In addition, 0 a serial data out pin (SDO) allows for daisy-chaining when multiple –0.1 packages are used. A common, level-sensitive, load DAC strobe –0.2 LDAC ( ) input allows the simultaneous update of all DAC outputs 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to 0 at system turn-on. Figure 2. AD5544 INL vs. Code Plot (T = 25°C) A The MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0 or to half-scale code when MSB = 1. Re Rev. v. F F IIn nffo or rm mat atiio on n ffu urn rniis sh he ed d b by y A An nal alo og g D Dev eviic ce es s i is s b be elliiev eved ed t to o b be ac e acc cu ur rat ate an e and d rel reliiab ablle e.. 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INL ERROR (LSB) 00943-002 00943-001 AD5544/AD5554 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-On Reset .......................................................................... 17 Applications ....................................................................................... 1 ESD Protection Circuits ............................................................ 17 Functional Block Diagram .............................................................. 1 Power Supply Sequence ............................................................. 17 General Description ......................................................................... 1 Layout and Power Supply Bypassing ....................................... 18 Revision History ............................................................................... 2 Grounding ................................................................................... 18 Specifications ..................................................................................... 3 Applications Information .............................................................. 19 AD5544 Electrical Characteristics ............................................. 3 Reference Selection .................................................................... 19 AD5554 Electrical Characteristics ............................................. 4 Amplifier Selection .................................................................... 19 Timing Diagrams .......................................................................... 6 Evaluation Board for the AD5544 ................................................ 21 Absolute Maximum Ratings ............................................................ 7 System Demonstration Platform .............................................. 21 ESD Caution .................................................................................. 7 Operating the Evaluation Board .............................................. 21 Pin Configurations and Function Descriptions ........................... 8 Evaluation Board Schematics ................................................... 22 Typical Performance Characteristics ........................................... 10 Evaluation Board Layout ........................................................... 25 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 27 Digital-to-Analog Converter (DAC) ....................................... 13 Ordering Guide .......................................................................... 28 Serial Data Interface ....................................................................... 15 Truth Tables ................................................................................. 16 REVISION HISTORY Change to Table 2 .............................................................................. 4 1/12—Rev. E to Rev. F 8/09—Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Added Figure 18; Renumbered Sequentially .............................. 11 Changes to Features Section ............................................................ 1 Changes to Evaluation Board Schematics Section ..................... 22 Changes to Figure 2 ........................................................................... 1 6/11—Rev. D to Rev. E Changes to Table 1 ............................................................................. 3 Added 32-Lead LFCSP .................................................. Throughout Changes to Table 2 ............................................................................. 4 Changes to Table 1, Supply Characteristics Parameters .............. 3 Moved Timing Diagram ................................................................... 5 Changes to Table 2, Supply Characteristics Parameters .............. 5 Added Figure 4; Renumbered Sequentially ................................... 5 Added Figure 6, Renumbered Subsequent Figures, Changes Change to Table 3 .............................................................................. 6 to Table 4 ............................................................................................ 7 Changes to Table 4 ............................................................................. 7 Changed Applications Section to Applications Information Changes to Typical Performance Characteristics Section ........... 8 Section, Added Reference Selection and Amplifier Selection Changes to Figure 19 ...................................................................... 10 Sections ............................................................................................ 19 Moved Table 5, Table 6, and Table 7 ............................................ 12 Added Evaluation Board for the AD5544 Section ..................... 21 Moved Truth Tables Section ......................................................... 13 Updated Outline Dimensions ....................................................... 17 Deleted Figure 27; Renumbered Sequentially ............................ 14 Changes to Ordering Guide .......................................................... 18 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 9/09—Rev. C to Rev. D 12/04—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 4 Change to Electrical Characteristics Tables ................................... 4 Changes to Figure 12 ........................................................................ 9 Change to Pin Description Table ................................................. 10 Changes to Figure 19 ...................................................................... 10 Addition of Power Supply Sequence Section .............................. 19 Changes to Table 8 and Table 9 ..................................................... 13 Addition of Layout and Power Supply Bypassing Section ........ 19 Changes to Ordering Guide .......................................................... 16 Addition of Grounding Section .................................................... 19 Addition of Figure 32 ..................................................................... 19 8/09—Rev. B to Rev. C 4/00—Revision 0: Initial Version Change to Table 1 ............................................................................. 3 Rev. F | Page 2 of 28 Data Sheet AD5544/AD5554 SPECIFICATIONS AD5544 ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, V = 0 V, I x = virtual GND, A x = 0 V, V A = V B = V C = V D = 10 V, T = full operating temperature DD SS OUT GND REF REF REF REF A range of −40°C to +125°C, unless otherwise noted. Table 1. Parameter Symbol Test Condition/Comments Min Typ Max Unit 1 STATIC PERFORMANCE 16 Resolution N 1 LSB = V x/2 = 153 µV when V = 10 V 16 Bits REF REF Relative Accuracy INL AD5544BRSZ ±1 LSB AD5544ARSZ ±2 LSB AD5544BCPZ ±1 LSB AD5544ACPZ-1 ±4 LSB Differential Nonlinearity DNL AD5544BRSZ ±1 LSB AD5544ARSZ ±1.5 LSB AD5544BCPZ ±1 LSB AD5544ACPZ-1 ±1 LSB Output Leakage Current I x Data = 0x0000, T = 25°C 10 nA OUT A Data = 0x0000, T = 85°C 20 nA A Full-Scale Gain Error G Data = 0xFFFF ±0.75 ±3 mV FSE 2 Full-Scale Tempco TCV 1 ppm/°C FS Feedback Resistor R x V = 5 V 4 6 8 kΩ FB DD REFERENCE INPUT V x Range V x −15 +15 V REF REF Input Resistance R x 4 6 8 kΩ REF Input Resistance Match R x Channel-to-channel 0.35 % REF 2 Input Capacitance C x 5 pF REF ANALOG OUTPUT Output Current I x Data = 0xFFFF 1.25 2.5 mA OUT 2 Output Capacitance C x Code dependent 35 pF OUT LOGIC INPUT AND OUTPUT Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 1 µA IL 2 Input Capacitance C 10 pF IL Logic Output Low Voltage V I = 1.6 mA 0.4 V OL OL Logic Output High Voltage V I = 100 µA 4 V OH OH 2, 3 INTERFACE TIMING Clock Width High t 25 ns CH Clock Width Low t 25 ns CL CS to Clock Setup t 0 ns CSS Clock to CS Hold t 25 ns CSH Clock to SDO Propagation t 2 20 ns PD Delay Load DAC Pulse Width t 25 ns LDAC Data Setup t 20 ns DS Data Hold t 20 ns DH Load Setup t 5 ns LDS Load Hold t 25 ns LDH SUPPLY CHARACTERISTICS Power Supply Range V 2.7 5.5 V DD RANGE Positive Supply Current I Logic inputs = 0 V 5 µA DD Negative Supply Current I Logic inputs = 0 V, V = −5 V 0.001 9 µA SS SS Rev. F | Page 3 of 28 AD5544/AD5554 Data Sheet Parameter Symbol Test Condition/Comments Min Typ Max Unit Power Dissipation P Logic inputs = 0 V 1.25 mW DISS Power Supply Sensitivity PSS ∆V = ±5% 0.006 %/% DD 4 AC CHARACTERISTICS Output Voltage Settling Time t To ±0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 0.9 µs S Reference Multiplying BW − 3 dB V x = 5 V p-p, data = 0xFFFF, C = 2.0 pF, 12 MHz REF FB Bandwidth (BW) DAC Glitch Impulse Q V x = 8 V, data = 0x0000 to 0x8000 to 0x0000 −1 nV-sec REF Feedthrough Error V x/V x Data = 0x0000, V x = 100 mV rms, f = 100 kHz −65 dB OUT REF REF Crosstalk Error V A/V B Data = 0x0000, V B = 100 mV rms, adjacent channel, −90 dB OUT REF REF f = 100 kHz Digital Feedthrough Q CS = 1, f = 1 MHz 0.6 nV-sec CLK Total Harmonic Distortion THD V x = 5 V p-p, data = 0xFFFF, f = 1 kHz −98 dB REF Output Spot Noise Voltage e f = 1 kHz, BW = 1 Hz 7 nV/√Hz N 1 All static performance tests (except I x) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 R terminal OUT FB is tied to the amplifier output. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All input control signals are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier. AD5554 ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, V = 0 V, I x = virtual GND, A x = 0 V, V A = V B = V C = V D = 10 V, T = full operating temperature DD SS OUT GND REF REF REF REF A range of −40°C to +125°C, unless otherwise noted. Table 2. Parameter Symbol Test Condition/Comments Min Typ Max Unit 1 STATIC PERFORMANCE 14 Resolution N 1 LSB = V x/2 = 610 µV when V x = 10 V 14 Bits REF REF Relative Accuracy INL ±0.5 LSB Differential Nonlinearity DNL ±1 LSB Output Leakage Current I x Data = 0x0000, T = 25°C 10 nA OUT A Data = 0x0000, T = 85°C 20 nA A Full-Scale Gain Error G Data = 0x3FFF ±2 ±10 mV FSE 2 Full-Scale Tempco TCV 1 ppm/°C FS Feedback Resistor R x V = 5 V 4 6 8 kΩ FB DD REFERENCE INPUT V x Range V x −15 +15 V REF REF Input Resistance R x 4 6 8 kΩ REF Input Resistance Match R x Channel-to-channel 1 % REF 2 Input Capacitance C x 5 pF REF ANALOG OUTPUT Output Current I x Data = 0x3FFF 1.25 2.5 mA OUT 2 Output Capacitance C x Code dependent 80 pF OUT LOGIC INPUT AND OUTPUT Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 1 µA IL 2 Input Capacitance C 10 pF IL Logic Output Low Voltage V I = 1.6 mA 0.4 V OL OL Logic Output High Voltage V I = 100 µA 4 V OH OH 2, 3 INTERFACE TIMING Clock Width High t 25 ns CH Clock Width Low t 25 ns CL CS to Clock Setup t 0 ns CSS Clock to CS Hold t 25 ns CSH Rev. F | Page 4 of 28 Data Sheet AD5544/AD5554 Parameter Symbol Test Condition/Comments Min Typ Max Unit Clock to SDO Propagation t 2 20 ns PD Delay Load DAC Pulse Width t 25 ns LDAC Data Setup t 20 ns DS Data Hold t 20 ns DH Load Setup t 5 ns LDS Load Hold t 25 ns LDH SUPPLY CHARACTERISTICS Power Supply Range V 2.7 5.5 V DD RANGE Positive Supply Current I Logic inputs = 0 V 5 µA DD Negative Supply Current I Logic inputs = 0 V, V = −5 V 0.001 9 µA SS SS Power Dissipation P Logic inputs = 0 V 1.25 mW DISS Power Supply Sensitivity PSS ∆V = ±5% 0.006 %/% DD 4 AC CHARACTERISTICS Output Voltage Settling Time t To ±0.1% of full scale, data = 0x0000 to 0x3FFF to 0x0000 0.9 µs S Reference Multiplying BW − 3 dB V x = 5 V p-p, data = 0xFFFF, C = 2.0 pF 12 MHz REF FB Bandwidth (BW) DAC Glitch Impulse Q V x = 8 V, data = 0x0000 to 0x2000 to 0x0000 −1 nV-sec REF Feedthrough Error V x/V x Data = 0x0000, V x = 100 mV rms, f = 100 kHz −65 dB OUT REF REF Crosstalk Error V A/V B Data = 0x0000, V B = 100 mV rms, adjacent channel, −90 dB OUT REF REF f = 100 kHz Digital Feedthrough Q = 1, f = 1 MHz 0.6 nV-sec CS CLK Total Harmonic Distortion THD V x = 5 V p-p, data = 0x3FFF, f = 1 kHz −98 dB REF Output Spot Noise Voltage e f = 1 kHz, BW = 1 Hz 7 nV/√Hz N 1 All static performance tests (except I ) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 R terminal is OUT FB tied to the amplifier output. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All input control signals are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier,. Rev. F | Page 5 of 28 AD5544/AD5554 Data Sheet TIMING DIAGRAMS SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 INPUT REG CLK LD t t t t DS DH CH CL t CSH CS t CSS t LDS t LDAC LDH t t LDAC PD SDO Figure 3. AD5544 Timing Diagram SDI A1 A0 D13 D12 D11 D10 D09 D08 D1 D0 INPUT REG CLK LD t t t t DS DH CH CL t CSH t CS CSS t LDS t LDH LDAC t t LDAC PD SDO Figure 4. AD5554 Timing Diagram Rev. F | Page 6 of 28 00943-005 00943-004 Data Sheet AD5544/AD5554 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND −0.3 V, +8 V DD other conditions above those indicated in the operational V to GND +0.3 V, −7 V SS sections of this specification is not implied. Exposure to V x to GND −18 V, +18 V REF absolute maximum rating conditions for extended periods may Logic Input and Output to GND −0.3 V, +8 V affect device reliability. V(I x) to GND −0.3 V, V + 0.3 V OUT DD A x to DGND −0.3 V, +0.3 V GND Input Current to Any Pin Except Supplies ±50 mA ESD CAUTION Package Power Dissipation (T max − T )/θ J A JA Thermal Resistance θ JA 28-Lead SSOP 100°C/W 32-Lead LFCSP 32.5°C/W Maximum Junction Temperature (T Max) 150°C J Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature Vapor Phase, 60 Sec 215°C Infrared, 15 Sec 220°C Rev. F | Page 7 of 28 AD5544/AD5554 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A A 1 28 GND A D GND I A 2 27 OUT I D OUT V A 3 26 REF V D REF A A 1 24 DGND R A 4 25 R D GND FB FB 2 23 I A V OUT SS MSB 5 24 DGND A F V A 3 22 GND REF AD5544 6 23 V R A 4 21 LDAC RS FB SS AD5544/ TOP VIEW MSB 5 20 SDO V 7 22 A F (Not to Scale) AD5554 DD GND RS 6 19 NC V CS 8 TOP VIEW 21 DD 7 18 LDAC R C FB (Not to Scale) CS 8 17 V C REF CLK 9 20 SDO 10 SDI 19 NC 11 18 R B FB R C FB 12 17 V B REF V C REF 13 16 I B OUT I C OUT NOTES 14 15 A B A C GND GND 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. NC = NO CONNECT Figure 6. LFCSP Pin Configuration Figure 5. TSSOP Pin Configuration Table 4. Pin Function Descriptions LFCSP TSSOP Pin No. Pin No. Mnemonic Description 1 1 A A DAC A Analog Ground. GND 2 2 I A DAC A Current Output. OUT 3 3 V A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be REF tied to the V pin. DD 4 4 R A Establish the voltage output for DAC A by connecting to an external amplifier output. FB 5 5 MSB MSB Bit. Set pin during a reset pulse (RS) or at system power-on if tied to ground or V . DD 6 6 Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code RS (0x8000 for the AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin. Register data = 0x0000 when MSB = 0. 7 7 V Positive Power Supply Input. Specified range of operation: 5 V ± 10%. DD 8 8 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. Does not affect LDAC operation. 9 9 CLK Clock Input. Positive edge clocks data into the shift register. 10 10 SDI Serial Data Input. Input data loads directly into the shift register. 11 11 R B Establish the voltage output for DAC B by connecting to an external amplifier output. FB 12 12 V B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be REF tied to the V pin. DD 13 13 I B DAC B Current Output. OUT 14 14 A B DAC B Analog Ground. GND 15 15 A C DAC C Analog Ground. GND 16 16 I C DAC C Current Output. OUT 17 17 V C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be REF tied to the V pin. DD 18 18 R C Establish the voltage output for DAC C by connecting to an external amplifier output. FB 19 19 NC No Connect. Leave the pin unconnected. 20 20 SDO Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for the AD5544 and 17 clock pulses for the AD5554 after input at the SDI pin. 21 21 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 8 and Table 9 for operation. 22 22 A F High Current Analog Force Ground. GND 23 23 V Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V. SS 24 24 DGND Digital Ground Pin. 25 25 R D Establish the voltage output for DAC D by connecting to an external amplifier output. FB Rev. F | Page 8 of 28 00943-003 CLK 9 32 NC SDI 10 31 NC R B 11 30 NC FB V B 12 29 NC REF I B 13 28 A D OUT GND A B 14 27 I D GND OUT A C 15 26 V D GND REF I C 16 25 R D OUT FB 00943-035 Data Sheet AD5544/AD5554 LFCSP TSSOP Pin No. Pin No. Mnemonic Description 26 26 V D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be REF tied to the V pin. DD 27 27 I D DAC D Current Output. OUT 28 28 A D DAC D Analog Ground. GND N/A 29 NC Do not connect. N/A 30 NC Do not connect. N/A 31 NC Do not connect. N/A 32 NC Do not connect. N/A 33 EPAD Connect the exposed pad to AGNDx. Rev. F | Page 9 of 28 AD5544/AD5554 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.10 1.5 V = 5V DD 0x0FFF V = 10V 0.05 REF 1.0 0 0xF000 –0.05 0.5 0x7FFF –0.10 0x8000 –0.15 0 –0.20 –0.5 –0.25 –0.30 –1.0 –0.35 –1.5 –0.40 –2000 –1500 –1000 –500 0 500 1000 1500 2000 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 CODE OFFSET VOLTAGE (µV) Figure 7. AD5544 DNL vs. Code, T = 25°C Figure 10. AD5544 Integral Nonlinearity Error vs. Op Amp Offset A 0.20 1.00 V = 5V DD V = 10V REF 0.15 0.75 0.10 0.50 0.05 0.25 0x0FFF 0 0 0xF000 –0.05 –0.25 0x8000 –0.10 –0.50 –0.15 –0.75 –0.20 –1.00 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 –1000 –750 –500 –250 0 250 500 750 1000 CODE OP AMP OFFSET (µV) Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset Figure 8. AD5554 INL vs. Code, T = 25°C A 0.10 10 V = 5V DD V = 10V REF 5 0.05 0 0 –5 –0.05 –10 –0.10 –15 –0.15 –20 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 –1500 –1000 –500 0 500 1000 1500 CODE OP AMP OFFSET (µV) Figure 9. AD5554 DNL vs. Code, T = 25°C Figure 12. AD5544 Gain Error vs. Op Amp Offset A Rev. F | Page 10 of 28 DNL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 00943-008 00943-007 00943-006 GAIN ERROR (LSB) DNL (LSB) INL (LSB) 00943-009 00943-013 00943-011 Data Sheet AD5544/AD5554 10,000 –3.88 –3.90 –3.92 1000 ZERO SCALE –3.94 MIDSCALE FULL SCALE –3.96 0x5555 –3.98 100 –4.00 –4.02 10 –4.04 –4.06 1 –4.08 1k 10k 100k 1M 10M 100M 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 CLOCK FREQUENCY (Hz) TIME (µs) Figure 13. AD5544 Midscale Transition Figure 16. AD5544 Power Supply Current vs. Clock Frequency 100 V = 5V DD V = 5V DD V = 10V REF 90 V = 10V REF 80 V OUT 70 60 50 LDAC 40 30 20 10 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 14. AD5544 Large Signal Settling Time Figure 17. AD5544/AD5554 Power Supply Rejection vs. Frequency 0.1 4 20 0 0 –20 0 –4 –40 –60 –8 –80 –0.1 –12 –100 –120 –16 –140 –0.2 –20 –160 –2 0 2 4 6 8 10 0 5k 10k 15k 20k 25k FREQUENCY (Hz) TIME (µs) Figure 18. AD5544/AD5554 Analog THD Figure 15. AD5544 Small Signal Settling Time Rev. F | Page 11 of 28 V (V) OUT V (V) OUT 5V/DIV 00943-018 LDAC (V) 00943–012 00943-019 I (µA) DD POWER SPECTRUM (dB) PSRR (dB) 00943-118 00943-020 00943-015 AD5544/AD5554 Data Sheet 300 250 200 150 100 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT (V) Figure 19. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage Rev. F | Page 12 of 28 SUPPLY CURRENT (µA) 00943-017 Data Sheet AD5544/AD5554 THEORY OF OPERATION The AD5544 and the AD5554 contain four 16-bit and 14-bit, These DACs are also designed to accommodate ac reference input current output DACs, respectively. Each DAC has its own inde- signals. Both the AD5544 and the AD5554 accommodate input pendent multiplying reference input. Both the AD5544 and the reference voltages in the range of −15 V to +15 V. The reference AD5554 use a 3-wire, SPI-compatible serial data interface, with voltage inputs exhibit a constant nominal input resistance of 5 kΩ ± RS 30%. On the other hand, the I A, I B, I C, and I D a configurable asynchronous pin for half-scale (MSB = 1) or OUT OUT OUT OUT DAC outputs are code dependent and produce various output LDAC zero-scale (MSB = 0) preset. In addition, an strobe enables resistances and capacitances. The choice of external amplifier 4-channel, simultaneous updates for hardware synchronized should take into account the variation in impedance generated by output voltage changes. the AD5544/AD5554 on the inverting input node of the amplifier. DIGITAL-TO-ANALOG CONVERTER (DAC) The feedback resistance, in parallel with the DAC ladder resistance, Each part contains four current-steering R-R ladder DACs. dominates output voltage noise. For multiplying mode applications, Figure 20. shows a typical equivalent DAC. Each DAC contains an external feedback compensation capacitor, C , may be needed FB a matching feedback resistor for use with an external I-to-V to provide a critically damped output response for step changes in converter amplifier. The R x pin connects to the output of the reference input voltages. Figure 21 shows the gain vs. frequency FB external amplifier. The I x terminal connects to the inverting performance at various attenuation settings using a 23 pF external OUT input of the external amplifier. The A x pin should be Kelvin- GND feedback capacitor connected across the I x and R x terminals OUT FB connected to the load point, requiring full 16-bit accuracy. These for the AD5544 and the AD5554, respectively. To maintain good DACs are designed to operate with both negative and positive analog performance, power supply bypassing of 0.01 µF, in parallel reference voltage. with 1 µF, is recommended. Under these conditions, a clean power supply with low ripple voltage capability should be used. Switching The V power pin is used only by the logic to drive the DAC DD power supplies is usually not suitable for this application due to switches on and off. Note that a matching switch is used in series the higher ripple voltage and PSS frequency-dependent charac- with the internal 5 kΩ feedback resistor. If users attempt to teristics. It is best to derive the supply of the AD5544/AD5554 measure the value of R , power must be applied to V to achieve FB DD from system analog supply voltages. Do not use the digital continuity. An additional V bias pin is used to guard the substrate SS supply (see Figure 22). during high temperature applications, minimizing zero-scale 2 leakage currents that double every 10°C. The DAC output voltage is determined by V and the digital data (D) in the REF following equations: 0 D (1) V =−V × (for the AD5544) OUT REF 65,536 –2 D (2) V =−V × (for the AD5554) OUT REF –4 16,384 Note that the output polarity is opposite the V polarity for dc REF –6 reference voltages. V DD R R R –8 V X R X FB REF 100k 1M 10M 100M 2R 2R 2R R 5kΩ FREQUENCY (Hz) Figure 21. AD5554 Reference Multiplying Bandwidth vs. Code S2 S1 I X OUT A F GND A X GND FROM OTHER DACS A GND V DGND SS DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY. SWITCHES S1 AND S2 ARE CLOSED, AND V MUST BE POWERED. DD Figure 20. Typical Equivalent DAC Channel Rev. F | Page 13 of 28 00943-025 GAIN (dB) 00943-026 AD5544/AD5554 Data Sheet 15V ANALOG 2R POWER SUPPLY 5V + R V DD AD5544 R X RR R FB V X REF 2R 2R 2R R 5kΩ 15V S2 S1 V I X CC OUT A F V GND OUT A1 A X GND + V EE LOAD FROM OTHER DACS A GND DGND V SS DIGITAL INTERFACE CONNECTIONS OMITTED. FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED, AND V MUST BE POWERED. DD Figure 22. Recommended Kelvin-Sensed Hookup Rev. F | Page 14 of 28 00943-028 Data Sheet AD5544/AD5554 SERIAL DATA INTERFACE Similarly, two right-justified data bytes can be written to the The AD5544/AD5554 use a 3-wire (CS, SDI, CLK), SPI-compatible AD5554. Keeping the CS line low between the first and second serial data interface. Serial data of the AD5544/AD5554 is clocked byte transfer results in a successful serial register update. into the serial input register in an 18-bit and 16-bit data-word format, respectively. The MSB bits are loaded first. Table 5 defines When the data is properly aligned in the shift register, the posi- the 18 data-word bits for the AD5544, and Table 6 defines the CS tive edge of the initiates the transfer of new data to the target 16 data-word bits for the AD5554. Data is placed on the SDI pin DAC register, determined by the decoding of Address Bit A1 and clocked into the register on the positive clock edge of CLK, and Address Bit A0. For the AD5544, Table 5, Table 7, Table 8, subject to the data setup and data hold time requirements specified and Figure 3 define the characteristics of the software serial in the interface timing specifications (see Table 1 and Table 2). interface. Data can be clocked in only while the CS chip select pin is active For the AD5554, Table 6, Table 7, Table 9, and Figure 4 define low. For the AD5544, only the last 18 bits clocked into the serial the characteristics of the software serial interface. Figure 23 and CS Figure 24 show the equivalent logic interface for the key digital register are interrogated when the pin returns to the logic high control pins for the AD5544. The AD5554 has a similar configu- state; extra data bits are ignored. For the AD5554, only the last RS 16 bits clocked into the serial register are interrogated when the ration, except that it has 14 data bits. Two additional pins, and MSB, provide hardware control over the preset function and CS pin returns to the logic high state. Because most microcon- DAC register loading. If these functions are not needed, the RS trollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the AD5544. Keeping the CS line low pin can be tied to logic high. The asynchronous input RS pin between the first, second, and third byte transfers results in a forces all input and the DAC registers to either the zero-code successful serial register update. state (MSB = 0) or the half-scale state (MSB = 1). 1 Table 5. AD5544 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format) MSB LSB B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the CS line returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. 1 Table 6. AD5554 Serial Input Register Data Format (Data Is Loaded in the MSB-First Format) MSB LSB B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the positive edge of the CS line returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 7. Address Decode A1 A0 DAC Decoded 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D Rev. F | Page 15 of 28 AD5544/AD5554 Data Sheet TRUTH TABLES 1 Table 8. AD5544 Control Logic Truth Table 2 3 CS LDAC RS CLK MSB Serial Shift Register Function Input Register Function DAC Register High X High High X No effect Latched Latched Low Low High High X No effect Latched Latched 3 Low High High X Shift register data advanced one bit Latched Latched ￪+ Low High High High X No effect Latched Latched 3 Low High High X No effect Selected DAC updated with Latched ￪+ 4 current shift register contents High X Low High X No effect Latched Transparent High X High High X No effect Latched Latched 3 High X High X No effect Latched Latched ￪+ High X High Low 0 No effect Latched data = 0x0000 Latched data = 0x0000 High X High Low High No effect Latched data = 0x8000 Latched data = 0x8000 1 For the AD5544, data appears at the SDO pin 19 clock pulses after input at the SDI pin. 2 X = don’t care. 3 ￪ + is a positive logic transition . 4 At power-on, both the input register and the DAC register are loaded with all 0s. 1 Table 9. AD5554 Control Logic Truth Table 2 3 3 CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register High X High High X No effect Latched Latched Low L High High X No effect Latched Latched 3 Low High High X Shift register data advanced one bit Latched Latched ￪+ Low High High High X No effect Latched Latched 3 Low High High X No effect Selected DAC updated with Latched ￪+ 4 current shift register contents High X Low High X No effect Latched Transparent High X High High X No effect Latched Latched 3 High X High X No effect Latched Latched ￪+ High X High Low 0 No effect Latched data = 0x0000 Latched data = 0x0000 High X High Low High No effect Latched data = 0x2000 Latched data = 0x2000 1 For the AD5554, data appears at the SDO pin 17 clock pulses after input at the SDI pin. 2 X = don’t care. 3 ￪ + is a positive logic transition . 4 At power-on, both the input register and the DAC register are loaded with all 0s. Rev. F | Page 16 of 28 Data Sheet AD5544/AD5554 V A B C D REF CS EN AD5544 V DD CLK R A FB SDI D0 16 INPUT DAC A D1 I A DAC A OUT REGISTER REGISTER R D2 R D3 A A GND D4 D5 D6 D7 D8 D9 D10 R B FB D11 INPUT DAC B D12 DAC B I B OUT REGISTER REGISTER R R D13 D14 A B DAC A GND SDO D15 B A0 C A1 D 2:4 DECODE R C FB INPUT DAC C DAC C I C OUT REGISTER REGISTER R R A C GND R D FB INPUT DAC D DAC D I D OUT REGISTER REGISTER R R A D GND SET SET MSB MSB A F POWER- GND ON RESET DGND MSB RS V LDAC SS Figure 23. System Level Digital Interfacing TO INPUT REGISTER ESD PROTECTION CIRCUITS A All logic input pins contain back-biased ESD protection Zener ADDRESS B CS C diodes that are connected to ground (DGND) and V , as DECODER DD D shown in Figure 25. EN V DD SHIFT REGISTER CLK 5kΩ DIGITAL SDI TH TH 19 /17 INPUTS CLOCK SDO DGND Figure 24. AD5544/AD5554 Equivalent Logic Interface Figure 25. Equivalent ESD Production Circuits POWER-ON RESET POWER SUPPLY SEQUENCE When the V power supply is turned on, an internal reset strobe DD As standard practice, it is recommended that V , V , and ground forces all the input and DAC registers to the zero-code state or DD SS be powered up prior to any reference. The ideal power-up sequence half-scale state, depending on the MSB pin voltage. The V power DD is as follows: A x, DGND, V , V , V x, and the digital inputs. GND DD SS REF supply should have a smooth positive ramp without drooping to A noncompliance power-up sequence may elevate the reference have consistent results, especially in the region of V = 1.5 V to DD current, but the devices resume normal operation once V and DD 2.3 V. The V supply has no effect on the power-on reset perform- SS V are powered up. SS ance. The DAC register data stays at a zero-scale or half-scale setting until a valid serial register data load takes place. Rev. F | Page 17 of 28 00943-030 00943-031 00943-029 AD5544/AD5554 Data Sheet AD5544/AD5554 LAYOUT AND POWER SUPPLY BYPASSING V DD V DD It is good practice to employ a compact, minimum lead length + C3 C1 10µF 0.1µF layout design. The leads to the input should be as direct as possible A X GND C2 C4 with a minimum conductor length. Ground paths should have 10µF 0.1µF V low resistance and low inductance. V SS SS DGND Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device Figure 26. Power Supply Bypassing and Grounding Connection should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capaci- GROUNDING tors should also be applied at V to minimize any transient DD The DGND and A x pins of the AD5544/AD5554 serve as GND disturbance and filter any low frequency ripple (see Figure 26). digital and analog ground references. To minimize the digital Users should not apply switching regulators for V due to the DD ground bounce, the DGND terminal should be joined remotely power supply rejection ratio (PSRR) degradation over frequency. at a single point to the analog ground plane (see Figure 26). Rev. F | Page 18 of 28 00943-032 Data Sheet AD5544/AD5554 REFERENCE SELECTION APPLICATIONS INFORMATION When selecting a reference for use with the AD55xx series The AD5544/AD5554 are, inherently, two-quadrant multiplying of current output DACs, pay attention to the output voltage, DACs. That is, they can be easily set up for unipolar output temperature coefficient specification of the reference. Choosing operation. The full-scale output polarity is the inverse of the a precision reference with a low output temperature coefficient reference input voltage. minimizes error sources. Table 10 lists some of the references In some applications, it may be necessary to generate the full available from Analog Devices, Inc., that are suitable for use four-quadrant multiplying capability or a bipolar output swing. with this range of current output DACs. This is easily accomplished using an additional external ampli- AMPLIFIER SELECTION fier (A2) configured as a summing amplifier (see Figure 27). The primary requirement for the current-steering mode is an 10kΩ 10kΩ amplifier with low input bias currents and low input offset voltage. 10V Because of the code-dependent output resistance of the DAC, 5kΩ V REF A2 V OUT the input offset voltage of an op amp is multiplied by the variable AD588 gain of the circuit. A change in this noise gain between two –10V < V < +10V OUT adjacent digital fractions produces a step change in the output V DD V X R X REF FB voltage due to the amplifier’s input offset voltage. This output I X OUT ONE CHANNEL voltage change is superimposed upon the desired change in AD5544 A1 output between the two codes and gives rise to a differential V A F SS GND A X GND linearity error, which, if large enough, can cause the DAC to be nonmonotonic. DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY. The input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the Figure 27. Four-Quadrant Multiplying Application Circuit feedback resistor, R . FB In this circuit, the first and second amplifiers (A1 and A2) Common-mode rejection of the op amp is important in voltage- provide a total gain of 2, which increases the output voltage span switching circuits because it produces a code-dependent error to 20 V. Biasing the external amplifier with a 10 V offset from at the voltage output of the circuit. the reference voltage results in a full four-quadrant multiplying circuit. The transfer equation of this circuit shows that both Provided that the DAC switches are driven from true wideband, negative and positive output voltages are created as the input low impedance sources (V and AGND), they settle quickly. IN data (D) is incremented from code zero (V = −10 V) to OUT Consequently, the slew rate and settling time of a voltage-switching midscale (V = 0 V) to full scale (V = 10 V). OUT OUT DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance D   (3) at the V node (the voltage output node in this application) of V  − 1× − V (for the AD5544) REF OUT REF 32,768   the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. D   V − 1 × −V (for the AD5554) (4)   OUT REF 8192 Analog Devices offers a wide range of amplifiers for both precision   dc and ac applications, as listed in Table 11 and Table 12. Rev. F | Page 19 of 28 00943-0-033 AD5544/AD5554 Data Sheet Table 10. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) I (mA) Output Noise (µV p-p) Package(s) SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Table 11. Suitable Analog Devices Precision Op Amps V Maximum I Maximum 0.1 Hz to 10 Hz Supply OS B Part No. Supply Voltage (V) (µV) (nA) Noise (µV p-p) Current (µA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8, PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Table 12. Suitable Analog Devices High Speed Op Amps Slew Rate Part No. Supply Voltage (V) BW at ACL (MHz) V (Max) (µV) I (Max) (nA) Package(s) (V/µs) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8392 10 to 24 65 900 5000 15,000 TSSOP-28, LFCSP-32 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000, 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Rev. F | Page 20 of 28 Data Sheet AD5544/AD5554 EVALUATION BOARD FOR THE AD5544 The EVAL-AD5544SDZ is used in conjunction with an SDP1Z system demonstration platform board available from Analog Devices, which is purchased separately from the evaluation board. The USB-to-SPI communication to the AD5544 is completed using this Blackfin®-based demonstration board. SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, see the system demonstration platform web page. OPERATING THE EVALUATION BOARD The evaluation board requires ±12 V and +5 V supplies. The +12 V V and −12 V V are used to power the output DD SS amplifier, and the +5 V is used to power the DAC (DVDD). Figure 29. Evaluation Board Software—AD5544 Quad DAC Figure 28. Evaluation Board Software—Device Selection Window Rev. F | Page 21 of 28 00943-100 00943-101 AD5544/AD5554 Data Sheet EVALUATION BOARD SCHEMATICS Figure 30. EVAL-AD5544SDZ Schematic Part A Rev. F | Page 22 of 28 VSS C26 10uF C14 5.6pF DVDD VOUTB1 C31 0.1uF C27 10uF 4 VOUT B1 2 - V- 6 AD8065 3 V+ + J5 C29 0.1uF 7 C38 10uF U1 SCLK1 SDIN1 /CS1 DGND VDD C39 0.1uF U2 VDD 16 SCLK SCLK 9 8 SDIN SDIN RFBB VSS 11 6 /CS C10 10uF CS IOUTB 5 /LDAC1 /RS1 MSB1 C9 AGNDB 5.6pF C11 0.1uF VOUTA1 1 RFBA VOUT A1 4 2 3 IOUTA - V- 15 6 /LDAC LDAC AD8065 3 4 V+ AGNDA + 10 /RS J3 RS 7 2 VREFA U4 C12 10uF VREFA 14 7 MSB VREFB MSB VREFB DGND VDD AD5545 CRUZ C13 0.1uF DGND 12 13 + + + + + 00943-102 Data Sheet AD5544/AD5554 BMODE1: Pull up with a 10Kresistor to set SDP to boot froma SPI FLASH on the daughter board J11 60 61 RESET_IN BMODE1 59 62 UART_RX UART_TX 58 63 GND GND 57 64 Board ID EEPROM (24LC64) must be on I2C bus 0, address is at user discretion NC NC 56 65 SDP NC NC 55 66 STANDARD NC NC 3.3V_BF 54 67 CONNECTOR NC NC U10 53 68 NC NC 52 69 1 8 GND GND A0 VCC 51 70 2 7 NC NC A1 WP 50 71 3 6 NC NC A2 SCL 49 72 4 5 * TMR_C TMR_D VSS SDA 48 73 TIMERS TMR_A TMR_B 47 74 24LC64 GPIO6 GPIO7 46 75 GND GND 45 76 GENERAL GPIO4 GPIO5 MSB 44 77 INPUT/OUTPUT GPIO2 GPIO3 43 78 GPIO0 GPIO1 /RS /LDAC 42 79 SCL_1 SCL_0 41 80 I2C SDA_1 SDA_0 40 81 GND GND 39 82 Main I2C bus (Connected to blackfin TWI - Pull up resistors not required) SPI_SEL1/SPI_SS SPI_CLK 38 83 SPI_SEL_C SPI_MISO 37 84 SPI I2C bus 1 is common across both connectors on SDP - Pull up resistors required SPI_SEL_B SPI_MOSI 36 85 (connected to blackfin GPIO - use I2C_0 first) GND SPI_SEL_A 35 86 SPORT_INT GND 34 87 * SPORT_DT3 SPORT_TSCLK SCLK 33 88 * SPORT_DT2 SPORT_DT0 SDIN 32 89 SPORT SPORT_DT1 SPORT_TFS /CS 31 90 SPORT_DR1 SPORT_RFS 30 91 * SPORT_DR2 SPORT_DR0 SDO 29 92 * SPORT_DR3 SPORT_RSCLK 28 93 GND GND 27 94 PAR_FS1 PAR_CLK 26 95 PAR_FS3 PAR_FS2 25 96 PAR_A1 PAR_A0 24 97 PAR_A3 PAR_A2 23 98 GND GND 22 99 PAR_INT PAR_CS 21 100 PAR_RD PAR_WR 20 101 PAR_D1 PAR_D0 19 102 PARALLEL PAR_D3 PAR_D2 18 103 PORT PAR_D5 PAR_D4 17 104 GND GND 16 105 PAR_D7 PAR_D6 15 106 PAR_D9 PAR_D8 14 107 PAR_D11 PAR_D10 13 108 PAR_D13 PAR_D12 12 109 PAR_D14 GND 11 110 GND PAR_D15 10 111 * * PAR_D17 PAR_D16 9 112 * * PAR_D19 PAR_D18 USB_VBUS 3.3V_BF 8 113 * * PAR_D21 PAR_D20 7 114 * * PAR_D23 PAR_D22 6 115 GND GND 5 116 USB_VBUS VIO(+3.3V) VIO: USE to set IO voltage max draw 20mA 4 117 GND GND 3 118 GND GND 2 119 NC NC 1 120 *NC on BLACKFIN SDP VIN NC VIN: Use this pin to power the SDP requires 4-7V 200mA Figure 31. EVAL-AD5544SDZ Schematic Part B Rev. F | Page 23 of 28 00943-103 AD5544/AD5554 Data Sheet Figure 32. EVAL-AD5544SDZ Schematic Part C Rev. F | Page 24 of 28 VSS VDD J1-1 10uF C48 C47 + VOUTD 1.8pF 0.1uF C49 C1 C4 10uF 0.1uF 4 2 J1-2 - V- 6 DVDD VOUT D 3 V+ + AD8065 J16 7 + C50 10uF C2 C5 C16 U6 10uF 10uF 0.1uF VDD 0.1uF C51 VSS J1-3 C17 VSS 0.1uF 10uF C36 SCLK SDIN /CS SDO C35 J4-1 DVDD 1.8pF VOUTC 0.1uF U5 C44 + VDD VOUT C C3 C6 9 SCLK SCLK 4 J15 25 2 0.1uF 10uF RFBD - V- 10 6 SDIN SDIN 27 3 V+ IOUTD + J4-2 AD8065 8 /CS CS 7 28 AGNDD C45 10uF 20 SDO U9 SDO 18 VDD /LDAC /RS MSB RFBC C46 0.1uF 16 IOUTC 21 15 /LDAC LDAC AGNDC 6 11 /RS RS RFBB 13 IOUTB 5 MSB MSB VSS 14 AGNDB C30 10uF AD5544 C28 4 1.8pF VOUTB RFBA C32 0.1uF 23 2 VOUT B NC IOUTA 19 VSS NC1 4 J14 1 2 10uF C22 AGNDA - V- 22 6 C21 AGNDF 3 1.8pF V+ + AD8065 3 VOUTA C23 0.1uF VREFA 7 12 VREFB C33 17 VOUT A 10uF U8 VREFC 26 4 J13 VREFD 2 VDD - V- 6 C34 0.1uF 3 V+ DGND + AD8065 7 VREFA VREFB VREFC VREFD C24 VREFA 10uF U7 VREFB VDD ADR01BKSZ U3 VDD 3 LK2 C25 0.1uF +VIN 4 VOUT A 5 B TRIM C18 + C19 C20 C GND D 0.1uF 10uF 2 0.1uF 24 7 + + + + + + + + + 00943-104 Data Sheet AD5544/AD5554 EVALUATION BOARD LAYOUT Figure 33. Silkscreen Figure 34. Component Side Rev. F | Page 25 of 28 00943-106 00943-105 AD5544/AD5554 Data Sheet Figure 35. Solder Side Rev. F | Page 26 of 28 00943-107 Data Sheet AD5544/AD5554 OUTLINE DIMENSIONS 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 7.40 1 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 COPLANARITY PLANE 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 36. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC EXPOSED 3.65 PAD 3.50 SQ 3.45 8 17 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 37. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-11) Dimensions shown in millimeters Rev. F | Page 27 of 28 PIN 1 INDICATOR 060106-A 112408-A AD5544/AD5554 Data Sheet ORDERING GUIDE Temperature Package 1 Model RES Bit INL LSB DNL LSB Range Package Description Option AD5544ARS 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5544ARSZ 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5544ARSZ-REEL7 16 ±2 ±1.5 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5544BRSZ 16 ±1 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5544BRSZ-REEL7 16 ±1 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5544ACPZ-1-R2 16 ±4 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11 AD5544ACPZ-1-RL7 16 ±4 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11 AD5544BCPZ-R2 16 ±1 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11 AD5544BCPZ-RL7 16 ±1 ±1 −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11 AD5554BRSZ 14 ±0.5 ±1 −40°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28 EVAL-AD5544SDZ Evaluation Board 1 Z = RoHS Compliant Part. 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2000–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00943-0-1/12(F) Rev. F | Page 28 of 28