ANALOG DEVICES AD5547

Dual-Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors Data Sheet AD5547/AD5557 FEATURES FUNCTIONAL BLOCK DIAGRAM R R V R 1A COMA REFA OFSA Dual channel R FBA 16-bit resolution: AD5547 V DD 14-bit resolution: AD5557 INPUT DAC A D0..D15 DAC A I D0 TO D15 OUTA 2- or 4-quadrant, 6.8 MHz BW multiplying DAC REGISTER REGISTER OR (AD5547) RS RS AGNDA D0..D13 D0 TO D13 ±1 LSB DNL (AD5557) ±1 LSB INL AGNDB Operating supply voltage: 2.7 V to 5.5 V DAC B INPUT DAC B I OUTB REGISTER REGISTER Low noise: 12 nV/√Hz RS RS DAC A Low power: I = 10 μA max WR DAC B DD R FBB R OFSB 0.5 μs settling time POWER A0, A1 ADDR ON DECODE AD5547/AD5557 Built-in R facilitates current-to-voltage conversion FB RESET Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V, DGND RS MSB LDAC R R V 1B COMB REFB or ±10 V outputs Figure 1. 2 mA full-scale current ± 20%, with V = 10 V REF Extended automotive operating temperature range GENERAL DESCRIPTION −40°C to +125°C The AD5547/AD5557 are dual precision, 16-/14-bit, multiplying, Selectable zero-scale/midscale power-on presets low power, current-output, parallel input, digital-to-analog Compact 38-lead TSSOP package converters (DACs). They are designed to operate from single +5 V supply with ±10 V multiplying references for 4-quadrant outputs with 6.8 MHz bandwidth. APPLICATIONS Automatic test equipment The built-in, 4-quadrant resistors facilitate resistance matching Instrumentation and temperature tracking, which minimize the number of Digitally controlled calibration components needed for multiquadrant applications. In addition, Digital waveform generation the feedback resistor (RFB) simplifies the I-to-V conversion with an external buffer. The AD5547/AD5557 are available in a compact, 38-lead TSSOP package and operate at the extended automotive temperature range of −40°C to +125°C. VREF U1 –VREF C1 R R V R R 1A COMA REFA OFSA FBA C2 ROFS RFB R1 R2 U2 IOUTA VOUTA 16-/14-BIT AD5547/AD5557 16/14 DATA DAC A AGNDA –VREF TO +VREF POWER-ON RESET WR LDAC RS MSB A0, A1 WR (ONE CHANNEL SHOWN ONLY) 2 LDAC RS MSB A0, A1 Figure 2. 16-/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Is Shown) Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04452-002 04452-013 AD5547/AD5557 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Section................................................................................ 12  Applications....................................................................................... 1  Digital Section ............................................................................ 13  Functional Block Diagram .............................................................. 1  PCB Layout, Power Supply Bypassing, and Ground Connections ................................................................................ 13  General Description ......................................................................... 1  Applications Information .............................................................. 14  Revision History ............................................................................... 2  Unipolar Mode ........................................................................... 14  Specifications..................................................................................... 3  Bipolar Mode .............................................................................. 16  Electrical Characteristics............................................................. 3  Reference Selection .................................................................... 18  Absolute Maximum Ratings............................................................ 5  Amplifier Selection .................................................................... 18  ESD Caution.................................................................................. 5  Outline Dimensions....................................................................... 20  Pin Configurations and Function Descriptions ........................... 6  Ordering Guide .......................................................................... 20  Typical Performance Characteristics ........................................... 10  Circuit Operation ........................................................................... 12  REVISION HISTORY 11/11—Rev. B to Rev. C 9/09—Rev. 0 to Rev. A Added Figure 14; Renumbered Sequentially .............................. 11 Changes to Features Section ............................................................1 Changes to Static Performance, Relative Accuracy, 4/10—Rev. A to Rev. B Grade: AD5547C Parameter, Table 1..............................................3 Changes to Features Section and General Description Section . 1 Changes to Ordering Guide .......................................................... 19 Changes to Table 1............................................................................ 3 Deleted Figure 17 and Figure 18; Renumbered Sequentially ... 10 1/04—Revision 0: Initial Version Changes to Figure 15 and Figure 16............................................. 11 Changes to Figure 20...................................................................... 14 Added Reference Selection Section, Amplifier Selection Section, Table 10, and Table 11; Renumbered Sequentially..................... 18 Added Table 12 ............................................................................... 19 Rev. C | Page 2 of 20 Data Sheet AD5547/AD5557 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, I = virtual GND, GND = 0 V, V = −10 V to +10 V, T = −40°C to +125°C, unless otherwise noted. DD OUT REF A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit 1 STATIC PERFORMANCE 16 Resolution N AD5547, 1 LSB = VREF/2 = 153 μV at VREF = 10 V 16 Bits 14 AD5557, 1 LSB = V /2 = 610 μV at V = 10 V 14 Bits REF REF Relative Accuracy INL Grade: AD5557C ±1 LSB Grade: AD5547B ±2 LSB Grade: AD5547C ±1 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current I Data = zero scale, T = 25°C 10 nA OUT A Data = zero scale, T = T maximum 20 nA A A Full-Scale Gain Error G Data = full scale ±1 ±4 mV FSE Bipolar Mode Gain Error GE Data = full scale ±1 ±4 mV Bipolar Mode Zero-Scale Error GZSE Data = full scale ±1 ±3 mV 2 Full-Scale Temperature Coefficient TCVFS 1 ppm/°C REFERENCE INPUT VREF Range VREF −18 +18 V REF Input Resistance REF 4 5 6 kΩ R1 and R2 Resistance R1 and R2 4 5 6 kΩ R1-to-R2 Mismatch Δ(R1 to R2) ±0.5 ±1.5 Ω Feedback and Offset Resistance RFB, ROFS 8 10 12 kΩ 2 Input Capacitance CREF 5 pF ANALOG OUTPUT Output Current IOUT Data = full scale 2 mA 2 Output Capacitance COUT Code dependent 200 pF LOGIC INPUT AND OUTPUT Logic Input Low Voltage VIL VDD = 5 V 0.8 V VDD = 3 V 0.4 V Logic Input High Voltage VIH VDD = 5 V 2.4 V V = 3 V 2.1 V DD Input Leakage Current I 10 μA IL 2 Input Capacitance CIL 10 pF 2, 3 INTERFACE TIMING See Figure 3 Data to WR Setup Time t V = 5 V 20 ns DS DD VDD = 3 V 35 ns Data to WR Hold Time tDH VDD = 5 V 0 ns VDD = 3 V 0 ns WR Pulse Width t V = 5 V 20 ns DD WR VDD = 3 V 35 ns LDAC Pulse Width tLDAC VDD = 5 V 20 ns V = 3 V 35 ns DD RS Pulse Width t V = 5 V 20 ns RS DD VDD = 3 V 35 ns WR to LDAC Delay Time tLWD VDD = 5 V 0 ns VDD = 3 V 0 ns Rev. C | Page 3 of 20 AD5547/AD5557 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE 2.7 5.5 V Positive Supply Current IDD Logic inputs = 0 V 10 μA Power Dissipation P Logic inputs = 0 V 0.055 mW DISS Power Supply Sensitivity P ∆V = ±5% 0.003 %/% SS DD 4 AC CHARACTERISTICS Output Voltage Settling Time t To ±0.1% of full scale, data cycles from zero scale 0.5 μs S to full scale to zero scale Reference Multiplying BW BW VREF = 100 mV rms, data = full scale 6.8 MHz DAC Glitch Impulse Q VREF = 0 V, midscale – 1 to midscale −3.5 nV-s Multiplying Feedthrough Error VOUT/VREF VREF = 100 mV rms, f = 10 kHz −78 dB Digital Feedthrough Q WR = 1, LDAC toggles at 1 MHz 7 nV-s D Total Harmonic Distortion THD V = 5 V p-p, data = full scale, f = 1 kHz −104 dB REF Output Noise Density e f = 1 kHz, BW = 1 Hz 12 nV/√Hz N Analog Crosstalk CAT Signal input at Channel A and measures the −95 dB output at Channel B, f = 1 kHz 1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is tied to the amplifier output. The +IN pin of the OP97 is grounded, and the I of the DAC is tied to the OP97’s −IN pin. Typical values represent average readings OUT measured at 25°C. 2 Guaranteed by design; not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used. Timing Diagram t WR WR DATA t DH t DS t LWD LDAC t LDAC t RS RS Figure 3. AD5547/AD5557 Timing Diagram Rev. C | Page 4 of 20 04452-018 Data Sheet AD5547/AD5557 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress V to GND −0.3 V to +8 V DD rating only; functional operation of the device at these or any R , R , R1, R , and VREF to GND −18 V to +18 V FB OFS COM other conditions above those indicated in the operational Logic Inputs to GND −0.3 V to +8 V section of this specification is not implied. Exposure to absolute V(IOUT) to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Input Current to Any Pin except Supplies ±50 mA 1 device reliability. Thermal Resistance (θJA) Maximum Junction Temperature (T ) 150°C J MAX Operating Temperature Range −40°C to +125°C ESD CAUTION Storage Temperature Range −65°C to +150°C Lead Temperature Vapor Phase, 60 sec 215°C Infrared, 15 sec 220°C 1 Package power dissipation = (TJ MAX − TA)/θJA. Rev. C | Page 5 of 20 AD5547/AD5557 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D1 1 38 D2 37 D0 2 D3 R 3 36 D4 OFSA R 4 35 D5 FBA R 5 34 D6 1A R 6 33 D7 COMA 32 D8 V 7 REFA I 8 31 D9 OUTA AD5547 30 D10 AGNDA 9 TOP VIEW 29 VDD DGND 10 (Not to Scale) 28 D11 AGNDA 11 27 D12 I 12 OUTB 26 D13 V 13 REFB 25 D14 R 14 COMB 24 D15 R 15 1B 23 RS R 16 FBB 22 MSB R 17 OFSB 21 LDAC WR 18 20 A1 A0 19 Figure 4. AD5547 Pin Configuration Table 3. AD5547 Pin Function Descriptions Pin No. Mnemonic Function D0 to D15 Digital Input Data Bits D0 to D15. Signal level must be ≤ V + 0.3 V. 1, 2, 24 to DD 28, 30 to 38 3 ROFSA Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, R ties to R . In 4-quadrant mode, R OFSA FBA OFSA ties to R and the external reference. 1A 4 R Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. FBA 5 R1A 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do not connect when operating in unipolar mode. 6 RCOMA Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting node of the reference amplifier. In 2-quadrant mode, R shorts to the associated V pin. Do not connect if COMA REFA operating in unipolar mode. 7 V REFA DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external reference amplifier. 8 IOUTA DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output. 9 AGNDA DAC A Analog Ground. 10 DGND Digital Ground. 11 AGNDB DAC B Analog Ground. 12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. 13 VREFB DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured with an external op amp for 4-quadrant multiplying, V becomes –V . REFB REF 14 R Center Tap Point of the Two 4-Quadrant Resistors, R and R . In 4-quadrant mode, R ties to the inverting COMB 1B 2B COMB node of the reference amplifier. In 2-quadrant mode, R shorts to the V pin. Do not connect if operating in COMB REFB unipolar mode. 15 R1B 4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not connect if operating in unipolar mode. 16 R Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. FBB 17 R Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, R ties to R . In 4-quadrant mode, R OFSB OFSB FBB OFSB ties to R1B and an external reference. 18 WR Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. Signal level must be ≤VDD + 0.3 V. Rev. C | Page 6 of 20 04452-003 Data Sheet AD5547/AD5557 Pin No. Mnemonic Function 19 A0 Address Pin 0. Signal level must be ≤VDD + 0.3 V. 20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V. 21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. 22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤V + 0.3 V. DD 23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. 29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Rev. C | Page 7 of 20 AD5547/AD5557 Data Sheet NC 1 38 D0 NC 2 37 D1 R 3 36 D2 OFSA 35 D3 R 4 FBA R 5 34 D4 1A 33 D5 R 6 COMA V 7 32 D6 REFA 31 D7 I 8 OUTA AD5557 30 D8 AGNDA 9 DGND 10 TOP VIEW 29 VDD (Not to Scale) 28 D9 AGNDB 11 I 12 27 D10 OUTB 26 D11 V 13 REFB 25 D12 R 14 COMB 24 D13 R 15 1B 23 RS R 16 FBB 22 MSB R 17 OFSB 21 LDAC WR 18 20 A1 A0 19 NC = NO CONNECT Figure 5. AD5557 Pin Configuration Table 4. AD5557 Pin Function Descriptions Pin No. Mnemonic Function 1, 2 NC No Connection. Do not connect anything other than the dummy pads to these pins. 3 R Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, R ties to R . In 4-quadrant mode, R OFSA OFSA FBA OFSA ties to R and the external reference. 1A 4 R Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. FBA 5 R1A 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do not connect when operating in unipolar mode. 6 R Center Tap Point of the Two 4-Quadrant Resistors, R and R . In 4-quadrant mode, R ties to the inverting COMA 1A 2A COMA node of the reference amplifier. In 2-quadrant mode, R shorts to the V pin. Do not connect if operating COMA REFA in unipolar mode. 7 VREFA DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external reference amplifier. 8 I DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage OUTA output. 9 AGNDA DAC A Analog Ground. 10 DGND Digital Ground. 11 AGNDB DAC B Analog Ground. 12 IOUTB DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. 13 V DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured REFB with an external op amp for 4-quadrant multiplying, V becomes –V . REFB REF 14 RCOMB Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREFB pin. Do not connect if operating in unipolar mode. 15 R 4-Quandrant Resistor. In 2-quadrant mode, R shorts to the V pin. In 4-quadrant mode, R ties to R . Do 1B 1B REFB 1B OFSB not connect if operating in unipolar mode. 16 R Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. FBB 17 ROFSB Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB ties to R1B and an external reference. 18 WR Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge. Signal level must be ≤V + 0.3 V. DD 19 A0 Address Pin 0. Signal level must be ≤V + 0.3 V. DD 20 A1 Address Pin 1. Signal level must be ≤VDD + 0.3 V. 21 LDAC Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. 22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤V + 0.3 V. DD Rev. C | Page 8 of 20 04452-004 Data Sheet AD5547/AD5557 Pin No. Mnemonic Function 23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. 24 to 28, D13 to D0 Digital Input Data Bits D13 to D0. Signal level must be ≤VDD + 0.3 V. 30 to 38 29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Table 5. Address Decoder Pins A1 A0 Output Update 0 0 DAC A 0 1 None 1 0 DAC A and DAC B 1 1 DAC B Table 6. Control Inputs RS WR LDAC Register Operation 0 X X Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1. 1 0 0 Load the input register with data bits. 1 1 1 Load the DAC register with the contents of the input register. 1 0 1 The input and DAC registers are transparent. 1 When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse. 1 1 0 No register operation. Rev. C | Page 9 of 20 AD5547/AD5557 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) CODE (Decimal) Figure 6. AD5547 Integral Nonlinearity Error Figure 9. AD5557 Differential Nonlinearity Error 1.5 1.0 V = 2.5V REF 0.8 T = 25°C A 1.0 0.6 0.4 0.5 0.2 INL 0 0 DNL –0.2 –0.5 –0.4 –0.6 –1.0 GE –0.8 –1.5 –1.0 24 68 10 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 SUPPLY VOLTAGE V (V) DD CODE (Decimal) Figure 10. Linearity Error vs. Supply Voltage, V Figure 7. AD5547 Differential Nonlinearity Error DD 1.0 5 V = 5V DD 0.8 T = 25°C A 0.6 4 0.4 0.2 3 0 –0.2 2 –0.4 –0.6 1 –0.8 –1.0 0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CODE (Decimal) LOGIC INPUT VOLTAGE V (V) IH Figure 8. AD5557 Integral Nonlinearity Error Figure 11. Supply Current vs. Logic Input Voltage Rev. C | Page 10 of 20 DNL (LSB) INL (LSB) INL (LSB) 04452-021 04452-020 04452-019 DNL (LSB) SUPPLY CURRENT I (LSB) LINEARITY ERROR (LSB) DD 04452-023 04452-022 04452-010 Data Sheet AD5547/AD5557 3.0 2.5 LDAC 1 2.0 0x5555 1.5 2 0x8000 1.0 0xFFFF V 0x0000 OUT 0.5 CH1 5.00V CH2 2.00V M 200ns A CH1 2.70V B CH1 –6.20V 400.00ns 0 10k 100k 1M 10M 100M CLOCK FREQUENCY (Hz) Figure 12. AD5547 Supply Current vs. Clock Frequency Figure 15. Settling Time from Full Scale to Zero Scale 90 –3.85 V = 5V ± 10% DD 80 –3.90 V = 10V REF 70 –3.95 60 –4.00 50 40 –4.05 30 –4.10 20 –4.15 10 0 –4.20 10 100 1k 10k 100k 1M –20 –10 0 10 20 30 40 FREQUENCY (Hz) TIME (ns) Figure 13. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 16. AD5547 Midscale Transition and Digital Feedthrough 20 2 0 0 –2 –20 –4 –40 –6 –60 –8 –80 –10 –100 –12 –120 –14 –140 –16 –160 –18 0 5 10 15 20 25 10k 100k 1M 10M 100M FREQUENCY (kHz) FREQUENCY (Hz) Figure 14. AD5547/AD5557 Analog Total Harmonic Distortion (THD) Figure 17. AD5547 Unipolar Reference Multiplying Bandwidth Rev. C | Page 11 of 20 POWER SPECTRUM (dB) PSRR (–dB) SUPPLY CURRENT (mA) 04452-014 04452-024 04452-114 GSIN (dB) V (V) OUT 04452-025 04452-017 04452-0016 AD5547/AD5557 Data Sheet CIRCUIT OPERATION The reference voltage inputs exhibit a constant input resistance DAC SECTION of 5 kΩ ± 20%. The impedance of IOUT, the DAC output, is code The AD5547/AD5557 are 16-/14-bit, multiplying, current- dependent. External amplifier choice should take into account output, parallel input DACs. The devices operate from a single the variation of the AD5547/AD5557 output impedance. The 2.7 V to 5.5 V supply and provide both unipolar (0 V to –V REF feedback resistance in parallel with the DAC ladder resistance or 0 V to +VREF) and bipolar (±VREF) output ranges from –18 V dominates output voltage noise. To maintain good analog to +18 V references. In addition to the precision conversion RFB performance, it is recommended that the power supply is commonly found in current output DACs, there are three addi- bypassed with a 0.01 μF to 0.1 μF ceramic or chip capacitor in tional precision resistors for 4-quadrant bipolar applications. parallel with a 1 μF tantalum capacitor. Also, to minimize gain The AD5547/AD5557 consist of two groups of precision R-2R error, PCB metal traces between VREF and RFB should match. ladders, which make up the 12/10 LSBs, respectively. Furthermore, Every code change of the DAC corresponds to a step function; the 4 MSBs are decoded into 15 segments of resistor value 2R. gain peaking at each output step may occur if the op amp has Figure 18 shows the architecture of the 16-bit AD5547. Each of limited GBP and excessive parasitic capacitance present at the the 16 segments and the R-2R ladder carries an equally weighted inverting node of the op amp. A compensation capacitor, therefore, current of one-sixteenth of full scale. The feedback resistor RFB may be needed between the I-to-V op amp inverting and output and 4-quadrant resistor ROFS have values of 10 kΩ. Each 4-quadrant nodes to smooth the step transition. Such a compensation capacitor resistor, R1 and R2, equals 5 kΩ. In 4-quadrant operation, R1, should be found empirically, but a 20 pF capacitor is generally R2, and an external op amp work together to invert the reference adequate for the compensation. voltage and apply it to the V input. With R and R REF OFS FB The VDD power is used primarily by the internal logic to drive connected as shown in Figure 2, the output can swing from the DAC switches. Note that the output precision degrades if −V to +V . REF REF the operating voltage falls below the specified voltage. Users should also avoid using switching regulators because device power supply rejection degrades at higher frequencies. V REF 2R 2R 2R 2R R2 80kΩ 80kΩ 80kΩ 80kΩ 5kΩ RCOM R1 4 MSB 5kΩ 15 SEGMENTS R1 R R R R R R R R 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 2R 2R 2R 2R 2R 2R 2R 2R 2R 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 8-BIT R2R ROFS RA R R R R RFB 2R 2R 2R 2R 2R RB 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 10kΩ 10kΩ 4-BIT R2R IOUT AGND 15 8 4 ADDRESS DECODER LDAC LDAC DAC REGISTER RS RS WR INPUT REGISTER RS WR D15 D14 D0 Figure 18. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown Rev. C | Page 12 of 20 04452-011 Data Sheet AD5547/AD5557 The voltage reference temperature coefficient (TC) and long- DIGITAL SECTION term drift are primary considerations. For example, a 5 V The AD5547/AD5557 have 16-/14-bit parallel inputs. The devices reference with a TC of 5 ppm/°C means the output changes by are double buffered with 16-/14-bit registers. The double buffered 25 μV/°C. As a result, a reference operating at 55°C contributes feature allows the simultaneous update of several AD5547s/ an additional 750 μV full-scale error. AD5557s. For the AD5547, the input register is loaded directly WR Similarly, the same 5 V reference with a ±50 ppm long-term from a 16-bit controller bus when is brought low. The DAC drift means the output may change by ±250 μV over time. register is updated with data from the input register when LDAC Therefore, it is practical to calibrate a system periodically to is brought high. Updating the DAC register updates the DAC maintain its optimum precision. output with the new data (see Figure 18). To make both registers transparent, tie WR low and LDAC high. The asynchronous RS PCB LAYOUT, POWER SUPPLY BYPASSING, AND pin resets the part to zero scale if MSB = 0 and to midscale if GROUND CONNECTIONS MSB = 1. It is a good practice to employ a compact, minimum lead length, ESD Protection Circuits PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance. All logic input pins contain back-biased ESD protection Zeners connected to ground (DGND) and VDD, as shown in Figure 19. The PCB metal traces between VREF and RFB should also be As a result, the voltage level of the logic input should not be matched to minimize gain error. greater than the supply voltage. It is also essential to bypass the power supply with quality V DD capacitors for optimum stability. Supply leads to the device DIGITAL should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic INPUTS 5kΩ capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supply in parallel with the ceramic capacitor to minimize transient disturbance and filter out low frequency ripple. DGND To minimize the digital ground bounce, the AD5547/AD5557 Figure 19. Equivalent ESD Protection Circuits DGND terminal should be joined with the AGND terminal at a Amplifier Selection single point. Figure 20 illustrates the basic supply bypassing In addition to offset voltage, the bias current is important in op configuration and AGND/DGND connection for the AD5547/AD5557. amp selection for precision current output DACs. A 30 nA input bias current in the op amp contributes to 1 LSB in the V full-scale error of the AD5547. The OP1177 and AD8628 op DD + C2 C1 amps are good candidates for the I-to-V conversion. 5V AD5547/AD5557 1µF 0.1µF – AGND Reference Selection The initial accuracy and rated output of the voltage reference determine the full-span adjustment. The initial accuracy of the DGND reference is usually a secondary concern because it can be trimmed. Figure 25 shows an example of a trimming circuit. Figure 20. Power Supply Bypassing The zero-scale error can also be minimized by standard op amp nulling techniques. Rev. C | Page 13 of 20 04452-026 04452-015 AD5547/AD5557 Data Sheet APPLICATIONS INFORMATION In this case, the output voltage polarity is opposite the VREF UNIPOLAR MODE polarity (see Figure 21). Table 7 shows the negative output vs. 2-Quadrant Multiplying Mode, V = 0 V to –V OUT REF code for the AD5547. The AD5547/AD5557 DAC architecture uses a current-steering R-2R ladder design that requires an external reference and op Table 7. AD5547 Unipolar Mode Negative Output vs. Code amp to convert the unipolar mode of the output voltage to D in Binary VOUT (V) 1111 1111 1111 1111 –VREF (65,535/65,536) VOUT = −VREF × D/65,536 (AD5547) (1) 1000 0000 0000 0000 –VREF/2 V = −V × D/16,384 (AD5557) (2) OUT REF 0000 0000 0000 0001 –VREF (1/65,536) where D is the decimal equivalent of the input code. 0000 0000 0000 0000 0 +5V 2 U3 ADR03 C1 C2 1µF 0.1µF V IN 5 TRIM 6 +2.5V V OUT GND V REFA 4 R R R R 1A COMA OFSA FBA 6.8pF C6 VDD ROFS RFB R1 R2 C3 2.5V I OUTA 0.1µF +V V AD5547/AD5557 OUTA 16-/14-BIT AD8628 AGNDA U1 –V –2.5V TO 0V 16/14 DATA C4 WR LDAC RS MSB A0, A1 0.1µF C5 WR LDAC 2 1µF RS MSB –5V A0, A1 Figure 21. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to –VREF Rev. C | Page 14 of 20 04452-007 Data Sheet AD5547/AD5557 2-Quadrant Multiplying Mode, V = 0 V to +V Table 8 shows the positive output vs. code for the AD5547. OUT REF The AD5547/AD5557 are designed to operate with either Table 8. AD5547 Unipolar Mode Positive Output vs. Code positive or negative reference voltages. As a result, a positive D in Binary V (V) OUT output can be achieved with an additional op amp, (see 1111 1111 1111 1111 +VREF(65,535/65,536) Figure 22); the output becomes 1000 0000 0000 0000 +V /2 REF V = +V × D/65,536 (AD5547) (3) OUT REF 0000 0000 0000 0001 +V (1/65,536) REF 0000 0000 0000 0000 0 V = +V × D/16,384 (AD5557) (4) OUT REF +5V 2 U3 C1 C2 U2A 1µF 1µF V IN 5 TRIM 6 V OUT AD8628 GND C7 –2.5V 4 ADR03 +2.5V +5V C4 1µF R R V R R 1A COMA REFA OFSA FBA C6 C5 0.1µF U2B VDD ROFS RFB R1 R2 C3 I 0.1µF OUTA +V 16-/14-BIT V AD8628 OUTA AGNDA AD5547/AD5557 –V 16/14 DATA 0V TO +2.5V WR LDAC RS MSB A0, A1 WR LDAC 2 RS MSB A0, A1 Figure 22. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to +VREF Rev. C | Page 15 of 20 04452-005 AD5547/AD5557 Data Sheet BIPOLAR MODE 4-Quadrant Multiplying Mode, V = –V to +V Table 9 shows some of the results for the 16-bit AD5547. OUT REF REF The AD5547/AD5557 contain on-chip all the 4-quadrant Table 9. AD5547 Output vs. Code resistors necessary for precision bipolar multiplying operation. D in Binary VOUT Such a feature minimizes the number of exponent components 1111 1111 1111 1111 +V (32,767/32,768) REF to only a voltage reference, dual op amp, and compensation 1000 0000 0000 0001 +VREF (1/32,768) capacitor (see Figure 23). For example, with a +10 V reference, 1000 0000 0000 0000 0 the circuit yields a precision, bipolar –10 V to +10 V output. 0111 1111 1111 1111 –VREF (1/32,768) VOUT = (D/32768 − 1) × VREF (AD5547) (5) 0000 0000 0000 0000 –V REF V = (D/16384 − 1) × V (AD5557) (6) OUT REF +15V 2 U3 C1 C2 1µF 0.1µF V IN 5 TRIM 6 V OUT GND U2A 4 ADR01 AD8512 C8 –10V +10V R R V R R 1A COMA REFA OFSA FBA +5V VDD C4 1µF ROFS RFB +15V R1 R2 C9 C5 0.1µF U2B C3 0.1µF I OUTA AD5547/AD5557 16-/14-BIT +V VOUT DAC A AD8512 –V U1 AGNDA 16/14 DATA C6 0.1µF –10V TO +10V C7 1µF WR LDAC RS MSB A0, A1 WR LDAC 2 –15V RS MSB A0, A1 Figure 23. 4-Quadrant Multiplying Mode, V = –V to +V OUT REF REF Rev. C | Page 16 of 20 04452-006 Data Sheet AD5547/AD5557 AC Reference Signal Attenuator System Calibration Besides handling the digital waveform decoded from the The initial accuracy of the system can be adjusted by trimming parallel input data, the AD5547/AD5557 can also handle low the voltage reference ADR0x with a digital potentiometer (see frequency ac reference signals for signal attenuation, channel Figure 25). The AD5170 provides a one-time programmable equalization, and waveform generation applications. The (OTP), 8-bit adjustment that is ideal and reliable for such maximum signal range can be up to ±18 V (see Figure 24). calibration. Analog Devices, Inc., OTP digital potentiometer comes with programmable software that simplifies factory calibration. U2A OP2177 C7 +10V –10V +15V C4 1µF R R V R R 1A COMA REFA OFSA FBA C6 +5V C5 0.1µF VDD R1 U2B R2 ROFS RFB C1 C2 I 1µF 0.1µF OUTA 16-/14-BIT V +V OUTA AD5547/AD5557 OP2177 AGNDA –V U1 16/14 DATA C8 1µF WR LDAC RS MSB A0, A1 WR C9 0.1µF LDAC 2 RS MSB –15V A0, A1 Figure 24. Signal Attenuator with AC Reference +5V 2 AD5170 U3 C1 C2 U4 1µF 0.1µF V IN R3 5 TRIM 10kΩ 470kΩ B V U2 OUT 6 R7 1kΩ GND AD8628 4 ADR03 –2.5V C7 +2.5V +5V C4 1µF R 1A R V R R COMA REFA OFSA FBA C6 C5 0.1µF U2B VDD R1 R2 ROFS RFB C3 I 0.1µF OUTA V 16-/14-BIT +V OUTA AD5547/AD5557 AD8628 AGNDA –V U1 0V TO +2.5V 16/14 DATA WR LDAC RS MSB A0, A1 WR LDAC 2 REF 01/AD RS MSB A0, A1 Figure 25. Full-Span Calibration Rev. C | Page 17 of 20 04452-008 04452-009 AD5547/AD5557 Data Sheet The input bias current of an op amp also generates an offset at REFERENCE SELECTION the voltage output because of the bias current flowing in the When selecting a reference for use with the AD55xx series of feedback resistor, R . FB current output DACs, pay attention to the output voltage, temperature coefficient specification of the reference. Choosing Common-mode rejection of the op amp is important in voltage- a precision reference with a low output temperature coefficient switching circuits because it produces a code-dependent error minimizes error sources. Table 10 lists some of the references at the voltage output of the circuit. available from Analog Devices, Inc., that are suitable for use Provided that the DAC switches are driven from true wideband with this range of current output DACs. low impedance sources (V and AGND), they settle quickly. IN Consequently, the slew rate and settling time of a voltage-switching AMPLIFIER SELECTION DAC circuit is determined largely by the output op amp. To obtain The primary requirement for the current-steering mode is an minimum settling time in this configuration, minimize capacitance amplifier with low input bias currents and low input offset voltage. at the VREF node (the voltage output node in this application) of Because of the code-dependent output resistance of the DAC, the DAC. This is done by using low input capacitance buffer the input offset voltage of an op amp is multiplied by the variable amplifiers and careful board design. gain of the circuit. A change in this noise gain between two Analog Devices offers a wide range of amplifiers for both precision adjacent digital fractions produces a step change in the output dc and ac applications, as listed in Table 11 and Table 12. voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Table 10. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package(s) ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Table 11. Suitable Analog Devices Precision Op Amps VOS Maximum IB Maximum 0.1 Hz to 10 Hz Part No. Supply Voltage (V) (μV) (nA) Noise (μV p-p) Supply Current (μA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Rev. C | Page 18 of 20 Data Sheet AD5547/AD5557 Table 12. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) V (Max) (μV) I (Max) (nA) Package(s) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Table 13 lists the latest DACS available from Analog Devices. Table 13. ADI Current Output DACs Model Bits Outputs Interface Package Comments AD5425 8 1 SPI, 8-Bit Load MSOP-10 Fast 8-bit load; see also AD5426 AD5426 8 1 SPI MSOP-10 See also AD5425 fast load AD5450 8 1 SPI TSOT-8 See also AD5425 fast load AD5424 8 1 Parallel TSSOP-16 AD5429 8 2 SPI TSSOP-16 AD5428 8 2 Parallel TSSOP-20 AD5432 10 1 SPI MSOP-10 AD5451 10 1 SPI TSOT-8 AD5433 10 1 Parallel TSSOP-20 AD5439 10 2 SPI TSSOP-16 AD5440 10 2 Parallel TSSOP-24 AD5443 12 1 SPI MSOP-10 See also AD5452 and AD5444 AD5452 12 1 SPI TSOT-8 Higher accuracy version of AD5443; see also AD5444 AD5445 12 1 Parallel TSSOP-20 AD5444 12 1 SPI MSOP-10 Higher accuracy version of AD5443; see also AD5452 AD5449 12 2 SPI TSSOP-16 AD5415 12 2 SPI TSSOP-24 Uncommitted resistors AD5447 12 2 Parallel TSSOP-24 AD5405 12 2 Parallel LFCSP-40 Uncommitted resistors AD5453 14 1 SPI TSOT-8 AD5553 14 1 SPI MSOP-8 AD5556 14 1 Parallel TSSOP-28 AD5446 14 1 SPI MSOP-10 MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426 AD5555 14 2 SPI TSSOP-16 AD5557 14 2 Parallel TSSOP-38 AD5543 16 1 SPI MSOP-8 AD5546 16 1 Parallel TSSOP-28 AD5545 16 2 SPI TSSOP-16 AD5547 16 2 Parallel TSSOP-38 Rev. C | Page 19 of 20 AD5547/AD5557 Data Sheet OUTLINE DIMENSIONS 9.80 9.70 9.60 38 20 4.50 4.40 4.30 6.40 BSC 1 19 PIN 1 1.20 MAX 0.15 0.05 8° 0.50 0.27 0° 0.70 SEATING 0.20 COPLANARITY BSC 0.17 0.60 PLANE 0.10 0.09 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-BD-1 Figure 26. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimension s shown in millimeters ORDERING GUIDE DNL INL Package Ordering 1 Model Resolution (Bits) (LSB) (LSB) Temperature Range Package Description Option Quantity AD5547BRU 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 50 AD5547BRU-REEL7 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 1,000 AD5547BRUZ 16 ±1 ±2 −40°C to +125°C 38-Lead TSSOP RU-38 50 AD5547CRUZ 16 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50 AD5547CRUZ-REEL7 16 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 1,000 AD5557CRU 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50 AD5557CRU-REEL7 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 1,000 AD5557CRUZ 14 ±1 ±1 −40°C to +125°C 38-Lead TSSOP RU-38 50 1 Z = RoHS Compliant Part. ©2004–2011 Analog Devices, Inc. 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