ANALOG DEVICES AD5546

Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with Four-Quadrant Resistors Data Sheet AD5546/AD5556 FEATURES FUNCTIONAL BLOCK DIAGRAM R1 R REF R COM OFS 16-bit resolution 14-bit resolution R R R1 R2 OFS FB R FB 2- or 4-quadrant multiplying DAC ±1 LSB DNL DAC I AD5546/ OUT V DD AD5556 ±1 LSB INL 16/14 Operating supply voltage: 2.7 V to 5.5 V WR CONTROL Low noise: 12 nV/√Hz LOGIC DAC LDAC REGISTER GND Low power: I = 10 μA DD DB0 TO DB15 0.5 μs settling time POR Built-in R facilitates current-to-voltage conversion FB Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V, MSB RS or ±10 V outputs Figure 1. AD5546/AD5556 Simplified Block Diagram 2 mA full-scale current ±20%, with V = 10 V REF Automotive operating temperature: –40°C to +125°C GENERAL DESCRIPTION Compact TSSOP-28 package The AD5546/AD5556 are precision 16-/14-bit, multiplying, low power, current output, parallel input digital-to-analog converters APPLICATIONS (DACs). They operate from a single 2.7 V to 5.5 V supply with Automatic test equipment ±10 V multiplying references for four-quadrant outputs. Built- Instrumentation in four-quadrant resistors facilitate the resistance matching and Digitally controlled calibration temperature tracking that minimize the number of components Digital waveform generation needed for multiquadrant applications. The feedback resistor (R ) simplifies the I-V conversion with an external buffer. The FB AD5546/AD5556 are packaged in compact TSSOP-28 packages with operating temperatures from –40°C to +125°C. The EVAL-AD5546SDZ is available for evaluating DAC perfor- mance. For more information, see the UG-309 evaluation board user guide. + U2A OP2177 – +10V C7 –10V R1A R VREFA R R COMA OFSA FBA +15V C4 C6 1µF R1 R2 R R OFS FB +5V V DD C5 C1 C2 I OUT 0.1µF 16-/14-BIT 1µF 0.1µF – V+ U1 DATA U2B AD5546/AD5556 VOUT OP2177 GND V– + 16-/14-BIT C8 DATA 1µF WR LDAC RS MSB WR C9 LDAC 0.1µF RS –15V MSB Figure 2. 16-/14-Bit, Four-Quadrant Multiplying DAC with a Minimum of External Components Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03810-024 03810-001 AD5546/AD5556 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Section ............................................................................ 11 Applications ....................................................................................... 1 ESD Protection Circuits ............................................................ 11 Functional Block Diagram .............................................................. 1 Amplifier Selection .................................................................... 11 General Description ......................................................................... 1 Reference Selection .................................................................... 11 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications ..................................................................................... 3 Unipolar Mode ........................................................................... 12 Electrical Characteristics ............................................................. 3 Bipolar Mode .............................................................................. 13 Timing Diagram ........................................................................... 4 AC Reference Signal Attenuator ............................................... 14 Absolute Maximum Ratings ............................................................ 5 System Calibration ..................................................................... 14 ESD Caution .................................................................................. 5 Reference Selection .................................................................... 15 Pin Configurations and Function Descriptions ........................... 6 Amplifier Selection .................................................................... 15 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 17 Circuit Operation ........................................................................... 10 Ordering Guide .......................................................................... 17 Digital-to-Analog (DAC) Converter Section ......................... 10 REVISION HISTORY 11/11—Rev. C to Rev. D Changes to General Description Section ...................................... 1 Changes to Ordering Guide .......................................................... 18 1/11—Rev. B to Rev. C Changes to Figure 2 .......................................................................... 1 Changes to Figure 21 ...................................................................... 13 4/10—Rev. A to Rev. B Changes to Table 1 ............................................................................ 4 Moved Timing Diagram Section and Figure 5 to Specifications Section....................................................................... 4 Moved Table 5 Through Table 7 to Digital Section Section ....... 7 Replaced Figure 15 and Figure 16 .................................................. 9 Deleted Figure 17 and Figure 18 ..................................................... 9 Added Reference Selection Section, Amplifier Selection Section, and Table 11 Through Table 13 .................................................... 15 9/09—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Static Performance, Relative Accuracy, Grade: AD5546C Parameter, Table 1 ............................................. 3 Changes to Ordering Guide .......................................................... 16 1/04—Revision 0: Initial Version Rev. D | Page 2 of 20 Data Sheet AD5546/AD5556 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, I = virtual GND, GND = 0 V, V = –10 V to 10 V, T = full operating temperature range, unless otherwise noted. DD OUT REF A Table 1. Parameter Symbol Conditions Min Typ Max Unit 1 STATIC PERFORMANCE 16 Resolution N AD5546, 1 LSB = V /2 = 153 µV at 16 Bits REF V = 10 V REF 14 AD5556, 1 LSB = V /2 = 610 µV at 14 Bits REF VREF = 10 V Relative Accuracy INL Grade: AD5556C ±1 LSB Grade: AD5546B ±2 LSB Grade: AD5546C ±1 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current I Data = zero scale, T = 25°C 10 nA OUT A Data = zero scale, TA = TA maximum 20 nA Full-Scale Gain Error GFSE Data = full scale ±1 ±4 mV Bipolar Mode Gain Error G Data = full scale ±1 ±4 mV E Bipolar Mode Zero-Scale G Data = full scale ±1 ±2.5 mV ZSE Error 2 Full-Scale Tempco TCVFS 1 ppm/°C REFERENCE INPUT V Range V –18 +18 V REF REF REF Input Resistance REF 4 5 6 kΩ R1 and R2 Resistance R1 and R2 4 5 6 kΩ R1-to-R2 Mismatch ∆(R1 to R2) ±0.5 ±1.5 Ω Feedback and Offset R , R 8 10 12 kΩ FB OFS Resistance 2 Input Capacitance CREF 5 pF ANALOG OUTPUT Output Current I Data = full scale 2 mA OUT 2 Output Capacitance COUT Code dependent 200 pF LOGIC INPUT AND OUTPUT Logic Input Low Voltage V V = 5 V 0.8 V IL DD VDD = 3 V 0.4 V Logic Input High Voltage VIH VDD = 5 V 2.4 V VDD = 3 V 2.1 V Input Leakage Current I 10 µA IL 2 Input Capacitance C 10 pF IL 2, 3 INTERFACE TIMING Data to WR Setup Time t V = 5 V 20 ns DS DD V = 3 V 35 ns DD Data to WR Hold Time tDH VDD = 5 V 0 ns VDD = 3 V 0 ns WR Pulse Width t VDD = 5 V 20 ns WR VDD = 3 V 35 ns LDAC Pulse Width tLDAC VDD = 5 V 20 ns VDD = 3 V 35 ns Rev. D | Page 3 of 20 AD5546/AD5556 Data Sheet Parameter Symbol Conditions Min Typ Max Unit RS Pulse Width tRS VDD = 5 V 20 ns VDD = 3 V 35 ns WR to LDAC Delay Time tLWD VDD = 5 V 0 ns V = 3 V 0 ns DD SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE 2.7 5.5 V Positive Supply Current I Logic inputs = 0 V 10 μA DD Power Dissipation P Logic inputs = 0 V 0.055 mW DISS Power Supply Sensitivity P ∆V = ±5% 0.003 %/% SS DD 4 AC CHARACTERISTICS Output Voltage Settling t To ±0.1% of full scale, data cycles from zero 0.5 μs S Time scale to full scale to zero scale 5 Reference Multiplying BW BW VREF = 100 mV rms, data = full scale, C6 =5.6 pF 6.8 MHz DAC Glitch Impulse Q VREF = 0 V, midscale minus 1 to midscale −3 nV-s Multiplying Feedthrough V /V V = 100 mV rms, f = 10 kHz 79 dB OUT REF REF Error Digital Feedthrough Q 7 nV-s D WR = 1, LDAC toggles at 1 MHz Total Harmonic Distortion THD VREF = 5 V p-p, data = full-scale, f = 1 kHz –103 dB Output Noise Density eN f = 1 kHz, BW = 1 Hz 12 nV/rt Hz 1 All static performance tests (except IOUT) are performed in a closed-loop system, using an external precision OP97 I-V converter amplifier. The AD554x RFB terminal is tied to the amplifier output. The op amp +IN is grounded, and the DAC I is tied to the op amp –IN. Typical values represent average readings measured at 25°C. OUT 2 These parameters are guaranteed by design and are not subject to production testing. 3 All input control signals are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-V converter amplifier except for THD where an AD8065 was used. 5 C6 is the C6 capacitor shown in Figure 20. TIMING DIAGRAM t WR WR DATA t DH t DS t LWD LDAC t LDAC t RS RS Figure 3. AD5546/AD5556 Timing Diagram Rev. D | Page 4 of 20 03810-005 Data Sheet AD5546/AD5556 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any V to GND –0.3 V, +8 V DD other conditions above those listed in the operational sections R , R , R1, R , and REF to GND –18 V, 18 V FB OFS COM of this specification is not implied. Exposure to absolute Logic Inputs to GND –0.3 V, +8 V maximum rating conditions for extended periods may affect V (IOUT) to GND –0.3 V, VDD + 0.3 V device reliability. Input Current to Any Pin Except Supplies ±50 mA Thermal Resistance (θ ) 128°C JA ESD CAUTION Maximum Junction Temperature (T ) 150°C J MAX Operating Temperature Range –40°C to +125°C Storage Temperature Range –65°C to +150°C Lead Temperature: Vapor Phase, 60 s 215°C Infrared, 15 s 220°C Package Power Dissipation (T – T )/θ J MAX A JA Rev. D | Page 5 of 20 AD5546/AD5556 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D7 1 28 V D5 1 28 V DD DD D6 2 27 D8 D4 2 27 D6 D5 3 26 D9 D3 3 26 D7 D4 4 25 D10 D2 4 25 D8 D3 5 24 D11 D1 5 24 D9 D2 6 23 D12 D0 6 23 D10 AD5546 AD5556 D1 7 22 D13 NC 7 22 D11 TOP VIEW TOP VIEW (Not to Scale) (Not to Scale) D0 8 21 D14 NC 8 21 D12 R 9 20 D15 R 9 20 D13 OFS OFS R 10 19 GND R 10 19 GND FB FB R1 11 18 RS R1 11 18 RS R 12 17 MSB R 12 17 MSB COM COM REF 13 16 WR REF 13 16 WR I 14 15 LDAC I 14 15 LDAC OUT OUT NC = NO CONNECT Figure 4. AD5546 Pin Configuration Figure 5. AD5556 Pin Configuration Table 3. AD5546 Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 D7 to D0 Digital Input Data Bits[D7: D0]. The signal level must be ≤ V + 0.3 V. DD 9 R Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to R . In four-quadrant mode, ties to R1 OFS FB and the external reference. 10 RFB Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion. 11 R1 Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to ROFS. 12 R Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of COM the reference amplifier. In two-quadrant mode, shorts to the REF pin. 13 REF DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the external reference amplifier. 14 I DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion. OUT 15 LDAC Digital Input Load DAC Control. Signal level must be ≤ V + 0.3 V. DD 16 Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The WR signal level must be ≤ VDD + 0.3 V. 17 MSB Power-On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be ≤ VDD + 0.3 V. 18 RS Reset in Active Low. Resets to zero scale if MSB = 0, and resets to midscale if MSB = 1. The signal level must be ≤ V + 0.3 V. DD 19 GND Analog and Digital Grounds. 20 to 21 D15 to D14 Digital Input Data Bits[D15:D14]. The signal level must be ≤ VDD + 0.3 V. 22 to 27 D13 to D8 Digital Input Data Bits[D13:D8]. The signal level must be ≤ VDD + 0.3 V. 28 VDD Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V. Table 4. AD5556 Pin Function Descriptions Pin No. Mnemonic Description 1 to 6 D5 to D0 Digital Input Data Bits[D5:D0]. The signal level must be ≤ VDD+0.3 V. 7 to 8 NC No Connection. The user should not connect anything other than dummy pads on these terminals. 9 R Bipolar Offset Resistor. Accepts up to ±18 V. In two-quadrant mode, ties to RFB. In four-quadrant mode, ties to R1 OFS and the external reference. 10 R Internal Matching Feedback Resistor. Connects to the output of an external op amp for I-V conversion. FB 11 R1 Four-Quadrant Resistor R1. In two-quadrant mode, shorts to the REF pin. In four-quadrant mode, ties to R . OFS 12 RCOM Center Tap Point of Two Four-Quadrant Resistors, R1 and R2. In four-quadrant mode, ties to the inverting node of the reference amplifier. In two-quadrant mode, shorts to the REF pin. Rev. D | Page 6 of 20 03810-003 03810-004 Data Sheet AD5546/AD5556 Pin No. Mnemonic Description 13 REF DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the external reference amplifier. 14 I DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion. OUT 15 LDAC Digital Input Load DAC Control. The signal level must be ≤ V + 0.3 V. DD 16 WR Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The signal level must be ≤ VDD + 0.3 V. 17 MSB Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be ≤ V + 0.3 V. DD 18 RS Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be ≤ V + 0.3 V. DD 19 GND Analog and Digital Grounds. 20 to 27 D13 to D6 Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V. 28 VDD Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V. Rev. D | Page 7 of 20 AD5546/AD5556 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0 0248 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) CODE (Decimal) Figure 9. AD5556 Differential Nonlinearity Error Figure 6. AD5546 Integral Nonlinearity Error 1.0 1.5 V = 2.5V REF T = 25°C 0.8 A 1.0 0.6 0.4 0.5 0.2 INL 0 0 DNL –0.2 –0.5 –0.4 –0.6 –1.0 GE –0.8 –1.5 –1.0 24 68 10 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 SUPPLY VOLTAGE V (V) CODE (Decimal) DD Figure 7. AD5546 Differential Nonlinearity Error Figure 10. Linearity Error vs. VDD 1.0 5 V = 5V DD 0.8 T = 25°C A 0.6 4 0.4 0.2 3 0 –0.2 2 –0.4 –0.6 1 –0.8 –1.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) LOGIC INPUT VOLTAGE V (V) IH Figure 11. Supply Current vs. Logic Input Voltage Figure 8. AD5556 Integral Nonlinearity Error Rev. D | Page 8 of 20 INL (LSB) DNL (LSB) INL (LSB) 03810-008 03810-007 03810-006 SUPPLY CURRENT I (LSB) LINEARITY ERROR (LSB) DNL (LSB) DD 03810-011 03810-010 03810-009 Data Sheet AD5546/AD5556 3.0 –3.80 –3.85 2.5 –3.90 2.0 0x5555 –3.95 1.5 –4.00 0x8000 –4.05 1.0 0xFFFF –4.10 0x0000 0.5 –4.15 0 –4.20 10k 100k 1M 10M 100M –200 –100 0 100 200 300 400 CLOCK FREQUENCY (Hz) TIME (ns) Figure 12. AD5546 Supply Current vs. Clock Frequency Figure 15. AD5546 Midscale Transition 2 90 V = 5V ± 10% 0 DD 80 V = 10V REF –2 70 –4 60 –6 50 –8 40 –10 30 –12 20 –14 10 –16 –18 0 10 100 1k 10k 100k 1M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Power Supply Rejection Ratio vs. Frequency Figure 16. AD5546 Unipolar Reference Multiplying Bandwidth LDAC 1 2 V OUT CH1 5.00V CH2 2.00V M 200ns A CH1 2.70V B CH1 –6.20V 400.00ns Figure 14. Settling Time from Full Scale to Zero Scale Rev. D | Page 9 of 20 SUPPLY CURRENT (mA) PSRR (–dB) 03810-014 03810-013 03810-012 V (V) OUT GAIN (dB) 03810-116 03810-115 AD5546/AD5556 Data Sheet CIRCUIT OPERATION variation of the AD5546/AD5556 output impedance. The DIGITAL-TO-ANALOG (DAC) CONVERTER SECTION feedback resistance in parallel with the DAC ladder resistance The AD5546/AD5556 are 16-/14-bit multiplying, current out- dominates output voltage noise. To maintain good analog put, and parallel input DACs. The devices operate from a single performance, it is recommended to bypass the power supply 2.7 V to 5.5 V supply and provide both unipolar 0 V to –V , or REF with a 0.01 μF to 0.1 μF ceramic or chip capacitor in parallel 0 V to +VREF, and bipolar ±VREF output ranges from a –18 V to with a 1 μF tantalum capacitor. Also, to minimize gain error, +18 V reference. In addition to the precision conversion RFB PCB metal traces between V and R should match. REF FB commonly found in current output DACs, there are three addi- Every code change of the DAC corresponds to a step function; tional precision resistors for four-quadrant bipolar applications. gain peaking at each output step may occur if the op amp has The AD5546/AD5556 consist of two groups of precision R-2R limited GBP and excessive parasitic capacitance present at the ladders, which make up the 12/10 LSBs, respectively. Further- op amp inverting node. A compensation capacitor, therefore, more, the four MSBs are decoded into 15 segments of resistor may be needed between the I-V op amp inverting and output value 2R. Figure 17 shows the architecture of the 16-bit AD5546. nodes to smooth the step transition. Such a compensation Each of the 16 segments in the R-2R ladder carries an equally capacitor should be found empirically, but a 20 pF capacitor is weighted current of one-sixteenth of full scale. The feedback generally adequate for the compensation. resistor, RFB, and four-quadrant resistor, ROFS, have values of 10 The VDD power is used primarily by the internal logic and to kΩ. Each four-quadrant resistor, R1 and R2, equals 5 kΩ. In drive the DAC switches. Note that the output precision four-quadrant operation, R1, R2, and an external op amp work degrades if the operating voltage falls below the specified together to invert the reference voltage and apply it to the REF voltage. The user should also avoid using switching regulators input. With R and R connected as shown in Figure 2, the OFS FB because device power supply rejection degrades at higher output can swing from –V to +V . REF REF frequencies. The reference voltage inputs exhibit a constant input resistance of 5 kΩ ±20%. The DAC output, IOUT, impedance is code depen- dent. External amplifier choice should take into account the REF 2R 2R 2R 2R R2 80kΩ 80kΩ 80kΩ 80kΩ 5kΩ R COM R1 4 MSB 5kΩ 15 SEGMENTS R1 R R R R R R R R 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 2R 2R 2R 2R 2R 2R 2R 2R 2R 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 8-BIT R–2R R OFS RA R R R R R FB 2R 2R 2R 2R 2R RB 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 10kΩ 10kΩ 4-BIT R–2R I OUT GND 16 8 4 ADDRESS DECODER LDAC LDAC DAC REGISTER RS RS WR INPUT REGISTER RS WR D15 D14 D0 Figure 17. 16-Bit AD5546 Equivalent R-2R DAC Circuit with Digital Section Rev. D | Page 10 of 20 03810-019 Data Sheet AD5546/AD5556 DIGITAL SECTION The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit WR controller bus when the pin is brought low. The DAC register is updated with data from the input register when LDAC is brought WR high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie RS low and LDAC high. The asynchronous pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1. Table 5. AD5546 Parallel Input Data Format MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 6. AD5556 Parallel Input Data Format MSB LSB Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 7. Control Inputs RS WR LDAC Register Operation 1 1 0 X X Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1. 1 0 0 Load input register with data bits. 1 1 1 Load DAC register with the contents of the input register. 1 0 1 Input and DAC registers are transparent. 1 When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse. 1 1 0 No register operation. 1 X = don’t care. are good candidates for the I-V conversion. ESD PROTECTION CIRCUITS All logic input pins contain back-biased ESD protection Zeners REFERENCE SELECTION connected to ground (GND) and V , as shown in Figure 18. As DD The initial accuracy and the rated output of the voltage refer- a result, the voltage level of the logic input should not be greater ence determine the full span adjustment. The initial accuracy is than the supply voltage. usually a secondary concern in precision because it can be V DD trimmed. Figure 23 shows an example of a trimming circuit. The zero scale error can also be minimized by standard op amp DIGITAL INPUTS 5kΩ nulling techniques. The voltage reference temperature coefficient (TC) and long- term drift are primary considerations. For example, a 5 V ref- o erence with a TC of 5 ppm/ C means that the output changes by DGND 25 µV per degree Celsius. As a result, the reference that operates Figure 18. Equivalent ESD Protection Circuits o at 55 C contributes an additional 750 µV full-scale error. AMPLIFIER SELECTION Similarly, the same 5 V reference with a ±50 ppm long-term In addition to offset voltage, the bias current is important in op drift means that the output may change by ±250 µV over time. Therefore, it is practical to calibrate a system periodically to amp selection for precision current output DACs. An input bias maintain its optimum precision. current of 30 nA in the op amp contributes to 1 LSB in the AD5546’s full-scale error. The OP1177 and AD8628 op amps Rev. D | Page 11 of 20 03810-020 R1 AD5546/AD5556 Data Sheet APPLICATIONS INFORMATION Two-Quadrant Multiplying Mode, V = 0 V to +V UNIPOLAR MODE OUT REF Two-Quadrant Multiplying Mode, V = 0 V to –V The AD5546/AD5556 are designed to operate with either OUT REF positive or negative reference voltages. As a result, positive The AD5546/AD5556 DAC architecture uses a current-steering output can be achieved with an additional op amp, (see R-2R ladder design that requires an external reference and op Figure 20), and the output becomes amp to convert the unipolar mode of output voltage to AD5546 AD5546 VOUT = +VREF × D/65,536 (3) V = –V × D/65,536 (1) OUT REF AD5556 AD5556 VOUT = +VREF × D/16,384 (4) V = –V × D/16,384 (2) OUT REF Table 9 shows the positive output vs. code for the AD5546. where D is the decimal equivalent of the input code. The output voltage polarity is opposite to the VREF polarity in Table 9. AD5546 Unipolar Mode Positive Output vs. Code this case (see Figure 19). Table 8 shows the negative output vs. D in Binary V (V) OUT code for the AD5546. 1111 1111 1111 1111 +VREF(65,535/65,536) 1000 0000 0000 0000 +VREF/2 Table 8. AD5546 Unipolar Mode Negative Output vs. Code 0000 0000 0000 0001 +V (1/65,536) REF D in Binary VOUT (V) 0000 0000 0000 0000 0 1111 1111 1111 1111 –VREF(65,535/65,536) 1000 0000 0000 0000 –VREF/2 0000 0000 0000 0001 –V (1/65,536) REF 0000 0000 0000 0000 0 +5V 2 V IN C1 C2 U3 1µF 0.1µF ADR03 5 TRIM V OUT GND 4 R1 R REF R R COM OFS FB C6 2.2pF R2 R R OFS FB V DD C3 I OUT 16-/14-BIT 0.1µF – V+ U1 DATA U2 AD5546/AD5556 VOUT AD8628 –2.5V TO 0V GND V– + C4 16-/14-BIT 0.1µF DATA WR LDAC RS MSB C5 WR 1µF –5V LDAC RS MSB Figure 19. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to –VREF Rev. D | Page 12 of 20 03810-021 R1 Data Sheet AD5546/AD5556 + U2A OP2177 – +10V C7 –10V R1A R VREFA R R COMA OFSA FBA +15V C4 C6 1µF R1 R2 R R OFS FB +5V V DD C5 C1 C2 I 0.1µF OUT 16-/14-BIT 1µF 0.1µF – V+ U1 DATA U2B AD5546/AD5556 VOUT OP2177 GND V– + 16-/14-BIT C8 DATA 1µF WR LDAC RS MSB WR C9 LDAC 0.1µF RS –15V MSB Figure 20. Unipolar Two-Quadrant Multiplying Mode, VOUT = 0 to +VREF 5V 2 + V IN U2A U3 OP2177 ADR03 – 5 C1 TRIM –VREF +VREF 6 V OUT GND R1 R REF R R COM OFS FB 4 R2 R R OFS FB C2 5V V DD I OUT 16-/14-BIT – U1 DATA U2B AD5546/AD5556 VOUT OP2177 16-/14-BIT GND + DATA –VREF TO +VREF WR LDAC RS MSB WR LDAC RS MSB Figure 21. Four-Quadrant Multiplying Mode, V = –V to +V OUT REF REF 10 V reference, the circuit yields a precision, bipolar –10 V to BIPOLAR MODE +10 V output. Four-Quadrant Multiplying Mode, V = –V to +V OUT REF REF AD5546 The AD5546/AD5556 contain on-chip all the four-quadrant VOUT = (D/32768 − 1) × VREF (5) resistors necessary for the precision bipolar multiplying operation. Such a feature minimizes the number of exponent AD5556 components to only a voltage reference, dual op amp, and V = (D/16384 − 1) × V (6) OUT REF compensation capacitor (see Figure 21). For example, with a Table 10 shows some of the results for the 16-bit AD5546. Rev. D | Page 13 of 20 03810-002 03810-024 AD5546/AD5556 Data Sheet ac reference signals for signal attenuation, channel equalization, Table 10. AD5546 Output vs. Code and waveform generation applications. The maximum signal D in Binary V OUT range can be up to ±18 V (see Figure 22). 1111 1111 1111 1111 +VREF(32,767/32,768) 1000 0000 0000 0001 +VREF(1/32,768) SYSTEM CALIBRATION 1000 0000 0000 0000 0 The initial accuracy of the system can be adjusted by trimming 0111 1111 1111 1111 –V (1/32,768) REF the voltage reference ADR0x with a digital potentiometer (see 0000 0000 0000 0000 –V REF Figure 23). The AD5170 provides an OTP (one time program- AC REFERENCE SIGNAL ATTENUATOR mable), 8-bit adjustment that is ideal and reliable for such cali- bration. The Analog Devices, Inc., OTP digital potentiometer Besides handling digital waveforms decoded from parallel input comes with programmable software that simplifies the factory data, the AD5546/AD5556 handle equally well low frequency calibration process. + U2A OP2177 – +10V C7 –10V R1A RCOMA VREFA ROFSA RFBA +15V C4 C6 1F R1 R2 ROFS RFB +5V VDD C5 C1 C2 IOUT 0.1F 1F 0.1F – 16/14-BIT V+ U1 U2B AD5546/AD5556 VOUT OP2177 GND V– + 16/14 DATA C8 1F WR LDAC RS MSB WR C9 LDAC 0.1F RS –15V MSB Figure 22. Signal Attenuator with AC Reference +5V 2 + V+ V IN C1 C2 U4 U2A 1µF 0.1µF U3 AD5170 R3 AD8628 ADR03 470kΩ V– 5 C8 – 10kΩ TRIM 0.1µF 6 B V OUT R7 GND 1kΩ C9 4 –2.5V 1µF –5V C7 +2.5V R1A R VREFA R R COMA OFSA FBA +5V C4 C6 1µF R1 R2 R R OFS FB V DD C5 C3 I OUT 0.1µF 16-/14-BIT 0.1µF – V+ U1 DATA U2B AD5546/AD5556 VOUT AD8628 0V TO +2.5V GND V– + 16-/14-BIT DATA WR LDAC RS MSB WR LDAC RS MSB Figure 23. Full Span Calibration Rev. D | Page 14 of 20 03810-0-024 03810-025 Data Sheet AD5546/AD5556 The input bias current of an op amp also generates an offset at REFERENCE SELECTION the voltage output because of the bias current flowing in the When selecting a reference for use with the AD55xx series feedback resistor, R . FB of current output DACs, pay attention to the output voltage Common-mode rejection of the op amp is important in voltage- temperature coefficient specification of the reference. Choosing switching circuits because it produces a code-dependent error a precision reference with a low output temperature coefficient at the voltage output of the circuit. minimizes error sources. Table 11 lists some of the references available from Analog Devices that are suitable for use with this Provided that the DAC switches are driven from true wideband range of current output DACs. low impedance sources, they settle quickly. Consequently, the slew rate and settling time of a voltage-switching DAC circuit is AMPLIFIER SELECTION determined largely by the output op amp. To obtain minimum The primary requirement for the current-steering mode is an settling time in this configuration, minimize capacitance at the amplifier with low input bias currents and low input offset voltage. VREF node (the voltage output node in this application) of the Because of the code-dependent output resistance of the DAC, DAC. This is done by using low input capacitance buffer the input offset voltage of an op amp is multiplied by the variable amplifiers and careful board design. gain of the circuit. A change in this noise gain between two Analog Devices offers a wide range of amplifiers for both precision adjacent digital fractions produces a step change in the output dc and ac applications, as listed in Table 12 and Table 13. voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Table 11. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) ISS (mA) Output Noise (µV p-p) Package(s) ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Rev. D | Page 15 of 20 AD5546/AD5556 Data Sheet Table 12. Suitable Analog Devices Precision Op Amps V Maximum I Maximum 0.1 Hz to 10 Hz OS B Part No. Supply Voltage (V) (µV) (nA) Noise (µV p-p) Supply Current (µA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-23-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Table 13. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) V (Max) (µV) I (Max) (nA) Package(s) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899-1 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Rev. D | Page 16 of 20 Data Sheet AD5546/AD5556 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 0.19 SEATING COPLANARITY 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 24. 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 Dimensions shown in millimeters ORDERING GUIDE RES DNL INL Temperature 1 Model (Bit) (LSB) (LSB) Range (°C) Package Description Package Option Ordering Quantity AD5546BRU 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 50 AD5546BRU-REEL7 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 1,000 AD5546BRUZ 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 50 AD5546BRUZ-REEL7 16 ±1 ±2 −40 to +125 28-Lead TSSOP RU-28 1,000 AD5546CRUZ 16 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50 AD5546CRUZ-REEL7 16 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 1,000 AD5556CRU 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50 AD5556CRU-REEL7 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 1,000 AD5556CRUZ 14 ±1 ±1 −40 to +125 28-Lead TSSOP RU-28 50 EVAL-AD5546SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 17 of 20 AD5546/AD5556 Data Sheet NOTES Rev. D | Page 18 of 20 Data Sheet AD5546/AD5556 NOTES Rev. D | Page 19 of 20 AD5546/AD5556 Data Sheet NOTES ©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03810-0-11/11(D) Rev. D | Page 20 of 20