ANALOG DEVICES AD5543

Current Output/Serial Input, 16-/14-Bit DACs Data Sheet AD5543/AD5553 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-bit resolution AD5543 AD5543/AD5553 R 14-bit resolution AD5553 FB V DD ±1 LSB DNL ±1 LSB INL V I REF DAC OUT Low noise: 12 nV/√Hz Low power: I = 10 µA DD 16 OR 14 0.5 µs settling time CONTROL DAC 4Q multiplying reference input CS REGISTER LOGIC 2 mA full-scale current ± 20%, with V = 10 V REF 16 OR 14 Built-in RFB facilitates voltage conversion CLK GND 3-wire interface 16-BIT/14-BIT SHIFT REGISTER SDI Ultracompact 8-lead MSOP and 8-lead SOIC packages Figure 1. APPLICATIONS 1.0 Automatic test equipment 0.8 Instrumentation 0.6 Digitally controlled calibration 0.4 Industrial control PLCs 0.2 0 GENERAL DESCRIPTION –0.2 The AD5543/AD5553 are precision 16-/14-bit, low power, –0.4 current output, small form factor digital-to-analog converters –0.6 (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference. –0.8 –1.0 The applied external reference, V , determines the full-scale REF output current. An internal feedback resistor (R ) facilitates the FB CODE R-2R and temperature tracking for voltage conversion when combined with an external op amp. Figure 2. Integral Nonlinearity 2 A serial-data interface offers high speed, 3-wire microcontroller- compatible inputs using serial data in (SDI), clock (CLK), and 0 chip select (CS). –2 The AD5543/AD5553 are packaged in ultracompact (3 mm × –4 4.7 mm) 8-lead MSOP and 8-lead SOIC packages. –6 –8 –10 –12 –14 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 3. Reference Multiplying Bandwidth Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) INL (LSB) 0 4096 8152 12,288 16,384 20,480 24,575 28,672 32,768 36,864 40,960 45,056 49,152 53,248 57,344 61,440 65,536 02917-001 02917-002 02917-025 AD5543/AD5553 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 11  Applications ....................................................................................... 1  Stability ........................................................................................ 11  General Description ......................................................................... 1  Positive Voltage Output ............................................................. 11  Functional Block Diagram .............................................................. 1  Bipolar Output ............................................................................ 11  Revision History ............................................................................... 2  Programmable Current Source ................................................ 12  Specif ica t ions ..................................................................................... 3  Reference Selection .................................................................... 12  Timing Diagrams .......................................................................... 4  Amplifier Selection .................................................................... 12  Absolute Maximum Ratings ............................................................ 5  Evaluation Board ............................................................................ 14  ESD Caution .................................................................................. 5  System Development Platform ................................................. 14  Pin Configuration and Function Descriptions ............................. 6  AD5543/AD5553 to SPORT Interface .................................... 14  Typical Performance Characteristics ............................................. 7  Waveform Generator ................................................................. 14  Circuit Operation ............................................................................. 9  Operating the Evaluation Board .............................................. 14  DAC Section .................................................................................. 9  Bill of Materials ........................................................................... 18  Serial Data Interface ....................................................................... 10  Outline Dimensions ....................................................................... 19  ESD Protection Circuits............................................................. 10  Ordering Guide .......................................................................... 20  PCB Layout and Power Supply Bypassing .............................. 10  REVISION HISTORY 1/12—Rev. E to Rev. F 10/09—Rev. B to Rev. C Updated Outline Dimensions ..................................................... 14 Added Figure 15, Renumbered Sequentially ................................ 8 Change to Table 9 ........................................................................... 13 Changes to Ordering Guide .......................................................... 15 Changes to Figure 27 ...................................................................... 15 Changes to Figure 28 ...................................................................... 16 7/09—Rev. A to Rev. B Replaced Figure 29, Figure 30, and Figure 31 ............................. 17 Updated Format .................................................................. Universal Change to Features Section .............................................................. 1 2/11—Rev. D to Rev. E Updated Outline Dimensions ....................................................... 14 Added Evaluation Board Section ................................................. 14 Changes to Ordering Guide .......................................................... 15 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 2/03—Rev. 0 to Rev. A Changes to Ordering Guide ............................................................. 3 4/10—Rev. C to Rev. D Changes to Figure 3 .......................................................................... 1 12/02—Revision 0: Initial Version Changes to Table 1 ............................................................................ 3 Moved Timing Diagrams Section .................................................. 4 Moved Table 4 ................................................................................... 6 Delete Figure 13; Renumbered Sequentially ................................. 8 Changes to Figure 14 ........................................................................ 8 Changes to Figure 18 ........................................................................ 9 Moved Table 5 and Table 6 ............................................................ 10 Added Reference Selection Section and Amplifier Selection Section .............................................................................................. 12 Added Table 7, Table 8, and Table 9; Renumbered Sequentially .............................................................. 13 Rev. F | Page 2 of 20 Data Sheet AD5543/AD5553 SPECIFICATIONS VDD = 5 V ± 10%, VSS = 0 V, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted. Table 1. Parameter Symbol Condition 5 V ± 10% Unit 1 STATIC PERFORMANCE 16 Resolution N 1 LSB = V /2 = 153 µV when V = 10 V (AD5543) 16 Bits REF REF 14 1 LSB = VREF/2 = 610 µV when VREF = 10 V (AD5553) 14 Bits Relative Accuracy INL Grade: AD5553C ±1 LSB max Grade: AD5543C ±1 LSB max Grade: AD5543B ±2 LSB max Differential Nonlinearity DNL Monotonic ±1 LSB max Output Leakage Current I Data = 0x0000, T = 25°C 10 nA max OUT A Data = 0x0000, TA = TA maximum 20 nA max Full-Scale Gain Error GFSE Data = 0xFFFF ±1/±4 mV typ/max 2 Full-Scale Temperature Coefficient TCV 1 ppm/°C typ FS REFERENCE INPUT VREF Range VREF −15/+15 V min/max 3 Input Resistance R 5 kΩ typ REF 2 Input Capacitance C 5 pF typ REF ANALOG OUTPUT Output Current I Data = 0xFFFF for AD5543 2 mA typ OUT Data = 0x3FFF for AD5553 2 Output Capacitance C Code dependent 200 pF typ OUT LOGIC INPUTS AND OUTPUT Logic Input Low Voltage V 0.8 V max IL Logic Input High Voltage VIH 2.4 V min Input Leakage Current IIL 10 µA max 2 Input Capacitance CIL 10 pF max 2, 4 INTERFACE TIMING See Figure 4 and Figure 5 Clock Input Frequency fCLK 50 MHz Clock Width High tCH 10 ns min Clock Width Low t 10 ns min CL CS to Clock Setup t 0 ns min CSS t 10 ns min Clock to CS Hold CSH Data Setup tDS 5 ns min Data Hold tDH 10 ns min SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE 4.5/5.5 V min/max Positive Supply Current IDD Logic inputs = 0 V 10 µA max Power Dissipation P Logic inputs = 0 V 0.055 mW max DISS Power Supply Sensitivity P ΔV = ±5% 0.006 %/% max SS DD Rev. F | Page 3 of 20 AD5543/AD5553 Data Sheet Parameter Symbol Condition 5 V ± 10% Unit 4 AC CHARACTERISTICS Output Voltage Settling Time tS To ±0.1% of full scale, 0.5 µs typ Data = 0x0000 to 0xFFFF to 0x0000 for AD5543 Data = 0x0000 to 0x3FFF to 0x0000 for AD5553 Reference Multiplying Bandwidth BW V = 100 mV rms, data = 0xFFFF 6.6 MHz typ REF DAC Glitch Impulse Q V = 0 V, data = 0x7FFF to 0x8000 for AD5543 7 nV-sec REF Feedthrough Error VOUT/VREF Data = 0x0000, VREF = 100 mV rms, same channel −83 dB Digital Feedthrough Q CS = 1 and fCLK = 1 MHz 7 nV-sec Total Harmonic Distortion THD V = 5 V p-p, data = 0xFFFF, f = 1 kHz −103 dB typ REF Output Spot Noise Voltage e f = 1 kHz, BW = 1 Hz 12 nV/√Hz N 1 All static performance tests (except I ) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R terminal is OUT FB tied to the amplifier output. The +IN op amp is grounded, and the DAC IOUT is tied to the −IN op amp. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and are not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used. 4 All input control signals are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. R F TIMING DIAGRAMS SDI D15 D14 D13 D12 D11 D10 D9 D8 D1 D0 CLK t t t t DS DH CH CL t CSS t CSH CS Figure 4. AD5543 Timing Diagram SDI D13 D12 D11 D10 D9 D8 D7 D6 D1 D0 CLK t t t t DS DH CH CL t CSS t CSH CS Figure 5. AD5553 Timing Diagram Rev. F | Page 4 of 20 02917-017 02917-016 Data Sheet AD5543/AD5553 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any VDD to GND −0.3 V to +8 V other conditions above those indicated in the operational VREF to GND −18 V to +18 V section of this specification is not implied. Exposure to absolute Logic Inputs to GND −0.3 V to +8 V maximum rating conditions for extended periods may affect V(I ) to GND −0.3 V to V + 0.3 V OUT DD device reliability. Input Current to Any Pin Except Supplies ±50 mA Package Power Dissipation (TJ Max − TA )/θJA ESD CAUTION Thermal Resistance, θJA 8-Lead Surface Mount (MSOP) 150°C/W 8-Lead Surface Mount (SOIC) 100°C/W Maximum Junction Temperature (T ) 150°C J Max Operating Temperature Range Model B and Model C −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature R-8, RM-8 (Vapor Phase, 60 sec) 215°C R-8, RM-8 (Infrared, 15 sec) 220°C Rev. F | Page 5 of 20 AD5543/AD5553 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK 1 8 CS AD5543/ SDI 2 7 V DD AD5553 R 3 6 GND FB TOP VIEW (Not to Scale) V 4 5 I REF OUT Figure 6. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Clock Input. Positive-edge triggered, clocks data into shift register. 2 SDI Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. 3 RFB Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output. 4 V DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. REF 5 I DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for OUT voltage output. 6 GND Analog and Digital Ground. 7 VDD Positive Power Supply Input. Specified range of operation at 5 V ± 10%. 8 CS Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge. See Table 4 for operation. Table 4. Control-Logic Truth Table CLK CS Serial Shift Register Function DAC Register X H No effect Latched 1 L Shift register data advanced one bit Latched ↑+ 1 X H No effect Latched 1 1 X Shift register data transferred to DAC register New data loaded from serial register ↑+ 1 ↑+ = positive logic transition; X = don't care. Rev. F | Page 6 of 20 02917-004 Data Sheet AD5543/AD5553 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) CODE (Decimal) Figure 7. AD5543 Integral Nonlinearity Error Figure 10. AD5553 Differential Nonlinearity Error 1.5 1.0 V = 2.5V REF T = 25°C A 0.8 1.0 0.6 0.4 0.5 0.2 INL 0 0 DNL –0.2 –0.5 –0.4 –0.6 –1.0 GE –0.8 –1.5 –1.0 2 4 6 8 10 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 SUPPLY VOLTAGE V (V) CODE (Decimal) DD Figure 8. AD5543 Differential Nonlinearity Error Figure 11. Linearity Error vs. VDD 5 1.0 V = 5V DD T = 25°C A 0.8 4 0.6 0.4 3 0.2 0 2 –0.2 –0.4 1 –0.6 –0.8 0 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 LOGIC INPUTVOLTAGE V (V) CODE (Decimal) IH Figure 9. AD5553 Integral Nonlinearity Error Figure 12. Supply Current vs. Logic Input Voltage Rev. F | Page 7 of 20 INL (LSB) DNL (LSB) INL (LSB) 02917-007 02917-006 02917-005 DNL (LSB) LINEARITY ERROR (LSB) SUPPLY CURRENT I (mA) DD 02917-010 02917-009 02917-008 AD5543/AD5553 Data Sheet 3.0 A2 –5V DLY 67.72µs 2.5 2.0 0x5555 1.5 0x8000 1.0 0xFFFF 0x0000 0.5 0 10k 100k 1M 10M 100M 5V 2V 136ns CLOCK FREQUENCY (Hz) Figure 16. Settling Time Figure 13. AD5543 Supply Current vs. Clock Frequency –3.65 90 V = 5V ± 10% DD V = 10V –3.70 REF 80 –3.75 70 60 –3.80 50 –3.85 40 –3.90 30 –3.95 20 –4.00 10 –4.05 0 –20 –10 0 10 20 30 40 10 100 1k 10k 100k 1M FREQUENCY (Hz) TIME (ns) Figure 14. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 17. Midscale Transition and Digital Feedthrough 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 5 10 15 20 25 FREQUENCY (kHz) Figure 15. AD5543/AD5553 Analog THD Rev. F | Page 8 of 20 POWER SPECTRUM (dB) SUPPLY CURRENT (mA) PSRR (dB) 02917-012 02917-011 02917-200 V (V) OUT 02917-014 02917-026 Data Sheet AD5543/AD5553 CIRCUIT OPERATION The AD5543/AD5553 contain 16-/14-bit current output, DACs, Note that a matching switch is used in series with the internal serial input registers, and DAC registers. Both converters use a 5 kΩ feedback resistor. If users attempt to measure RFB, power 3-wire serial data interface. must be applied to VDD to achieve continuity. V DD DAC SECTION R2 The DAC architecture uses a current steering R-2R ladder C1 V R DD FB design. Figure 18 shows the typical equivalent DAC structure. I 1 AD5543/ OUT The DAC contains a matching feedback resistor for use with an V V REF REF A1 AD5553 R1 GND external op amp (see Figure 19). With RFB and IOUT terminals V = 0 TO –V OUT REF SYNC SCLK SDIN connected to the op amp output and inverting node, respectively, AGND a precision voltage output is achieved as V = −V × D/65,536 (AD5543) (1) OUT REF µCONTROLLER = −V × D/16,384 (AD5553) (2) NOTES VOUT REF 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (4pF TO 6pF) MAY BE REQUIRED Note that the output voltage polarity is the opposite of the VREF IF A1 IS A HIGH SPEED AMPLIFIER. polarity for dc reference voltages. Figure 19. Voltage Output Configuration These DACs are designed to operate with either negative or These DACs are also designed to accommodate ac reference positive reference voltages. The VDD power pin is only used input signals. The AD5543 accommodates input reference by the internal logic to drive the on and off states of the DAC voltages in the range of −12 V to +12 V. The reference voltage switches. inputs exhibit a constant nominal input resistance value of 5 kΩ ± 30%. The DAC output (I ) is code dependent, producing OUT V DD various resistances and capacitances. External amplifier choice R R R R V REF FB should take into account the variation in impedance generated 2R 2R 2R R 5kΩ by the AD5543 on the inverting input node of the amplifier. S2 S1 The feedback resistance, in parallel with the DAC ladder I OUT resistance, dominates output voltage noise. To maintain good analog performance, power supply bypassing of 0.01 µF to 0.1 µF GND ceramic or chip capacitors, in parallel with a 1 µF tantalum capacitor, is recommended. Due to degradation of PSRR in DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY; frequency, users must avoid using switching power supplies. SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED. DD Figure 18. Equivalent R-2R DAC Circuit Rev. F | Page 9 of 20 02917-018 02917-019 AD5543/AD5553 Data Sheet SERIAL DATA INTERFACE V DD The AD5543/AD5553 use a 3-wire (CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register DIGITAL INPUTS in a 16-bit data-word format for the AD5543. The MSB is loaded 5kΩ first. Table 5 defines the 16 data-word bits. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK, subject to the data setup-and-hold time requirements DGND that are specified in the interface timing specifications. Only the Figure 20. Equivalent ESD Protection Circuits last 16 bits clocked into the serial register are interrogated when PCB LAYOUT AND POWER SUPPLY BYPASSING the CS pin is strobed to transfer the serial register data to the DAC register. Because most microcontrollers output serial data in 8- It is a good practice to employ compact, minimum lead length bit bytes, two data bytes can be written to the AD5543/AD5553. PCB layout design. The leads to the input should be as short as CS After loading the serial register, the rising edge of transfers possible to minimize IR drop and stray inductance. the serial register data to the DAC register; during this strobe, It is also essential to bypass the power supplies with quality the CLK should not be toggled. For the AD5553, with 16-bit capacitors for optimum stability. Supply leads to the device clock cycles, the two LSBs are ignored. should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic ESD PROTECTION CIRCUITS capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize All logic input pins contain back-biased ESD protection Zener transient disturbance and filter out low frequency ripple. diodes that are connected to ground (DGND) and V , as DD shown in Figure 20. The PCB metal traces between V and R should also be REF FB matched to minimize gain error. Table 5. AD5543 Serial Input Register Data Format; Data Loaded MSB-First Format B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 6. AD5553 Serial Input Register Data Format; Data Loaded MSB-First Format 1 B13 (MSB) B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when CS returns to logic high. Rev. F | Page 10 of 20 02917-020 Data Sheet AD5543/AD5553 APPLICATIONS INFORMATION STABILITY BIPOLAR OUTPUT V DD The AD5543/AD5553 are inherently 2-quadrant multiplying U1 DACs. That is, they can easily be set up for unipolar output C1 V R DD FB operation. The full-scale output polarity is the inverse of the I V V OUT reference input voltage. REF REF V O AD8628 In some applications, it may be necessary to generate the full GND 4-quadrant multiplying capability or a bipolar output swing, AD5543/AD5553 which is easily accomplished by using an additional U4 external U2 amplifier configured as a summing amplifier (see Figure 23). In Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention this circuit, the second amplifier, U4, provides a gain of 2 that In the I-to-V configuration, the IOUT of the DAC and the inverting increases the output span magnitude to 5 V. Biasing the external node of the op amp must be connected as close as possible to amplifier with a 2.5 V offset from the reference voltage results in a each other, and proper PCB layout technique must be employed. full 4-quadrant multiplying circuit. The transfer equation of this Because every code change corresponds to a step function, gain circuit shows that both negative and positive output voltages are peaking may occur if the op amp has limited GBP and there is created as the input data (D) is incremented from code zero excessive parasitic capacitance at the inverting node. (VOUT = −2.5 V) to midscale (VOUT = 0 V) to full-scale (VOUT = An optional compensation capacitor, C1, can be added for +2.5 V). stability, as shown in Figure 21. C1 should be found empirically, V = (D/32,768 − 1) × V (AD5543) (3) OUT REF but 20 pF is generally adequate for the compensation. V = (D/16,384 − 1) × V (AD5553) (4) OUT REF POSITIVE VOLTAGE OUTPUT For the AD5543, the resistance tolerance becomes the dominant To achieve the positive voltage output, an applied negative error of which users should be aware. reference to the input of the DAC is preferred over the output R1 R2 inversion through an inverting amplifier because of the tolerance 10kΩ ± 0.01% 10kΩ ± 0.01% errors of the resistors. To generate a negative reference, the C2 reference can be level-shifted by an op amp such that the VOUT U4 +5V and GND pins of the reference become the virtual ground and +5V 5kΩ ± 0.01% V −2.5 V, respectively (see Figure 22). V+ O R3 ADR03 U1 1/2AD8620 C1 +5V V R V– DD FB ADR03 V I V V +5V OUT IN REF OUT –5V 1/2AD8620 GND GND V –2.5V < V < +2.5V V O OUT IN U3 U4 +5V U1 GND C1 AD5553 ONLY V R DD FB U2 V+ U3 I V 1/2AD8620 REF OUT Figure 23. 4-Quadrant Multiplying Application Circuit V O –2.5V V– 1/2AD8628 GND –5V AD5543/AD5553 U2 0V < V < +2.5V O Figure 22. Positive Voltage Output Configuration Rev. F | Page 11 of 20 02917-021 02917-022 02917-023 AD5543/AD5553 Data Sheet PROGRAMMABLE CURRENT SOURCE REFERENCE SELECTION Figure 24 shows a versatile V-I conversion circuit using an When selecting a reference for use with the AD55xx series of improved Howland current pump. In addition to the precision current output DACs, pay attention to the output voltage, current conversion it provides, this circuit enables a bidirectional temperature coefficient specification of the reference. Choosing current flow and high voltage compliance. This circuit can be used a precision reference with a low output temperature coefficient in 4 mA to 20 mA current transmitters with up to 500 Ω of load. In minimizes error sources. Table 7 lists some of the references Figure 24, it can be shown that if the resistor network is matched, available from Analog Devices, Inc., that are suitable for use the load current is with this range of current output DACs. (R2+ R3)/R1 AMPLIFIER SELECTION I = × V × D (5) L REF R3 The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset R3 in theory can be made small to achieve the current needed voltage. Because of the code-dependent output resistance of the within the U3 output current driving capability. This circuit is DAC, the input offset voltage of an op amp is multiplied by the versatile such that AD8510 can deliver ±20 mA in both directions variable gain of the circuit. A change in this noise gain between and the voltage compliance approaches 15 V, which is limited two adjacent digital fractions produces a step change in the mainly by the supply voltages of U3. However, users must pay output voltage due to the amplifier’s input offset voltage. This attention to the compensation. Without C1, it can be shown output voltage change is superimposed upon the desired change that the output impedance becomes in output between the two codes and gives rise to a differential R1' R3(R1+ R2) linearity error, which, if large enough, can cause the DAC to be Z = (6) O R1(R2'+ R3')− R1'(R2+ R3) nonmonotonic. If the resistors are perfectly matched, ZO is infinite, which is The input bias current of an op amp also generates an offset at desirable, and behaves as an ideal current source. On the other the voltage output because of the bias current flowing in the hand, if they are not matched, ZO can be either positive or negative. feedback resistor, RFB. Negative can cause oscillation. As a result, C1 is needed to prevent Common-mode rejection of the op amp is important in voltage- the oscillation. For critical applications, C1 could be found switching circuits because it produces a code-dependent error empirically but typically falls in the range of a few picofarads (pF). at the voltage output of the circuit. V DD Provided that the DAC switches are driven from true wideband U1 low impedance sources (VIN and AGND), they settle quickly. V R FB DD Consequently, the slew rate and settling time of a voltage- V V I OUT R1' REF REF R2' switching DAC circuit is determined largely by the output op 150kΩ 15kΩ AD8628 GND amp. To obtain minimum settling time in this configuration, C1 10pF minimize capacitance at the V node (the voltage output node REF AD5543/AD5553 U2 in this application) of the DAC. This is done by using low input V DD R3' capacitance buffer amplifiers and careful board design. 50Ω U3 V+ Analog Devices offers a wide range of amplifiers for both AD8510 V– precision dc and ac applications, as listed in Table 8 and Table 9. R3 50Ω V SS V L R1 R2 150kΩ 15kΩ I LOAD L Figure 24. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities Rev. F | Page 12 of 20 02917-024 Data Sheet AD5543/AD5553 Table 7. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package(s) SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Table 8. Suitable Analog Devices Precision Op Amps V Maximum I Maximum 0.1 Hz to 10 Hz OS B Part No. Supply Voltage (V) (μV) (nA) Noise (μV p-p) Supply Current (μA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) V (Max) (μV) I (Max) (nA) Package(s) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899-1 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Rev. F | Page 13 of 20 AD5543/AD5553 Data Sheet EVALUATION BOARD The EVAL-AD5543/EVAL-AD5553 is used in conjunction with SPORT_TFS CS an SDP1Z system development platform board available from Analog Devices, which is purchased separately from the SPORT_TSCLK SCLK evaluation board. The USB-to-SPI communication to the SPORT_DTO SDIN AD5543 is completed using this Blackfin-based development board. The software offers a waveform generator. SYSTEM DEVELOPMENT PLATFORM The system development platform (SDP) is a hardware and ADSP-BF527 AD5543/AD5553 software evaluation tool for use in conjunction with product Figure 25. AD5543/AD5553 to SPORT Interface evaluation boards. The SDP board is based on the Blackfin WAVEFORM GENERATOR BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this The evaluation board software offers a waveform generator to show every change introduced and transmitted to the output. device, see the system development platform web page. OPERATING THE EVALUATION BOARD AD5543/AD5553 TO SPORT INTERFACE The evaluation board requires ±12 V and +5 V supplies. The The Analog Devices SDP has one SPORT serial port. The SPORT interface is used to control the AD5543/AD5553, +12 V VDD and VSS are used to power the output amplifier, while the +5 V is used to power the DAC (VDD1). allowing clock frequencies up to 30 MHz. Figure 26. Evaluation Board Software—Waveform Generator Rev. F | Page 14 of 20 02917-125 02917-124 Data Sheet AD5543/AD5553 Figure 27. Schematic of AD5543/AD5553 Evaluation Board Rev. F | Page 15 of 20 DVDD J1-1 DAC + VIN FOR SDP J1-2 DGND VDD J1-5 J1-4 OP AMP + REFERENCE SUPPLY J1-3 DVDD VSS C1 10uF C2 0.1uF VOUT C4 10uF 7 SDIN /CS VOUT VDD SCLK VSS C5 U1 0.1uF J4 1 3 SCLK C3 SCLK RFB 5.6pF U3 2 5 2 SDIN SDIN IOUT - 4 V- 6 OP 8 4 V+ /CS 7 CS VREF 3 DIS + 8 AD5543_53 C6 10uF AGND VDD C7 0.1uF 6 VDD LK1 VREF 2 6 +VIN VOUT U2 J3 C10 ADR435 5 + C9 C8 TRIM 0.1uF GND 10uF 0.1uF 4 AGND + + + 02917-126 AD5543/AD5553 Data Sheet BMODE1: PULL UP WITH A 10k RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD J2 60 61 RESET_IN BMODE1 59 62 UART_RX UART_TX 63 58 GND GND 57 64 NC NC BOARD ID EEPROM (24LC64) MUST BE ON I2C BUS 0, ADDRESS IS AT USER DISCRETION 56 65 SDP NC NC 55 66 STANDARD NC NC 3.3V_BF 54 67 CONNECTOR NC NC U4 53 68 NC NC 52 69 1 8 GND A0 VCC GND 51 70 2 7 NC NC A1 WP 50 71 3 6 NC NC A2 SCL 49 72 4 5 * TMR_C TMR_D VSS SDA 48 73 TIMERS TMR_A TMR_B 47 74 24LC64 GPIO6 GPIO7 46 75 GND GND 45 76 GENERAL GPIO4 GPIO5 44 77 INPUT/OUTPUT GPIO2 GPIO3 STATUS 43 78 GPIO0 GPIO1 START 42 79 SCL_1 SCL_0 41 80 I2C SDA_1 SDA_0 40 81 GND GND 39 82 MAIN I2C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED) SPI_SEL1/SPI_SS SPI_CLK 38 83 SPI_SEL_C SPI_MISO 37 84 SPI I2C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED SPI_SEL_B SPI_MOSI 36 85 (CONNECTED TO BLACKFIN GPIO - USE I2C_0 FIRST) GND SPI_SEL_A 35 86 SPORT_INT GND 34 87 * SPORT_DT3 SPORT_TSCLK SCLK 33 88 * SPORT_DT2 SPORT_DT0 SDIN 32 89 SPORT SPORT_DT1 SPORT_TFS /CS 31 90 SPORT_DR1 SPORT_RFS 30 91 * SPORT_DR2 SPORT_DR0 29 92 * SPORT_DR3 SPORT_RSCLK 93 28 GND GND 27 94 PAR_FS1 PAR_CLK 26 95 PAR_FS3 PAR_FS2 25 96 PAR_A1 PAR_A0 24 97 PAR_A3 PAR_A2 23 98 GND GND 22 99 PAR_CS PAR_INT 100 21 PAR_RD PAR_WR 20 101 PAR_D1 PAR_D0 19 102 PARALLEL PAR_D3 PAR_D2 18 103 PORT PAR_D5 PAR_D4 17 104 GND GND 16 105 PAR_D7 PAR_D6 15 106 PAR_D9 PAR_D8 14 107 PAR_D11 PAR_D10 13 108 PAR_D13 PAR_D12 12 109 PAR_D14 GND 11 110 USB_VBUS GND PAR_D15 10 111 * * PAR_D17 PAR_D16 9 112 * * PAR_D19 PAR_D18 8 113 3.3V_BF * * PAR_D21 PAR_D20 7 114 * * PAR_D23 PAR_D22 6 115 GND GND 5 116 VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA USB_VBUS VIO(+3.3V) 4 117 GND GND VIN: USE THIS PIN TO POWER THE SDP 3 118 GND GND REQUIRES 4-7V 200mA 2 119 NC NC 1 120 *NC ON BLACKFIN SDP VIN NC Figure 28. Schematic of SDP Interface Rev. F | Page 16 of 20 02917-127 Data Sheet AD5543/AD5553 Figure 29. Silkscreen—Component Side View (Top Layer) Figure 30 Component Side Artwork Figure 31. Solder Side Artwork Rev. F | Page 17 of 20 02917-130 02917-129 02917-128 AD5543/AD5553 Data Sheet BILL OF MATERIALS Table 10. Name Part Description Value PCB Decal Part Description CS Testpoint Testpoint Red testpoint AGND Testpoint Testpoint Black testpoint C1 Capacitor+ 10 µF RTAJ_A 10 V SMD tantalum capacitor C2 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C3 Capacitor 5.6 pF C0603 Multilayer ceramic capacitor C4 Capacitor+ 10 µF RTAJ_B 16 V tantalum capacitor C5 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C6 Capacitor+ 10 µF RTAJ_B 16 V tantalum capacitor C7 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C8 Capacitor+ 10 µF RTAJ_B 16 V tantalum capacitor C9 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C10 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C11 Capacitor 10 µF C0805 10 V 10 µF ceramic capacitor 10% X5R 0805 C12 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor GL1 Ground link Component link Copper short J1 CON\POWER5 CON\POWER5 5-pin terminal block J2 SDP-STANDARD-CONN CON-120/FX8-120S-SV 120-way connector, 0.6 mm pitch, receptacle J3 SMB SMB Straight PCB mount SMB jack—50 Ω J4 SMB SMB Straight PCB mount SMB jack—50 Ω SCLK Testpoint Testpoint Red testpoint SDIN Testpoint Testpoint Red testpoint U1 AD5543/AD5553 SO8NB Digital-to-analog converter U2 ADR435 SO8NB 5 V reference U3 AD8038 SO8NB Single op amp 8-pin U4 24LC64 MSO8 64K I2C serial EEPROM MSOP8 USB_VBUS Testpoint Testpoint Black testpoint VOUT Testpoint Testpoint Red testpoint VREF Testpoint Testpoint Red testpoint X1 MTHOLE-3MM MTHOLE-3MM 3 mm NPTH hole X2 MTHOLE-3MM MTHOLE-3MM 3 mm NPTH hole Rev. F | Page 18 of 20 Data Sheet AD5543/AD5553 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 32. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 19 of 20 10-07-2009-B 012407-A AD5543/AD5553 Data Sheet ORDERING GUIDE 1, 2 Model INL (LSB) RES (LSB) Temperature Range Package Description Package Option Branding AD5543CRMZ ±1 16 −40°C to +85°C 8-Lead MSOP RM-8 DEV AD5543CRMZ-REEL7 ±1 16 −40°C to +85°C 8-Lead MSOP RM-8 DEV AD5543BR ±2 16 −40°C to +85°C 8-Lead SOIC_N R-8 AD5543BRZ ±2 16 −40°C to +85°C 8-Lead SOIC_N R-8 AD5543BRM ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB AD5543BRM-REEL7 ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB AD5543BRMZ ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB# AD5543BRMZ-REEL7 ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB# AD5553CRM ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC AD5553CRM-REEL7 ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC AD5553CRMZ ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC# AD5553CRMZ-REEL7 ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC# EVAL-AD5543SDZ Evaluation Board 1 The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil. 2 Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked. ©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02917-0-1/12(F) Rev. F | Page 20 of 20