ANALOG DEVICES AD5542A

2.7 V to 5.5 V, Serial-Input, Voltage-Output, 12-/16-Bit DAC AD5512A/AD5542A FEATURES FUNCTIONAL BLOCK DIAGRAM V 12-/16-bit resolution DD 1 LSB INL R FB R FB 11.8 nV/√Hz noise spectral density INV REFF R INV 1 µs settling time 16-BIT DAC V OUT 1.1 nV-sec glitch energy REFS 0.05 ppm/°C temperature drift AGNDF 5 kV HBM ESD classification V LOGIC 16-BIT DAC LATCH AGNDS 0.375 mW power consumption at 3 V CS CONTROL 2.7 V to 5.5 V single-supply operation LDAC LOGIC SCLK CLR LDAC Hardware and functions SERIAL INPUT REGISTER DIN 50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface AD5512A/ Power-on reset clears DAC output to midscale AD5542A Available in 3 mm × 3 mm, 10-/16-lead LFCSP and CLR DGND 16-lead TSSOP Figure 1. 16-Lead TSSOP and 16-Lead LFCSP APPLICATIONS GND 10 Automatic test equipment 8 R FB AD5542A-1 R FB Precision source-measure instruments 7 INV R Data acquisition systems INV 1 16-BIT DAC 6 V REF OUT Medical and aerospace instrumentation Communication equipment CS 2 16-BIT DAC LATCH CLR 5 CONTROL LOGIC SCLK 3 DIN 4 SERIAL INPUT REGISITER 9 GENERAL DESCRIPTION V DD The AD5512A/AD5542A are single, 12-/16-bit, serial input, Figure 2. 10-Lead LFCSP unbuffered voltage output digital-to-analog converters (DAC) that operate from a single 2.7 V to 5.5 V supply. The DAC Table 1. Related Devices output range extends from 0 V to V and is guaranteed REF Part No. Description monotonic, providing 1 LSB INL accuracy at 16 bits without AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs adjustment over the full specified temperature range of −40°C 2.7 V to 5.5 V 16-bit voltage output DACs AD5541/AD5542 to +85°C (AD5542A) or −40°C to +125°C (AD5512A). 18-/20-bit voltage output DACs AD5781/AD5791 16-bit ±12 V/±15 V bipolar output DAC AD5570 Offering unbuffered outputs, the AD5512A/AD5542A achieve 4.5 V to 5.5 V, 12-/16-bit quad channel DAC AD5024/AD5064 a 1 μs settling time with low offset errors ideal for high speed AD5764 16-bit, bipolar, voltage output DAC open loop control. The AD5512A/AD5542A incorporate a bipolar mode of operation PRODUCT HIGHLIGHTS that generates a ±V output swing. The AD5512A/AD5542A REF 1. 16-bit performance without adjustment. also include Kelvin sense connections for the reference and 2. 2.7 V to 5.5 V single supply operation. analog ground pins to reduce layout sensitivity. 3. Low 11.8 nV/√Hz noise spectral density. The AD5512A/AD5542A are available in a 16-lead LFCSP with 4. Low 0.05 ppm/°C temperature drift. the AD5542A also available in a 10-lead LFCSP and a 16-lead 5. 3 mm × 3 mm LFCSP and TSSOP packaging. TSSOP. The AD5512A/AD5542A use a versatile 3-wire interface that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface standards. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 09199-002 09199-001 AD5512A/AD5542A TABLE OF CONTENTS Features .............................................................................................. 1 Unipolar Output Operation ...................................................... 15 Applications ....................................................................................... 1 Bipolar Output Operation ......................................................... 16 General Description ......................................................................... 1 Output Amplifier Selection ....................................................... 17 Functional Block Diagram .............................................................. 1 Force Sense Amplifier Selection ............................................... 17 Product Highlights ........................................................................... 1 Reference and Ground ............................................................... 17 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 17 Specifications ..................................................................................... 3 Power Supply and Reference Bypassing .................................. 17 AD5512A ....................................................................................... 3 Applications Information .............................................................. 18 AD5542A ....................................................................................... 4 Microprocessor Interfacing ....................................................... 18 AC Characteristics ........................................................................ 5 AD5512A/AD5542A to ADSP-BF531 Interface .................... 18 Timing Characteristics ................................................................ 6 AD5512A/AD5542A to SPORT Interface .............................. 18 Absolute Maximum Ratings ............................................................ 7 AD5512A/AD5542A to 68HC11/68L11 Interface .................... 18 ESD Caution .................................................................................. 7 AD5512A/AD5542A to ADSP-2101 Interface ....................... 18 Pin Configuration and Function Descriptions ............................. 8 AD5512A/AD5542A to MICROWIRE Interface .................. 18 Typical Performance Characteristics ........................................... 10 Layout Guidelines....................................................................... 19 Terminology .................................................................................... 14 Galvanically Isolated Interface ................................................. 19 Theory of Operation ...................................................................... 15 Decoding Multiple DACs .......................................................... 19 Digital-to-Analog Section ......................................................... 15 Outline Dimensions ....................................................................... 20 Serial Interface ............................................................................ 15 Ordering Guide .......................................................................... 21 REVISION HISTORY 5/11—Rev. 0 to Rev. A Changes to Table 3, Power Dissipation Value and Endnote 1 .... 4 Changes to Table 5 ............................................................................ 6 Changes to Ordering Guide .......................................................... 21 10/10—Revision 0: Initial Version Rev. A | Page 2 of 24 AD5512A/AD5542A SPECIFICATIONS AD5512A V = 2.7 V to 5.5 V, V = 2.7 V to 5.5 V, V = 2.5 V, AGND = DGND = 0 V, −40°C < T < +125°C, unless otherwise noted. DD LOGIC REF A Table 2. 1 Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error +0.5 ±2 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero-Code Error 0.03 ±0.5 LSB Unipolar Zero-Code Temperature Coefficient ±0.05 ppm/°C Bipolar Resistor Matching 1 Ω/Ω R /R , typically R = R = 28 kΩ FB INV FB INV ±0.02 ±0.08 % Ratio error Bipolar Zero Offset Error ±0.07 ±2 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero-Code Offset Error ±0.02 ±0.5 LSB Bipolar Gain Error ±0.07 ±2 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 V − 1 LSB V Unipolar operation REF −V +V − 1 LSB V Bipolar operation REF REF DAC Output Impedance 6.25 kΩ Tolerance typically 20% Power Supply Rejection Ratio ±1.0 LSB ΔV ± 10% DD Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x840 (AD5512A) or 0x8400 (AD5542A), frequency = 1 kHz, unipolar mode Output Noise 0.134 μV p-p 0.1 Hz to 10 Hz, unipolar mode 2 DAC REFERENCE INPUT Reference Input Range 2.0 V V DD 3 Reference Input Resistance 9 kΩ Unipolar operation 7.5 kΩ Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0x3FFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V INL DD Input High Voltage, V 2.4 V V = 2.7 V to 5.5 V INH DD 2 Input Capacitance 10 pF 2 Hysteresis Voltage 0.15 V POWER REQUIREMENTS V 2.7 5.5 V All digital inputs at 0 V, V , or V DD LOGIC DD I 125 150 µA V = V or V and V = GND DD IH LOGIC DD IL V 1.8 5.5 V LOGIC I 15 24 µA All digital inputs at 0 V, V , or V LOGIC LOGIC DD Power Dissipation 1.5 6.05 mW 1 Temperatures are as follows: A version −40°C to +125°C. 2 Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x855. Rev. A | Page 3 of 24 AD5512A/AD5542A AD5542A V = 2.7 V to 5.5 V, V = 2.7 V to 5.5 V, V = 2.5 V, AGND = DGND = 0 V, −40°C < T < +85°C, unless otherwise noted. DD LOGIC REF A Table 3. 1 Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade ±2.0 A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error +0.5 ±2 LSB T = 25°C A ±3 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero-Code Error 0.3 ±0.7 LSB T = 25°C A ±1.5 LSB Unipolar Zero-Code Temperature Coefficient ±0.05 ppm/°C Bipolar Resistor Matching 1.000 Ω/Ω R /R , typically R = R = 28 kΩ FB INV FB INV ±0.0015 ±0.0076 % Ratio error Bipolar Zero Offset Error ±1 ±5 LSB T = 25°C A ±6 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero-Code Offset Error ±1 ±5 LSB T = 25°C A ±6 LSB Bipolar Gain Error ±1 ±5 LSB T = 25°C A ±6 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 V − 1 LSB V Unipolar operation REF −V +V − 1 LSB V Bipolar operation REF REF DAC Output Impedance 6.25 kΩ Tolerance typically 20% Power Supply Rejection Ratio ±1.0 LSB ΔV ± 10% DD Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x840 (AD5512A) or 0x8400 (AD5542A), frequency = 1 kHz, unipolar mode Output Noise 0.134 μV p-p 0.1 Hz to 10 Hz 2 DAC REFERENCE INPUT Reference Input Range 2.0 V V DD 3 Reference Input Resistance 9 kΩ Unipolar operation 7.5 kΩ Bipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V INL DD Input High Voltage, V 2.4 V V = 2.7 V to 5.5 V INH DD 2 Input Capacitance 10 pF 2 Hysteresis Voltage 0.15 V POWER REQUIREMENTS V 2.7 5.5 V All digital inputs at 0 V, V , or V DD LOGIC DD I 125 150 µA V = V or V and V = GND DD IH LOGIC DD IL V 1.8 5.5 V LOGIC I 15 24 µA All digital inputs at 0 V, V , or V LOGIC LOGIC DD Power Dissipation 0.625 0.825 mW 1 For 2.7 V ≤ V ≤ 5.5 V, temperatures are as follows: A, B versions −40°C to +85°C. LOGIC 2 Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x8555. Rev. A | Page 4 of 24 AD5512A/AD5542A AC CHARACTERISTICS V = 2.7 V to 5.5 V, V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ V , AGND = DGND = 0 V, −40°C < T < +125°C, unless otherwise noted. DD LOGIC REF DD A Table 4. Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time 1 μs To 1/2 LSB of FS, C = 10 pF L Slew Rate 17 V/µs C = 10 pF, measured from 0% to 63% L Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, V = 1 V p-p at 100 kHz REF Digital Feedthrough 0.2 nV-sec Signal-to-Noise Ratio 92 dB Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz Total Harmonic Distortion 74 dB DAC code = 0x3FFF (AD5512A) or 0xFFFF (AD5542A), frequency 10 kHz, V = 2.5 V ± 1 V p-p REF Rev. A | Page 5 of 24 AD5512A/AD5542A TIMING CHARACTERISTICS VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted. Table 5. 1, 2 3 4 Parameter Limit 1.8 ≤ VLOGIC ≤ 2.7 V Limit 2.7 V ≤ VLOGIC ≤ 5.5 V Unit Description fSCLK 14 50 MHz max SCLK cycle frequency t1 70 20 ns min SCLK cycle time t 35 10 ns min SCLK high time 2 t 35 10 ns min SCLK low time 3 t 5 5 ns min CS low to SCLK high setup 4 t 5 5 ns min CS high to SCLK high setup 5 t 5 5 ns min SCLK high to CS low hold time 6 t 10 5 ns min SCLK high to CS high hold time 7 t 35 10 ns min Data setup time 8 t 5 4 ns min Data hold time (V = 90% of V , V = 10% of V ) INH DD INL DD 9 t 5 5 ns min Data hold time (V = 3 V, V = 0 V) INH INL 9 t 20 20 ns min LDAC pulsewidth 10 10 10 ns min t CS high to LDAC low setup 11 t 15 15 ns min CS high time between active periods 12 t 15 15 ns CLR pulsewidth 13 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 1 ns/V and timed from a voltage level of (V + V )/2. R F INL INH 3 −40°C < TA < +105°C. 4 −40°C < T < +125°C. A t 1 SCLK t t t 2 3 6 t 5 t t 7 4 CS t 12 t 8 t 9 1 DB15 DIN 2 DB11 t 11 t 10 LDAC t 13 CLR NOTES 1. FOR AD5542A = DB15. 2. FOR AD5512A = DB11. Figure 3. Timing Diagram Rev. A | Page 6 of 24 09199-003 AD5512A/AD5542A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 6. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to AGND −0.3 V to +6 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to DGND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect V to AGND −0.3 V to V + 0.3 V OUT DD device reliability. AGNDF, AGNDS to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA ESD CAUTION Operating Temperature Range AD5512A Industrial (A Version) −40°C to +125°C AD5542A Industrial (A, B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (T max) 150°C J Package Power Dissipation (T max − T )/θ J A JA Thermal Impedance, θ JA TSSOP (RU-16) 113°C/W 73°C/W LFCSP (CP-16-22) 74°C/W LFCSP (CP-10-9) Lead Temperature, Soldering 1 Peak Temperature 260°C 2 ESD 5 kV 1 As per JEDEC Standard 20. 2 HBM classification. Rev. A | Page 7 of 24 AD5512A/AD5542A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 GND CS 2 9 V DD V 1 12 DGND OUT AD5542A-1 SCLK 3 8 R FB TOP VIEW AGNDF 2 11 LDAC TOP Not to Scale DIN 4 7 INV VIEW AGNDS 3 10 CLR CLR 5 6 V OUT REFS 4 9 DIN NOTES NC = NO CONNECT 1. THE EXPOSED PADDLE SHOULD BE (Not to Scale) TIED TO THE POINT OF LOWEST POTENTIAL, IN THIS CASE, GND. Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration Table 7. AD5512A/AD5542A Pin Function Descriptions Pin No. 16-Lead 10-Lead LFCSP LFCSP Mnemonic Description 1 6 V Analog Output Voltage from the DAC. OUT 2 AGNDF Ground Reference Point for Analog Circuitry (Force). 3 AGNDS Ground Reference Point for Analog Circuitry (Sense). 4 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 5 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 6 2 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 7 NC No Connect. 8 3 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 9 4 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 10 5 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale. 11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. 13 7 INV Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting input in bipolar mode. 14 V Logic Power Supply. LOGIC 15 9 V Analog Supply Voltage, 5 V ± 10%. DD 16 8 R Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. FB 1 REF Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can range from 2 V to V . DD 10 GND Ground. EPAD Exposed Pad The exposed pad should be tied to the point of lowest potential, in this case, GND. Rev. A | Page 8 of 24 09199-036 09199-034 REFF 5 16 R FB CS 6 15 V DD NC 7 14 V LOGIC SCLK 8 13 INV AD5512A/AD5542A 1 16 R V FB DD 2 15 V V OUT LOGIC 3 14 AGNDF INV AD5542A TOP VIEW 4 13 AGNDS DGND (Not to Scale) REFS 5 12 LDAC REFF 6 11 CLR NC 7 10 DIN 8 9 CS SCLK NC = NO CONNECT Figure 6. AD5542A 16-Lead TSSOP Pin Configuration Table 8. AD5542A Pin Function Descriptions Pin No. Mnemonic Description 1 R Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. FB 2 V Analog Output Voltage from the DAC. OUT 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 7 NC No Connect. 8 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 9 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When is activated, the DAC register is cleared to the model selectable midscale. CLR 12 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 13 DGND Digital Ground. Ground reference for digital circuitry. 14 INV Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting input in bipolar mode. 15 V Logic Power Supply. LOGIC 16 V Analog Supply Voltage, 5 V ± 10%. DD Rev. A | Page 9 of 24 09199-035 AD5512A/AD5542A TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 V = 5V V = 5V DD DD V = 2.5V V = 2.5V REF REF 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.75 –0.50 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE CODE Figure 7. AD5542A Integral Nonlinearity vs. Code Figure 10. AD5542A Differential Nonlinearity vs. Code 0.25 0.75 V = 5V V = 5V DD DD V = 2.5V V = 2.5V REF REF 0 0.50 –0.25 0.25 –0.50 0 –0.75 –0.25 –1.00 –0.50 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. AD5542A Integral Nonlinearity vs. Temperature Figure 11. AD5542A Differential Nonlinearity vs. Temperature 0.50 0.75 V = 2.5V V = 5V DD REF T = 25°C T = 25°C A A 0.25 0.50 DNL DNL 0 0.25 –0.25 0 INL –0.50 –0.25 INL –0.75 –0.50 2 3 4 5 6 7 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 9. AD5542A Linearity Error vs. Supply Voltage Figure 12. AD5542A Linearity Error vs. Reference Voltage Rev. A | Page 10 of 24 INTEGRAL NONLINEARITY (LSB) LINEARITY ERROR (LSB) INTEGRAL NONLINEARITY (LSB) 09199-008 09199-007 09199-006 DIFFERENTIAL NONLINEARITY (LSB) LINEARITY ERROR (LSB) DIFFERENTIAL NONLINEARITY (LSB) 09199-011 09199-010 09199-009 AD5512A/AD5542A 0 0.15 V = 5V V = 5V DD DD V = 2.5V V = 2.5V REF REF –0.1 T = 25°C T = 25°C A A 0.10 –0.2 –0.3 0.05 –0.4 0 –0.5 –0.6 –0.05 –0.7 –0.10 –0.8 –0.9 –0.15 –40 25 85 –40 25 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. AD5512A/AD5542A Gain Error vs. Temperature Figure 16. AD5512A/AD5542A Zero-Code Error vs. Temperature 2.0 132 T = 25°C A V = 5V DD V = 2.5V REF 130 T = 25°C A 1.5 128 REFERENCE VOLTAGE V = 5V DD 126 1.0 SUPPLY VOLTAGE 124 V = 2.5V REF 122 0.5 120 118 0 116 0 1 2 3 4 5 6 –40 25 85 VOLTAGE (V) TEMPERATURE (°C) Figure 17. AD5512A/AD5542A Supply Current vs. Reference Voltage or Figure 14. AD5512A/AD5542A Supply Current vs. Temperature Supply Voltage 200 200 V = 5V DD V = 2.5V 180 REF T = 25°C A 160 150 140 120 100 100 80 60 50 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 DIGITAL INPUT VOLTAGE (V) CODE (Decimal) Figure 15. AD5512A/AD5542A Supply Current vs. Digital Input Voltage Figure 18. AD5512A/AD5542A Reference Current vs. Code Rev. A | Page 11 of 24 SUPPLY CURRENT (µA) GAIN ERROR (LSB) SUPPLY CURRENT (µA) 09199-014 09199-013 09199-012 REFERENCE CURRENT (µA) SUPPLY CURRENT (µA) ZERO-CODE ERROR (LSB) 09199-015 09199-016 09199-017 AD5512A/AD5542A V = 2.5V REF V = 2.5V REF V = 5V DD V = 5V DD T = 25°C A T = 25°C A 100 100 V (1V/DIV) DIN (5V/DIV) OUT 90 90 V (50mV/DIV) OUT V (50mV/DIV) OUT GAIN = –216 N 10 1LSB = V /(2 )–1 10 REF 0 0 2µs/DIV 0.5µs/DIV Figure 19. AD5512A/AD5542A Digital Feedthrough Figure 22. AD5512A/AD5542A Small Signal Settling Time 5 1.236 5 +125°C +25°C CS –55°C 0 1.234 4 –5 1.232 3 –10 1.230 –15 2 1.228 V –20 OUT 1 1.226 –25 0 1.224 –30 90 100 110 120 –0.5 0 0.5 1.0 1.5 2.0 I SUPPLY (µA) DD TIME (ns) Figure 20. AD5512A/AD5542A Digital-to-Analog Glitch Impulse Figure 23. AD5512A/AD5542A Analog Supply Current Histogram 6 +125°C +25°C –55°C V = 2.5V REF 5 2µs/DIV V = 5V DD T = 25°C A CS (5V/DIV) 100 4 90 10pF 3 50pF 100pF 2 200pF 1 10 0 0 V (0.5V/DIV) 15 16 17 18 19 OUT I AT RAILS (µA) LOGIC Figure 21. AD5512A/AD5542A Large Signal Settling Time Figure 24. AD5512A/AD5542A Digital Supply Current Histogram Rev. A | Page 12 of 24 VOLTAGE (V) 09199-018 09199-032 09199-020 HITS HITS 09199-043 09199-042 09199-021 AD5512A/AD5542A 10 40 V = 5V DD V = 5V DD V = 5V REF V = 2.5V 20 REF T = 25°C A T = 25°C A DATA = 0x0000 0 5 –20 –40 0 –60 –80 –5 –100 0 20 40 60 80 100 120 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. AD5512A/AD5542A 0.1 Hz to 10 Hz Output Noise Figure 28. AD5512A/AD5542A Total Harmonic Distortion 40 10 V = 5V DD 35 V = 2.5V 0 REF T = 25°C A 30 –10 25 –20 20 –30 15 –40 10 V = 5V DD –50 V = 2.5V ± 0.2V 5 REF 0 –60 600 700 800 900 1000 1100 1200 1300 1400 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. AD5512A/AD5542A Noise Spectral Density vs. Frequency,1 kHz Figure 29. AD5512A/AD5542A Multiplying Bandwidth 14 12 10 8 6 4 V = 5V DD 2 V = 2.5V REF T = 25°C A 0 9600 9700 9800 9900 10,000 10,100 10,200 10,300 10,400 FREQUENCY (Hz) Figure 27. AD5512A/AD5542A Noise Spectral Density vs. Frequency, 10 kHz Rev. A | Page 13 of 24 NOISE SPECTRAL DENSITY (nV rms/ Hz) NOISE SPECTRAL DENSITY (nV rms/ Hz) OUTPUT NOISE (µV rms) 09199-037 09199-038 09199-039 V /V (dBm) V (dBm) OUT REF OUT 09199-041 09199-040 AD5512A/AD5542A TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy or Integral Nonlinearity (INL) Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy or INL is a measure of the analog output when the input code in the DAC register changes maximum deviation, in LSBs, from a straight line passing state. It is normally specified as the area of the glitch in nV-sec through the endpoints of the DAC transfer function. A typical and is measured when the digital input code is changed by INL vs. code plot is shown in Figure 7. 1 LSB at the major carry transition. A digital-to-analog glitch Differential Nonlinearity (DNL) impulse plot is shown in Figure 20. DNL is the difference between the measured change and the Digital Feedthrough ideal 1 LSB change between any two adjacent codes. A specified Digital feedthrough is a measure of the impulse injected into differential nonlinearity of ±1 LSB maximum ensures mono- the analog output of the DAC from the digital inputs of the tonicity. A typical DNL vs. code plot is shown in Figure 10. DAC, but it is measured when the DAC output is not updated. Gain Error CS is held high while the SCLK and DIN signals are toggled. It Gain error is the difference between the actual and ideal analog is specified in nV-sec and is measured with a full-scale code output range, expressed as a percent of the full-scale range. change on the data bus, that is, from all 0s to all 1s and vice It is the deviation in slope of the DAC transfer characteristic versa. A typical digital feedthrough plot is shown in Figure 19. from ideal. Power Supply Rejection Ratio (PSRR) Gain Error Temperature Coefficient PSRR indicates how the output of the DAC is affected by changes Gain error temperature coefficient is a measure of the change in the power supply voltage. The power supply rejection ratio is in gain error with changes in temperature. It is expressed in quoted in terms of percent change in output per percent change ppm/°C. in V for full-scale output of the DAC. V is varied by ±10%. DD DD Zero-Code Error Reference Feedthrough Zero-code error is a measure of the output error when zero Reference feedthrough is a measure of the feedthrough from the code is loaded to the DAC register. V input to the DAC output when the DAC is loaded with all 0s. REF Zero-Code Temperature Coefficient A 100 kHz, 1 V p-p is applied to V . Reference feedthrough is REF This is a measure of the change in zero-code error with a expressed in mV p-p. change in temperature. It is expressed in mV/°C. Rev. A | Page 14 of 24 AD5512A/AD5542A THEORY OF OPERATION The AD5512A/AD5542A are single, 12-/16-bit, serial input, SERIAL INTERFACE voltage output DACs. They operate from a single supply The AD5512A/AD5542A are controlled by a versatile 3- or 4- ranging from 2.7 V to 5 V and consume typically 125 µA wire serial interface that operates at clock rates of up to 50 MHz with a supply of 5 V. Data is written to these devices in a and is compatible with SPI, QSPI, MICROWIRE, and DSP 12-bit (AD5512A) or 16-bit (AD5542A) word format, via a interface standards. The timing diagram is shown in Figure 3. 3- or 4-wire serial interface. To ensure a known power-up Input data is framed by the chip select input, CS. After a high- state, these parts are designed with a power-on reset function. to-low transition on CS, data is shifted synchronously and In unipolar mode, the output is reset to midscale; in bipolar latched into the input register on the rising edge of the serial mode, the output is set to 0 V. Kelvin sense connections for the clock, SCLK. Data is loaded MSB first in 12-bit (AD5512A) reference and analog ground are included on the AD5512A/ or 16-bit (AD5542A) words. After 12 (AD5512A) or 16 AD5542A. (AD5542A) data bits have been loaded into the serial input DIGITAL-TO-ANALOG SECTION register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can be loaded to the part The DAC architecture consists of two matched DAC sections. only while CS is low. A simplified circuit diagram is shown in Figure 30. The DAC architecture of the AD5512A/AD5542A is segmented. The four The AD5512A/AD5542A have an LDAC function that allows MSBs of the 16-bit (AD5542A)/12-bit (AD5512A) data-word LDAC the DAC latch to be updated asynchronously by bringing are decoded to drive 15 switches, E1 to E15. Each switch CS LDAC low after goes high. should be maintained high while connects one of 15 matched resistors to either AGND or V . REF LDAC data is written to the shift register. Alternatively, can be The remaining 12 bits of the data-word drive the S0 to S11 tied permanently low to update the DAC synchronously. With switches of a 12-bit voltage mode R-2R ladder network. LDAC tied permanently low, the rising edge of CS loads the data to R R V OUT the DAC. 2R 2R 2R . . . . . 2R 2R 2R . . . . . 2R UNIPOLAR OUTPUT OPERATION These DACs are capable of driving unbuffered loads of 60 kΩ. S0 S1 . . . . . S11 E1 E2 . . . . . E15 Unbuffered operation results in low supply current, typically V REF 300 μA, and a low offset error. The AD5512A/AD5542A provide a unipolar output swing ranging from 0 V to V . REF FOUR MSBs DECODED 12-BIT R-2R LADDER The AD5512A/AD5542A can be configured to output both INTO 15 EQUAL SEGMENTS unipolar and bipolar voltages. Figure 31 shows a typical Figure 30. DAC Architecture unipolar output voltage circuit. The code table for this With this type of DAC configuration, the output impedance mode of operation is shown in Table 9. is independent of code, while the input impedance seen by 5V 2.5V the reference is heavily code dependent. The output voltage is 10µF dependent on the reference voltage, as shown in the following 0.1µF 0.1µF equation: V × D SERIAL REF V = INTERFACE V REFF REFS DD OUT N AD820/ CS 2 OP196 UNIPOLAR DIN AD5512A/ V OUT OUTPUT where: SCLK AD5542A D is the decimal data-word loaded to the DAC register. EXTERNAL LDAC DGND AGNDF AGNDS OP AMP N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following: Figure 31. Unipolar Output 2.5× D Table 9. AD5542A Unipolar Code Table V = OUT 65,536 DAC Latch Contents MSB LSB Analog Output This gives a V of 1.25 V with midscale loaded, and 2.5 V OUT 1111 1111 1111 1111 V × (65,535/65,536) with full scale loaded to the DAC. REF 1000 0000 0000 0000 V × (32,768/65,536) = ½ V REF REF The LSB size is V /65,536. REF 0000 0000 0000 0001 V × (1/65,536) REF 0000 0000 0000 0000 0 V Rev. A | Page 15 of 24 09199-022 + 09199-023 AD5512A/AD5542A 2.5 V reference and the AD8628 low offset and zero-drift Assuming a perfect reference, the unipolar worst-case output reference buffer. voltage can be calculated from the following equation: Table 10. AD5542A Bipolar Code Table D V = ×(V + V )+ V + INL OUT−UNI N REF GE ZSE 2 DAC Latch Contents MSB LSB Analog Output where: 1111 1111 1111 1111 +V × (32,767/32,768) REF V is the unipolar mode worst-case output. OUT−UNI 1000 0000 0000 0001 +V × (1/32,768) D is the code loaded to DAC. REF 1000 0000 0000 0000 0 V N is the resolution of the DAC. 0111 1111 1111 1111 −V × (1/32,768) V is the reference voltage applied to the part. REF REF 0000 0000 0000 0000 −V × (32,768/32,768) = −V REF REF V is the gain error in volts. GE V is the zero-scale error in volts. ZSE Assuming a perfect reference, the worst-case bipolar output INL is the integral nonlinearity in volts. voltage can be calculated from the following equation: BIPOLAR OUTPUT OPERATION [(V + V )(2+ RD)− V (1+ RD)] OUT−UNI OS REF V = With the aid of an external op amp, the AD5512A/AD5542A OUT−BIP 1+ (2+ RD) can be configured to provide a bipolar voltage output. A typical A circuit is shown in Figure 32. The matched bipolar offset resistors, where: R and R , are connected to an external op amp to achieve FB INV V is the bipolar mode worst-case output OUT−BIP this bipolar output swing, typically R = R = 28 kΩ. Table 10 FB INV V is the unipolar mode worst-case output. OUT−UNI shows the transfer function for this output operating mode. V is the external op amp input offset voltage. OS Also provided on the AD5542A are a set of Kelvin connections RD is the R and R resistor matching error. FB INV to the analog ground inputs. The example includes the ADR421 A is the op amp open-loop gain. +5V +2.5V 10µF 0.1µF 0.1µF R +5V FB SERIAL V REFF REFS DD INTERFACE R FB CS INV DIN R INV BIPOLAR V OUT AD5512A/ OUTPUT SCLK AD5542A LDAC –5V DGND AGNDF AGNDS EXTERNAL OP AMP Figure 32. Bipolar Output Rev. A | Page 16 of 24 + 09199-024 AD5512A/AD5542A REFERENCE AND GROUND OUTPUT AMPLIFIER SELECTION Because the input impedance is code-dependent, the refer- For bipolar mode, a precision amplifier should be used and ence pin should be driven from a low impedance source. The supplied from a dual power supply. This provides the ±V REF AD5512A/AD5542A operate with a voltage reference ranging output. In a single-supply application, selection of a suitable op from 2 V to V . References below 2 V result in reduced accuracy. DD amp may be more difficult because the output swing of the ampli- The full-scale output voltage of the DAC is determined by the fier does not usually include the negative rail, in this case, reference. Table 9 and Table 10 outline the analog output voltage AGND. This can result in some degradation of the specified or particular digital codes. For optimum performance, Kelvin performance unless the application does not use codes near zero. sense connections are provided on the AD5512A/AD5542A. The selected op amp must have a very low-offset voltage (the If the application doesn’t require separate force and sense lines, DAC LSB is 38 μV for the AD5542A with a 2.5 V reference) tie the lines close to the package to minimize voltage drops to eliminate the need for output offset trims. Input bias current between the package leads and the internal die. should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 kΩ), adds to the POWER-ON RESET zero-code error. Rail-to-rail input and output performance is The AD5512A/AD5542A have a power-on reset function to required. For fast settling, the slew rate of the op amp should ensure that the output is at a known state on power-up. On not impede the settling time of the DAC. Output impedance power-up, the DAC register contains all 0s until the data is of the DAC is constant and code-independent, but to minimize loaded from the serial register. However, the serial register is gain errors, the input impedance of the output amplifier should not cleared on power-up; therefore, its contents are undefined. be as high as possible. The amplifier should also have a 3 dB When loading data initially to the DAC, 16 bits or more should bandwidth of 1 MHz or greater. The amplifier adds another be loaded to prevent erroneous data appearing on the output. time constant to the system, thus increasing the settling time If more than 16 bits are loaded, the last 16 are kept, and if less of the output. A higher 3 dB amplifier bandwidth results in a than 16 bits are loaded, bits remain from the previous word. shorter effective settling time of the combined DAC and amplifier. If the AD5512A/AD5542A must be interfaced with data shorter FORCE SENSE AMPLIFIER SELECTION than 16 bits, the data should be padded with 0s at the LSBs. Use single-supply, low-noise amplifiers. A low-output impedance POWER SUPPLY AND REFERENCE BYPASSING at high frequencies is preferred because the amplifiers must be For accurate high-resolution performance, it is recommended able to handle dynamic currents of up to ±20 mA. that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor. Rev. A | Page 17 of 24 AD5512A/AD5542A APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5512A/AD5542A TO 68HC11/68L11 INTERFACE Microprocessor interfacing to the AD5512A/AD5542A is via Figure 35 shows a serial interface between the AD5512A/ a serial bus that uses standard protocol that is compatible with AD5542A and the 68HC11/68L11 microcontroller. SCK of DSP processors and microcontrollers. The communications the 68HC11/68L11 drives the SCLK of the DAC, and the channel requires a 3- or 4-wire interface consisting of a clock MOSI output drives the serial data line serial DIN. The CS signal, a data signal, and a synchronization signal. The signal is driven from one of the port lines. The 68HC11/68L11 is AD5512A/AD5542A require a 16-bit data-word with data configured for master mode: MSTR = 1, CPOL = 0, and CPHA = valid on the rising edge of SCLK. The DAC update can be 0. Data appearing on the MOSI output is valid on the rising done automatically when all the data is clocked in, or it can edge of SCK. LDAC be done under the control of the . PC6 LDAC AD5512A/AD5542A TO ADSP-BF531 INTERFACE 68HC11/ PC7 CS AD5512A/ 68L11* MOSI DIN AD5542A* The SPI interface of the AD5512A/AD5542A is designed to be SCK SCLK easily connected to industry-standard DSPs and micro- controllers. Figure 33 shows how the AD5512A/AD5542A *ADDITIONAL PINS OMITTED FOR CLARITY. can be connected to the Analog Devices, Inc., Blackfin® DSP. Figure 35. AD5512A/AD5542A to 68HC11/68L11 Interface The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5512A/AD5542A. AD5512A/AD5542A TO ADSP-2101 INTERFACE Figure 36 shows a serial interface between the AD5512A/ AD5512A/ AD5542A AD5542A and the ADSP-2101. The ADSP-2101 should be SPISELx CS set to operate in the SPORT transmit alternate framing mode. SCK SCLK The ADSP-2101 is programmed through the SPORT control MOSI DIN register and should be configured as follows: internal clock ADSP-BF531 operation, active low framing, 16-bit word length. Transmission PF9 LDAC is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out on each rising edge Figure 33. AD5512A/AD5542A to ADSP-BF531 Interface of the serial clock, an inverter is required between the DSP and the DAC, because the AD5512A/AD5542A clock data in on the AD5512A/AD5542A TO SPORT INTERFACE falling edge of the SCLK. The Analog Devices ADSP-BF527 has one SPORT serial port. FO LDAC Figure 34 shows how one SPORT interface can be used to TFS CS control the AD5512A/AD5542A. AD5512A/ ADSP-2101 DT DIN AD5542A* AD5512A/ SCLK SCLK SPORT_TFS CS AD5542A SPORT_TSCK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. SPORT_DTO DIN Figure 36. AD5512A/AD5542A to ADSP-2101 Interface AD5512A/AD5542A TO MICROWIRE INTERFACE ADSP-BF527 GPIO0 LDAC Figure 37 shows an interface between the AD5512A/AD5542A and any MICROWIRE-compatible device. Serial data is shifted Figure 34. AD5512A/AD5542A to ADSP-BF527 Interface out on the falling edge of the serial clock and into the AD5512A/ AD5542A on the rising edge of the serial clock. No glue logic is required because the DAC clocks data into the input shift register on the rising edge. CS CS AD5512A/ MICROWIRE* SO DIN AD5542A* SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. AD5512A/AD5542A to MICROWIRE Interface Rev. A | Page 18 of 24 09919-045 09199-044 09199-025 09199-026 09199-027 AD5512A/AD5542A LAYOUT GUIDELINES DECODING MULTIPLE DACS In any circuit where accuracy is important, careful consider- The CS pin of the AD5512A/AD5542A can be used to select ation of the power supply and ground return layout helps to one of a number of DACs. All devices receive the same serial ensure the rated performance. Design the printed circuit board CS clock and serial data, but only one device receives the signal (PCB) on which the AD5512A/AD5542A is mounted so that at any one time. The DAC addressed is determined by the the analog and digital sections are separated and confined to decoder. There is some digital feedthrough from the digital certain areas of the board. If the AD5512A/AD5542A are in a input lines. Using a burst clock minimizes the effects of digital system where multiple devices require an analog ground-to- feedthrough on the analog signal channels. Figure 39 shows a digital ground connection, make the connection at one point typical circuit. only. Establish the star ground point as close as possible to the AD5512A/ SCLK device. AD5542A CS V OUT The AD5512A/AD5542A should have ample supply bypassing DIN DIN V DD of 10 μF in parallel with 0.1 μF on each supply located as close SCLK to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF ENABLE EN AD5512A/ AD5542A CS capacitor should have low effective series resistance (ESR) CODED V DECODER OUT ADDRESS DIN and low effective series inductance (ESI), such as the common SCLK ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal DGND AD5512A/ logic switching. AD5542A CS V OUT GALVANICALLY ISOLATED INTERFACE DIN SCLK In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being AD5512A/ controlled to protect and isolate the controlling circuitry AD5542A CS from any hazardous common-mode voltages that may occur. V OUT DIN iCoupler® products from Analog Devices provide voltage SCLK isolation in excess of 2.5 kV. The serial loading structure Figure 39. Addressing Multiple DACs of the AD5512A/AD5542A makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 38 shows a 4-channel isolated interface to the AD5512A/AD5542A using an ADuM1400. For further information, visit http://www.analog.com/icouplers. CONTROLLER 1 ADuM1400 V V IA OA TO SERIAL ENCODE DECODE SCLK CLOCK IN V V IB OB TO SERIAL ENCODE DECODE DATA OUT DIN V V IC OC TO SYNC OUT ENCODE DECODE CS V V ID OD LOAD DAC TO ENCODE DECODE OUT LDAC 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. Isolated Interface Rev. A | Page 19 of 24 09199-046 09199-030 AD5512A/AD5542A OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 2.90 PIN 1 0.18 INDICATOR 13 16 0.50 12 1 BSC EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 8 5 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 40. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. A | Page 20 of 24 PIN 1 INDICATOR 08-16-2010-E AD5512A/AD5542A 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Temperature Power On 1 Model INL DNL Range Package Description Package Option Branding Reset to Code AD5512AACPZ-REEL7 ±1 LSB ±1 LSB Midscale −40°C to +125°C 16-Lead LFCSP CP-16-22 DFQ AD5512AACPZ-500RL7 ±1 LSB ±1 LSB Midscale −40°C to +125°C 16-Lead LFCSP CP-16-22 DFQ AD5542ABRUZ ±1 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead TSSOP RU-16 AD5542ABRUZ-REEL7 ±1 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead TSSOP RU-16 AD5542AARUZ ±2 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead TSSOP RU-16 AD5542AARUZ-REEL7 ±2 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead TSSOP RU-16 AD5542ABCPZ-REEL7 ±1 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead LFCSP_WQ CP-16-22 DFL AD5542AACPZ-REEL7 ±2 LSB ±1 LSB Midscale −40°C to +85°C 16-Lead LFCSP_WQ CP-16-22 DFK AD5442ABCPZ-1-RL7 ±1 LSB ±1 LSB Midscale −40°C to +85°C 10-Lead LFCSP_WQ CP-10-9 DFM AD5542ABCPZ-500RL7 ±1 LSB ±1 LSB Midscale −40°C to +125°C 16-Lead LFCSP CP-16-22 DFL EVAL-AD5542ASDZ AD5541A Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 21 of 24 PIN 1 INDICATOR (R 0.15) 121009-A AD5512A/AD5542A NOTES Rev. A | Page 22 of 24 AD5512A/AD5542A NOTES Rev. A | Page 23 of 24 AD5512A/AD5542A NOTES ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09199-0-5/11(A) Rev. A | Page 24 of 24