ANALOG DEVICES AD5535

32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V AD5535 FEATURES GENERAL DESCRIPTION High integration The AD5535 is a 32-channel, 14-bit DAC with an on-chip high 32-channel, 14-bit DAC with integrated high voltage voltage output amplifier. This device is targeted for optical output amplifier micro-electromechanical systems. The output voltage range is Guaranteed monotonic programmable via the REF_IN pin. The output range is 0 V to Housed in 15 mm × 15 mm CSP_BGA package 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Full-scale output voltage Each amplifier can source 700 μA, which is ideal for the Programmable from 50 V to 200 V via reference input deflection and control of optical MEMS mirrors. 700 μA drive capability Integrated silicon diode for temperature monitoring The selected DAC register is written to via the 3-wire interface. DSP-/microcontroller-compatible serial interface The serial interface operates at clock rates of up to 30 MHz and 1.2 MHz channel update rate is compatible with DSP and microcontroller interface standards. Asynchronous RESET facility The device is operated with AVCC = 4.75 V to 5.25 V, DVCC = –10°C to +85°C temperature range 2.7 V to 5.25 V, V− = −4.75 V to −5.25 V, V+ = 4.75 V to 5.25 V, and VPP = 210 V. REF_IN is buffered internally on the AD5535 APPLICATIONS and should be driven from a stable reference source. Optical micro-electromechanical systems (MEMS) Optical crosspoint switches Micropositioning applications using piezoelectric actuators Level setting in automotive test and measurement FUNCTIONAL BLOCK DIAGRAM DV REF_IN AV V PGND V V CC CC – PP + ANODE RESET AD5535 CATHODE DAC R1 V 0 OUT RF 14-BIT BUS DAC R1 V 1 OUT DAC_GND RF DAC R1 V 30 OUT AGND RF DAC R1 V 31 OUT INTERFACE CONTROL RF DGND LOGIC SCLK D SYNC IN Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. 05068-001 AD5535 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 12 Applications....................................................................................... 1 Serial Interface ............................................................................ 12 General Description ......................................................................... 1 Microprocessor Interfacing....................................................... 12 Functional Block Diagram .............................................................. 1 Applications..................................................................................... 14 Specifications..................................................................................... 3 MEMS Mirror Control Application......................................... 14 Timing Characteristics ................................................................ 5 IPC-221-Compliant Board Layout........................................... 14 Absolute Maximum Ratings............................................................ 6 Power Supply Sequencing and Decoupling Recommendations...................................................................... 15 ESD Caution.................................................................................. 6 Guidelines for Printed Circuit Board Layout ......................... 15 Pin Configuration and Function Descriptions............................. 7 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 16 Terminology .................................................................................... 11 Functional Description .................................................................. 12 DAC Section................................................................................ 12 REVISION HISTORY 8/05—Rev. 0 to Rev. A Changes to Table 3............................................................................ 6 Changes to Ordering Guide .......................................................... 16 5/05—Revision 0: Initial Version Rev. A | Page 2 of 16 AD5535 SPECIFICATIONS VPP = 210 V, V− = −5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V; all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 A Grade 1 Parameter Unit Conditions/Comments Min Typ Max 3 DC PERFORMANCE Resolution 14 Bits Integral Nonlinearity (INL) ±0.1 % of FSR Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Guaranteed monotonic Zero-Code Voltage 1 2.5 V Output Offset Error –2 +2 V Offset Drift 0.02 mV/°C Voltage Gain 47.5 50 52.5 V/V Gain Temperature Coefficient 5 ppm/°C 4 Channel-to-Channel Gain Match –5 +5 % Full-Scale Voltage Drift 3 ppm/°C OUTPUT CHARACTERISTICS 3 Output Voltage Range 2.5 VPP − 10 V Output Impedance 50 Ω 4, 5 Resistive Load 1 MΩ 4 Capacitive Load 200 pF Short-Circuit Current 0.7 mA 4 DC Crosstalk 3 LSB DC Power Supply Rejection (PSRR), VPP 70 dB 4 AC CHARACTERISTICS Settling Time ¼ to ¾ Scale Step 30 μs No load 65 μs 200 pF load 1 LSB Step 10 μs No load 10 μs 200 pF load Slew Rate 10 V/μs No load 3 V/μs 200 pF load –3 dB Bandwidth 5 kHz Output Noise Spectral Density 4.5 μV/√Hz Measured at 10 kHz 0.1 Hz to 10 Hz Output Noise Voltage 1 mV p-p Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Analog Crosstalk 13 μV-s Digital Feedthrough 1 nV-s 6 VOLTAGE REFERENCE, REF_IN AVCC must exceed REF_IN by 1.15 V min 4 Input Voltage Range 1 4.096 V Input Current 1.25 μA 4 TEMPERATURE MEASUREMENT DIODE Peak Inverse Voltage, P 5 V Cathode to anode IV Forward Diode Drop, VF 0.65 0.8 V IF = 100 μA, anode to cathode Forward Diode Current, I 100 μA Anode to cathode F V Temperature Coefficient, T −2.20 mV/°C Anode to cathode F C Rev. A | Page 3 of 16 AD5535 2 A Grade 1 Parameter Unit Conditions/Comments Min Typ Max 4 DIGITAL INPUTS Input Current ±5 ±10 μA Input Low Voltage 0.8 V Input High Voltage 2.0 V Input Hysteresis (SCLK and SYNC Only) 200 mV Input Capacitance 10 pF 7 POWER SUPPLY VOLTAGES V (50 × REF_IN) + 10 225 V PP V –5.25 –4.75 V – V 4.75 5.25 V + AVCC 4.75 5.25 V DVCC 2.7 5.25 V 7 POWER SUPPLY CURRENTS IPP 75 100 μA/channel I− 2.3 3.5 mA I 0.5 1 mA + AI 15 18 mA CC DI 0.25 0.5 mA CC 7 POWER DISSIPATION 594 mW 1 See the Terminology section. 2 A Grade temperature range: −10°C to +85°C; typical = +25°C. 3 Linear output voltage range: +7 V to VPP − 10 V. 4 Guaranteed by design and characterization, not production tested. 5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section. 6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to V − 10 V. PP 7 Outputs unloaded. Rev. A | Page 4 of 16 AD5535 TIMING CHARACTERISTICS VPP = 210 V, V− = –5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1, 2, 3 Parameter A Grade Unit Conditions/Comments fUPDATE 1.2 MHz max Channel Update Rate fCLKIN 30 MHz max SCLK Frequency t1 13 ns min SCLK High Pulse Width t 13 ns min SCLK Low Pulse Width 2 t 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 3 t4 50 ns min SYNC Low Time t5 10 ns min SYNC High Time t6 10 ns min DIN Setup Time t 5 ns min D Hold Time 7 IN th t 200 ns min 19 SCLK Falling Edge to SYNC Falling Edge for Next Write 8 t 20 ns min RESET Pulse Width 9 1 See Figure 2. 2 Guaranteed by design and characterization, not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of (V + V )/2. CC IL IH t 1 SCLK 1 23 4 5 16 17 18 19 1 t 3 t 2 t 5 SYNC t t t 4 6 8 t 7 D IN MSB LSB RESET t 9 Figure 2. Serial Interface Timing Diagram Rev. A | Page 5 of 16 05068-002 AD5535 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND 0.3 V to 250 V PP rating only; functional operation of the device at these or any V to AGND +0.3 V to −6 V − other conditions above those indicated in the operational V+ to AGND −0.3 V to +7 V section of this specification is not implied. Exposure to absolute AVCC to AGND, DAC_GND −0.3 V to +7 V maximum rating conditions for extended periods may affect DVCC to DGND −0.3 V to +7 V device reliability. Digital Inputs to DGND −0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_GND −0.3 V to AVCC + 0.3 V Transient currents up to 100 mA do not cause SCR latch-up. V (0 to 31) to AGND V– to V OUT PP This device is an integrated high voltage circuit with an ESD Anode/Cathode to AGND, DAC_GND −0.3 V to +7 V rating of <2 kV, and it is ESD sensitive. Proper precautions AGND to DGND −0.3 V to +0.3 V should be taken for handling and assembly. Operating Temperature Range Industrial −10°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 124-Lead CSP_BGA Package, 40°C/W θJA Thermal Impedance Lead Temperature Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Reflow Soldering (Pb-free) Peak Temperature 260(0/−5)°C Time at Peak Temperature 10 sec to 40 sec ESD (Human Body Model) 450 V ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 16 AD5535 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A A B B C C D D E E F F G G H H J J K K L L M M N N P P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure 3. Pin Configuration Table 4. 124-Lead CSP-BGA Ball Configuration CSP_BGA CSP_BGA CSP_BGA CSP_BGA No. Ball Name No. Ball Name No. Ball Name No. Ball Name A1 NC C14 V 29 H2 V N2 PGND OUT PP A2 V 1 H4 to H11 AGND N3 CATHODE OUT D1 V 2 OUT A4 V 7 H13 V 27 N4 ANODE OUT D13 V 23 OUT OUT A6 VOUT11 E2 V 5 J3 to J12 AGND N5 to N14 AGND OUT A8 VOUT16 K1 V+ P1 NC E4 VOUT8 A10 VOUT20 K2 V+ P2 REF_IN E6 VOUT12 A12 V 25 K3 to K14 AGND P3 DAC_GND OUT E8 V 15 OUT A14 NC L1 V P4 RESET E10 V 19 – OUT B1 V 0 L2 V OUT E12 V 24 – OUT P5 DVCC B3 VOUT4 L3 to L13 AGND E14 VOUT31 P6 DGND B5 VOUT9 L14 DAC_GND F3 VOUT6 P7 TEST B7 V 13 M1 AGND OUT F5 VOUT10 P8 D IN B9 V 17 M2 AGND OUT F7 V 14 P9 SCLK OUT B11 V 21 M3 to M12 AGND OUT F9 V 18 P10 SYNC OUT B13 VOUT26 F13 V 30 M13 AVCC OUT P11 to P13 AGND C2 VOUT3 M14 AVCC G14 VOUT28 P14 NC C12 VOUT22 N1 PGND H1 VPP Rev. A | Page 7 of 16 05068-003 AD5535 Table 5. Pin Function Descriptions Mnemonic Description AGND Analog GND Pins. AVCC Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. V Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 10 V to 225 V. PP V V Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V. + + V V Amplifier Supply Pins. Voltage range from −4.75 V to −5.25 V. – – PGND Output Amplifier Ground Reference Pins. DGND Digital GND Pins. DVCC Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. DAC_GND Reference GND Supply for All DACs. REF_IN Reference Voltage for Channel 0 to Channel 31. Reference input range is 1 V to 4 V and can be used to program the full- scale output voltage from 50 V to 200 V. VOUT0 to VOUT31 Analog Output Voltages from the 32 Channels. ANODE Anode of Internal Diode for Diode Temperature Measurement. CATHODE Cathode of Internal Diode for Diode Temperature Measurement. SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in upon the falling edge of SCLK. 1 SCLK Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. 1 DIN Serial Data Input. Data must be valid upon the falling edge of SCLK. TEST Allows the same data to be simultaneously loaded to all channels of the AD5535. This pin is used for calibration purposes when loading zero scale and full scale to all channels. To invoke this feature, bring the TEST pin high. In normal operation, TEST should be tied low. 1 RESET Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is loaded to the DACs. NC No connect pins. The user should not connect any signals to these pins. 1 Internal pull-up device on logic input; therefore, it can be left floating and defaults to a logic high condition. Rev. A | Page 8 of 16 AD5535 TYPICAL PERFORMANCE CHARACTERISTICS 16 1.00 V = 60V V = 210V PP PP V = –5V V = –5V 12 – 0.75 – V = AV = +5V V = AV = +5.25V + CC + CC REF_IN = 1V REF_IN = 4.096V 8 0.50 T = 25°C T = 25°C A A 4 0.25 0 0 –4 –0.25 –8 –0.50 –12 –0.75 –16 –1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 INPUT CODE INPUT CODE Figure 4. Integral Linearity with Full-Scale Range = 50 V Figure 7. Differential Nonlinearity with Full-Scale Range = 200 V 1.00 1.00 V = 60V PP CHANNEL 2 CHANNEL 1 V = –5V – 0.75 0.75 V = AV = +5V + CC 10kΩ REF_IN = 1V DAC AMP 0.50 T = 25°C 0.50 A 0.25 0.25 0 0 CHANNEL 2 –0.25 –0.25 –0.50 –0.50 T CHANNEL 1 –0.75 –0.75 –1.00 –1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 0CH1 5V 2048 4096 CH2 5V 6144 8192 M 500ns 10240 12288 CH1 21.6V 14336 16384 INPUT CODE INPUT CODE Figure 5. Differential Nonlinearity with Full-Scale Range = 50 V Figure 8. Short-Circuit Current Limit Timing 16 1.00 T V = 210V PP V = –5V 12 – 0.75 V = AV = +5.25V + CC REF_IN = 4.096V 8 0.50 T = 25°C A CHANNEL 2 AREA 11μVs 4 0.25 0 0 2 V = 210V –4 PP –0.25 V = –5V – V = AV = +5.25V + CC –8 –0.50 1 REF_IN = 4.096V V = 100V OUT T = 25°C A –12 –0.75 CHANNEL 1: CHANNEL OUTPUT SLEW CHANNEL 2: AC CROSSTALK –16 –1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 0CH1 50V 2048 4096 CH2 6144 200mV 8192 10240 M 1012288 μs 14336 CH116384 INPUT CODE INPUT CODE Figure 6. Integral Linearity with Full-Scale Range = 200 V Figure 9. Worst-Case Adjacent Channel Crosstalk Rev. A | Page 9 of 16 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 05068-020 05068-019 05068-018 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 05068-009 05068-008 05068-021 AD5535 0.04 140 V = 210V PP V = –5V – 0.03 V = AV = +5.25V + CC 120 REF_IN = 4.096V T = 25°C 0.02 A 100 0.01 80 0 60 –0.01 V = 210V PP 40 V = –5V – –0.02 V = AV = +5.25V + CC VICTIM CHANNEL = 31 REF_IN = 4.096V 20 V 31 = MIDSCALE V = 70V OUT OUT –0.03 FULL-SCALE TRANSITION ON T = 25°C A OTHER CHANNELS IN SEQUENCE. 0 –0.04 –5 –4 –3 –2 –1 0 1 2 03 5 101520 250 SOURCE/SINK CURRENT (mA) CHANNEL NUMBER Figure 10. Output Amplifier Source and Sink Capability Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output, Switching All Other Channels in Sequence 12.0 180 V = 210V PP 0pF V = –5V – 11.5 160 V = AV = +5.25V + CC REF_IN = 4.096V 140 11.0 100pF 120 10.5 100 10.0 200pF 80 9.5 V = 210V 60 PP V = –5V – 9.0 V = AV = +5.25V + CC 40 REF_IN = 4.096V 8.5 T = 25°C A 20 1/4 FULL-SCALE TO 3/4 FULL-SCALE STEP 8.0 0 –10 0 1020304050607080 0 0.02 0.04 0.06 0.08 0.10 TEMPERATURE (°C) TIME (ms) Figure 11. Offset Error vs. Temperature Figure 14. Settling Time vs. Capacitive Load –1.0 1.00 V = 210V PP 0.75 V = –5V – V = AV = +5.25V + CC –1.1 REF_IN = 4.096V 0.50 0.25 –1.2 20 –1.3 –0.25 V = 210V PP –0.50 CHANNEL 2 V = –5V – 6.88mV p-p –1.4 V = AV = +5.25V + CC REF_IN = 4.096V –0.75 CHANNEL 2 RMS V = 100V OUT 1.02mV T = 25°C A –1.5 –1.00 –10 0 1020304050607080 CH2 200mV M 1s CH1 300mV 0 2048 4096 6144 8192 10240 12288 14336 16384 TEMPERATURE (°C) INPUT CODE Figure 12. Gain Error vs. Temperature Figure 15. Wideband Noise Rev. A | Page 10 of 16 GAIN ERROR (%) OFFSET ERROR (mV) OUTPUT VOLTAGE (V) 05068-029 05068-028 05068-022 OUTPUT VOLTAGE (V) DC CROSSTALK (V) DNL ERROR (LSB) 05068-027 05068-026 05068-025 AD5535 TERMINOLOGY Integral Nonlinearity (INL) DC Crosstalk A measure of the maximum deviation from a straight line The dc change in the output level of one DAC at midscale in passing through the endpoints of the DAC transfer function. response to a full-scale code change (all 0s to all 1s and vice It is expressed as a percentage of full-scale range. versa) and the output change of all other DACs. It is expressed in LSB. Differential Nonlinearity (DNL) The difference between the measured change and the ideal Output Voltage Settling Time 1 LSB change between any two adjacent codes. A specified The time taken from when the last data bit is clocked into the DNL of ±1 LSB maximum ensures monotonicity. DAC until the output has settled to within ±0.5 LSB of its final value. Measured for a step change of ¼ to ¾ full scale. Zero-Code Voltage A measure of the output voltage present at the device output Digital-to-Analog Glitch Impulse with all 0s loaded to the DAC. It includes the offset of the The area of the glitch injected into the analog output when DAC and the output amplifier and is expressed in V. the code in the DAC register changes state. It is specified as the area of the glitch in nV-s when the digital code is changed Offset Error by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 Calculated by taking two points in the linear region of the or 100 . . . 00 to 011 . . . 11). transfer function, drawing a line through these points, and extrapolating back to the y-axis. It is expressed in V. Analog Crosstalk The area of the glitch transferred to the output (VOUT) of one Voltage Gain DAC due to a full-scale change in the output (VOUT) of another Calculated from the change in output voltage for a change in DAC. The area of the glitch is expressed in nV-s. code, multiplied by 16,384, and divided by the REF_IN voltage. This is calculated between two points in the linear section of the Digital Feedthrough transfer function. A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to Gain Error ( is high). It is specified in nV-s and measured with a SYNC A measure of the output error with all 1s loaded to the DAC, worst-case change on the digital input pins, for example, from and the difference between the ideal and actual analog output all 0s to all 1s and vice versa. range. Ideally, the output should be 50 × REF_IN. It is expressed Output Noise Spectral Density as a percentage of full-scale range. A measure of internally generated random noise. Random noise DC Power Supply Rejection Ratio (PSRR) is characterized as a spectral density (voltage per √Hz). It is A measure of the change in analog output for a change in V PP measured by loading all DACs to midscale and measuring noise supply voltage. It is expressed in dB, and V is varied ±5%. PP at the output. It is measured in nV/√Hz. Rev. A | Page 11 of 16 AD5535 FUNCTIONAL DESCRIPTION A4 to A0 Bits The AD5535 consists of a 32 channel, 14-bit DAC with 200 V high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA These bits can address any one of the 32 channels. A4 is the package. The output voltage range is programmable via the MSB of the address; A0 is the LSB. REF_IN pin. The output range is 0 V to 50 V when REF_IN = DB13 to DB0 Bits 1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to the device is through a serial interface operating at clock These bits are used to write a 14-bit word into the addressed rates of up to 30 MHz, which is compatible with DSP and DAC register. microcontroller interface standards. A 5-bit address and a Figure 2 is the timing diagram for a serial write to the AD5535. 14-bit data-word are loaded into the AD5535 input register The serial interface works with both a continuous and a discon- via the serial interface. The channel address is decoded, and tinuous serial clock. The first falling edge of SYNC resets the the data-word is converted into an analog output voltage for serial clock counter to ensure that the correct number of bits are this channel. shifted into the serial shift register. Any further edges on SYNC At power-on, all the DAC registers are loaded with 0s. are ignored until the correct number of bits are shifted in. Once 19 bits have been shifted in, the SCLK is ignored. For another DAC SECTION serial transfer to take place, the counter must be reset by the The architecture of each DAC channel consists of a resistor falling edge of SYNC. The user must allow 200 ns (minimum) string DAC, followed by an output buffer amplifier operating between successive writes. with a nominal gain of 50. The voltage at the REF_IN pin LSB MSB provides the reference voltage for the corresponding DAC. The A4 A3 A2 A1 A0 DB13–DB0 input coding to the DAC is straight binary, and the ideal DAC Figure 16. Serial Data Format output voltage is given by 50×V × D REF _ IN MICROPROCESSOR INTERFACING V = OUT 14 2 AD5535-to-ADSP-21xx Interface where D is the decimal equivalent (0 to 16,383) of the binary The ADSP-21xx family of DSPs is easily interfaced to the code, which is loaded to the DAC register. AD5535 without the need for extra logic. A data transfer is initiated by writing a word to the TX register after SPORT is The output buffer amplifier is specified to drive a load of 1 MΩ enabled. In a write sequence, data is clocked out upon each and 200 pF. The linear output voltage range for the output rising edge of the DSP’s serial clock and clocked into the amplifier is from 7 V to V − 10 V. The amplifier output band- PP AD5535 upon the falling edge of its SCLK. The easiest way to width is typically 5 kHz, and is capable of sourcing 700 μA and provide the 19-bit data-word required by the AD5535 is to sinking 2.8 mA. Settling time for a ¼ to ¾ full-scale step change transmit two 10-bit data-words from the ADSP-21xx. Ensure is typically 30 μs with no load and 65 μs with a 200 pF load. that the data is positioned correctly in the TX register so that the first 19 bits transmitted contain valid data. RESET FUNCTION The reset function on the AD5535 can be used to reset all nodes Set up the SPORT control register as shown in Table 6. on the device to their power-on reset condition. All the DACs Table 6. are loaded with 0s, and all registers are cleared. The reset Name Value Description function is implemented by taking the RESET pin low. TFSW 1 Alternate framing INVTFS 1 Active low frame signal SERIAL INTERFACE DTYPE 00 Right justify data The serial interface is controlled by three pins: ISCLK 1 Internal serial clock TFSR 1 Frame every word • SYNC is the frame synchronization pin for the serial interface. ITFS 1 Internal framing signal • SCLK is the serial clock input. This pin operates at clock SLEN 1001 10-bit data-word speeds of up to 30 MHz. • D is the serial data input. Data must be valid upon the IN falling edge of SCLK. To update a single DAC channel, a 19-bit data-word is written to the AD5535 input register. Rev. A | Page 12 of 16 05068-010 AD5535 Figure 17 shows the connection diagram. AD5535-to-PIC16C6x/7x Interface The PIC16C6x/7x synchronous serial port (SSP) is configured ADSP-2101/ AD5535* ADSP-2103* as an SPI master with the clock polarity bit = 0. This is done SCLK SCLK by writing to the synchronous serial port control register D DT IN (SSPCON). See the PIC16/17 Microcontroller User Manual. TFS SYNC In this example, I/O port RA1 is being used to pulse SYNC *ADDITIONAL PINS OMITTED FOR CLARITY and enable the serial port of the AD5535. This microcontroller transfers only eight bits of data during each serial transfer Figure 17. AD5535-to-ADSP-2101/ADSP-2103 Interface operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB AD5535-to-MC68HC11 Interface first. It is important to left justify the data in the SPDR register The serial peripheral interface (SPI) on the MC68HC11 is so that the first 19 bits transmitted contain valid data. RA1 must configured for master mode (MSTR = 1), clock polarity bit be pulled low to start a transfer. It must be brought high and (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is pulled low again before any further write cycles can take place. configured by writing to the SPI control register (SPCR)—see Figure 19 shows the connection diagram. the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD5535 and the MOSI output drives the serial AD5535* PIC16C6x/7x* data line (DIN) of the AD5535. The SYNC signal is derived from SCLK SCK/RC3 a port line (PC7). When data is being transmitted to the D SDI/RC4 IN AD5535, the line is taken low (PC7). SYNC SYNC RA1 Data appearing on the MOSI output is valid on the falling edge *ADDITIONAL PINS OMITTED FOR CLARITY of SCK. The MC68HC11 transfers only eight bits of data during Figure 19. AD5535-to-PIC16C6x/7x Interface each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is AD5535-to-8051 Interface transmitted MSB first. It is important to left justify the data in The AD5535 requires a clock synchronized to the serial data. The the SPDR register so that the first 19 bits transmitted contain 8051 serial interface must therefore be operated in Mode 0. In valid data. PC7 must be pulled low to start a transfer. It is taken this mode, serial data exits the 8051 through R×D, and a shift high and pulled low again before any further write cycles can clock is output upon T×D. The SYNC signal is derived from a take place. See Figure 18. port line (P1.1). Figure 20 shows how the 8051 is connected to AD5535* MC68HC11* the AD5535. Because the AD5535 shifts data out upon the rising edge of the shift clock and latches data in upon the falling edge, SCK SCLK the shift clock must be inverted. Note also that the AD5535 D MOSI IN requires its data with the MSB first. Because the 8051 outputs the SYNC PC7 LSB first, the transmit routine must take this into account. *ADDITIONAL PINS OMITTED FOR CLARITY 8051* AD5535* Figure 18. AD5535-to-MC68HC11 Interface SCLK TxD RxD D IN SYNC P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. AD5535-to-8051 Interface Rev. A | Page 13 of 16 05068-012 05068-011 05068-014 05068-013 250μm RAD SPACE = 405μm 100μm SPACE = 405μm 250μm RAD AD5535 APPLICATIONS REF198 MEMS MIRROR CONTROL APPLICATION +5V +210V (4.096V) OUTPUT RANGE 0V TO 200V The AD5535 is targeted to all optical switching control systems V V REF_IN + PP based on MEMS technology. The AD5535 is a 32-channel, SENSOR 14-BIT DAC 8-CHANNEL 14-bit DAC with integrated high voltage amplifiers. The output + V 0 OUT ADC (AD7856) 4-TO-1 MUX ACTUATORS amplifiers are capable of generating an output range of 0 V to (ADG739) FOR OR MEMS 200 V when using a 4 V reference. The full-scale output voltage OR MIRROR V 31 OUT SINGLE- ARRAY 14-BIT DAC CHANNEL is programmable from 50 V to 200 V using reference voltages 32-TO-1 MUX ADC (AD7671) (ADG732) from 1 V to 4 V. Each amplifier can output 700 μA and directly AD5535 drives the control actuators, which determine the position of V – MEMS mirrors in optical switch applications. –5V ADSP-21065L The AD5535 is generally used in a closed-loop feedback system, Figure 21. AD5535 in a MEMS-Based Optical Switch as shown in Figure 21, with a high resolution ADC and DSP. The exact position of each mirror is measured using capacitive sensors. The sensor outputs are multiplexed using an ADG739 IPC-221-COMPLIANT BOARD LAYOUT 4:1 multiplexer to an 8-channel, 14-bit ADC (AD7856). An The diagram in Figure 22 is a typical 2-layer printed circuit board alternative solution is to multiplex using a 32-to-1 multiplexer layout for the AD5535 that complies with the specifications (ADG732) into a single-channel ADC (AD7671). The control outlined in IPC-221. No signals should be connected to the four loop is driven by an ADSP-21065L, a 32-bit SHARC® DSP with corner balls labeled as original no connects. Balls labeled as an SPI-compatible SPORT interface. With 14-bit monotonic additional no connects should be connected to AGND. behavior and 0 V to 200 V output range, coupled with its fast serial interface, the AD5535 is ideally suited for controlling a The routing shown in Figure 22 shows the feasibility of cluster of MEMS-based mirrors. connecting to the high voltage balls while complying with the spacing requirements of IPC-221. Figure 22 also shows the physical distances that are available. A1 BALL PAD CORNER 1 1 2 3 4 5 7 9 10 11 12 13 14 6 8 A 1.414mm B DETAIL A C D E F ORIGINAL NO CONNECTS G 250μm RAD H ADDITIONAL NO CONNECTS J SPACE = 433μm 100μm K 2mm SPACE = 433μm L 100μm M SPACE = 433μm 1 N 250μm RAD P 1 1 Figure 22. Layout Guidelines to Comply with IPC-221 Rev. A | Page 14 of 16 05068-016 05068-015 AD5535 Use as large a trace as possible for the supply lines of the device POWER SUPPLY SEQUENCING AND DECOUPLING to provide low impedance paths and reduce the effects of glitches RECOMMENDATIONS on the power supply line. Components, such as clocks with fast- The diagram in Figure 23 shows the recommended decoupling switching signals, should be shielded with digital ground to avoid and power supply protection for the AD5535. On the AD5535, radiating noise to other sections of the board. Clock signals it is recommended to tie all grounds together as close to the device should never be run near the analog inputs of the device. Avoid as possible. If the number of supplies must be reduced, all supplies crossovers of digital and analog signals. Traces for analog inputs should be brought back separately and a provision should be should be kept as wide and short as possible and should be made on the board via a link option to drive the AV and V CC + shielded with analog ground if possible. Traces on opposite from the same supply. All power supplies should be adequately sides of a 2-layer printed circuit board should run at right decoupled with 10 μF tantalum and 0.1 μF ceramic capacitors. angles to each other to reduce the effects of feedthrough Note that the capacitors on the V supply must be rated at PP through the board. greater than 210 V. To overcome issues associated with power supply sequencing when using high voltage supplies, the use of A microstrip technique is by far the best, but it is not always protection diodes as indicated in Figure 23 is recommended. possible to use with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, V = –5V V = +5V V = +210V – + PP and signals are placed on the solder side. Multilayer printed 10μF 10μF SCHOTTKY DIODE circuit boards with dedicated ground, power, and tracking MANUFACTURER: ITT HIGH VOLTAGE DIODE layers offer the optimum solution in terms of obtaining analog MANUFACTURER: GS 0.1μF 0.1μF performance, but at increased manufacturing costs. 0.1μF 10μF SD103C RS1G Good decoupling is vitally important when using high resolu- PGND V V V – + PP tion converters. All analog supplies should be decoupled with AGND 10 μF tantalum in parallel with 0.1 μF ceramic capacitors to AV AV = +5V CC CC DACGND 10μF analog ground. To achieve the best from the decoupling 0.1μF AD5535 components, these should be placed as close to the device as DGND possible, ideally right up against the IC or the IC socket. The DV DV = +5V CC CC 10μF main aim of a bypassing element is to maximize the charge 0.1μF stored in the bypass loop while simultaneously minimizing the Figure 23. Recommended Power Supply Sequencing and Decoupling inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close to the device GUIDELINES FOR PRINTED as possible, the loop area is kept as small as possible, thereby CIRCUIT BOARD LAYOUT reducing the possibility of power supply spikes. Digital supplies Printed circuit boards should be designed such that the analog of high resolution converters should be decoupled with 10 μF and digital sections are separated and confined to designated tantalum and 0.1 μF ceramic to the digital ground plane. The analog and digital sections of the board. This facilitates the use amplifiers’ VDD and VSS supplies should be decoupled with 10 μF of ground planes that can be separated easily. A minimum etch and 0.1 μF to AGND. technique is generally found to be the best for ground planes All logic chips should be decoupled with 0.1 μF to digital because it optimizes shielding of sensitive signal lines. Digital ground to decouple high frequency effects associated with and analog ground planes should be joined only in one place, at digital circuitry. the AGND and DGND pins of the high resolution converter. Data and address buses on the board should be buffered or latched to isolate the high frequency bus of the processor from the bus of the high resolution converters. These act as a faraday shield and increase the signal-to-noise performance of the converters by reducing the amount of high frequency digital coupling. Avoid running digital lines under the device because they couple noise onto the die. The ground plane should be allowed to run under the IC to avoid noise coupling. Rev. A | Page 15 of 16 05068-017 AD5535 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 15.00 BSC SQ 14 13 12 11 10 9 8 7 6 5 4 3 1 2 A B C D E F G TOP VIEW H J K L M N P 1.00 BSC BOTTOM VIEW DETAIL A 1.70 MAX * DETAIL A 1.25 MAX 0.85 MIN * 0.41 0.36 0.31 0.12 NOM SEATING COPLANARITY * 0.46 NOM PLANE BALL DIAMETER * COMPLIANT WITH JEDEC STANDARDS MO-192-AAE-1 WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK. NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm. Figure 24. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-124-2) Dimensions shown in millimeters ORDERING GUIDE Model Function Output Voltage Span Temperature Range Package Description Package Option AD5535ABC 32 DACs 0 V to 200 V maximum −10°C to +85°C 124-Lead CSP_BGA BC-124-2 1 AD5535ABCZ 32 DACs 0 V to 200 V maximum −10°C to +85°C 124-Lead CSP_BGA BC-124-2 EVAL-AD5535EB Evaluation Board 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05068-0-8/05(A) TTTT Rev. A | Page 16 of 16