ANALOG DEVICES AD5532HS

32-Channel 14-Bit DAC with a High-Speed 3-Wire Serial Interface AD5532HS FEATURES GENERAL DESCRIPTION 2 High Integration: 32-Channel DAC in 12 � 12 mm LFBGA The AD5532HS is a 32-channel voltage-output 14-bit DAC Guaranteed Monotonic with a high-speed serial interface. The selected DAC register is DSP-/Microcontroller-Compatible Serial Interface written to via the 3-wire interface. The serial interface operates Channel Update Rate 1.1 MHz at clock rates up to 30 MHz and is compatible with DSP and Output Impedance 0.5 � microcontroller interface standards. The output voltage range is Selectable Output Voltage 0 V to 5 V or –2.5 V to +2.5 V 0 V to 5 V or –2.5 V to +2.5 V and is determined by the offset Asynchronous RESET Facility voltage at the OFFS_IN pin. It is restricted to a range from Temperature Range –40�C to +85�C V + 2 V to V – 2 V because of the headroom of the out- SS DD put amplifier. APPLICATIONS The device is operated with AV = 5 V ± 5%, DV = 2.7 V CC CC Optical Networks to 5.25 V, V = –4.75 V to –12 V and V = +4.75 V to +12 V SS DD Level Setting and requires a stable 2.5 V reference on REF_IN. Instrumentation Automatic Test Equipment PRODUCT HIGHLIGHTS Industrial Control Systems 1. 32 14-bit DACs in one package, guaranteed monotonic. Data Acquisition Low Cost I/O 2. The AD5532HS is available in a 74-ball LFBGA package with a body size of 12 mm by 12 mm. FUNCTIONAL BLOCK DIAGRAM DV AV V V CC CC REF_IN OFFS_IN DD SS R AD5532HS R V 0 OUT DAC RESET R R DAC_GND V 1 OUT DAC AGND R R DGND V 30 OUT DAC R R INTERFACE CONTROL V 31 OUT LOGIC DAC SCLK D SYNC IN REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 14-BIT BUS AD5532HS–SPECIFICATIONS (V = +4.75 V to +12 V, V = –4.75 V to –12 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = DD SS CC CC 2.5 V; OFFS_IN = 0 V; All outputs unloaded. All specifications T to T unless otherwise noted.) MIN MAX 2 A Version 1 Parameter Min Typ Max Unit Conditions/Comments DAC DC PERFORMANCE Resolution 14 Bits Integral Nonlinearity (INL) –0.39 ±0.1 +0.39 % of FSR See TPC 7 Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Monotonic Offset Error –10 +15 +50 mV See TPC 8 Full-Scale Error –1 –0.3 +0.5 % of FSR See TPC 9 VOLTAGE REFERENCE REF_IN 3 Input Voltage Range 2.375 2.5 2.625 V Input Current ±0.001 ±1 µA ANALOG INPUT OFFS_IN 3, 4 0V – 1.5 V Input Voltage Range DD Input Current ±0.1 ±1 µA ANALOG OUTPUTS (V 0–V 31) OUT OUT 3, 5 Output Temperature Coefficient 20 ppm/°C 3 DC Output Impedance 0.5 Ω 4 Output Range OFFS_IN = 0 0 – 2REF_IN V OFFS_IN = REF_IN –REF_IN to +REF_IN V 3 Resistive Load 5kΩ 3 Capacitive Load 100 pF 3 Short-Circuit Current 7mA 3 DC Power-Supply Rejection Ratio –70 dB V = +10 V ± 5% DD –70 dB V = –10 V ± 5% SS 3 DC Crosstalk 120 µV 3 DIGITAL INPUTS Input Current ±5 ±10 µA Input Low Voltage 0.8 V DV = 5 V ± 5% CC 0.4 V DV = 3 V ± 10% CC Input High Voltage 2.4 V DV = 5 V ± 5% CC 2.0 V DV = 3 V ± 10% CC Input Hysteresis (SCLK and SYNC Only) 200 mV Input Capacitance 10 pF POWER SUPPLY VOLTAGES V +4.75 +12 V DD V –4.75 –12 V SS AV 4.75 5.25 V CC DV 2.7 5.25 V CC 6 POWER SUPPLY CURRENTS I 9 12 mA All Channels Full Scale DD I 9 12 mA All Channels Full Scale SS AI 6.5 10 mA CC DI 0.1 0.5 mA V = DV and V = DGND CC IH CC IL 6 POWER DISSIPATION 123 mW V = +5 V, V = –5 V DD SS NOTES 1 See Terminology 2 A Version: Industrial temperature range –40°C to +85°C; typical at 25°C. 3 Guaranteed by design and characterization, not production tested. 4 Output range is restricted from V + 2 V to V – 2 V. SS DD 5 AD780 as reference for the AD5532HS. 6 Outputs unloaded. Specifications subject to change without notice. –2– REV. 0 AD5532HS (V = +4.75 V to +12 V, V = –4.75 V to –12 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; AGND = DD SS CC CC AC CHARACTERISTICS DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications T to T unless otherwise noted.) MIN MAX 1, 2 3 Parameter A Version Unit Conditions/Comments 4 Output Voltage Settling Time 10 µs max 100 pF, 5 kΩ Load; Full-Scale Change Slew Rate 0.85 V/µs typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry Digital Crosstalk 5 nV-s typ Analog Crosstalk 1 nV-s typ Digital Feedthrough 0.2 nV-s typ Output Noise Spectral Density @ 1 kHz 170 nV/√Hz typ NOTES 1 See Terminology 2 Guaranteed by design and characterization, not production tested 3 B Version: Industrial temperature range –40°C to +85°C. 4 Timed from the end of a write sequence. Specifications subject to change without notice. TIMING CHARACTERISTICS (V = +4.75 V to +12 V, V = –4.75 V to –12 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; DD SS CC CC AGND = DGND = DAC_GND = 0 V; All specifications T to T unless otherwise noted.) MIN MAX Limit at T , T MIN MAX 1, 2, 3 Parameter (A Version) Unit Conditions/Comments f 1.1 MHz max Channel Update Rate UPDATE f 30 MHz max SCLK Frequency CLKIN t 13 ns min SCLK High Pulsewidth 1 t 13 ns min SCLK Low Pulsewidth 2 t 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 3 t 50 ns min SYNC Low Time 4 t 10 ns min SYNC High Time 5 t 10 ns min D Setup Time 6 IN t 5 ns min D Hold Time 7 IN t 280 ns min 19th SCLK Falling Edge to SYNC Falling Edge for Next Write 8 t 20 ns min RESET Pulsewidth 9 NOTES 1 See Timing Diagrams in Figure 1. 2 Guaranteed by design and characterization, not production tested. 3 All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of (V + V )/2. R F CC IL IH Specifications subject to change without notice. t 1 1 SCLK 23 45 16 17 18 19 1 t 3 t 2 t 5 SYNC t t 4 t 6 8 t 7 D IN MSB LSB RESET t 9 Figure 1. Serial Interface Timing Diagram REV. 0 –3– AD5532HS 1, 2 Junction Temperature (T max) . . . . . . . . . . . . . . . . . . 150°C ABSOLUTE MAXIMUM RATINGS J (T = 25°C unless otherwise noted) 74-Lead LFBGA Package, θ Thermal Impedance . . . 41°C/W A JA Reflow Soldering V to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V DD Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C V to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V SS Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec AV to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V CC Max Power Dissipation at T = 70°C, A DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V CC 3 Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV + 0.3 V CC (for T > 70°C, derate at 26 mW for each °C over 70°C) A REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V NOTES V 0–V 31 to AGND . . . . . . . V – 0.3 V to V + 0.3 V OUT OUT SS DD 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- V 0–V 31 to V . . . . . . . . . . . . . . . . . . –0.3 V to +24 V OUT OUT SS nent damage to the device. This is a stress rating only; functional operation of the OFFS_IN to AGND . . . . . . . . . . . V – 0.3 V to V + 0.3 V SS DD device at these or any other conditions above those listed in the operational AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V sections of this specification is not implied. Exposure to absolute maximum rating Operating Temperature Range conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C 3 This limit includes load power and applies only when there is a resistive load on Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C V outputs. OUT ORDERING GUIDE Output Package Package Model Function Voltage Span Description Option AD5532HSABC 32 DACs 5 V 74-Ball LFBGA BC-74 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. FULL-SCALE ERROR ACTUAL IDEAL OFFSET ERROR 0 DAC CODE 16k Figure 2. DAC Transfer Function (OFFS_IN = 0) –4– REV. 0 OUTPUT VOLTAGE AD5532HS PIN CONFIGURATION 123456789 10 11 A A B B C C D D E E F F TOP VIEW G G H H J J K K L L 123456789 10 11 AD5532HS 74-Ball (LFBGA) Configuration LFBGA Ball LFBGA Ball LFBGA Ball Number Name Number Name Number Name A1 N/C C10 AVCC1 J10 VO9 A2 N/C C11 N/C J11 VO11 A3 N/C D1 VO20 K1 VO17 A4 N/C D2 DAC_GND2 K2 VO15 A5 SYNC D10 AVCC2 K3 VO27 A6 DVCC D11 N/C K4 VSS3 A7 SCLK E1 VO26 K5 VSS1 A8 N/C E2 VO14 K6 VSS4 A9 N/C E10 AGND1 K7 VDD2 A10 RESET E11 OFFS_IN K8 VO2 A11 N/C F1 VO25 K9 VO10 B1 VO16 F2 VO21 K10 VO13 B2 N/C F10 AGND2 K11 VO12 B3 N/C F11 VO6 L1 N/C B4 N/C G1 VO24 L2 VO28 B5 N/C G2 VO8 L3 VO29 B6 DGND G10 VO5 L4 VO30 B7 DIN G11 VO3 L5 VDD3 B8 DGND H1 VO23 L6 VDD1 B9 N/C H2 N/C L7 VDD4 B10 N/C H10 VO4 L8 VO31 B11 REF_IN H11 VO7 L9 VO0 C1 VO18 J1 VO22 L10 VO1 C2 DAC_GND1 J2 VO19 L11 N/C C6 N/C J6 VSS2 REV. 0 –5– AD5532HS PIN FUNCTION DESCRIPTIONS Pin Function AGND (1–2) Analog GND Pins. AV (1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. CC V (1–4) V Supply Pins. Voltage range from 8 V to 12 V. DD DD V (1–4) V Supply Pins. Voltage range from –4.75 V to –12 V. SS SS DGND Digital GND Pins. DV Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. CC DAC_GND (1–2) Reference GND Supply for All the DACs. REF_IN Reference Voltage for Channels 0–31. V 0–V 31 Analog Output Voltages from the 32 Channels. OUT OUT SYNC Active Low Input. This is the Frame Synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. SCLK* Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. D * Serial Data Input. Data must be valid on the falling edge of SCLK. IN OFFS_IN Offset Input. The user can connect this to GND or REF_IN to determine the output span. RESET* Active Low Input. This pin can also be used to reset the complete device to its power-on-reset conditions. *Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition. Output Voltage Settling Time TERMINOLOGY The time taken from when the last data bit is clocked into the Integral Nonlinearity (INL) DAC until the output has settled to within ±0.5 LSB of its A measure of the maximum deviation from a straight line pass- final value. ing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range. Digital-to-Analog Glitch Impulse The area of the glitch injected into the analog output when Differential Nonlinearity (DNL) the code in the DAC register changes state. It is specified as The difference between the measured change and the ideal 1 LSB the area of the glitch in nV-secs when the digital code is changed change between any two adjacent codes. A specified DNL of by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 ±1 LSB maximum ensures monotonicity. or 100 . . . 00 to 011 . . . 11). Offset Error Digital Crosstalk A measure of the error present at the device output with all 0s The glitch impulse transferred to the output of one DAC at loaded to the DAC. It includes the offset of the DAC and the midscale while a full-scale code change (all 1s to all 0s and vice output amplifier. It is expressed in mV. versa) is being written to another DAC. It is expressed in nV-secs. Full-Scale Error Analog Crosstalk A measure of the output error with all 1s loaded to the DAC. The area of the glitch transferred to the output (V ) of one OUT Ideally the output should be 2 REF_IN if OFFS_IN = 0. It is DAC due to a full-scale change in the output (V ) of another OUT expressed as a percentage of full-scale range. DAC. The area of the glitch is expressed in nV-secs. DC Power-Supply Rejection Ratio (PSRR) Digital Feedthrough A measure of the change in analog output for a change in supply A measure of the impulse injected into the analog outputs from the voltage (V and V ). It is expressed in dB. V and V are DD SS DD SS digital control inputs when the part is not being written to, i.e., varied ±5%. SYNC is high. It is specified in nV-secs and measured with a DC Crosstalk worst-case change on the digital input pins, e.g., from all 0s The dc change in the output level of one DAC at midscale in to all 1s and vice versa. response to a full-scale code change (all 0s to all 1s and vice Output Noise Spectral Density versa) and output change of all other DACs. It is expressed in µV. A measure of internally generated random noise. Random noise is Output Temperature Coefficient characterized as a spectral density (voltage per root Hertz). It is A measure of the change in analog output with changes in tem- measured by loading all DACs to midscale and measuring perature. It is expressed in ppm/°C. noise at the output. It is measured in nV/√Hz. –6– REV. 0 Typical Performance Characteristics–AD5532HS 1.0 1.0 0.2 5.000 V = 2.5V REF_IN V = 2.5V REFIN 0.8 V = 0V OFFS_IN V = 0V OFFS_IN T = 25�C A DAC LOADED TO FULL SCALE 0.6 0.5 0.1 0.4 4.995 DNL MAX INL MAX 0.2 0.0 0.0 0.0 –0.2 4.990 –0.4 INL MIN –0.5 –0.1 –0.6 –0.8 DNL MIN –1.0 –1.0 –0.2 4.985 –40 0 40 80 0 2K 4K 6K 8K 10K 12K 14K16K –40 04080 TEMPERATURE – �C DAC CODE TEMPERATURE – �C TPC 1. Typical DNL Plot TPC 3. V vs. Temperature TPC 2. INL Error and DNL Error vs. OUT Temperature 2.535 6 2.520 T = 25�C A 2.518 T = 25�C A V = 2.5V REFIN 5 V = 2.5V 2.516 REFIN V = 0V OFFS_IN V = 0V OFFS_IN 2.514 DAC LOADED TO MIDSCALE 4 2.512 2.530 2.510 3 2.508 2.506 2 2.504 2.525 2.502 1 T = 25�C A 2.500 V = 2.5V REFIN 2.498 0 V = 0V OFFS_IN 2.496 2.520 –1 2.494 64 20 –2 –4 –6 TIME BASE – 200ns/DIV TIME BASE – 1.25�s/DIV SINK/SOURCE CURRENT – mA TPC 4. V Source and Sink TPC 6. Major Code Transition Glitch OUT TPC 5. Full-Scale Settling Time Capability Impulse 15 20 15 10 10 10 5 5 0 0 0 0 0.1 0.2 0.3 –1.0 –0.5 0.0 0 10 20 30 % FSR mV % FSR TPC 7. INL Error Distribution at 25°C TPC 8. Offset Error Distribution TPC 9. Full-Scale Error Distribution at 25°C at 25°C REV. 0 –7– V – V OUT DAC ERROR –LSBs FREQUENCY – % DNL ERROR – LSBs FREQUENCY – % V – V OUT INL ERROR – % FSR V – V OUT V – V OUT FREQUENCY – % AD5532HS FUNCTIONAL DESCRIPTION Reset Function The AD5532HS consists of 32 DACs in a single package. A The reset function on the AD5532HS can be used to reset all 14-bit digital word is loaded into one of the 32 DAC registers nodes on the device to their power-on-reset condition. All the via the serial interface. This is then converted (with gain and DACs are loaded with 0s and all registers are cleared. The reset offset) into an analog output voltage (V 0–V 31). function is implemented by taking the RESET pin low. OUT OUT To update a DAC’s output voltage, the required DAC is SERIAL INTERFACE addressed via the serial port. When the 5-bit DAC address The serial interface is controlled by three pins as follows: and 14-bit DAC data have been loaded the selected DAC converts the code. SYNC: This pin is the Frame Synchronization pin for the serial interface. On power-on, all the DACs are loaded with zeros. SCLK: This pin is the Serial Clock Input. It operates at clock Digital-to-Analog Section speeds up to 30 MHz. The architecture of each DAC channel consists of a resistor- string DAC followed by an output buffer amplifier. The voltage D : This pin is the Serial Data Input. Data must be valid on IN at the REF_IN pin provides the reference voltage for the cor- the falling edge of SCLK. responding DAC. Since the input coding to the DAC is straight To update a single DAC channel a 19-bit data-word is written binary, the ideal DAC output voltage is given by: into the AD5532HS. See Table II. VD × REF _ IN V = DAC 14 Table II. Serial Data Format 2 where D = decimal equivalent of the binary code that is loaded MSB LSB to the DAC register i.e., 0–16,383. A4 A3 A2 A1 A0 DB13–DB0 Output Buffer Stage—Gain and Offset The function of the output buffer stage is to translate the A4–A0 Bits Used to address any one of the 32 channels (A4 = MSB of 0 V–2.5 V output of the DAC to a wider range. This is done by gaining up the DAC output by two and offsetting the voltage address, A0 = LSB). by the voltage on OFFS_IN pin. DB13–DB0 Bits VV =×() 2 –V OUT DAC OFFS _ IN These are used to write a 14-bit word into the addressed DAC register. V is the output of the DAC. DAC Figure 1 shows the timing diagram for a serial write to the V is the voltage at the OFFS_IN pin. OFFS_IN AD5532HS. The serial interface works with both a continuous and Table I shows how the output range of V relates to the offset OUT a noncontinuous serial clock. The first falling edge of SYNC resets voltage supplied by the user. a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial Table I. Sample Output Voltage Ranges shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once 19 bits have V V V OFFS_IN DAC OUT been shifted in or out, the SCLK is ignored. In order for another (V) (V) (V) serial transfer to take place, the counter must be reset by the 0 0 to 2.5 0 to 5 falling edge of SYNC. The user must allow 280 ns (min) 2.5 0 to 2.5 –2.5 to +2.5 between successive writes (refer to Timing Specifications). V is limited only by the headroom of the output amplifiers. OUT V must be within maximum ratings. OUT –8– REV. 0 AD5532HS MICROPROCESSOR INTERFACING AD5532HS-to-PIC16C6x/7x Interface AD5532HS-to-ADSP-21xx Interface The PIC16C6x/7x Synchronous Serial Port (SSP) is configured The ADSP-21xx family of DSPs are easily interfaced to the as an SPI Master with the Clock Polarity bit = 0. This is done AD5532HS without the need for extra logic. by writing to the Synchronous Serial Port Control Register (SSPCON). See user PIC16/17 Microcontroller User Manual. A data transfer is initiated by writing a word to the Tx register In this example I/O port RA1 is being used to pulse SYNC after the SPORT has been enabled. In a write sequence, data is and enable the serial port of the AD5532HS. This microcontroller clocked out on each rising edge of the DSP’s serial clock and transfers only eight bits of data during each serial transfer clocked into the AD5532HS on the falling edge of its SCLK. operation; therefore, three consecutive write operations are The easiest way to provide the 19-bit data-word required by necessary to transmit 19 bits of data. Data is transmitted MSB the AD5532HS, is to transmit two 10-bit data-words from the first. It is important to left-justify the data in the SPDR register ADSP-21xx. Ensure that the data is positioned correctly in the so that the first 19 bits transmitted contain valid data. RA1 TX register so that the first 19 bits transmitted contain valid must be pulled low to start a transfer. It is taken high and pulled data. The SPORT control register should be set up as follows: low again before any further write cycles can take place. Figure 5 TFSW = 1, Alternate Framing shows the connection diagram. INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data PIC16C6x/7x* AD5532HS* ISCLK = 1, Internal Serial Clock SCLK SCK/RC3 TFSR = 1, Frame Every Word D SDI/RC4 ITFS = 1, Internal Framing Signal IN SLEN = 1001, 10-Bit Data Word SYNC RA1 Figure 3 shows the connection diagram. *ADDITIONAL PINS OMITTED FOR CLARITY ADSP-2101/ AD5532HS* Figure 5. AD5532HS-to-PIC16C6x/7x Interface ADSP-2103* SCLK SCLK AD5532HS-to-8051 Interface D The AD5532HS requires a clock synchronized to the serial DT IN data. The 8051 serial interface must therefore be operated in TFS SYNC Mode 0. In this mode serial data exits the 8051 through RxD and a shift clock is output on TxD. The SYNC signal is derived *ADDITIONAL PINS OMITTED FOR CLARITY from a port line (P1.1). Figure 6 shows how the 8051 is connected to the AD5532HS. Because the AD5532HS shifts data out on Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface the rising edge of the shift clock and latches data in on the AD5532HS-to-MC68HC11 Interface falling edge, the shift clock must be inverted. Note also that The Serial Peripheral Interface (SPI) on the MC68HC11 is the AD5532HS requires its data with the MSB first. Since the configured for Master Mode (MSTR = 1), Clock Polarity Bit 8051 outputs the LSB first, the transmit routine must take this (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is into account. configured by writing to the SPI Control Register (SPCR)—see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of 8051* AD5532HS* the AD5532HS and the MOSI output drives the serial data line SCLK TxD (D ) of the AD5532HS. The SYNC signal is derived from a port IN D RxD IN line (PC7). When data is being transmitted to the AD5532HS, the P1.1 SYNC SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. The 68HC11 transfers *ADDITIONAL PINS OMITTED FOR CLARITY only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to Figure 6. AD5532HS-to-8051 Interface transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. See Figure 4. MC68HC11* AD5532HS* SCLK SCK D MOSI IN SYNC PC7 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 4. AD5532HS-to-MC68HC11 Interface REV. 0 –9– AD5532HS APPLICATION CIRCUITS PARAMETRIC MEASUREMENT SYSTEM BUS AD5532HS in an Optical Network Control Loop DAC UNIT The AD5532HS can be used in optical network applications ACTIVE DAC that require a large number of DACs to perform a control and LOAD measurement function. In the circuit shown in Figure 7, the DAC 0 V–5 V outputs of the AD5532HS are amplified to a range of STORED 0 V–180 V and then used to control actuators that determine DATA DRIVER the position of MEMS mirrors in an optical switch. The exact AND INHIBIT DAC PATTERN position of each mirror is measured using sensors. The sensor FORMATTER readings are muxed using four dual 4-channel matrix switches DUT DAC (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856). PERIOD ® GENERATION The control loop is driven by an ADSP-21065L, a 32-bit SHARC AND DAC DELAY DSP with an SPI-compatible SPORT interface. It writes data COMPARE TIMING REGISTER to the DAC, controls the multiplexor, and reads data from DAC the ADC via a 3-wire serial interface. COMPARATOR DACs SYSTEM BUS S E 1 1 1 ACTUATORS N Figure 9. AD5532HS in an ATE System 0V–180V ADG739 FOR MEMS AD7856 AD5532HS S AMPS MIRROR � 4 O ARRAY 32 8 32 R POWER SUPPLY DECOUPLING S In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the ADSP-21065L AD5532HS is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas Figure 7. AD5532HS and DSP Control an Optical Switch of the board. If the AD5532HS is in a system where multiple Alternatively, the AD5532HS can be driven by an ADMC401 devices require an AGND-to-DGND connection, the connection Motor-Controller as shown in the control-loop in Figure 8. The should be made at one point only. The star ground point should DAC outputs are fed into eight AD8534 quad transconductance be established as close as possible to the device. For supplies amps to generate currents for voice-coil actuators that determine with multiple pins (V , V , AV ), it is recommended to SS DD CC the position of the mirrors. The exact position of each mirror tie those pins together. The AD5532HS should have ample is measured and the readings are muxed into the on-chip supply bypassing of 10 µF in parallel with 0.1 µF on each supply 8-channel ADC of the ADMC401. located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance S 1 1 1 VOICE-COIL E (ESR) and Effective Series Inductance (ESI), like the common ACTUATORS N ADG704 AD5532HS FOR S ceramic types that provide a low impedance path to ground at � 8 MEMS O 32 32 8 MIRROR R high frequencies, to handle transient currents due to internal ARRAY S logic switching. AD8534 AD8544 � 8 � 2 3 The power supply lines of the AD5532HS should use as large a trace as possible to provide low impedance paths and reduce S 1 P 8-CH 3 the effects of glitches on the power supply line. Fast switching O 12-BIT ADMC401 R ADC signals such as clocks should be shielded with digital ground to 8 T avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed Figure 8. AD5532HS and ADMC401 Control an Optical between the D and SCLK lines will help reduce crosstalk IN Switch between them (not required on a multilayer board as there will AD5532HS in a Typical ATE System be a separate ground plane, but separating the lines will help). It The AD5532HS is ideally suited for use in Automatic Test is essential to minimize noise on REF_IN. Equipment. Several DACs are required to control pin drivers, Avoid crossover of digital and analog signals. Traces on opposite comparators, active loads, and signal timing. Traditionally, sides of the board should run at right angles to each other. This sample-and-hold devices were used in this application. reduces the effects of feedthrough through the board. A microstrip The AD5532HS has several advantages: no refreshing is required, technique is by far the best, but not always possible with a double- there is no droop, pedestal error is eliminated, and there is no sided board. In this technique, the component side of the board need for extra filtering to remove glitches. A higher level of is dedicated to ground plane while signal traces are placed on integration is achieved in a smaller area (see Figure 9). the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process. SHARC is a registered trademark of Analog Devices, Inc. –10– REV. 0 AD5532HS OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 74-Ball LFBGA (BC-74) 0.394 (10.00) BSC 0.472 (12.00) BSC 11 10 9 8 7 6 5 4 3 2 1 A B A1 C D 0.472 E 0.394 BOTTOM TOP VIEW (12.00) F (10.00) 0.039 VIEW BSC BSC G (1.00) H BSC J K L 0.039 (1.00) BSC DETAIL A 0.067 (1.70) DETAIL A 0.033 MAX (0.85) 0.020 MIN (0.50) MIN CONTROLLING DIMENSIONS 0.024 (0.60) ARE IN MILLIMETERS SEATING BSC PLANE BALL DIAMETER REV. 0 –11– –12– PRINTED IN U.S.A. C02548–1.5–6/01(0)