ANALOG DEVICES AD5531

Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters AD5530/AD5531 FEATURES FUNCTIONAL BLOCK DIAGRAM V V SS DD Pin-compatible 12-, 14-bit digital-to-analog converters Serial input, voltage output AD5530/AD5531 REFIN Maximum output voltage range of ±10 V 12-/14-BIT R R DAC Data readback V OUT R REFAGND 3-wire serial interface Clear function to a user-defined voltage R LDAC DUTGND DAC REGISTER Power-down function RBEN CLR Serial data output for daisy-chaining POWER-DOWN PD 16-lead TSSOP SDIN SHIFT REGISTER CONTROL LOGIC APPLICATIONS GND SCLK SYNC SDO Industrial automation Figure 1. Automatic test equipment Process control General-purpose instrumentation GENERAL DESCRIPTION The AD5530/AD5531 are single 12- and 14-bit (respectively) The DAC output is buffered by a gain of two amplifier and serial input, voltage output digital-to-analog converters (DAC). LDAC referenced to the potential at DUTGND. can be used to update the output of the DAC asynchronously. A power-down They utilize a versatile 3-wire interface that is compatible with PD pin ( ) allows the DAC to be put into a low power state, and SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data CLR a pin allows the output to be cleared to a user-defined is presented to the part in a 16-bit serial word format. Serial voltage, the potential at DUTGND. data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DAC The AD5530/AD5531 are available in 16-lead TSSOP. register via the SDO pin. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 00938-001 AD5530/AD5531 TABLE OF CONTENTS Features .............................................................................................. 1 PD Function................................................................................ 13 Applications....................................................................................... 1 Readback Function .................................................................... 13 Functional Block Diagram .............................................................. 1 CLR Function.............................................................................. 13 General Description ......................................................................... 1 Output Voltage............................................................................ 14 Revision History ............................................................................... 2 Bipolar Configuration................................................................ 14 Specifications..................................................................................... 3 Microprocessor Interfacing........................................................... 15 AC Performance Characteristics ................................................ 5 AD5530/AD5531 to ADSP-21xx.............................................. 15 Standalone Timing Characteristics............................................ 5 AD5530/AD5531 to 8051 Interface ......................................... 15 Daisy-Chaining and Readback Timing Characteristics.......... 6 AD5530/AD5531 to MC68HC11 Interface ............................ 15 Absolute Maximum Ratings............................................................ 7 Applications Information .............................................................. 17 ESD Caution.................................................................................. 7 Optocoupler Interface................................................................ 17 Pin Configuration and Function Descriptions............................. 8 Serial Interface to Multiple AD5530s or AD5531s ................ 17 Typical Performance Characteristics ............................................. 9 Daisy-Chaining Interface with Multiple AD5530s or AD5531s ...................................................................................... 17 Terminology .................................................................................... 12 Outline Dimensions....................................................................... 18 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 18 DAC Architecture....................................................................... 13 Serial Interface ............................................................................ 13 REVISION HISTORY 1/07—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Figure 28...................................................................... 17 3/06—Rev. 0 to Rev. A Change to Table 3 ............................................................................. 5 Change to Figure 4 ........................................................................... 8 Change to Output Voltage Section............................................... 14 Change to Ordering Guide............................................................ 18 5/02—Revision 0: Initial Version Rev. B | Page 2 of 20 AD5530/AD5531 SPECIFICATIONS VDD = 15 V ± 10%; VSS = −15 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter AD5530 AD5531 Unit Test Conditions/Comments ACCURACY Resolution 12 14 Bits Relative Accuracy ±1 ±2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Gain Error ±1 ±4 LSB typ 2 Gain Temperature Coefficient 0.5 0.5 ppm FSR/°C typ 10 10 ppm FSR/°C max 2 REFERENCE INPUTS Reference Input Range 0 to 5 0 to 5 V min to V max Max output range ±10 V DC Input Resistance 100 100 MΩ typ Input Current ±1 ±1 μA max Per input, typically ±20 nA 2 DUTGND INPUT DC Input Impedance 60 60 kΩ typ Max Input Current ±0.3 ±0.3 mA typ Input Range −4 to +4 −4 to +4 V min to V max Max output range ±10 V 2 O/P CHARACTERISTICS Output Voltage Swing ±10 ±10 V max Short-Circuit Current 15 15 mA max Resistive Load 5 5 kΩ min To 0 V Capacitive Load 1200 1200 pF max To 0 V DC Output Impedance 0.5 0.5 Ω max DIGITAL I/O VINH, Input High Voltage 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current ±10 ±10 μA max Total for all pins 2 C , Input Capacitance 10 10 pF max 3 pF typical IN SDO V , Output Low Voltage 0.4 0.4 V max I = 1 mA OL SINK POWER REQUIREMENTS V /V +15/−15 +15/−15 V nom ±10% for specified performance DD SS Power Supply Sensitivity ΔFull Scale/ΔV 110 110 dB typ DD ΔFull Scale/ΔVSS 100 100 dB typ IDD 2 2 mA max Outputs unloaded ISS 2 2 mA max Outputs unloaded I in Power-Down 150 150 μA max Typically 50 μA DD 1 Temperature range for B Version: −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. B | Page 3 of 20 AD5530/AD5531 V = 12 V ± 10%; V = −12 V ± 10%; GND = 0 V; R = 5 kΩ and C = 220 pF to GND; T = T to T , unless otherwise noted. DD SS L L A MIN MAX Table 2. 1 Parameter AD5530 AD5531 Unit Test Conditions/Comments ACCURACY Resolution 12 14 Bits Relative Accuracy ±1 ±2 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB Gain Error ±1 ±4 LSB typ 2 Gain Temperature Coefficient 0.5 0.5 ppm FSR/°C typ 10 10 ppm FSR/°C max 2 REFERENCE INPUTS Reference Input Range 0 to 4.096 0 to 4.096 V min to V max Max output range ±8.192 V DC Input Resistance 100 100 MΩ typ Input Current ±1 ±1 μA max Per input, typically ±20 nA 2 DUTGND INPUT DC Input Impedance 60 60 kΩ typ Max Input Current ±0.3 ±0.3 mA typ Input Range −3 to +3 −3 to +3 V min to V max Max output range ±8.192 V 2 O/P CHARACTERISTICS Output Voltage Swing ±8.192 ±8.192 V max Short-Circuit Current 15 15 mA max Resistive Load 5 5 kΩ min To 0 V Capacitive Load 1200 1200 pF max To 0 V DC Output Impedance 0.5 0.5 Ω max DIGITAL I/O V , Input High Voltage 2.4 2.4 V min INH V , Input Low Voltage 0.8 0.8 V max INL I , Input Current ±10 ±10 μA max Total for all pins INH 2 CIN, Input Capacitance 10 10 pF max 3 pF typical SDO VOL, Output Low Voltage 0.4 0.4 V max ISINK = 1 mA POWER REQUIREMENTS VDD/VSS +12/−12 +12/−12 V nom ±10% for specified performance Power Supply Sensitivity ΔFull Scale/ΔV 110 110 dB typ DD ΔFull Scale/ΔV 100 100 dB typ SS I 2 2 mA max Outputs unloaded DD ISS 2 2 mA max Outputs unloaded IDD in Power-Down 150 150 μA max Typically 50 μA 1 Temperature range for B Version: −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. B | Page 4 of 20 AD5530/AD5531 AC PERFORMANCE CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 20 μs typ Full-scale change to ±½ LSB. DAC latch contents alternately loaded with all 0s and all 1s. Slew Rate 1.3 V/μs typ Digital-to-Analog Glitch Impulse 120 nV-s typ DAC latch alternately loaded with 0x0FFF and 0x1000. Not dependent on load conditions. Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test. Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC. STANDALONE TIMING CHARACTERISTICS V = 10.8 V to 16.5 V, V = −10.8 V to −16.5 V; GND = 0 V; R = 5 kΩ and C = 220 pF to GND. All specifications T to T , unless DD SS L L MIN MAX otherwise noted. Table 4. 1, 2 Parameter Limit at T , T Unit Description MIN MAX fMAX 7 MHz max SCLK frequency t 140 ns min SCLK cycle time 1 t 60 ns min SCLK low time 2 t3 60 ns min SCLK high time t4 50 ns min SYNC to SCLK falling edge setup time t5 40 ns min SCLK falling edge to SYNC rising edge t 50 ns min Min SYNC high time 6 t 40 ns min Data setup time 7 t 15 ns min Data hold time 8 t9 5 ns min SYNC high to LDAC low t10 50 ns min LDAC pulse width t11 5 ns min LDAC high to SYNC low t 50 ns min CLR 12 pulse width 1 Guaranteed by design, not subject to production test. 2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH t t 1 3 SCLK t 2 t 4 t 5 SYNC t 6 t t 7 8 MSB LSB SDIN DB15 DB14 DB11 DB0 t 9 t 11 1 LDAC t 10 t 12 CLR 1 LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED. Figure 2. Timing Diagram for Standalone Mode Rev. B | Page 5 of 20 00938-002 AD5530/AD5531 DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 5. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description fMAX 2 MHz max SCLK frequency t1 500 ns min SCLK cycle time t2 200 ns min SCLK low time t 200 ns min SCLK high time 3 t 50 ns min SYNC to SCLK falling edge setup time 4 t 40 ns min 5 SCLK falling edge to SYNC rising edge t6 50 ns min Min SYNC high time t7 40 ns min Data setup time t 15 ns min Data hold time 8 t 50 ns min CLR pulse width 12 t 130 ns min SCLK falling edge to SDO valid 13 t14 50 ns max SCLK falling edge to SDO invalid t15 50 ns min RBEN to SCLK falling edge setup time t16 50 ns min RBEN hold time t 100 ns min RBEN falling edge to SDO valid 17 1 Guaranteed by design, not subject to production test. 2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH 3 SDO; R = 5 kΩ, C = 15 pF PULLUP L t t 1 3 SCLK t 2 t 4 t 5 SYNC t 6 t t 7 8 MSB LSB SDIN DB15 DB14 DB11 DB0 t 13 t 14 MSB LSB SDO (DAISY- DB15 DB11 DB0 CHAINING) t 15 t RBEN 16 t t 13 17 t 14 SDO 00 RB13 RB0 (READBACK) MSB LSB Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode Rev. B | Page 6 of 20 00938-003 AD5530/AD5531 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 6. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +17 V DD section of this specification is not implied. Exposure to absolute V to GND +0.3 V to −17 V SS maximum rating conditions for extended periods may affect Digital Inputs to GND −0.3 V to VDD + 0.3 V device reliability. SDO to GND −0.3 V to +6.5 V REFIN to REFAGND −0.3 V to +17 V REFIN to GND V − 0.3 V to V + 0.3 V SS DD ESD CAUTION REFAGND to GND V − 0.3 V to V + 0.3 V SS DD DUTGND to GND V − 0.3 V to V + 0.3 V SS DD Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (T ) 150°C J MAX Package Power Dissipation (T – T )/θ J MAX A JA Thermal Impedance θJA TSSOP (RU-16) 150.4°C/W Lead Temperature (Soldering 10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C Rev. B | Page 7 of 20 AD5530/AD5531 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REFAGND 1 16 V DD REFIN 2 15 V OUT LDAC 3 14 DUTGND AD5530/ AD5531 SDIN 4 13 V SS TOP VIEW (Not to Scale) SYNC 5 12 NC RBEN 6 11 GND SCLK 7 10 PD SDO 8 9 CLR NC = NO CONNECT Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V. 2 REFIN This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output. 3 LDAC Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC. 4 SDIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. 5 SYNC Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK. 6 RBEN Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data from the DAC register is shifted out on the SDO pin on each rising edge of SCLK. 7 SCLK Clock Input. Data is clocked into the input register on the falling edge of SCLK. 8 SDO Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left high impedance. 9 CLR Level Sensitive, Active Low Input. A falling edge of CLR resets V to DUTGND. The contents of the registers OUT are untouched. 10 PD This allows the DAC to be put into a power-down state. 11 GND Ground Reference. 12 NC Do not connect anything to this pin. 13 VSS Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance. 14 DUTGND V is referenced to the voltage applied to this pin. OUT 15 V DAC Output. OUT 16 VDD Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance. Rev. B | Page 8 of 20 00938-004 AD5530/AD5531 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.00 V = +15V V = +15V DD DD V = –15V V = –15V 0.8 SS SS 0.75 REFIN = +5V REFIN = +5V REFAGND = 0V REFAGND = 0V 0.6 T = 25°C T = 25°C A 0.50 A 0.4 0.25 0.2 0 0 –0.2 –0.25 –0.4 –0.50 –0.6 –0.75 –0.8 –1.0 –1.00 0 500 1000 1500 2000 2500 3000 3500 4000 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE CODE Figure 5. AD5530 Typical INL Plot Figure 8. AD5531 Typical DNL Plot 0.5 2.0 V = +15V V = +15V DD DD V = –15V V = –15V 0.4 SS SS 1.5 REFIN = +5V REFIN = +5V REFAGND = 0V REFAGND = 0V 0.3 T = 25°C A 1.0 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 –1.5 –0.4 –0.5 –2.0 0 500 1000 1500 2000 2500 3000 3500 4000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 6. AD5530 Typical DNL Plot Figure 9. AD5531 Typical INL Error vs. Temperature 1.0 V = +15V 2.0 DD V = +15V V = –15V DD 0.8 SS V = –15V REFIN = +5V SS 1.5 REFIN = +5V REFAGND = 0V 0.6 REFAGND = 0V T = 25°C 1.0 A 0.4 0.2 0.5 0 0 –0.2 –0.5 –0.4 –1.0 –0.6 –0.8 –1.5 –1.0 –2.0 –40 –20 0 20 40 60 80 0 2000 4000 6000 8000 10000 12000 14000 16000 TEMPERATURE (°C) CODE Figure 10. AD5531 Typical DNL Error vs. Temperature Figure 7. AD5531 Typical INL Plot Rev. B | Page 9 of 20 LSB LSB LSB 00938-007 00938-006 00938-005 ERROR (LSB) ERROR (LSB) LSB 00938-010 00938-009 00938-008 AD5530/AD5531 3 0.03 V = +15V DD V = –15V SS REFIN = 0V 2 T = 25°C A –40°C POSITIVE INL 0.02 1 +25°C +85°C 0 NEGATIVE INL –1 0.01 –2 –3 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 10 11 12 13 14 15 16 17 REFIN VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 11. AD5531 Typical INL Error vs. Reference Voltage Figure 14. IDD in Power-Down vs. Supply 0 12 V = +15V DD V = –15V SS REFIN = +5V 8 REFAGND = 0V –0.5 4 –1.0 0 –1.5 –4 V = +15V DD –2.0 V = –15V SS –8 REFIN = +5V REFAGND = 0V T = 25°C A –2.5 –12 –40 –20 0 20 40 60 80 0 5 10 15 20 25 TEMPERATURE (°C) TIME (µs) Figure 12. Typical Full-Scale and Offset Error vs. Temperature Figure 15. Settling Time 1.50 0 –0.02 1.45 +85°C –0.04 1.40 –0.06 +25°C 1.35 –0.08 –40°C –0.10 1.30 –0.12 V = +15V DD V = –15V SS 1.25 REFIN = +5V –0.14 REFAGND = 0V T = 25°C A 1.20 –0.16 10 11 12 13 14 15 16 17 V /V (V) DD SS TIME (750ns/DIV) Figure 13. IDD vs. VDD/VSS Figure 16. Typical Digital-to-Analog Glitch Impulse Rev. B | Page 10 of 20 ERROR (LSB) CURRENT (mA) ERROR (LSB) 00938-013 00938-012 00938-011 V (V) V (V) I (mA) OUT OUT DD 00938-016 00938-015 00938-014 AD5530/AD5531 V = +15V DD V OUT V = –15V SS REFIN = +5V REFAGND = 0V T = 25°C A PD 2V/DIV 2V/DIV Figure 17. Typical Power-Down Time Rev. B | Page 11 of 20 00938-017 AD5530/AD5531 TERMINOLOGY Gain Error Relative Accuracy Gain error is the difference between the actual and ideal analog Relative accuracy or endpoint linearity is a measure of the output range, expressed as a percent of the full-scale range. It is maximum deviation, in LSBs, from a straight line passing the deviation in slope of the DAC transfer characteristic from ideal. through the endpoints of the DAC transfer function. Output Voltage Settling Time Differential Nonlinearity This is the amount of time it takes for the output to settle to a Differential nonlinearity is the difference between the measured specified level for a full-scale input change. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum Digital-to-Analog Glitch Impulse ensures monotonicity. Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes Zero-Scale Error state. It is specified as the area of the glitch in nV-s and is Zero-scale error is a measure of the output error when all 0s are measured when the digital input code is changed by 1 LSB at loaded to the DAC latch. the major carry transition. Full-Scale Error Digital Feedthrough This is the error in DAC output voltage when all 1s are loaded Digital feedthrough is a measure of the impulse injected into into the DAC latch. Ideally the output voltage, with all 1s loaded the analog output of the DAC from the digital inputs of the into the DAC latch, should be 2 V − 1 LSB. REF DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Rev. B | Page 12 of 20 AD5530/AD5531 THEORY OF OPERATION DAC ARCHITECTURE REFIN 12-/14-BIT DAC OUTPUT The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs. 14 The AD5530 consists of a straight 12-bit R-2R voltage mode DAC, and the AD5531 consists of a 14-bit R-2R section. Using a LDAC DAC REGISTER 5 V reference connected to the REFIN pin and REFAGND tied to 0 V, a bipolar ±10 V voltage output results. The DAC coding 14 is straight binary. SYNC REGISTER SYNC SERIAL INTERFACE 14 Serial data on the SDIN input is loaded to the input register under the control of SCLK, SYNC, and LDAC. A write 16-BIT SHIFT SDIN SDO REGISTER operation transfers a 16-bit word to the AD5530/AD5531. Figure 20. Simplified Serial Interface Figure 2 and Figure 3 show the timing diagrams. Figure 18 and Figure 19 show the contents of the input shift register. Twelve or 14 bits of the serial word are data bits; the rest are don’t cares. Data written to the part via SDIN is available on the SDO pin 16 DB15 (MSB) DB0 (LSB) clocks later if the readback function is not used. SDO data is XX D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X clocked out on the falling edge of the serial clock with some delay. DATA BITS PD FUNCTION Figure 18. AD5530 Input Shift Register Contents PD The pin allows the user to place the device into power-down DB15 (MSB) DB0 (LSB) mode. While in this mode, power consumption is at a minimum; XX D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PD the device draws only 50 μA of current. The function does DATA BITS not affect the contents of the DAC register. Figure 19. AD5531 Input Shift Register Contents READBACK FUNCTION SYNC The serial word is framed by the signal, . After a high-to- The AD5530/AD5531 allows the data contained in the DAC SYNC low transition on , data is latched into the input shift register to be read back if required. The pins involved are the register on the falling edges of SCLK. There are two ways the RBEN RBEN and SDO (serial data out). When is taken low, on LDAC DAC register and output can be updated. The signal is the next falling edge of SCLK, the contents of the DAC register examined on the falling edge of SYNC; depending on its status, are transferred to the shift register. RBEN can be used to frame either a synchronous or asynchronous update is selected. If the readback data by leaving it low for 16 clock cycles, or it can LDAC is low, then the DAC register and output are updated on be asserted high after the required hold time. The shift register the low-to-high transition of SYNC. Alternatively, if LDAC is contains the DAC register data and this is shifted out on the high upon sampling, the DAC register is not loaded with the SDO line on each falling edge of SCLK with some delay. This SYNC new data on a rising edge of . The contents of the DAC ensures the data on the serial data output pin is valid for the LDAC register and the output voltage are updated by bringing falling edge of the receiving part. The two MSBs of the 16-bit LDAC low any time after the 16-bit data transfer is complete. word are 0s. can be tied permanently low if required. A simplified diagram CLR FUNCTION of the input loading circuitry is illustrated in Figure 20. CLR The falling edge of causes VOUT to be reset to the same potential as DUTGND. The contents of the registers remain unchanged, so the user can reload the previous data with LDAC after CLR is asserted high. Alternatively, if LDAC is tied low, the output is loaded with the contents of the DAC register auto- CLR matically after is brought high. Rev. B | Page 13 of 20 00938-019 00938-018 00938-020 AD5530/AD5531 +15V OUTPUT VOLTAGE The DAC transfer function is as follows: 2 V OUT 6 V OUT D REFIN V OUT 9 (–10V TO +10V) VOUT = 2 × [2 × ((REFIN − REFAGND) × ) + 2 × N 2 AD586 5 R1 AD5530/ 10kΩ 1 REFAGND − REFIN] − DUTGND AD5531 C1 1µF 4 DUTGND where: GND REFAGND D is the decimal data-word loaded to the DAC register. V SS N is the resolution of the DAC. SIGNAL SIGNAL GND GND BIPOLAR CONFIGURATION –15V Figure 21 shows the AD5530/AD5531 in a bipolar circuit 1 ADDITIONAL PINS OMITTED FOR CLARITY. configuration. REFIN is driven by the AD586, 5 V reference, Figure 21. Bipolar ±10 V Operation and the REFAGND and DUTGND pins are tied to GND. This results in a bipolar output voltage ranging from −10 V to +10 V. 2 REFIN Resistor R1 is provided (if required) for gain adjust. Figure 22 shows the transfer function of the DAC when REFAGND is tied to 0 V. 0V –2 REFIN DAC INPUT CODE 000 001 (3)FFF Figure 22. Output Voltage vs. DAC Input Codes (Hex) Rev. B | Page 14 of 20 DAC OUTPUT VOLTAGE 00938-022 00938-021 AD5530/AD5531 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5530/AD5531 is via a The 8051 provides the LSB of its SBUF register as the first bit in serial bus that uses standard protocol compatible with micro- the data stream. The user has to ensure that the data in the SBUF controllers and DSP processors. The communications channel register is arranged correctly because the DAC expects MSB first. is a 3-wire (minimum) interface consisting of a clock signal, a 1 80C51/80L51 AD5530/ 1 data signal, and a synchronization signal. The AD5530/AD5531 AD5531 requires a 16-bit data-word with data valid on the falling edge P3.4 LDAC of SCLK. P3.3 SYNC For all the interfaces, the DAC output update can be done RxD SDIN automatically when all the data is clocked in or asynchronously TxD SCLK under the control of LDAC. 1 ADDITIONAL PINS OMITTED FOR CLARITY. The contents of the DAC register can be read using the Figure 24. AD5530/AD5531 to 8051 Interface RBEN readback function. is used to frame the readback data, When data is to be transmitted to the DAC, P3.3 is taken low. which is clocked out on SDO. Figure 23, Figure 24, and Figure 25 Data on RxD is clocked out of the microcontroller on the rising show these DACs interfacing with a simple 4-wire interface. edge of TxD and is valid on the falling edge. As a result no glue The serial interface of the AD5530/AD5531 can be operated logic is required between this DAC and microcontroller interface. from a minimum of three wires. The 8051 transmits data in 8-bit bytes with only eight falling AD5530/AD5531 TO ADSP-21xx clock edges occurring in the transmit cycle. As the DAC expects An interface between the AD5530/AD5531 and the ADSP-21xx a 16-bit word, P3.3 must be left low after the first 8 bits are is shown in Figure 23. In the interface example shown, SPORT0 transferred. After the second byte has been transferred, the P3.3 is used to transfer data to the DAC. The SPORT control register LDAC line is taken high. The DAC can be updated using via should be configured as follows: internal clock operation, P3.4 of the 8051. alternate framing mode; active low framing signal. AD5530/AD5531 TO MC68HC11 INTERFACE Transmission is initiated by writing a word to the Tx register Figure 25 shows an example of a serial interface between the after the SPORT has been enabled. As the data is clocked out of AD5530/AD5531 and the MC68HC11 microcontroller. SCK of the DSP on the rising edge of SCLK, no glue logic is required to the MC68HC11 drives the SCLK of the DAC, and the MOSI interface the DSP to the DAC. In the interface shown, the DAC output drives the serial data lines, SDIN. SYNC is driven from LDAC output is updated using the pin via the DSP. Alternatively, one of the port lines, in this case PC7. the LDAC input could be tied permanently low and then the 1 MC68HC11 AD5530/ update takes place automatically when TFS is taken high. 1 AD5531 AD5530/ ADSP-2101/ PC6 LDAC 1 1 ADSP-2103 AD5531 PC7 SYNC FO LDAC MOSI SDIN TFS SYNC SCK SCLK DT SDIN SCLK SCLK 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 25. AD5530/AD5531 to MC68HC11 Interface 1 ADDITIONAL PINS OMITTED FOR CLARITY. The MC68HC11 is configured for master mode, MSTR = 1, Figure 23. AD5530/AD5531 to ADSP-21xx Interface CPOL = 0, and CPHA = 1. When data is transferred to the part, AD5530/AD5531 TO 8051 INTERFACE PC7 is taken low and data is transmitted MSB first. Data A serial interface between the AD5530/AD5531 and the 8051 is appearing on the MOSI output is valid on the falling edge of SCK. shown in Figure 24. TxD of the 8051 drives SCLK of the Eight falling clock edges occur in the transmit cycle, so to load the AD5530/AD5531, while RxD drives the serial data line, SDIN. required 16-bit word, PC7 is not brought high until the second P3.3 and P3.4 are bit-programmable pins on the serial port and 8-bit word has been transferred to the DAC input shift register. are used to drive and , respectively. SYNC LDAC Rev. B | Page 15 of 20 00938-023 00938-025 00938-024 AD5530/AD5531 LDAC data back from the DAC register, the SDO line can be is controlled by the PC6 port output. The DAC can be RBEN LDAC connected to MISO of the MC68HC11, with tied to updated after each 2-byte transfer by bringing low. This another port output controlling and framing the readback CLR example does not show other serial lines for the DAC. If data transfer. were used, it could be controlled by port output PC5. To read Rev. B | Page 16 of 20 AD5530/AD5531 APPLICATIONS INFORMATION SERIAL INTERFACE TO MULTIPLE AD5530s OR OPTOCOUPLER INTERFACE AD5531s In many process control applications, it is necessary to provide Figure 27 shows how the SYNC pin is used to address multiple an isolation barrier between the controller and the unit being AD5530/AD5531s. All devices receive the same serial clock and controlled. Opto-isolators can provide voltage isolation in SYNC serial data, but only one device receives the signal at any excess of 3 kV. The serial loading structure of the AD5530/ one time. The DAC addressed is determined by the decoder. AD5531 makes it ideal for opto-isolated interfaces because the There is some feedthrough from the digital input lines, the number of interface lines is kept to a minimum. Figure 26 effects of which can be minimized by using a burst clock. shows a 4-channel isolated interface to the AD5530/AD5531. To reduce the number of opto-isolators, if simultaneous LDAC updating is not required, then the pin can be tied 1 AD5530/AD5531 SCLK permanently low. SYNC V CC SDIN SDIN V OUT SCLK V µCONTROLLER CC CONTROL OUT TO LDAC 1 ENABLE EN AD5530/AD5531 SYNC 1 DECODER SYNC OUT TO SYNC SDIN V OUT CODED ADDRESS DGND SCLK SERIAL CLOCK OUT TO SCLK 1 1 ADDITIONAL PINS AD5530/AD5531 OMITTED FOR CLARITY. SYNC SERIAL DATA OUT TO SDIN SDIN V OUT SCLK OPTOCOUPLER 1 AD5530/AD5531 Figure 26. Opto-Isolated Interface SYNC SDIN V OUT SCLK Figure 27. Addressing Multiple AD5530/AD5531s DAISY-CHAINING INTERFACE WITH MULTIPLE AD5530s OR AD5531s A number of these DAC parts can be daisy-chained together using the SDO pin. Figure 28 illustrates such a configuration. V DD R R R 1 1 1 AD5530/AD5531 AD5530/AD5531 AD5530/AD5531 SCLK SCLK SCLK SCLK SDIN SDIN SDO SDIN SDO SDIN SDO SYNC SYNC SYNC SYNC TO OTHER SERIAL DEVICES 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 28. Daisy-Chaining Multiple AD5530/AD5531s Rev. B | Page 17 of 20 00938-026 00938-028 00938-027 AD5530/AD5531 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 29. 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Resolution INL (LSBs) DNL (LSBs) Package Description Package Option AD5530BRU −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 AD5530BRU-REEL −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 AD5530BRU-REEL7 −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 1 AD5530BRUZ −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 1 AD5530BRUZ-REEL −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 1 AD5530BRUZ-REEL7 −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16 AD5531BRU −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 AD5531BRU-REEL −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 AD5531BRU-REEL7 −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 1 AD5531BRUZ −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 1 AD5531BRUZ-REEL −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 1 AD5531BRUZ-REEL7 −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16 1 Z = Pb-free part. Rev. B | Page 18 of 20 AD5530/AD5531 NOTES Rev. B | Page 19 of 20 AD5530/AD5531 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00938-0-1/07(B) Rev. B | Page 20 of 20