ANALOG DEVICES AD5516

16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode * AD5516 FEATURES GENERAL DESCRIPTION High Integration: The AD5516 is a 16-channel, 12-bit voltage-output DAC. The 16-Channel DAC in 12 mm � 12 mm CSPBGA selected DAC register is written to via the 3-wire serial inter- 14-Bit Resolution via Increment/Decrement Mode face. DAC selection is accomplished via address bits A3–A0. Guaranteed Monotonic 14-bit resolution can be achieved by fine adjustment in Incre- ® Low Power, SPI , QSPI™, MICROWIRE™, and ment/Decrement Mode (Mode 2). The serial interface operates DSP Compatible at clock rates up to 20 MHz and is compatible with standard 3-Wire Serial Interface SPI, MICROWIRE, and DSP interface standards. The output Output Impedance 0.5 � voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2), Output Voltage Range and ±10 V (AD5516-3). Access to the feedback resistor in each �2.5 V (AD5516-1) channel is provided via the R 0 to R 15 pins. FB FB �5 V (AD5516-2) The device is operated with AV = 5 V ± 5%, DV = 2.7 V CC CC �10 V (AD5516-3) to 5.25 V, V = –4.75 V to –12 V, and V = +4.75 V to +12 V, SS DD Asynchronous Reset Facility (via RESET Pin) and requires a stable 3 V reference on REF_IN. Asynchronous Power-Down Facility (via PD Pin) Daisy-Chain Mode PRODUCT HIGHLIGHTS Temperature Range: –40�C to +85�C 1. Sixteen 12-bit DACs in one package, guaranteed monotonic. APPLICATIONS 2. Available in a 74-lead CSPBGA package with a body size of Level Setting 12 mm � 12 mm. Instrumentation Automatic Test Equipment Optical Networks Industrial Control Systems Data Acquisition Low Cost I/O FUNCTIONAL BLOCK DIAGRAM DV AV V V CC CC REF_IN DD SS V BIAS R R OFFS FB R 0 FB AD5516 V 0 OUT DAC RESET R R OFFS FB R 1 FB BUSY V 1 ANALOG OUT DAC CALIBRATION LOOP R R OFFS FB R 14 FB DACGND V 14 OUT DAC AGND R R OFFS FB DGND MODE1 R 15 FB V 15 OUT DAC INTERFACE MODE2 DCEN CONTROL POWER-DOWN 7-BIT BUS LOGIC LOGIC SCLK D D PD SYNC IN OUT *Protected by U.S. Patent No. 5,969,657. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. 12-BIT BUS (V = +4.75 V to +13.2 V, V = –4.75 V to –13.2 V; AV = 4.75 V to 5.25 V; DV = DD SS CC CC 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. AD5516–SPECIFICATIONS All specifications T to T , unless otherwise noted.) MIN MAX 1 2 Parameter A Version Unit Conditions/Comments DAC DC PERFORMANCE Resolution 12 Bits Integral Nonlinearity (INL) ±2 LSB max Mode 1 Differential Nonlinearity (DNL) –1/+1.3 LSB max ±0.5 LSB typ, Monotonic; Mode 1 Increment/Decrement Step-Size ±0.25 LSB typ Monotonic; Mode 2 Only Bipolar Zero Error ±7 LSB max Positive Full-Scale Error ±10 LSB max Negative Full-Scale Error ±10 LSB max VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3 V 3 Input Voltage Range 2.875/3.125 V min/max Input Current ±1 mA max < 1 nA typ ANALOG OUTPUTS (V 0–15) OUT 3, 4 Output Temperature Coefficient 10 ppm/∞C typ of FSR 3 DC Output Impedance 0.5 W typ 5 Output Range AD5516-1 ±2.5 V typ 100 mA Output Load AD5516-2 ±5V typ 100 mA Output Load AD5516-3 ±10 V typ 100 mA Output Load 3, 6, 7 Resistive Load 5kW min 3, 6 Capacitive Load 200 pF 3 Short Circuit Current 7 mA typ 3 DC Power Supply Rejection Ratio –85 dB typ V = +12 V ± 5%, V = –12 V ± 5% DD SS 3 DC Crosstalk 0.1 LSB max 3 DIGITAL INPUTS Input Current ±10 mA max ±5 mA typ Input Low Voltage 0.8 V max DV = 5 V ± 5% CC 0.4 V max DV = 3 V ± 10% CC Input High Voltage 2.4 V min DV = 5 V ± 5% CC 2V min DV = 3 V ± 10% CC Input Hysteresis (SCLK and SYNC) 150 mV typ Input Capacitance 10 pF max 5 pF typ 3 DIGITAL OUTPUTS (BUSY, D ) OUT Output Low Voltage, DV = 5 V 0.4 V max Sinking 200 mA CC Output High Voltage, DV = 5 V 4 V min Sourcing 200 mA CC Output Low Voltage, DV = 3 V 0.4 V max Sinking 200 mA CC Output High Voltage, DV = 3 V 2.4 V min Sourcing 200 mA CC High Impedance Leakage Current (D only) ±1 mA max DCEN = 0 OUT High Impedance Output Capacitance (D only) 5 pF typ DCEN = 0 OUT POWER REQUIREMENTS Power Supply Voltages V 4.75/15.75 V min/max DD V –4.75/–15.75 V min/max SS AV 4.75/5.25 V min/max CC DV 2.7/5.25 V min/max CC 8 Power Supply Currents I 5 mA max 3.5 mA typ. All Channels Full-Scale. DD I 5 mA max 3.5 mA typ. All Channels Full-Scale. SS AI 17 mA max 13 mA typ CC DI 1.5 mA max 1 mA typ CC 8 Power-Down Currents I 1 mA typ DD I 1 mA typ SS AI 2 mA max 200 nA typ CC DI 2 mA max 200 nA typ CC 8 Power Dissipation 105 mW typ V = +5 V, V = –5 V DD SS NOTES 1 See Terminology section. 2 A Version: Industrial temperature range –40∞C to +85∞C; typical at +25∞C. 3 Guaranteed by design and characterization; not production tested. 4 AD780 as reference for the AD5516. 5 Output range is restricted from V + 2 V to V – 2 V. Output span varies with reference voltage and is functional down to 2 V. SS DD 6 Ensure that you do not exceed T . See Absolute Maximum Ratings section. J (MAX) 7 With 5 kW resistive load, footroom required is as follows: AD5516–1, 2 V; AD5516–2, 2.5 V; AD5516–3, 3 V. 8 Outputs unloaded. Specifications subject to change without notice. –2– REV. B AD5516 (V = +4.75 V to +13.2 V, V = –4.75 V to –13.2 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; DD SS CC CC AC CHARACTERISTICS AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded. All specifications T to T , unless otherwise noted.) MIN MAX 1, 2 3 Parameter A Version Unit Conditions/Comments 4 Output Voltage Settling Time (Mode 1) 100 pF, 5 kW Load Full-Scale Change AD5516–1 32 �s max AD5516–2 32 �s max AD5516–3 36 �s max 4 Output Voltage Settling Time (Mode 2) 100 pF, 5 kW Load, 127 Code Increment AD5516–1 2.5 �s max AD5516–2 3.35 �s max AD5516–3 7 �s max Slew Rate 0.85 V/�s typ Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry Digital Crosstalk 5 nV-s typ Analog Crosstalk AD5516–1 1 nV-s typ AD5516–2 5 nV-s typ AD5516–3 20 nV-s typ Digital Feedthrough 1 nV-s typ Output Noise Spectral Density @ 10 kHz 1/2 AD5516–1 150 nV/(Hz) typ 1/2 AD5516–2 350 nV/(Hz) typ 1/2 AD5516–3 700 nV/(Hz) typ NOTES 1 See Terminology section. 2 Guaranteed by design and characterization; not production tested. 3 A version: Industrial temperature range –40∞C to +85∞C. 4 Timed from the end of a write sequence and includes BUSY low time. Specifications subject to change without notice. (V = +4.75 V to +13.2 V, V = – 4.75 V to –13.2 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; DD SS CC CC TIMING CHARACTERISTICS AGND = DGND = DACGND = 0 V. All specifications T to T , unless otherwise noted.) MIN MAX Limit at T , T MIN MAX 1, 2, 3 Parameter (A Version) Unit Conditions/Comments f 32 kHz max DAC Update Rate (Mode 1) UPDATE1 f 750 kHz max DAC Update Rate (Mode 2) UPDATE2 f 20 MHz max SCLK Frequency CLKIN t 20 ns min SCLK High Pulsewidth 1 t 20 ns min SCLK Low Pulsewidth 2 t 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 3 t 5 ns min D Setup Time 4 IN t 5 ns min D Hold Time 5 IN t 0 ns min SCLK Falling Edge to SYNC Rising Edge 6 t 10 ns min Minimum SYNC High Time (Standalone Mode) 7 t 400 ns min Minimum SYNC High Time (Daisy-Chain Mode) 7MODE2 t 10 ns min BUSY Rising Edge to SYNC Falling Edge 8MODE1 t 200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode) 9MODE2 t 10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode) 10 4 t 20 ns max SCLK Rising Edge to D Valid (Daisy-Chain Mode) 11 OUT t 20 ns min RESET Pulsewidth 12 NOTES 1 See Timing Diagrams in Figures 1 and 2. 2 Guaranteed by design and characterization; not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of (V + V )/2. CC IL IH 4 This is measured with the load circuit of Figure 3. Specifications subject to change without notice. REV. B –3– AD5516 TIMING DIAGRAMS SCLK 12 17 18 t 3 t t 2 1 t t 6 7 SYNC t MODE2 t 4 9 t 5 MSB LSB DIN BIT 17 BIT 0 t MODE1 8 BUSY t 12 RESET Figure 1. Serial Interface Timing Diagram SCLK t 3 t t t 2 1 10 t MODE2 7 t 6 SYNC t 4 t MSB 5 LSB D IN BIT 17 BIT 0 BIT 17 BIT 0 INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N+1 t 11 D BIT 17 BIT 0 OUT t MODE1 UNDEFINED INPUT WORD FOR DEVICE N 8 BUSY Figure 2. Daisy-Chaining Timing Diagram I 200�A OL TO OUTPUT 1.6V PIN C L 50pF 200�A I OH Figure 3. Load Circuit for D Timing Specifications OUT –4– REV. B AD5516 1, 2 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C (T = 25°C, unless otherwise noted.) Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . 150°C A J MAX V to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V 74-Lead CSPBGA Package, � Thermal Impedance . . . 41°C/W DD JA V to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V Reflow Soldering SS AV to AGND, DACGND . . . . . . . . . . . . . . .–0.3 V to +7 V Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C CC DV to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec CC Digital Inputs to DGND . . . . . . . . . . . –0.3 V to DV + 0.3 V CC NOTES 1 Digital Outputs to DGND . . . . . . . . . . –0.3 V to DV + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent CC damage to the device. This is a stress rating only; functional operation of the device REF_IN to AGND, DACGND . . . . . . –0.3 V to AV + 0.3 V CC at these or any other conditions above those listed in the operational sections of this V 0–15 to AGND . . . . . . . . . . . . V – 0.3 V to V + 0.3 V OUT SS DD specification is not implied. Exposure to absolute maximum rating conditions for AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V extended periods may affect device reliability. 2 R 0–15 to AGND . . . . . . . . . . . . . V – 0.3 V to V +0.3 V FB SS DD Transient currents of up to 100 mA will not cause SCR latch-up. Operating Temperature Range, Industrial . . . . . –40°C to +85°C ORDERING GUIDE Model Function Output Voltage Span Package Option AD5516ABC-1 16 DACs ±2.5 V 74-Lead CSPBGA AD5516ABC-2 16 DACs ±5 V 74-Lead CSPBGA AD5516ABC-3 16 DACs ±10 V 74-Lead CSPBGA EVAL-AD5516-1EB Evaluation Board EVAL-AD5516-2EB Evaluation Board EVAL-AD5516-3EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– AD5516 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E F TOP VIEW F G G H H J J K K LL 1 2 3 4 5 6 7 8 9 10 11 74-LEAD CSPBGA BALL CONFIGURATION CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball Number Name Number Name Number Name Number Name Number Name K9 R 10 D11 NC H10 V 13 A1 NC B5 DGND FB OUT 9 E1 V 1 K10 R A2 NC B6 DGND H11 V 12 FB OUT OUT K11 V 11 A3 RESET B7 NC E2 NC J1 R 3 OUT FB E10 AGND1 L1 NC A4 BUSY B8 NC J2 V 4 OUT L2 V 6 E11 PD A5 DGND B9 SCLK J6 NC OUT L3 R 6 2 A6 DV B10 NC F1 V J10 R 12 FB OUT CC FB L4 V 7 F2 R 1 A7 D B11 REF_IN J11 R 11 OUT OUT FB FB L5 NC A8 D C1 V 0 F10 AGND2 K1 R 4 IN OUT FB L6 V 2 A9 SYNC C2 DACGND F11 R 14 K2 V 5 DD FB OUT L7 V 1 A10 NC C6 NC G1 R 2 K3 R 5 DD FB FB L8 R 7 1 15 A11 NC C10 AV G2 R K4 NC FB CC FB L9 V 8 B1 NC C11 NC G10 V 14 K5 V 2 OUT OUT SS L10 R 8 B2 NC D1 R 0 G11 R 13 K6 V 1 FB FB FB SS L11 NC B3 NC D2 DACGND H1 V 3 K7 V 10 OUT OUT B4 DCEN D10 AV 2 K8 V 9 H2 V 15 CC OUT OUT NC = Not Internally Connected PIN FUNCTION DESCRIPTIONS Mnemonic Function AGND (1–2) Analog GND Pins AV (1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. CC V (1–2) V Supply Pins. Voltage range from 4.75 V to 15.75 V. DD DD V (1–2) V Supply Pins. Voltage range from –4.75 V to –15.75 V. SS SS DGND Digital GND Pins DV Digital Supply Pin. Voltage range from 2.7 V to 5.25 V. CC DACGND Reference GND Supply for All 16 DACs REF_IN Reference Input Voltage for All 16 DACs. The recommended value of REF_IN is 3 V. V (0–15) Analog Output Voltages from the 16 DAC Channels OUT R (0–15) Feedback Resistors. For nominal output voltage range, connect each R to its corresponding V . Access to FB FB OUT the feedback resistors enables the user to increase the DAC current drive or generate programmable current sources. They should not be used for gain adjustment. SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. –6– REV. B AD5516 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Function SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 20 MHz. D Serial Data Input. Data must be valid on the falling edge of SCLK. IN D Serial Data Output. D can be used for daisy-chaining a number of devices together or for reading back the OUT OUT data in the shift register for diagnostic purposes. Data is clocked out on D on the rising edge of SCLK and is OUT valid on the falling edge of SCLK. 1 DCEN Active High Control Input. This pin is tied high to enable Daisy-Chain Mode. 2 RESET Active Low Control Input. This resets all DAC registers to power-on value. 1 PD Active High Control Input. All DACs go into power-down mode when this pin is high. The DAC outputs go into a high impedance state. BUSY Active Low Output. This signal tells the user that the analog calibration loop is active. It goes low during conversion. The duration of the pulse on BUSY determines the maximum DAC update rate, f . Further writes to the UPDATE AD5516 are ignored while BUSY is active. NOTES 1 Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition. 2 Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition. TERMINOLOGY DC Crosstalk Integral Nonlinearity (INL) This is the dc change in the output level of one DAC at midscale This is a measure of the maximum deviation from a straight line in response to a full-scale code change (all 0s to all 1s and vice passing through the endpoints of the DAC transfer function. It is versa) and output change of another DAC. It is expressed in LSB. expressed in LSBs. Output Settling Time Differential Nonlinearity (DNL) This is the time taken from when the last data bit is clocked into Differential nonlinearity (DNL) is the difference between the the DAC until the output has settled to within ±0.5 LSB of its measured change and the ideal 1 LSB change between any two final value (see TPC 7). adjacent codes. A specified DNL of –1 LSB maximum ensures Digital-to-Analog Glitch Impulse monotonicity. This is the area of the glitch injected into the analog output when Bipolar Zero Error the code in the DAC register changes state. It is specified as the Bipolar zero error is the deviation of the DAC output from the ideal area of the glitch in nV-s when the digital code is changed by midscale of 0 V. It is measured with 10...00 loaded to the DAC. 1 LSB at the major carry transition (011...11 to 100...00 or It is expressed in LSBs. 100...00 to 011...11). Positive Full-Scale Error Digital Crosstalk This is the error in the DAC output voltage with all 1s loaded to This is the glitch impulse transferred to the output of one DAC at the DAC. Ideally the DAC output voltage, with all 1s loaded to the midscale while a full-scale code change (all 1s to all 0s and vice DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB versa) is being written to another DAC. It is expressed in nV-s. (AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs. Analog Crosstalk Negative Full-Scale Error This is the area of the glitch transferred to the output (V ) of OUT This is the error in the DAC output voltage with all 0s loaded to one DAC due to a full-scale change in the output (V ) of OUT the DAC. Ideally the DAC output voltage, with all 0s loaded to the another DAC. The area of the glitch is expressed in nV-s. DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2), Digital Feedthrough and –10 V (AD5516-3). It is expressed in LSBs. This is a measure of the impulse injected into the analog outputs Output Temperature Coefficient from the digital control inputs when the part is not being written This is a measure of the change in analog output with changes in to, i.e., SYNC is high. It is specified in nV-s and measured with temperature. It is expressed in ppm/∞C of FSR. a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa. DC Power Supply Rejection Ratio DC power supply rejection ratio (PSRR) is a measure of the change Output Noise Spectral Density in analog output for a change in supply voltage (V and V ). This is a measure of internally generated random noise. Random DD SS It is expressed in dB. V and V are varied ±5%. noise is characterized as a spectral density (voltage per root hertz). DD SS 1/2 It is measured in nV/(Hz) . REV. B –7– AD5516–Typical Performance Characteristics 1.0 1.0 2.0 REF_IN = 3V REF_IN = 3V REF_IN = 3V T = 25�C T = 25�C 0.8 0.8 A A 1.5 0.6 0.6 1.0 INL 0.4 0.4 0.5 0.2 0.2 +VE DNL 0 0 0 –0.2 –0.2 –0.5 –VE –0.4 –0.4 DNL –1.0 –0.6 –0.6 –1.5 –0.8 –0.8 –1.0 –1.0 –2.0 0 1000 2000 3000 4000 0 1000 2000 3000 4000 –40 –20 0 20 40 60 80 DAC CODE DAC CODE TEMPERATURE (�C) TPC 2. Typical INL Plot TPC 1. Typical DNL Plot TPC 3. Typical INL Error and DNL Error vs. Temperature 3 0.003 0.01 AV = +12V DD AV = +12V REF_IN = 3V DD 0.008 AV = –12V AV = –12V SS SS 2 0.002 REF_IN = 3V 0.006 REF_IN = 3V T = 25�C MIDSCALE LOADED A 0.004 1 0.001 BIPOLAR ZERO ERROR 0.002 0 0 0.0 –0.002 MIDSCALE –1 –0.001 –0.004 NEGATIVE FS ERROR –0.006 –2 –0.002 POSITIVE FS ERROR –0.008 –0.003 –3 –0.01 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 –8 –6 –4 –2 0 2 4 6 8 CURRENT (mA) TEMPERATURE (�C) TEMPERATURE (�C) TPC 5. V vs. Temperature TPC 4. Bipolar Zero Error and TPC 6. V Source and Sink OUT OUT Full-Scale Error vs. Temperature Capability 3.0 –0.029 T = 25�C T = 25�C A T = 25�C A A REF_IN = 3V REF_IN = 3V REF_IN = 3V 2.0 NEW –0.030 VALUE 5V/DIV 1.0 PD CALIBRA TION TIME 0 2V/DIV –0.031 V OUT OLD VALUE –1.0 2.5�s/DIV TIME BASE = 2.5�s/DIV 2�s/DIV –0.032 –2.0 5V 0V BUSY –3.0 –0.033 TPC 7. AD5516–1 Full-Scale TPC 8. Exiting Power-Down to TPC 9. AD5516–1 Major Code Settling Time Full Scale Transition Glitch Impulse –8– REV. B DNL ERROR (LSB) V ( V) OUT ERROR (LSB) V (V) OUT INL ERROR (LSB) V (V) OUT ERROR (LSB) AD5516 450 40 40 REF_IN = 3V REF_IN = 3V T = 25�C T = 25�C 400 A A 350 300 250 20 20 200 150 100 50 0 0 0 –10 0 10 –10 0 10 2.4893 2.4896 2.4899 LSBs LSBs V (V) OUT TPC 10. AD5516–1 V Repeatability; TPC 11. Bipolar Error Distribution TPC 12. Positive Full-Scale OUT Programming the Same Code Error Distribution Multiple Times 30 2.5 6 REF_IN = 3V REF_IN = 3V REF_IN = 3V T = 25�C T = 25�C A A T = 25�C A 5 2.0 20 4 1.5 3 1.0 10 2 0.5 1 0 0 0 –10 0 10 020 40 6080 100 120 130 0 500 1000 1500 2000 2500 3000 3500 4000 LSBs STEP SIZE CODE TPC 15. Accuracy vs. Increment TPC 13. Negative Full-Scale Error TPC 14. Accuracy vs. Increment Step Step, Using All 12 Mode 2 Bits Distribution REV. B –9– FREQUENCY (%) FREQUENCY ERROR (LSB) FREQUENCY (%) FREQUENCY (%) ERROR (LSB) AD5516 FUNCTIONAL DESCRIPTION Where: The AD5516 consists of sixteen 12-bit DACs in a single pack- D = decimal equivalent of the binary code that is loaded to age. A single reference input pin (REF_IN) is used to provide a the DAC register, i.e., 0–4095 3V reference for all 16 DACs. To update a DAC’s output N = DAC resolution = 12 voltage, the required DAC is addressed via the 3-wire serial Table I illustrates ideal analog output versus DAC code. interface. Once the serial write is complete, the selected DAC converts the code into an output voltage. The output amplifiers Table I. DAC Register Contents AD5516-1 translate the DAC output range to give the appropriate voltage range (±2.5 V, ±5 V, or ±10 V) at output pins V 0 to V 15. OUT OUT MSB LSB Analog Output, V OUT The AD5516 uses a self-calibrating architecture to achieve 12-bit 1111 1111 1111 V ¥ 2.5/3 – 1 LSB REF_IN performance. The calibration routine servos to select the appro- 1000 0000 0000 0 V priate voltage level on an internal 14-bit resolution DAC. BUSY 0000 0000 0000 –V ¥ 2.5/3 REF_IN output goes low for the duration of the calibration and further writes to the AD5516 are ignored while BUSY is low. BUSY low time is typically 25 ms. Noise during the calibration (BUSY MODES OF OPERATION low period) can result in the selection of a voltage within a The AD5516 has two modes of operation. ±0.25 LSB band around the normal selected voltage. See TPC 10. Mode 1 (MODE bits = 00): The user programs a 12-bit data- It is essential to minimize noise on REFIN for optimal perfor- word to one of 16 channels via the serial interface. This word is mance. The AD780’s specified decoupling makes it the ideal loaded into the addressed DAC register and is then converted reference to drive the AD5516. into an analog output voltage. During conversion, the BUSY output is low and all SCLK pulses are ignored. At the end of a Upon power-on, all DACs power up to a reset value (see the conversion BUSY goes high, indicating that the update of the RESET section). addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. Mode 1 conversion takes 25ms typ. DIGITAL-TO-ANALOG SECTION The architecture of each DAC channel consists of a resistor Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the string DAC followed by an output buffer amplifier with offset user to increment or decrement the DAC output in 0.25 LSB steps, and gain. The voltage at the REF_IN pin provides the reference resulting in a 14-bit monotonic DAC. The amount by which the voltage for all 16 DACs. The input coding to the DACs is offset DAC output is incremented or decremented is determined by binary; this results in ideal output voltages as follows: Mode 2 bits DB11–DB0, e.g., for a 0.25 LSB increment/decrement DB11...DB0 = 0000 0000 0001, while for a 2.5 LSB increment/ 22 ¥¥VD .5¥V ¥25 . REF__ IN REF IN decrement, DB11...DB0 = 0000 0000 1010. The MODE bits V = – AD5516-1: OUT N 3 determine whether the DAC data is incremented (01) or dec- 32 ¥ remented (10). The maximum amount that the user is allowed to increment or decrement the DAC output is 4095 steps of 42 ¥¥VD .5¥22V ¥ .5 REF__ IN REF IN V = – AD5516-2: OUT 0.25 LSB, i.e., DB11...DB0 = 1111 1111 1111. Mode 2 update N 3 32 ¥ takes approximately 1 ms. The Mode 2 feature allows increased resolution, but overall increment/decrement accuracy varies with 82 ¥¥VD .5¥42V ¥ .5 REF__ IN REF IN increment/decrement step as shown in TPC 14 and TPC 15. V = – AD5516-3: OUT N 3 32 ¥ Mode 2 is useful in applications where greater resolution is required, for example, in servo applications requiring fine-tune to 14-bit resolution. MSB LSB 00 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MODE ADDRESS DATA BITS BITS BITS Figure 4. Mode 1 Data Format MSB LSB 01 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MODE ADDRESS 12 INCREMENT BITS BITS BITS MSB LSB 10 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MODE ADDRESS 12 DECREMENT BITS BITS BITS Figure 5. Mode 2 Data Format –10– REV. B AD5516 The user must allow 200 ns (min) between two consecutive SYNC must be taken high and low again for further serial data Mode 2 writes in Standalone Mode and 400 ns (min) between transfer. SYNC may be taken high after the falling edge of the two consecutive Mode 2 writes in Daisy-Chain Mode. During a 18th SCLK pulse, observing the minimum SCLK falling edge Mode 2 operation the BUSY signal remains high. to SYNC rising edge time, t . If SYNC is taken high before the 6 18th falling edge of SCLK, the data transfer will be aborted and See Figures 4 and 5 for Mode 1 and Mode 2 data formats. the addressed DAC will not be updated. See the timing diagram When MODE bits = 11, the device is in No Operation mode. in Figure 1. This may be useful in daisy-chain applications where the user Daisy-Chain Mode (DCEN = 1) does not wish to change the settings of the DACs. Simply write In Daisy-Chain Mode, the internal gating on SCLK is disabled. 11 to the MODE bits and the following address and data bits The SCLK is continuously applied to the input shift register will be ignored. when SYNC is low. If more than 18 clock pulses are applied, the data ripples out of the shift register and appears on the D OUT SERIAL INTERFACE line. This data is clocked out on the rising edge of SCLK and is The AD5516 has a 3-wire interface that is compatible with valid on the falling edge. By connecting this line to the D IN SPI/QSPI/MICROWIRE, and DSP interface standards. Data is input on the next device in the chain, a multidevice interface is written to the device in 18-bit words. This 18-bit word consists constructed. Eighteen clock pulses are required for each device of two mode bits, four address bits, and 12 data bits as shown in the system. Therefore, the total number of clock cycles must in Figure 4. equal 18N, where N is the total number of devices in the chain. The serial interface works with both a continuous and burst See the timing diagram in Figure 2. clock. The first falling edge of SYNC resets a counter that counts When the serial transfer to all devices is complete, SYNC should the number of serial clocks to ensure the correct number of bits be taken high. This prevents any further data being clocked into the is shifted in and out of the serial shift registers. In order for input shift register. A burst clock containing the exact number of another serial transfer to take place, the counter must be reset clock cycles may be used and SYNC taken high some time later. by the falling edge of SYNC. After the rising edge of SYNC, data is automatically transferred A3–A0 from each device’s input shift register to the addressed DAC. Four address bits (A3 = MSB Address, A0 = LSB). These are RESET Function used to address one of 16 DACs. The RESET function on the AD5516 can be used to reset all nodes on this device to their power-on reset condition. This is Table II. Selected DAC implemented by applying a low going pulse of 20 ns minimum A3 A2 A1 A0 Selected DAC to the RESET Pin on the device. 0 000 DAC 0 Table III. Typical Power-On Values 0 001 DAC 1 : ::: Device Output Voltage 1 111 DAC 15 AD5516-1 –0.073 V AD5516-2 –0.183 V DB11–DB0 AD5516-3 –0.391 V These are used to write a 12-bit word into the addressed DAC register. Figures 1 and 2 show the timing diagram for a write BUSY Output cycle to the AD5516. During conversion, the BUSY output is low and all SCLK pulses SYNC FUNCTION are ignored. At the end of a conversion, BUSY goes high indi- In both Standalone and Daisy-Chain Modes, SYNC is an edge- cating that the update of the addressed DAC is complete. It is triggered input that acts as a frame synchronization signal and recommended that SCLK is not pulsed while BUSY is low. chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be MICROPROCESSOR INTERFACING taken low observing the minimum SYNC falling to SCLK falling The AD5516 is controlled via a versatile 3-wire serial interface edge setup time, t . that is compatible with a number of microprocessors and DSPs. 3 Standalone Mode (DCEN = 0) AD5516 to ADSP-2106x SHARC DSP Interface After SYNC goes low, serial data will be shifted into the device’s The ADSP-2106x SHARC DSPs are easily interfaced to the input shift register on the falling edges of SCLK for 18 clock AD5516 without the need for extra logic. pulses. After the falling edge of the 18th SCLK pulse, data will The AD5516 expects a t (SYNC falling edge to SCLK falling 3 automatically be transferred from the input shift register to the edge setup time) of 15 ns min. Consult the ADSP-2106x User addressed DAC. Manual for information on clock and frame sync frequencies for the SPORT Register and contents of the TDIV and RDIV Registers. REV. B –11– AD5516 A data transfer is initiated by writing a word to the TX Register AD5516 to PIC16C6x/7x after the SPORT has been enabled. In write sequences, data is The PIC16C6x/7x synchronous serial port (SSP) is configured clocked out on each rising edge of the DSP’s serial clock and as an SPI master with the Clock Polarity Bit (CKP) = 0. This is clocked into the AD5516 on the falling edge of its SCLK. The done by writing to the Synchronous Serial Port Control Register SPORT transmit control register should be set up as follows: (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to provide a SYNC signal DTYPE = 00, Right Justify Data and enable the serial port of the AD5516. This microcontroller ICLK = 1, Internal Serial Clock transfers only eight bits of data during each serial transfer opera- TFSR = 1, Frame Every Word tion; therefore, three consecutive write operations are required. INTF = 1, Internal Frame Sync Figure 8 shows the connection diagram. LTFS = 1, Active Low Frame Sync Signal LAFS = 0, Early Frame Sync PIC16C6x/7x* AD5516* SENDN = 0, Data Transmitted MSB First SLEN = 10011, 18-Bit Data-Words (SLEN = Serial Word) SCLK SCK/RC3 Figure 6 shows the connection diagram. D SDI/RC4 IN RA1 SYNC ADSP-2106x* AD5516* *ADDITIONAL PINS OMITTED FOR CLARITY TFS SYNC Figure 8. AD5516 to PIC16C6x/7x Interface D DT IN AD5516 to 8051 SCLK SCLK A serial interface between the AD5516 and the 80C51/80L51 *ADDITIONAL PINS OMITTED FOR CLARITY microcontroller is shown in Figure 9. The AD5516 requires a clock synchronized to the serial data. The 8051 serial interface Figure 6. AD5516 to ADSP-2106x Interface must therefore be operated in Mode 0. TxD of the microcon- AD5516 to MC68HC11 troller drives the SCLK of the AD5516, while RxD drives the The serial peripheral interface (SPI) on the MC68HC11 is serial data line. P1.1 is a bit programmable pin on the serial port configured for Master Mode (MSTR = 1), Clock Polarity Bit that is used to drive SYNC. The 80C51/80L51 provides the (CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is LSB first, while the AD5516 expects MSB of the 18-bit word configured by writing to the SPI Control Register (SPCR)—see first. Care should be taken to ensure the transmit routine takes the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK this into account. of the AD5516, the MOSI output drives the serial data line (D ) of the AD5516. The SYNC signal is derived from a port IN 8051* AD5516* line (PC7). When data is being transmitted to the AD5516, the SCLK TxD SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the D RxD IN 68HC11 is transmitted in 8-bit bytes with only eight falling P1.1 SYNC clock edges occurring in the transmit cycle. Data is transmitted *ADDITIONAL PINS OMITTED FOR CLARITY MSB first. In order to transmit 18 data bits, it is important to left justify the data in the SPDR Register. PC7 must be pulled Figure 9. AD5516 to 8051 Interface low to start a transfer and taken high and low again before any When data is to be transmitted to the DAC, P1.1 is taken low. further read/write cycles can take place. A connection diagram is Data on RxD is valid on the falling edge of TxD, so the clock shown in Figure 7. must be inverted as the AD5516 clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 MC68HC11* AD5516* transmits its data in 8-bit bytes with only eight falling clock edges PC7 SYNC occurring in the transmit cycle. As the DAC requires an 18-bit word, P1.1 must be left low after the first eight bits are transferred SCLK SCK and brought high after the complete 18 bits have been transferred. D MOSI IN DOUT may be tied to RxD for data verification purposes when *ADDITIONAL PINS OMITTED FOR CLARITY the device is in Daisy-Chain Mode. Figure 7. AD5516 to MC68HC11 Interface –12– REV. B AD5516 APPLICATION CIRCUITS so that the DAC output has enough headroom to drive the The AD5516 is suited for use in many applications, such as level BJT ~ 0.7 V above the maximum output voltage. setting, optical, industrial systems, and automatic test applications. V DD In level setting and servo applications where a fine-tune adjust is required, the Mode 2 function increases resolution. The following figures show the AD5516 used in some potential applications. V AD5516 in a Typical ATE System DD AD5516-1 The AD5516 is ideally suited for the level setting function in V DAC 0 V automatic test equipment. A number of DACs are required to OUT control pin drivers, comparators, active loads, parametric mea- R 0 FB X surement units, and signal timing. Figure 10 shows the AD5516 in such a system. V = – 2.5V TO +2.5V x R DAC PARAMETRIC MEASUREMENT SYSTEM BUS V SS UNIT ACTIVE DAC LOAD Figure 12. AD5516 in a High Current Circuit DAC Note it is not intended that the R nodes be used to alter FB amplifier gain or for force/sense in remote sense applications. DRIVER STORED DATA AND DAC INHIBIT POWER SUPPLY DECOUPLING PATTERN FORMATTER In any circuit where accuracy is important, careful consideration DUT of the power supply and ground return layout helps to ensure the DAC rated performance. The printed circuit board on which the AD5516 PERIOD GENERATION is mounted should be designed so that the analog and digital AND DAC DELAY sections are separated and confined to certain areas of the board. If TIMING COMPARE the AD5516 is in a system where multiple devices require an REGISTER DAC AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as DACs SYSTEM BUS COMPARATOR close as possible to the device. For supplies with multiple pins (AV 1, AV 2), it is recommended to tie those pins together. The CC CC Figure 10. AD5516 in an ATE System AD5516 should have ample supply bypassing of 10 mF in parallel with 0.1 mF on each supply located as closely to the package as AD5516 in an Optical Network Control Loop possible, ideally right up against the device. The 10mF capacitors The AD5516 can be used in optical network control applica- are the tantalum bead type. The 0.1 mF capacitor should have low tions that require a large number of DACs to perform a control effective series resistance (ESR) and effective series inductance and measurement function. In the example shown in Figure 11, (ESI), like the common ceramic types that provide a low impedance the outputs of the AD5516 are fed into amplifiers and used to path to ground at high frequencies, to handle transient currents control actuators that determine the position of MEMS mirrors due to internal logic switching. in an optical switch. The exact position of each mirror is measured and the readings are multiplexed into an 8-channel, 14-bit ADC The power supply lines of the AD5516 should use as large a trace (AD7865). The increment and decrement modes of the DACs are as possible to provide low impedance paths and reduce the effects useful in this application as they allow 14-bit resolution. of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating The control loop is driven by an ADSP-2106x, a 32-bit ® noise to other parts of the board, and should never be run near SHARC DSP. the reference inputs. A ground line routed between the D and IN SCLK lines will help reduce crosstalk between them (not required S E on a multilayer board as there will be a separate ground plane, but 0 0 0 MEMS N ADG609 separating the lines will help). It is essential to minimize noise S MIRROR AD5516 AD7865 � 2 O ARRAY on REFIN. 15 15 7 R S Avoid crossover of digital and analog signals. Traces on opposite AD8644 sides of the board should run at right angles to each other. This � 2 reduces the effects of feedthrough through the board. A micro- ADSP-2106x strip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of Figure 11. AD5516 in an Optical Control Loop the board is dedicated to ground plane while signal traces are AD5516 in a High Current Circuit placed on the solder side. Access to the feedback loop of the AD5516 amplifier provides As is the case for all thin packages, care must be taken to avoid greater flexibility, e.g., it enables the user to configure the device flexing the package and to avoid a point load on the surface of as a digitally programmable current source or increase the out- the package during the assembly process. put drive current. See Figure 12. Note that V must be chosen DD REV. B –13– AD5516 OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters A1 CORNER INDEX AREA 12.00 BSC SQ 11 10 9 8 7 6 5 4 3 2 1 A B A1 C D E 1.00 10.00 BSC BOTTOM TOP VIEW F BSC VIEW SQ G H J K L 1.00 BSC 1.70 DETAIL A MAX DETAIL A 0.30 MIN 0.20 MAX COPLANARITY 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1 –14– REV. B AD5516 Revision History Location Page 8/03—Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to Mode 2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8/02—Data Sheet changed from REV. 0 to REV. A. Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to DIGITAL-TO-ANALOG section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Added AD5516 in a High Current Circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Added Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REV. B –15– –16– C02792–0–8/03(B)