ANALOG DEVICES AD5453

8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5450/AD5451/AD5452/AD5453 FEATURES FUNCTIONAL BLOCK DIAGRAM 12 MHz multiplying bandwidth V V DD REF INL of ±0.25 LSB at 8-bit R FB 8-lead TSOT and MSOP packages R AD5450/ 2.5 V to 5.5 V supply operation AD5451/ 8-/10-/12-/14-BIT REF AD5452/ I 1 OUT Pin-compatible 8-/10-/12-/14-bit current output DACs R-2R DAC AD5453 ±10 V reference input 50 MHz serial interface DAC REGISTER 2.7 MSPS update rate POWER-ON Extended temperature range: –40°C to +125°C RESET 4-quadrant multiplication INPUT LATCH Power-on reset with brownout detect <0.4 μA typical current consumption SYNC CONTROL LOGIC Guaranteed monotonic AND INPUT SHIFT SCLK REGISTER SDIN Qualified for automotive applications GND APPLICATIONS Figure 1. Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION 1 The AD5450/AD5451/AD5452/AD5453 are CMOS 8-/10-/12-/ The applied external reference input voltage (VREF) determines 14-bit current output digital-to-analog converters, respectively. the full-scale output current. These parts can handle ±10 V These devices operate from a 2.5 V to 5.5 V power supply, inputs on the reference, despite operating from a single-supply making them suited to several applications, including battery- power supply of 2.5 V to 5.5 V. An integrated feedback resistor powered applications. (R ) provides temperature tracking and full-scale voltage FB output when combined with an external current-to-voltage As a result of manufacture on a CMOS submicron process, precision amplifier. these DACs offer excellent 4-quadrant multiplication characteristics of up to 12 MHz. The AD5450/AD5451/AD5452/AD5453 DACs are available in small 8-lead TSOT, and the AD5452/AD5453 are also available These DACs use a double-buffered, 3-wire serial interface that in MSOP packages. The AD5453 also comes in 8-lead LFCSP. is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. Upon power-up, the internal shift register The EVAL-AD5443SDZ/EVAL-AD5446SDZ/EVAL- and latches are filled with 0s, and the DAC output is at zero scale. AD5453SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. 1 U.S. Patent Number 5,689,257. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04587-001 AD5450/AD5451/AD5452/AD5453 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Section................................................................................ 16  Applications....................................................................................... 1  Circuit Operation ....................................................................... 16  Functional Block Diagram .............................................................. 1  Single-Supply Applications ....................................................... 18  General Description ......................................................................... 1  Adding Gain................................................................................ 18  Revision History ............................................................................... 2  Divider or Programmable Gain Element................................ 19  Specifications..................................................................................... 3  Reference Selection .................................................................... 19  Timing Characteristics ................................................................ 5  Amplifier Selection .................................................................... 19  Absolute Maximum Ratings............................................................ 6  Serial Interface ............................................................................ 21  ESD Caution.................................................................................. 6  Microprocessor Interfacing....................................................... 22  Pin Configurations and Function Descriptions ........................... 7  PCB Layout and Power Supply Decoupling ........................... 24  Typical Performance Characteristics ............................................. 8  Outline Dimensions....................................................................... 26  Terminology .................................................................................... 15  Ordering Guide .......................................................................... 27  General Description ....................................................................... 16  Automotive Products................................................................. 27  REVISION HISTORY 1/10—Rev. B to Rev. C 4/12—Rev. E to Rev. F Changes to DAC Control Bits C1, C0.......................................... 21 Changes to General Description Section ...................................... 1 Updated Outline Dimensions....................................................... 27 Deleted Evaluation Board for the DAC Section, Power Supplies Changes to Ordering Guide .......................................................... 28 for the Evaluation Board Section, and Figure 64; Renumbered Sequentially.............................................................. 25 3/06—Rev. A to Rev. B Deleted Figure 65 and Figure 66................................................... 26 Updated Format..................................................................Universal Deleted Figure 67............................................................................ 27 Changes to Features ..........................................................................1 Changes to Ordering Guide .......................................................... 27 Changes to General Description .....................................................1 Changes to Specifications.................................................................4 3/11—Rev. D to Rev. E Changes to Figure 27 and Figure 28............................................. 11 Changes to Function Section ............................................ 21 SYNC Change to Table 9 ........................................................................... 20 Added Figure 54 (Renumbered Sequentially) ............................ 21 Changes to Table 12 ....................................................................... 26 Added Figure 55 and Table 11 ..................................................... 22 Updated Outline Dimensions....................................................... 27 Changes to Ordering Guide .......................................................... 28 2/11—Rev. C to Rev. D Added 8-Lead LFCSP.........................................................Universal 7/05—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added AD5453 ...................................................................Universal Updated Outline Dimensions ....................................................... 27 Changes to Specifications.................................................................4 Changes to Ordering Guide .......................................................... 28 Change to Figure 21 ....................................................................... 10 Added Automotive Products Section .......................................... 28 Updated Outline Dimensions....................................................... 27 Changes to Ordering Guide .......................................................... 28 1/05—Revision 0: Initial Version Rev. F | Page 2 of 28 Data Sheet AD5450/AD5451/AD5452/AD5453 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE AD5450 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Total Unadjusted Error ±0.5 LSB Gain Error ±0.25 LSB AD5451 Resolution 10 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Total Unadjusted Error ±0.5 LSB Gain Error ±0.25 LSB AD5452 Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error ±1 LSB Gain Error ±0.5 LSB AD5453 Resolution 14 Bits Relative Accuracy ±2 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Total Unadjusted Error ±4 LSB Gain Error ±2.5 LSB 1 Gain Error Temperature Coefficient ±2 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, T = 25°C, I 1 A OUT ±10 nA Data = 0x0000, T = −40°C to +125°C, I 1 A OUT 1 REFERENCE INPUT Reference Input Range ±10 V V Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C REF R Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C FB Input Capacitance Zero-Scale Code 18 22 pF Full-Scale Code 18 22 pF 1 DIGITAL INPUTS/OUTPUTS Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V 1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 μA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, I ±1 nA T = 25°C IL A ±10 nA T = −40°C to +125°C A Input Capacitance 10 pF Rev. F | Page 3 of 28 AD5450/AD5451/AD5452/AD5453 Data Sheet Parameter Min Typ Max Unit Test Conditions 1 DYNAMIC PERFORMANCE Reference-Multiplying BW 12 MHz VREF = ±3.5 V, DAC loaded with all 1s Multiplying Feedthrough Error VREF = ±3.5 V, DAC loaded with all 0s 72 dB 100 kHz 64 dB 1 MHz 44 dB 10 MHz Output Voltage Settling Time VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 100 110 ns Measured to ±4 mV of FS 24 40 ns Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 10 30 ns Rise and fall times, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V Output Capacitance I 1 13 pF DAC latches loaded with all 0s OUT 28 pF DAC latches loaded with all 1s IOUT2 18 pF DAC latches loaded with all 0s 5 pF DAC latches loaded with all 1s Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 83 dB V = 3.5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 1 MHz, V = 3.5 V REF 50 kHz fOUT 71 dB 20 kHz fOUT 77 dB Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 1 MHz, V = 3.5 V REF 50 kHz fOUT 78 dB 20 kHz f 74 dB OUT SFDR Performance (Narrow Band) Clock = 1 MHz, V = 3.5 V REF 50 kHz fOUT 87 dB 20 kHz fOUT 85 dB Intermodulation Distortion 79 dB f = 20 kHz, f = 25 kHz, clock = 1 MHz, V = 3.5 V 1 2 REF POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.4 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD 0.6 μA T = 25°C, logic inputs = 0 V or V A DD 1 Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization, not subject to production test. Rev. F | Page 4 of 28 Data Sheet AD5450/AD5451/AD5452/AD5453 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter VDD = 2.5 V to 5.5 V Unit Description fSCLK 50 MHz max Maximum clock frequency t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t 8 ns min SCLK low time 3 t 8 ns min SYNC falling edge to SCLK active edge setup time 4 t 5 ns min Data setup time 5 t6 4.5 ns min Data hold time t7 5 ns min SYNC rising edge to SCLK active edge t 30 ns min Minimum SYNC high time 8 Update Rate 2.7 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. t 1 SCLK t t 2 3 t 8 t 7 SYNC t 6 t 5 DIN DB15 DB0 Figure 2. Timing Diagram Rev. F | Page 5 of 28 t 4 04587-002 AD5450/AD5451/AD5452/AD5453 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 3. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect VREF, RFB to GND −12 V to +12 V device reliability. IOUT1 to GND −0.3 V to +7 V Input Current to Any Pin Except Supplies ±10 mA 1 Logic Inputs and Output −0.3 V to V + 0.3 V DD ESD CAUTION Operating Temperature Range, Extended −40°C to +125°C (Y Version) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 8-Lead MSOP 206°C/W 8-Lead TSOT 211°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. Rev. F | Page 6 of 28 Data Sheet AD5450/AD5451/AD5452/AD5453 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS I 1 1 8R R 1 8 I 1 OUT FB FB OUT AD5450/ AD5453 V 2 7 GND AD5451/ REF GND 2 7V REF AD5452/ TOP VIEW V 3 6 SCLK DD SCLK 3 (Not to Scale) 6V AD5453 DD SYNC 4 5 SDIN 5SYNC SDIN 4 Figure 3. 8-Lead TSOT Pin Configuration NOTES 1. THE EXPOSED PAD MUST BE I 1 1 8 R OUT FB CONNECTED TO GROUND. GND 2 7 V REF AD5452/ Figure 5. 8-Lead LFCSP Pin Configuration SCLK 3 6 V AD5453 DD SDIN 4 5 SYNC Figure 4. 8-Lead MSOP Pin Configuration Table 4. Pin Function Descriptions 1 Pin No TSOT MSOP LFCSP Mnemonic Description 1 8 8 R DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external FB amplifier output. 2 7 7 V DAC Reference Voltage Input. REF 3 6 6 VDD Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V. 4 5 5 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the shift register upon the active edge of the following clocks. 5 4 4 SDIN Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial clock input. By default, in power-up mode data is clocked into the shift register upon the falling edge of SCLK. The control bits allow the user to change the active edge to a rising edge. 6 3 3 SCLK Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register upon the rising edge of SCLK. 7 2 2 GND Ground Pin. 8 1 1 I 1 DAC Current Output. OUT N/A N/A EPAD EPAD Exposed pad must be connected to ground. 1 N/A = not applicable. Rev. F | Page 7 of 28 04587-004 04587-003 04587-205 AD5450/AD5451/AD5452/AD5453 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.25 2.0 T = 25°C T = 25°C A A V = 10V V = 10V 0.20 REF 1.6 REF V = 5V V = 5V DD DD 0.15 1.2 0.10 0.8 0.05 0.4 0 0 –0.05 –0.4 –0.10 –0.8 –0.15 –1.2 –0.20 –1.6 –0.25 –2.0 0 32 64 96 128 160 192 224 256 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 6. INL vs. Code (8-Bit DAC) Figure 9. INL vs. Code (14-Bit DAC) 0.25 0.5 T = 25°C T = 25°C A A V = 10V V = 10V 0.20 REF 0.4 REF V = 5V V = 5V DD DD 0.15 0.3 0.10 0.2 0.05 0.1 0 0 –0.05 –0.1 –0.10 –0.2 –0.15 –0.3 –0.20 –0.4 –0.25 –0.5 0 128 256 384 512 640 768 896 1024 0 32 64 96 128 160 192 224 256 CODE CODE Figure 7. INL vs. Code (10-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 T = 25°C T = 25°C A A V = 10V V = 10V 0.4 REF 0.4 REF V = 5V V = 5V DD DD 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 512 1024 1536 2048 2560 3072 2584 4096 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 8. INL vs. Code (12-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) Rev. F | Page 8 of 28 INL (LSB) INL (LSB) INL (LSB) 04587-022 04587-021 04587-020 DNL (LSB) DNL (LSB) INL (LSB) 04587-025 04587-024 04587-023 Data Sheet AD5450/AD5451/AD5452/AD5453 1.0 2.0 T = 25°C A T = 25°C A V = 10V 0.8 REF 1.5 V = 5V DD = 5V V DD AD5452 0.6 1.0 0.4 MAX DNL 0.5 0.2 0 0 MIN DNL –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –1.0 –2.0 0 512 1024 1536 2048 2560 3072 2584 4096 2 345 678 9 10 CODE REFERENCE VOLTAGE (V) Figure 12. DNL vs. Code (12-Bit DAC) Figure 15. DNL vs. Reference Voltage 2.0 0.5 T = 25°C T = 25°C A A V = 10V V = 10V 1.6 REF 0.4 REF V = 5V V = 5V DD DD AD5450 1.2 0.3 0.8 0.2 0.4 0.1 0 0 –0.4 –0.1 –0.8 –0.2 –1.2 –0.3 –1.6 –0.4 –2.0 –0.5 0 2048 4096 6144 8192 10240 12288 14336 16384 0 32 64 96 128 160 192 224 256 CODE CODE Figure 13. DNL vs. Code (14-Bit DAC) Figure 16. TUE vs. Code (8-Bit DAC) 1.00 0.25 T = 25°C A T = 25°C A V = 10V 0.20 REF 0.75 V = 5V DD V = 5V DD AD5452 AD5451 0.15 0.50 MAX INL 0.10 0.25 0.05 0 0 –0.05 MIN INL –0.25 –0.10 –0.50 –0.15 –0.75 –0.20 –1.00 –0.25 2 345 678 9 10 0 128 256 384 512 640 768 896 1024 REFERENCE VOLTAGE (V) CODE Figure 14. INL vs. Reference Voltage Figure 17. TUE vs. Code (10-Bit DAC) Rev. F | Page 9 of 28 DNL (LSB) DNL (LSB) INL (LSB) 04587-070 04587-027 04587-026 TUE (LSB) TUE (LSB) DNL (LSB) 04587-031 04587-030 04587-071 AD5450/AD5451/AD5452/AD5453 Data Sheet 1.0 0.3 T = 25°C A V = 10V 0.8 REF V = 5V DD 0.2 0.6 0.4 0.1 V = 3V DD 0.2 V = 5V 0 0 DD –0.2 –0.1 –0.4 –0.6 –0.2 –0.8 –1.0 –0.3 0 512 1024 1536 2048 2560 3072 2584 4096 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 18. TUE vs. Code (12-Bit DAC) Figure 21. Gain Error (LSB) vs. Temperature 2.0 2.0 T = 25°C T = 25°C A A V = 10V V = 5V 1.6 REF DD 1.5 V = 5V AD5452 DD 1.2 1.0 0.8 0.5 0.4 0 0 –0.4 –0.5 –0.8 –1.0 –1.2 –1.5 –1.6 –2.0 –2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 2 345 6 7 89 10 CODE REFERENCE VOLTAGE (V) Figure 19. TUE vs. Code (14-Bit DAC) Figure 22. Gain Error (LSB) vs. Reference Voltage 2.0 2.0 T = 25°C A V = 5V I 1 V = 5V DD OUT DD 1.5 AD5452 1.6 1.0 I 1V = 3V OUT DD MAX TUE 0.5 1.2 0 MIN TUE 0.8 –0.5 –1.0 0.4 –1.5 –2.0 0 2 345 6 7 8 9 10 –40 –20 0 20 40 60 80 100 120 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 20. TUE vs. Reference Voltage Figure 23. IOUT1 Leakage Current vs. Temperature Rev. F | Page 10 of 28 INL (LSB) TUE (LSB) TUE (LSB) 04587-072 04587-033 04587-032 I 1 LEAKAGE (nA) OUT GAIN ERROR (LSB) GAIN ERROR (LSB) 04587-074 04587-073 04587-039 Data Sheet AD5450/AD5451/AD5452/AD5453 2.5 1.8 T = 25°C A T = 25°C A 1.6 V IH V 2.0 IL 1.4 1.2 1.5 1.0 0.8 1.0 V = 5V DD 0.6 0.4 0.5 0.2 V = 3V DD 0 0 01 2345 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) VOLTAGE (V) Figure 24. Supply Current vs. Logic Input Voltage Figure 27. Threshold Voltage vs. Supply Voltage 10 0.7 T = 25°C A ALL 1s LOADING ALL 0s 0 ALL ON ZS TO FS 0.6 DB13 –10 DB12 0.5 DB11 –20 V = 5V DD DB10 0.4 –30 DB9 DB8 –40 0.3 DB7 DB6 –50 DB5 0.2 DB4 –60 V = 3V DD V = 5V DB3 DD 0.1 V = ±3.5V REF –70 DB2 C = 1.8pF COMP AD8038 AMPLIFIER –80 0 10k 100k 1M 10M 100M –40 –20 0 20 40 60 80 100 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 25. Supply Current vs. Temperature Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code 0.6 6 T = 25°C A AD5452 0.4 LOADING 010101010101 5 0.2 4 0 –0.2 3 V = 5V DD –0.4 2 –0.6 T = 25°C –0.8 A V = 5V 1 DD V = ±3.5V REF –1.0 C = 1.8pF COMP V = 3V DD AD8038 AMPLIFIER 0 –1.2 1 10 100 1k 10k 100k 1M 10M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Supply Current vs. Update Rate Figure 29. Reference Multiplying Bandwidth—All 1s Loaded Rev. F | Page 11 of 28 CURRENT (μA) CURRENT (mA) CURRENT (mA) 04587-075 04587-037 04587-038 GAIN (dB) GAIN (dB) THRESHOLD VOLTAGE (V) 04587-076 04587-109 04587-108 AD5450/AD5451/AD5452/AD5453 Data Sheet 3 10 T = 25°C T = 25°C A A 0 V = 3V V = 5V DD DD AD8038 AMPLIFIER –10 0 –20 –30 –40 –3 FULL SCALE –50 –60 ZERO SCALE –70 –6 V = ±2V, AD8038 C = 1pF REF COMP V = ±2V, AD8038 C = 1.5pF REF COMP –80 V = ±15V, AD8038 C = 1pF REF COMP V = ±15V, AD8038 C = 1.5pF –90 REF COMP V = ±15V, AD8038 C = 1.8pF REF COMP –9 –100 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Reference Multiplying Bandwidth vs. Frequency and Figure 33. Power Supply Rejection Ratio vs. Frequency Compensation Capacitor 0.08 –60 T = 25°C T = 25°C V =5V A A DD V = 0V V = 5V 0x7FF TO 0x800 DD DD AD8038 AMPLIFIER 0.06 V = ±3.5V NRG = 2.154nVs REF –65 C = 1.8pF COMP V = 3V DD 0.04 0x7FF TO 0x800 –70 NRG = 1.794nVs 0.02 –75 0 –80 V =5V DD –0.02 0x800 TO 0x7FF NRG = 0.694nVs –85 –0.04 V =5V DD 0x800 TO 0x7FF NRG = 0.694nVs –0.06 –90 50 75 100 125 150 175 200 225 250 100 1k 10k 100k FREQUENCY (Hz) TIME (ns) Figure 34. THD + Noise vs. Frequency Figure 31. Midscale Transition, VREF = 0 V 100 –1.66 V =5V T = 25°C DD A MCLK = 200kHz 0x7FF TO 0x800 V = 3.5V DD MCLK = 500kHz –1.68 NRG = 2.154nVs AD8038 AMPLIFIER 80 C = 1.8pF COMP V = 3V MCLK = 1MHz DD –1.70 0x7FF TO 0x800 NRG = 1.794nVs 60 –1.72 –1.74 40 –1.76 V =5V DD 0x800 TO 0x7FF 20 NRG = 0.694nVs T = 25°C A –1.78 V =5V DD V = ±3.5V REF 0x800 TO 0x7FF AD8038 AMPLIFIER NRG = 0.694nVs 0 –1.80 05 10 20 30 400 50 75 100 125 150 175 200 225 250 f (kHz) OUT TIME (ns) Figure 32. Midscale Transition, VREF = 3.5 V Figure 35. Wideband SFDR vs. f Frequency OUT Rev. F | Page 12 of 28 GAIN (dB) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 04587-080 04587-079 04587-081 SFDR (dB) THD+N(dB) PSRR (dB) 04587-082 04587-083 04587-084 Data Sheet AD5450/AD5451/AD5452/AD5453 0 0 T = 25°C A T = 25°C A V = 5V DD V = 5V DD V = 3.5V REF V = 3.5V –20 –20 REF AD8038 AMPLIFIER AD8038 AMPLIFIER –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 100k 200k 300k 400k 500k 10k 15k 20k 25k 30k FREQUENCY (Hz) FREQUENCY (Hz) Figure 36. Wideband SFDR, f = 20 kHz, Clock = 1 MHz Figure 38. Narrow-Band SFDR, f = 20 kHz, Clock = 1 MHz OUT OUT 0 0 T = 25°C A T = 25°C A V = 5V DD V = 5V DD V = 3.5V REF V = 3.5V –20 REF –20 AD8038 AMPLIFIER AD8038 AMPLIFIER –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 100k 200k 300k 400k 500k 30k 40k 50k 60k 70k FREQUENCY (Hz) FREQUENCY (Hz) Figure 37. Wideband SFDR, f = 50 kHz, Clock = 1 MHz OUT Figure 39. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz Rev. F | Page 13 of 28 SFDR (dB) SFDR (dB) 04587-086 04587-085 SFDR (dB) SFDR (dB) 04587-088 04587-087 AD5450/AD5451/AD5452/AD5453 Data Sheet 0 80 T = 25°C T = 25°C A A AD8038 AMPLIFIER V = 3.5V –10 REF 70 AD8038 AMPLIFIER –20 60 FULL SCALE –30 LOADED TO DAC 50 –40 40 –50 MIDSCALE LOADED TO DAC –60 30 –70 20 –80 ZERO SCALE LOADED TO DAC 10 –90 0 –100 100 1k 10k 100k 1M 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 42. Output Noise Spectral Density Figure 40. Narrow-Band IMD, f = 20 kHz, 25 kHz, Clock = 1 MHz OUT 0 T = 25°C A –10 V = 3.5V REF AD8038 AMPLIFIER –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100k 200k 300k 400k 500k FREQUENCY (Hz) Figure 41. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz Rev. F | Page 14 of 28 IMD (dB) IMD (dB) 04587-090 04587-089 OUTPUT NOISE (nV/ Hz) 04587-091 Data Sheet AD5450/AD5451/AD5452/AD5453 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Feedthrough A measure of the maximum deviation from a straight line passing When the device is not selected, high frequency logic activity through the endpoints of the DAC transfer function. It is mea- on the device’s digital inputs may be capacitively coupled sured after adjusting for zero and full scale and is normally through the device and produce noise on the IOUT pins. This expressed in LSBs or as a percentage of the full-scale reading. noise is coupled from the outputs of the device onto follow-on circuitry. This noise is digital feedthrough. Differential Nonlinearity The difference between the measured change and the ideal 1 LSB Multiplying Feedthrough Error change between any two adjacent codes. A specified differential The error due to capacitive feedthrough from the DAC nonlinearity of −1 LSB maximum over the operating temperature reference input to the DAC IOUT1 terminal when all 0s are range ensures monotonicity. loaded to the DAC. Gain Error (Full-Scale Error) Total Harmonic Distortion (THD) A measure of the output error between an ideal DAC and the The DAC is driven by an ac reference. The ratio of the rms sum actual device output. For these DACs, ideal maximum output is of the harmonics of the DAC output to the fundamental value is V − 1 LSB. Gain error of the DACs is adjustable to zero with the THD. Usually only the lower-order harmonics, such as REF external resistance. second to fifth, are included. 2 2 2 2 V +V +V +V Output Leakage Current 2 3 4 5 THD= 20 log The current that flows into the DAC ladder switches when it is V 1 turned off. For the IOUT1 terminal, it can be measured by loading Digital Intermodulation Distortion (IMD) all 0s to the DAC and measuring the IOUT1 current. Second-order intermodulation measurements are the relative Output Capacitance magnitudes of the fa and fb tones generated digitally by the Capacitance from I 1 to AGND. OUT DAC and the second-order products at 2fa − fb and 2fb − fa. Output Current Settling Time Compliance Voltage Range The amount of time it takes for the output to settle to a specified The maximum range of (output) terminal voltage for which the level for a full-scale input change. For these devices, it is specified device provides the specified characteristics. with a 100 Ω resistor to ground. The settling time specification Spurious-Free Dynamic Range (SFDR) includes the digital delay from the SYNC rising edge to the full- The usable dynamic range of a DAC before spurious noise scale output change. interferes or distorts the fundamental signal. SFDR is the Digital-to-Analog Glitch Impulse measure of difference in amplitude between the fundamental The amount of charge injected from the digital inputs to the and the largest harmonically or nonharmonically related spur analog output when the inputs change state. This is normally from dc to full Nyquist bandwidth (half the DAC sampling rate specified as the area of the glitch in either pA-s or nV-s, depending or f /2). Narrow-band SFDR is a measure of SFDR over an S on whether the glitch is measured as a current or voltage signal. arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. F | Page 15 of 28 AD5450/AD5451/AD5452/AD5453 Data Sheet GENERAL DESCRIPTION DAC SECTION Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit current output DACs, respectively, consisting of a segmented V DD R2 (4-bit) inverting R-2R ladder configuration. A simplified diagram for the 12-bit AD5452 is shown in Figure 43. C1 V R DD FB AD5450/ RR R I 1 AD5451/ OUT V V V REF REF REF A1 AD5452/ R1 GND 2R 2R 2R 2R 2R AD5453 V = 0 TO –V OUT REF SYNC SCLK SDIN R S1 S2 S3 S12 R FB AGND I 1 OUT µCONTROLLER DAC DATA LATCHES NOTES AND DRIVERS AGND 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 43. AD5452 Simplified Ladder Figure 44. Unipolar Mode Operation The feedback resistor, R , has a value of R. The value of R is FB These DACs are designed to operate with either negative or typically 9 kΩ (with a minimum value of 7 kΩ and a maximum positive reference voltages. The VDD power pin is only used by value of 11 kΩ). If IOUT1 is kept at the same potential as GND, a the internal digital logic to drive the on and off states of the constant current flows in each ladder leg, regardless of digital DAC switches. input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output These DACs are designed to accommodate ac reference input (I 1) is code-dependent, producing various resistances and OUT signals in the range of −10 V to +10 V. capacitances. When choosing the external amplifier, take into account the variation in impedance generated by the DAC on With a fixed 10 V reference, the circuit shown in Figure 44 gives the amplifier’s inverting input node. a unipolar 0 V to −10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Access is provided to the VREF, RFB, and IOUT1 terminals of the DAC, making the device extremely versatile and allowing it to be Table 5 shows the relationship between the digital code and configured in several operating modes; for example, it can provide the expected output voltage for a unipolar operation using the a unipolar output or can provide 4-quadrant multiplication in 8-bit AD5450. bipolar mode. Note that a matching switch is used in series with the internal R feedback resistor. If users attempt to measure FB Table 5. Unipolar Code Table for the AD5450 R , power must be applied to V to achieve continuity. FB DD Digital Input Analog Output (V) 1111 1111 −VREF (255/256) CIRCUIT OPERATION 1000 0000 −V (128/256) = −V /2 REF REF Unipolar Mode 0000 0001 −V (1/256) REF Using a single op amp, these devices can easily be configured to 0000 0000 −V (0/256) = 0 REF provide a 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 44. When an output amplifier is connected in unipolar mode, the output voltage is given by D V =− × V OUT REF n 2 where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5450). = 0 to 1023 (10-bit AD5451). = 0 to 4095 (12-bit AD5452). = 0 to 16,383 (14-bit AD5453). n is the number of bits. Rev. F | Page 16 of 28 04587-060 04587-009 Data Sheet AD5450/AD5451/AD5452/AD5453 Bipolar Mode When V is an ac signal, the circuit performs 4-quadrant IN In some applications, it may be necessary to generate a full multiplication. Table 6 shows the relationship between the 4-quadrant multiplying operation or a bipolar output swing. digital code and the expected output voltage for a bipolar This can be easily accomplished by using another external operation using the 8-bit AD5450. amplifier and some external resistors, as shown in Figure 45. In this circuit, the second amplifier, A2, provides a gain of 2. Table 6. Bipolar Code Table for the AD5450 Biasing the external amplifier with an offset from the reference Digital Input Analog Output (V) voltage results in full 4-quadrant multiplying operation. The 1111 1111 +V (127/128) REF transfer function of this circuit shows that both negative and 1000 0000 0 positive output voltages are created as the input data (D) is 0000 0001 −VREF (127/128) incremented from Code 0 (VOUT = − VREF) to midscale 0000 0000 −VREF (128/128) (VOUT − 0 V ) to full scale (VOUT = +VREF). D ⎛ ⎞ V = V × − V ⎜ ⎟ OUT REF REF n−1 ⎝ 2 ⎠ where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5450). = 0 to 1023 (10-bit AD5451). = 0 to 4095 (12-bit AD5452). n is the resolution of the DAC. R3 20kΩ V DD R2 R5 20kΩ C1 V R DD FB AD5450/ R4 I 1 OUT 10kΩ AD5451/ V REF V REF A1 ±10V AD5452/ R1 GND A2 V = –V TO +V OUT REF REF AD5453 SYNC SCLK SDIN AGND µCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 45. Bipolar Mode Operation (4-Quadrant Multiplication) Rev. F | Page 17 of 28 04587-010 AD5450/AD5451/AD5452/AD5453 Data Sheet Stability Positive Output Voltage In the I-to-V configuration, the IOUT of the DAC and the The output voltage polarity is opposite to the VREF polarity for inverting node of the op amp must be connected as close as dc reference voltages. To achieve a positive voltage output, an possible, and proper PCB layout techniques must be employed. applied negative reference to the input of the DAC is preferred Because every code change corresponds to a step function, gain over the output inversion through an inverting amplifier peaking may occur if the op amp has limited gain bandwidth because of the resistors’ tolerance errors. To generate a negative product (GBP) and there is excessive parasitic capacitance at the reference, the reference can be level-shifted by an op amp such inverting node. This parasitic capacitance introduces a pole into that the V and GND pins of the reference become the virtual OUT the open-loop response, which can cause ringing or instability ground and −2.5 V, respectively, as shown in Figure 47. in the closed-loop applications circuit. V = +5V DD ADR03 V V An optional compensation capacitor, C1, can be added in parallel OUT IN GND with RFB for stability, as shown in Figure 44 and Figure 45. Too +5V C1 V R small a value of C1 can produce ringing at the output, and too DD FB large a value can adversely affect the settling time. C1 should be I 1 –2.5V OUT V V = 0V TO +2.5V REF OUT found empirically, but 1 pF to 2 pF is generally adequate for the compensation. GND –5V SINGLE-SUPPLY APPLICATIONS NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. Voltage-Switching Mode 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 46 shows these DACs operating in the voltage-switching Figure 47. Positive Output Voltage with Minimum Components mode. The reference voltage, VIN, is applied to the IOUT1 pin, and the output voltage is available at the VREF terminal. In this ADDING GAIN configuration, a positive reference voltage results in a positive In applications in which the output voltage is required to be output voltage, making single-supply operation possible. The greater than VIN, gain can be added with an additional external output from the DAC is voltage at a constant impedance (the amplifier, or it can be achieved in a single stage. It is important DAC ladder resistance); therefore, an op amp is necessary to to consider the effect of the temperature coefficients of the buffer the output voltage. The reference input no longer sees DAC’s thin film resistors. Simply placing a resistor in series constant input impedance, but one that varies with code; with the R resistor causes mismatches in the temperature FB therefore, the voltage input should be driven from a low coefficients and results in larger gain temperature coefficient impedance source. errors. Instead, increase the gain of the circuit by using the R1 R2 recommended configuration shown in Figure 48. R1, R2, and V DD R3 should have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This R V FB DD V OUT approach is recommended in circuits where gains greater than 1 V I1V IN OUT REF are required. GND V DD NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED C1 V R DD FB IF A1 IS A HIGH SPEED AMPLIFIER. I 1 R1 OUT Figure 46. Single-Supply Voltage-Switching Mode V V IN REF V OUT R3 It is important to note that with this configuration V is limited IN GND R2 + R3 GAIN = R2 to low voltages because the switches in the DAC ladder do not R2 R2R3 have the same source-drain drive voltage. As a result, their on NOTES R1 = R2 + R3 1. ADDITIONAL PINS OMITTED FOR CLARITY. resistance differs, which degrades the integral linearity of the 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED DAC. Also, VIN must not go negative by more than 0.3 V, or an IF A1 IS A HIGH SPEED AMPLIFIER. internal diode turns on, causing the device to exceed the Figure 48. Increasing Gain of Current-Output DAC maximum ratings. In this type of application, the full range of multiplying capability of the DAC is lost. Rev. F | Page 18 of 28 04587-011 04587-013 04587-012 Data Sheet AD5450/AD5451/AD5452/AD5453 DIVIDER OR PROGRAMMABLE GAIN ELEMENT REFERENCE SELECTION Current-steering DACs are very flexible and lend themselves to When selecting a reference for use with this series of current- many different applications. If this type of DAC is connected as output DACs, pay attention to the reference’s output voltage the feedback element of an op amp and RFB is used as the input temperature coefficient specification. This parameter not only resistor as shown in Figure 49, the output voltage is inversely affects the full-scale error, but also may affect the linearity (INL proportional to the digital input fraction, D. and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. −n For D = 1 − 2 , the output voltage is For example, an 8-bit system is required to hold its overall −V −V specification to within 1 LSB over the temperature range 0°C to IN IN V = = OUT −n 50°C, and the system’s maximum temperature drift should be D () 1− 2 less than 78 ppm/°C. As D is reduced, the output voltage increases. For small values A 12-bit system within 2 LSB accuracy requires a maximum of the digital fraction, D, it is important to ensure that the drift of 10 ppm/°C. Choosing a precision reference with a low amplifier does not saturate and that the required accuracy is output temperature coefficient minimizes this error source. met. For example, an 8-bit DAC driven with the binary code Table 7 lists some dc references available from Analog Devices 0x10 (00010000), that is, 16 decimal, in the circuit of Figure 49 that are suitable for use with this range of current-output DACs. should cause the output voltage to be 16 times V . IN V DD AMPLIFIER SELECTION V IN The primary requirement for the current-steering mode is an R V amplifier with low input bias currents and low input offset voltage. FB DD I1V The input offset voltage of an op amp is multiplied by the variable OUT REF gain of the circuit due to the code-dependent output resistance of GND the DAC. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the V OUT offset voltage of the amplifier’s input. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which if NOTE ADDITIONAL PINS OMITTED FOR CLARITY large enough, could cause the DAC to be nonmonotonic. Figure 49. Current-Steering DAC Used as a Divider or Programmable Gain Element The input bias current of an op amp generates an offset at the voltage output as a result of the bias current flowing in the However, if the DAC has a linearity specification of ±0.5 LSB, D feedback resistor, RFB. Most op amps have input bias currents can have weight anywhere in the range of 15.5/256 to 16.5/256. low enough to prevent significant errors in 12-bit applications. Therefore, the possible output voltage is in the range of 15.5 V IN However, for 14-bit applications, some consideration should be to 16.5 V —an error of 3%, even though the DAC itself has a IN given to selecting an appropriate amplifier. maximum error of 0.2%. Common-mode rejection of the op amp is important in voltage- DAC leakage current is also a potential error source in divider switching circuits because it produces a code-dependent error circuits. The leakage current must be counterbalanced by an at the voltage output of the circuit. Most op amps have adequate opposite current supplied from the op amp through the DAC. common-mode rejection for use at 8-, 10-, and 12-bit resolutions. Because only a fraction, D, of the current in the VREF terminal is routed to the IOUT1 terminal, the output voltage changes as follows: Provided that the DAC switches are driven from true wideband low impedance sources (V and AGND), they settle quickly. IN Output Error Voltage Dueto Leakage = (Leakage × R)/D Consequently, the slew rate and settling time of a voltage- where R is the DAC resistance at the V terminal. REF switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain is important to minimize capacitance at the VREF node (the voltage (that is, 1/D) of 16, the error voltage is 1.6 mV. output node in this application) of the DAC. This is done by using low input-capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices. Rev. F | Page 19 of 28 04587-014 AD5450/AD5451/AD5452/AD5453 Data Sheet Table 7. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8 Rev. F | Page 20 of 28 Data Sheet AD5450/AD5451/AD5452/AD5453 SERIAL INTERFACE The serial interface to the AD5450 uses a 16-bit shift register. Take care to avoid incomplete data sequences as these will be The AD5450/AD5451/AD5452/AD5453 have an easy-to-use latched to update the DAC output. 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and most DSP interface standards. Data is written to the device in For example, 16-bit words. This 16-bit word consists of two control bits and 8, 10, 12, or 14 data bits, as shown in Figure 50, Figure 51, Figure 52, • Loading 0x3FFF (a complete data sequence) will update and Figure 53. The AD5453 uses all 14 bits of DAC data, the the output to 10 V (full scale). AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses • User intends to write 0x3200 but after 12 active edges 10 bits and ignores the four LSBs, and the AD5450 uses 8 bits SYNC goes high (incomplete write sequence). This will and ignores the six LSBs. actually update the following code: 0xF200. SYNC DAC Control Bits C1, C0 • The user expects an output of 5.6 V. However, if goes high after 12 valid clock edges then an incomplete Control Bits C1 and C0 allow the user to load and update the data sequence of 12 bits is loaded. To complete the shift new DAC code and to change the active clock edge. By default, register the 4 LSBs from the previous sequence are taken the shift register clocks data upon the falling edge; this can be and used as the 4 MSBs missing. The addition of these changed via the control bits. If changed, the DAC core is 4 bits will put the part in rising edge mode and the output inoperative until the next data frame, and a power recycle is will show no change. Figure 54, Figure 55, and Table 11 required to return it to active on the falling edge. A power cycle show the data frames for this example. resets the core to default condition. On-chip power-on reset circuitry ensures that the device powers on with zero scale Also note that if more then 16-bits are loaded to the part before loaded to the DAC register and I line. OUT SYNC goes high the last 16-bits will be latched. DB15 (MSB) Table 10. DAC Control Bits DB0 (LSB) C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X C1 C0 Function Implemented DATA BITS 0 0 Load and update (power-on default) CONTROL BITS 0 1 Reserved Figure 50. AD5450 8-Bit Input Shift Register Contents 1 0 Reserved 1 1 Clock data to shift register upon rising edge DB15 (MSB) DB0 (LSB) Function SYNC C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X SYNC is an edge-triggered input that acts as a frame- DATA BITS CONTROL BITS synchronization signal and chip enable. Data can only be Figure 51. AD5451 10-Bit Input Shift Register Contents transferred to the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC falling to SCLK falling edge setup time, t4. To DB15 (MSB) DB0 (LSB) minimize the power consumption of the device, the interface C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X powers up fully only when the device is being written to, that is, DATA BITS CONTROL BITS upon the falling edge of . The SCLK and SDIN input SYNC Figure 52. AD5452 12-Bit Input Shift Register Contents buffers are powered down upon the rising edge of SYNC. th After the falling edge of the 16 SCLK pulse, bring high DB15 (MSB) SYNC DB0 (LSB) C1 C0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 to transfer data from the input shift register to the DAC register. DATA BITS CONTROL BITS Figure 53. AD5453 14-Bit Input Shift Register Contents 00 1 1 1 11 11 1 1 11 1 1 1 DATA BITS CONTROL BITS Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF) Rev. F | Page 21 of 28 04587-054 04587-008 04587-006 04587-005 04587-007 AD5450/AD5451/AD5452/AD5453 Data Sheet 00 11 0 0 10 0 0 00 0 0 0 0 11 11 0 0 10 0 0 00 0 0 0 0 DATA BITS DATA BITS CONTROL BITS CONTROL BITS INTENDED DATA FRAME ACTUAL DATA FRAME Figure 55. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200) Table 11. Writing Data Write in Data Transfer to Sequence Shift Register Action Expected the Device Action Carried Out 1 0x3FFF Load and update 0x3FFF 0x3FFF Load and update 0x3FFF 2 0x3200 Load and update 0x3200 0xF200 Clock data to shift register upon rising edge (0xF200) MICROPROCESSOR INTERFACING AD5450/AD5451/ ADSP-2101/ AD5452/AD5453* ADSP-2103/ Microprocessor interfacing to a AD5450/AD5451/AD5452 ADSP-2191* TFS SYNC /AD5453 DAC is through a serial bus that uses standard protocol DT SDIN and is compatible with microcontrollers and DSP processors. SCLK SCLK The communication channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with *ADDITIONAL PINS OMITTED FOR CLARITY the default being data valid upon the falling edge of SCLK, but Figure 57. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface this is changeable using the control bits in the data-word. Communication between two devices at a given clock speed is ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453 possible when the following specifications are compatible: Interface frame delay and frame setup-and-hold, data delay SYNC SYNC The ADSP-21xx family of DSPs is easily interfaced to a AD5450/ and data setup-and-hold, and SCLK width. The DAC interface AD5451/AD5452/AD5453 DAC without the need for extra glue expects a t ( falling edge to SCLK falling edge setup time) 4 SYNC logic. Figure 56 is an example of an SPI interface between the DAC of 13 ns minimum. See the ADSP-21xx User Manual for infor- and the ADSP-2191M. SCK of the DSP drives the serial data line, mation on clock and frame SYNC frequencies for the SPORT SDIN. is driven from one of the port lines, in this case SYNC register. Table 12 shows the setup for the SPORT control register. SPIxSEL. Table 12. SPORT Control Register Setup AD5450/AD5451/ ADSP-2191* AD5452/AD5453* Name Setting Description SPIxSEL SYNC TFSW 1 Alternate framing MOSI SDIN INVTFS 1 Active low frame signal SCK SCLK DTYPE 00 Right justify data ISCLK 1 Internal serial clock TFSR 1 Frame every word *ADDITIONAL PINS OMITTED FOR CLARITY ITFS 1 Internal framing signal Figure 56. ADSP-2191 SPI-to-AD5450/AD5451/AD5452/AD5453 Interface SLEN 1111 16-bit data-word A serial interface between the DAC and DSP SPORT is shown ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 in Figure 57. In this example, SPORT0 is used to transfer data to Interface the DAC shift register. Transmission is initiated by writing a The ADSP-BF5xx family of processors has an SPI-compatible word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out upon each rising edge of the port that enables the processor to communicate with SPI- compatible devices. A serial interface between the BlackFin® DSP’s serial clock and clocked into the DAC input shift register processor and the AD5450/AD5451/AD5452/AD5453 DAC is upon the falling edge of its SCLK. The update of the DAC shown in Figure 58. In this configuration, data is transferred output takes place upon the rising edge of the SYNC signal. through the MOSI (master output, slave input) pin. SYNC is driven by the pin, which is a reconfigured SPIxSEL programmable flag pin. Rev. F | Page 22 of 28 04587-100 04587-055 04587-051 Data Sheet AD5450/AD5451/AD5452/AD5453 AD5450/AD5451/ AD5450/AD5451/ ADSP-BF5xx* 8051* AD5452/AD5453* AD5452/AD5453* SCLK TxD SYNC SPIxSEL RxD SDIN MOSI SDIN P1.1 SCK SCLK SYNC *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 60. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface Figure 58. ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface The ADSP-BF5xx processor incorporates channel synchronous serial ports (SPORT). A serial interface between the DAC and Figure 61 is an example of a serial interface between the DAC the DSP SPORT is shown in Figure 59. When the SPORT is and the MC68HC11 microcontroller. The serial peripheral enabled, initiate transmission by writing a word to the Tx register. interface (SPI) on the MC68HC11 is configured for master The data is clocked out upon each rising edge of the DSP’s serial mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock clock and clocked into the DAC’s input shift register upon the phase bit (CPHA) = 1. The SPI is configured by writing to the falling edge its SCLK. The DAC output is updated by using the SPI control register (SPCR); see the 68HC11 User Manual. SCK transmit frame synchronization (TFS) line to provide a SYNC of the 68HC11 drives the SCLK of the DAC interface; the MOSI signal. output drives the serial data line (SDIN) of the DAC. The SYNC signal is derived from a port line (PC7). When data AD5450/AD5451/ ADSP-BF5xx* AD5452/AD5453* is being transmitted to the AD5450/AD5451/AD5452/AD5453, TFS SYNC the line is taken low (PC7). Data appearing on the MOSI SYNC DT SDIN output is valid upon the falling edge of SCK. Serial data from the SCLK SCLK 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the DAC, PC7 is left low after the first eight *ADDITIONAL PINS OMITTED FOR CLARITY bits are transferred, and a second serial write operation is performed Figure 59. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface to the DAC. PC7 is taken high at the end of this procedure. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface MC68HC11* AD5450/AD5451/ AD5452/AD5453* A serial interface between the DAC and the 80C51/80L51 is PC7 SYNC shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of SCK SCLK the DAC serial interface, and RxD drives the serial data line, MOSI SDIN SDIN. P1.1 is a bit-programmable pin on the serial port and is used to drive . As data is transmitted to the switch, P1.1 is taken SYNC *ADDITIONAL PINS OMITTED FOR CLARITY low. The 80C51/80L51 transmit data only in 8-bit bytes; there- Figure 61. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface fore, only eight falling clock edges occur in the transmit cycle. If the user wants to verify the data previously written to the To load data correctly to the DAC, P1.1 is left low after the first input shift register, the SDO line can be connected to MISO of eight bits are transmitted, and a second write cycle is initiated to the MC68HC11. In this configuration with SYNC low, the shift transmit the second byte of data. Data on RxD is clocked out of register clocks data out upon the rising edges of SCLK. the microcontroller upon the rising edge of TxD and is valid upon the falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P1.1 is taken high following the completion of this cycle. The 80C51/80L51 provide the LSB of its SBUF register as the first bit in the data stream. The DAC input register acquires its data with the MSB as the first bit received. The transmit routine should take this into account. Rev. F | Page 23 of 28 04587-102 04587-103 04587-104 04587-105 AD5450/AD5451/AD5452/AD5453 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure Figure 62 shows an interface between the DAC and any the rated performance. The printed circuit board on which a MICROWIRE-compatible device. Serial data is shifted out AD5450/AD5451/AD5452/AD5453 DAC is mounted should be upon the falling edge of the serial clock, SK, and is clocked into designed so that the analog and digital sections are separated the DAC input shift register upon the rising edge of SK, which and confined to certain areas of the board. If the DAC is in a corresponds to the falling edge of the DAC’s SCLK. system where multiple devices require an AGND-to-DGND MICROWIRE* AD5450/AD5451/ connection, the connection should be made at one point only. AD5452/AD5453* The star ground point should be established as close as possible SK SCLK to the device. SO SDIN CS SYNC These DACs should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package *ADDITIONAL PINS OMITTED FOR CLARITY as possible, ideally right up against the device. The 0.1 μF Figure 62. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), like the common ceramic PIC16C6x/PIC16C7x-to- types that provide a low impedance path to ground at high AD5450/AD5451/AD5452/AD5453 Interface frequencies, to handle transient currents due to internal logic The PIC16C6x/PIC16C7x synchronous serial port (SSP) is switching. Low ESR 1 μF to 10 μF tantalum or electrolytic configured as an SPI master with the clock polarity bit (CKP) = 0. capacitors should also be applied at the supplies to minimize This is done by writing to the synchronous serial port control transient disturbance and filter out low frequency ripple. register (SSPCON); see the PIC16/PIC17 Microcontroller User Manual. Components, such as clocks, that produce fast switching signals should be shielded with a digital ground to avoid radiating noise In this example, I/O Port RA1 is used to provide a SYNC signal to other parts of the board, and they should never be run near and enable the serial port of the DAC. This microcontroller the reference inputs. transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are Avoid crossover of digital and analog signals. Traces on opposite required. Figure 63 shows the connection diagram. sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip PIC16C6x/PIC16C7x* AD5450/AD5451/ technique is the best solution, but its use is not always possible AD5452/AD5453* with a double-sided board. In this technique, the component SCK/RC3 SCLK side of the board is dedicated to the ground plane and signal SDI/RC4 SDIN traces are placed on the solder side. RA1 SYNC It is good practice to employ compact, minimum lead length *ADDITIONAL PINS OMITTED FOR CLARITY PCB layout design. Leads to the input should be as short as Figure 63. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface possible to minimize IR drops and stray inductance. The PCB metal traces between V and R should also be REF FB matched to minimize gain error. To optimize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Rev. F | Page 24 of 28 04587-106 04587-107 Data Sheet AD5450/AD5451/AD5452/AD5453 Table 13. Overview of AD54xx and AD55xx Devices 1 Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 12 MHZ BW, 50 MHz serial interface AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial interface AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial interface AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 n WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. F | Page 25 of 28 AD5450/AD5451/AD5452/AD5453 Data Sheet OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 13 2 4 PIN 1 INDICATOR 0.65 BSC 1.95 * 0.90 BSC 0.87 0.84 * 1.00 MAX 0.20 0.08 0.60 8° 0.45 0.38 0.10 MAX 4° 0.30 0.22 SEATING 0° PLANE * COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 64. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 65. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. F | Page 26 of 28 10-07-2009-B Data Sheet AD5450/AD5451/AD5452/AD5453 0.35 3.00 0.30 0.65 BSC BSC SQ 0.25 5 8 PIN 1 INDEX 1.74 EXPOSED AREA PAD 1.64 (BOTTOM VIEW) 1.49 0.50 0.40 4 1 0.30 TOP VIEW 2.48 2.38 0.80 MAX 2.23 0.80 0.55 NOM 0.05 MAX 0.75 FOR PROPER CONNECTION OF 0.02 NOM 0.70 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING FUNCTION DESCRIPTIONS PLANE SECTION OF THIS DATA SHEET. 0.20 REF Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-3) Dimensions shown in millimeters ORDERING GUIDE 1, 2 Model Resolution INL Temperature Range Package Description Package Option Branding AD5450YUJZ-REEL 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y AD5450YUJZ-REEL7 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y AD5451YUJZ-REEL 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z AD5451YUJZ-REEL7 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z AD5452YUJZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70 AD5452YUJZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70 AD5452YRM 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z AD5452YRM-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z AD5452YRMZ 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5452YRMZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5452YRMZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5453WBCPZ-RL 14 ±2 −40°C to +125°C 8-Lead LFCSP_WD CP-8-3 DG3 AD5453YUJZ-REEL 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH AD5453YUJZ-REEL7 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH AD5453YRM 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRM-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRM-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRMZ 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH AD5453YRMZ-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH AD5453YRMZ-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH EVAL-AD5453EBZ Evaluation Board EVAL-AD5453SDZ Evaluation Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5453WBCPZ-RL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. F | Page 27 of 28 PIN 1 INDICATOR (R 0.2) 04-16-2008-B AD5450/AD5451/AD5452/AD5453 Data Sheet NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04587-0-4/12(F) Rev. F | Page 28 of 28