ANALOG DEVICES AD5446

12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5444/AD5446 FEATURES GENERAL DESCRIPTION 1 12 MHz multiplying bandwidth The AD5444/AD5446 are CMOS 12-bit and 14-bit, current INL of ± 0.5 LSB at 12 bits output, digital-to-analog converters (DACs). Operating from a Pin-compatible 12-/14-bit current output DAC single 2.5 V to 5.5 V power supply, these devices are suited for 2.5 V to 5.5 V supply operation battery-powered and other applications. 10-lead MSOP package As a result of the CMOS submicron manufacturing process, ±10 V reference input these parts offer excellent 4-quadrant multiplication char- 50 MHz serial interface acteristics of up to 12 MHz. 2.7 MSPS update rate These DACs use a double-buffered, 3-wire serial interface that Extended temperature range: −40°C to +125°C is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP 4-quadrant multiplication interface standards. On power-up, the internal shift register and Power-on reset with brownout detection latches are filled with 0s, and the DAC output is at zero scale. 0.4 µA typical current consumption Guaranteed monotonic The applied external reference input voltage (V ) determines REF the full-scale output current. These parts can handle ±10 V APPLICATIONS inputs on the reference, despite operating from a single-supply Portable, battery-powered applications power supply of 2.5 V to 5.5 V. An integrated feedback resistor Waveform generators (R ) provides temperature tracking and full-scale voltage output FB Analog processing when combined with an external current-to-voltage precision Instrumentation applications amplifier. The AD5444/AD5446 DACs are available in small Programmable amplifiers and attenuators 10-lead MSOP packages, which are pin-compatible with the Digitally controlled calibration AD5425/AD5426/AD5432/AD5443 family of DACs. Programmable filters and oscillators The EVAL-AD5446SDZ board is available for evaluating DAC Composite video performance. For more information, see the UG-327 evaluation Ultrasound board user guide. Gain, offset, and voltage trimming Automotive radar 1 US Patent Number 5,689,257. FUNCTIONAL BLOCK DIAGRAM V V DD REF R FB R AD5444/ I 1 OUT AD5446 12-BIT R-2R DAC I 2 OUT DAC REGISTER POWER-ON RESET INPUT LATCH SYNC CONTROL LOGIC AND SCLK SDO INPUT SHIFT REGISTER SDIN GND Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. 04588-001 AD5444/AD5446 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 15 Applications ....................................................................................... 1 Circuit Operation ....................................................................... 15 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 17 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 17 Revision History ............................................................................... 2 Divider or Programmable Gain Element ................................ 17 Specifications ..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Reference Selection .................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Serial Interface ................................................................................ 20 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 21 Pin Configuration and Function Descriptions ............................. 7 PCB Layout and Power Supply Decoupling ................................ 23 Typical Performance Characteristics ............................................. 8 Overview of AD54xx and AD55xx Current Output Devices ... 24 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 25 General Description ....................................................................... 15 Ordering Guide .......................................................................... 25 REVISION HISTORY 4/12—Rev. C to Rev. D 4/05—Rev. 0 to Rev. A Changes to General Description Section ...................................... 1 Added AD5446 ................................................................... Universal Deleted Evaluation Board for the DAC Section ......................... 23 Changes to Features .......................................................................... 1 Deleted Power Supplies for the Evaluation Board Section ....... 23 Changes to General Description ..................................................... 1 Deleted Figure 54; Renumbered Sequentially............................. 24 Changes to Specifications ................................................................. 3 Deleted Figure 55 and Figure 56 ................................................... 25 Inserted Figure 7; Renumbered Sequentially................................. 9 Updated Outline Dimensions ....................................................... 25 Inserted Figure 9; Renumbered Sequentially................................. 9 Changes to Ordering Guide .......................................................... 25 Inserted Figure 13; Renumbered Sequentially ........................... 10 Deleted Figure 57 ............................................................................ 26 Changes to Figure 22 ...................................................................... 11 Changes to Figure 23 ...................................................................... 11 4/07—Rev. B to Rev. C Changes to Serial Interface ............................................................ 20 Changes to Figure 44 ...................................................................... 20 Changes to Table 9 .......................................................................... 19 Changes to Ordering Guide .......................................................... 28 Changes to Figure 45 ...................................................................... 20 Changes to Features .......................................................................... 1 Updated Outline Dimensions ....................................................... 28 Changes to General Description .................................................... 1 Changes to Ordering Guide .......................................................... 28 Changes to Table 1 ............................................................................ 3 Changes to Figure 22 ...................................................................... 10 10/04—Revision 0: Initial Version Changes to Figure 23 ...................................................................... 10 Changes to Table 9 .......................................................................... 19 Changes to Table 12 ........................................................................ 27 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 Rev. D | Page 2 of 28 Data Sheet AD5444/AD5446 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 10 V, I 2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , DD REF OUT MIN MAX unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5444 Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±1 LSB Gain Error ±0.5 LSB AD5446 Resolution 14 Bits Relative Accuracy ±2 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±4 LSB Gain Error ±2.5 LSB 1 Gain Error Temperature Coefficient ±2 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, T = 25°C, I 1 A OUT ±10 nA Data = 0x0000, T = −40°C to +125°C, I 1 A OUT 1 REFERENCE INPUT Reference Input Range ±10 V V Input Resistance 7 9 11 kΩ Input resistance T = −50 ppm/°C REF C R Feedback Resistance 7 9 11 kΩ Input resistance T = −50 ppm/°C FB C Input Capacitance Zero-Scale Code 18 22 pF Full-Scale Code 18 22 pF 1 DIGITAL INPUTS/OUTPUTS Input High Voltage, V 2.0 V V = 3.6 V to 5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5 V, I = 200 µA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 µA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5 V, I = 200 µA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 µA DD SINK Input Leakage Current, I ±1 nA T = 25°C IL A ±10 nA T = −40°C to +125°C A Input Capacitance 10 pF Rev. D | Page 3 of 28 AD5444/AD5446 Data Sheet Parameter Min Typ Max Unit Conditions 1 DYNAMIC PERFORMANCE Reference Multiplying Bandwidth 12 MHz V = ±3.5 V, DAC loaded with all 1s REF Multiplying Feedthrough Error V = ±3.5 V, DAC loaded with all 0s REF 72 dB 100 kHz 64 dB 1 MHz 44 dB 10 MHz Output Voltage Settling Time V = 10 V, R = 100 Ω, DAC latch alternately REF LOAD loaded with 0s and 1s Measured to ±1 mV of FS 100 110 ns Measured to ±4 mV of FS 24 40 ns Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10%-to-90% Settling Time 10 30 ns Rise and fall time, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V = 0 V REF Output Capacitance I 1 13 pF DAC latches loaded with all 0s OUT 28 pF DAC latches loaded with all 1s I 2 18 pF DAC latches loaded with all 0s OUT 5 pF DAC latches loaded with all 1s Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 83 dB V = 3.5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 1 MHz, V = 3.5 V REF 50 kHz f 71 dB OUT 20 kHz f 77 dB OUT Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 10 MHz, V = 3.5 V REF 50 kHz f 78 dB OUT 20 kHz f 74 dB OUT SFDR Performance (Narrow Band) Clock = 1 MHz, V = 3.5 V REF 50 kHz f 87 dB OUT 20 kHz f 85 dB OUT Intermodulation Distortion 79 dB f = 20 kHz, f = 25 kHz, clock = 1 MHz, V = 3.5 V 1 2 REF POWER REQUIREMENTS Power Supply Range, V 2.5 5.5 V DD Supply Current, I 0.4 10 µA T = −40°C to +125°C, logic inputs = 0 V or V DD A DD 0.6 µA T = 25°C, logic inputs = 0 V or V A DD 1 Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization; not subject to production test. Rev. D | Page 4 of 28 Data Sheet AD5444/AD5446 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. VDD = 4.5 V to VDD = 2.5 V to 1 Parameter 5.5 V 5.5 V Unit Conditions/Comments fSCLK 50 50 MHz max Maximum clock frequency. t 20 20 ns min SCLK cycle time. 1 t 8 8 ns min SCLK high time. 2 t 8 8 ns min SCLK low time. 3 t4 8 8 ns min SYNC falling edge to SCLK active edge setup time. t5 5 5 ns min Data setup time. t6 4.5 4.5 ns min Data hold time. t 5 5 ns min SYNC rising edge to SCLK active edge setup time 7 t 30 30 ns min Minimum SYNC high time. 8 t9 23 30 ns min SCLK active edge to SDO valid. Update Rate 2.7 2.7 MSPS Consists of cycle time, SYNC high time, data setup time and output voltage settling time. 1 Guaranteed by design and characterization; not subject to production test. t 1 SCLK t 2 t 3 t 4 t 7 SYNC t 8 t 6 t 5 DB15 DB0 SDIN Figure 2. Standalone Timing Diagram t 1 SCLK t t t 2 3 7 t 8 t 4 SYNC t 6 t 5 DB15 DB0 SDIN DB15 (N) DB0 (N) (N + 1) (N + 1) t 9 SDO DB15 (N) DB0 (N) NOTES ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram Rev. D | Page 5 of 28 04588-002 04588-003 AD5444/AD5446 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 3. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect V , R to GND −12 V to +12 V REF FB device reliability. I 1, I 2 to GND −0.3 V to +7 V OUT OUT 1 Only one absolute maximum rating can be applied at any one Logic Inputs and Outputs −0.3 V to V + 0.3 V DD time. Input Current (All Pins Except Supplies) ±10 mA Operating Temperature Range −40°C to +125°C I 200µA OL Extended (Y Version) Storage Temperature Range −65°C to +150°C TO V +V OH (MIN) OL (MAX) OUTPUT 2 Junction Temperature 150°C C PIN L 20pF 10-lead MSOP θ Thermal Impedance 206°C/W JA 200µA I OH Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C Figure 4. Load Circuit for SDO Timing Specifications 1 SYNC Overvoltages at SCLK, , and SDIN are clamped by internal diodes. ESD CAUTION Rev. D | Page 6 of 28 04588-004 Data Sheet AD5444/AD5446 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I 1 1 10 R OUT FB AD5444/ 2 I 2 9 V OUT REF AD5446 3 GND 8 V DD TOP VIEW 4 7 SCLK (Not to Scale) SDO 5 6 SDIN SYNC Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 I 1 DAC Current Output. OUT 2 I 2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. OUT 3 GND Ground Pin. 4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low, data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising edge of SYNC. 7 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to data loaded to the shift register. 8 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD 9 V DAC Reference Voltage Input. REF 10 R DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output. FB Rev. D | Page 7 of 28 04588-005 AD5444/AD5446 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 2.0 T = 25°C A T = 25°C A V = 10V 0.4 1.6 REF V = 10V REF V = 5V DD V = 5V DD 0.3 1.2 0.2 0.8 0.1 0.4 0 0 –0.1 –0.4 –0.2 –0.8 –0.3 –1.2 –0.4 –1.6 –2.0 –0.5 0 2048 4096 6144 8192 10240 12288 14336 16384 0 512 1024 1536 2048 2560 3072 3584 4096 CODE CODE Figure 6. INL vs. Code (12-Bit DAC) Figure 9. DNL vs. Code (14-Bit DAC) 2.0 1.00 T = 25°C A T = 25°C V = 10V A 1.6 REF V = 5V 0.75 V = 5V DD DD AD5444 1.2 0.50 MAX INL 0.8 0.25 0.4 0 0 –0.4 MIN INL –0.25 –0.8 –0.50 –1.2 –0.75 –1.6 –2.0 –1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 2 3 4 5 6 7 8 9 10 REFERENCE VOLTAGE (V) CODE Figure 10. INL vs. Reference Voltage Figure 7. INL vs. Code (14-Bit DAC) 1.0 2.0 T = 25°C T = 25°C A A 0.8 V = 5V V = 10V 1.5 REF DD AD5444 V = 5V DD 0.6 1.0 0.4 MAX DNL 0.5 0.2 0 0 MIN DNL –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –1.0 –2.0 0 512 1024 1536 2048 2560 3072 3584 4096 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 8. DNL vs. Code (12-Bit DAC) Figure 11. DNL vs. Reference Voltage Rev. D | Page 8 of 28 INL (LSB) DNL (LSB) INL (LSB) 04588-008 04588-006 04588-076 DNL (LSB) INL (LSB) DNL (LSB) 04588-048 04588-047 04588-077 Data Sheet AD5444/AD5446 1.0 0.3 V = 10V REF T = 25°C A 0.8 V = 10V REF 0.2 V = 5V 0.6 DD 0.4 0.1 V = 3V DD 0.2 V = 5V 0 0 DD –0.2 –0.1 –0.4 –0.6 –0.2 –0.8 –1.0 –0.3 0 512 1024 1536 2048 2560 3072 3584 4096 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 12. TUE vs. Code (12-Bit DAC) Figure 15. Gain Error vs. Temperature 2.0 2.0 T = 25°C A T = 25°C A V = 10V 1.6 REF V = 5V DD V = 5V 1.5 DD AD5444 1.2 1.0 0.8 0.5 0.4 0 0 –0.4 –0.5 –0.8 –1.0 –1.2 –1.5 –1.6 –2.0 –2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 13. TUE vs. Code (14-Bit DAC) Figure 16. Gain Error vs. Reference Voltage 2.0 2.0 T = 25°C A V = 5V DD 1.5 AD5444 I 1, V = 5V OUT DD 1.6 1.0 MAX TUE I 1, V = 3V 0.5 OUT DD 1.2 0 MIN TUE 0.8 –0.5 –1.0 0.4 –1.5 –2.0 0 2 3 4 5 6 7 8 9 10 –40 –20 0 20 40 60 80 100 120 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 17. I 1 Leakage Current vs. Temperature Figure 14. TUE vs. Reference Voltage OUT Rev. D | Page 9 of 28 INL (LSB) TUE (LSB) TUE (LSB) 04588-052 04588-013 04588-078 I 1 LEAKAGE (nA) GAIN ERROR (LSB) GAIN ERROR (LSB) OUT 04588-017 04588-051 04588-049 AD5444/AD5446 Data Sheet 2.5 1.8 T = 25°C A T = 25°C A 1.6 V IH V IL 2.0 1.4 1.2 1.5 1.0 V = 5V DD 0.8 1.0 0.6 0.4 0.5 V = 3V DD 0.2 0 0 0 1 2 3 4 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 18. Supply Current vs. Logic Input Voltage Figure 21. Threshold Voltage vs. Supply Voltage 0.7 10 T = 25°C A ALL 1s LOADING 0 ALL ON ALL 0s ZS TO FS 0.6 DB13 –10 DB12 0.5 DB11 –20 DB10 V = 5V DD 0.4 –30 DB9 DB8 –40 0.3 DB7 DB6 –50 DB5 0.2 –60 DB4 V = 3V DD V = 5V DB3 DD 0.1 V = ±3.5V REF –70 DB2 C = 1.8pF COMP AD8038 AMPLIFIER –80 0 –40 –20 0 20 40 60 80 100 120 10k 100k 1M 10M 100M FREQUENCY (Hz) TEMPERATURE (°C) Figure 22. Reference Multiplying Bandwidth vs. Frequency and Code Figure 19. Supply Current vs. Temperature 6 0.6 T = 25°C A AD5444 0.4 LOADING 0101 0101 0101 5 0.2 4 0 –0.2 3 V = 5V DD –0.4 2 –0.6 T = 25°C –0.8 A V = 5V 1 DD V = ±3.5V REF –1.0 C = 1.8pF COMP V = 3V DD AD8038 AMPLIFIER 0 –1.2 1 10 100 1k 10k 100k 1M 10M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. Supply Current vs. Update Rate Figure 23. Reference Multiplying Bandwidth vs. Frequency—All 1s Loaded Rev. D | Page 10 of 28 SUPPLY CURRENT (µA) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 04588-055 04588-019 04588-018 GAIN (dB) GAIN (dB) THRESHOLD VOLTAGE (V) 04588-053 04588-083 04588-084 Data Sheet AD5444/AD5446 3 10 T = 25°C A T = 25°C A V = 3V 0 V = 5V DD DD AD8038 AMPLIFIER –10 0 –20 –30 –40 –3 FULL SCALE –50 –60 ZERO SCALE –70 –6 V = ±2V, AD8038 C = 1pF REF COMP V = ±2V, AD8038 C = 1.5pF –80 REF COMP V = ±15V, AD8038 C = 1pF REF COMP –90 V = ±15V, AD8038 C = 1.5pF REF COMP V = ±15V, AD8038 C = 1.8pF REF COMP –9 –100 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Power Supply Rejection Ratio vs. Frequency Figure 24. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor –60 0.08 T = 25°C A V =5V DD T = 25°C V = 5V A DD 0x7FF TO 0x800 V = 0V V =±3.5V REF 0.06 REF NRG = 2.154nV-s –65 AD8038 AMP C = 1.8pF COMP V = 3V DD 0.04 0x7FF TO 0x800 –70 NRG = 1.794nV-s 0.02 –75 0 –80 V =5V DD –0.02 0x800 TO 0x7FF NRG = 0.694nV-s –85 –0.04 V =5V DD 0x800 TO 0x7FF NRG = 0.694nV-s –0.06 –90 50 75 100 125 150 175 200 225 250 100 1k 10k 100k FREQUENCY (Hz) TIME (ns) Figure 25. Midscale Transition, VREF = 0 V Figure 28. THD + Noise vs. Frequency –1.66 100 V =5V DD T = 25°C A 0x7FF TO 0x800 MCLK = 200kHz V = 3.5V MCLK = 500kHz –1.68 REF NRG = 2.154nV-s AD8038 AMP 80 C = 1.8pF COMP V = 3V DD –1.70 MCLK = 1MHz 0x7FF TO 0x800 NRG = 1.794nV-s 60 –1.72 –1.74 40 –1.76 V =5V DD 0x800 TO 0x7FF 20 NRG = 0.694nV-s –1.78 T = 25°C V =5V A DD V = 3.5V 0x800 TO 0x7FF REF AD8038 AMP NRG = 0.694nV-s –1.80 0 50 75 100 125 150 175 200 225 250 05 10 20 30 400 TIME (ns) f (kHz) OUT Figure 26. Midscale Transition, V = 3.5 V Figure 29. Wideband SFDR vs. fOUT Frequency REF Rev. D | Page 11 of 28 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) 04588-057 04588-059 04588-058 SFDR (dB) THD + N (dB) PSRR (dB) 04588-061 04588-060 04588-062 AD5444/AD5446 Data Sheet 0 0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD V = 3.5V V = 3.5V REF REF –20 –20 AD8038 AMP AD8038 AMP –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 100k 200k 300k 400k 500k 10k 15k 20k 25k 30k FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Wideband SFDR , f = 20 kHz, Clock = 1 MHz OUT Figure 32. Narrow-Band SFDR, f = 20 kHz, Clock = 1 MHz OUT 0 0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD V = 3.5V V = 3.5V REF REF –20 –20 AD8038 AMP AD8038 AMP –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 100k 200k 300k 400k 500k 30k 40k 50k 60k 70k FREQUENCY (Hz) FREQUENCY (Hz) Figure 31. Wideband SFDR, f = 50 kHz, Clock = 1 MHz Figure 33. Narrow-Band SFDR, f = 50 kHz, Clock = 1 MHz OUT OUT Rev. D | Page 12 of 28 SFDR (dB) SFDR (dB) 04588-064 04588-063 SFDR (dB) SFDR (dB) 04588-066 04588-065 Data Sheet AD5444/AD5446 0 80 T = 25°C A T = 25°C A V = 3.5V REF AD8038 AMP –10 AD8038 AMP 70 –20 60 FULL SCALE –30 LOADED TO DAC 50 –40 –50 40 MIDSCALE –60 LOADED TO DAC 30 –70 20 –80 ZERO SCALE 10 LOADED TO DAC –90 0 –100 100 1k 10k 100k 1M 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 34. Narrow-Band IMD, f = 20 kHz and 25 kHz, Clock = 1 MHz Figure 36. Output Noise Spectral Density OUT 0 T = 25°C A V = 3.5V –10 REF AD8038 AMP –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100k 200k 300k 400k 500k FREQUENCY (Hz) Figure 35. Wideband IMD, f = 20 kHz and 25 kHz, Clock = 1 MHz OUT Rev. D | Page 13 of 28 IMD (dB) IMD (dB) 04588-068 04588-067 OUTPUT NOISE (nV/ Hz) 04588-069 AD5444/AD5446 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity Digital Feedthrough Relative accuracy or integral nonlinearity is a measure of the When the device is not selected, high frequency logic activ- maximum deviation from a straight line passing through the ity on the device’s digital inputs can be capacitively coupled endpoints of the DAC transfer function. It is measured after through the device to show up as noise on the I 1 and I 2 OUT OUT adjusting for zero scale and full scale and is normally expressed pins and, subsequently, into the following circuitry. This noise is in LSBs or as a percentage of full-scale reading. digital feedthrough. Differential Nonlinearity Multiplying Feedthrough Error Differential nonlinearity is the difference between the measured Multiplying feedthrough error is due to capacitive feedthrough change and the ideal 1 LSB change between any two adjacent from the DAC reference input to the DAC I 1 line, when all OUT codes. A specified differential nonlinearity of −1 LSB maximum 0s are loaded to the DAC. over the operating temperature range ensures monotonicity. Total Harmonic Distortion (THD) Gain Error The DAC is driven by an ac reference. The ratio of the rms sum Gain error or full-scale error is a measure of the output error of the harmonics of the DAC output to the fundamental value is between an ideal DAC and the actual device output. For this the THD. Usually only the lower-order harmonics, such as second DAC, ideal maximum output is V − 1 LSB. Gain error of the to fifth, are included. REF DAC is adjustable to zero with external resistance. 2 2 2 2 V +V +V +V 2 3 4 5 THD= 20 log Output Leakage Current V 1 Output leakage current is current that flows in the DAC ladder switches when the ladder is turned off. For the I 1 line, it can Digital Intermodulation Distortion OUT be measured by loading all 0s to the DAC and measuring the Second-order intermodulation (IMD) measurements are the I 1 current. Minimum current flows in the I 2 line when relative magnitudes of the fa and fb tones digitally generated by OUT OUT the DAC is loaded with all 1s. the DAC and the second-order products at 2fa − fb and 2fb − fa. Output Capacitance Compliance Voltage Range The maximum range of (output) terminal voltage for which Capacitance from I 1 or I 2 to AGND. OUT OUT the device provides the specified characteristics. Output Current Settling Time Spurious-Free Dynamic Range (SFDR) The amount of time it takes for the output to settle to a speci- fied level for a full-scale input change. For this device, it is The usable dynamic range of a DAC before spurious noise specified with a 100 Ω resistor to ground. The settling time interferes or distorts the fundamental signal. SFDR is the SYNC measure of difference in amplitude between the fundamental specification includes the digital delay from the rising and the largest harmonically or nonharmonically related spur edge to the full-scale output change. from dc to full Nyquist bandwidth (half the DAC sampling Digital-to-Analog Glitch Impulse rate or f /2). Narrow-band SFDR is a measure of SFDR over S The amount of charge injected from the digital inputs to the an arbitrary window size, in this case 50% of the fundamental. analog output when the inputs change state. This is normally Digital SFDR is a measure of the usable dynamic range of the specified as the area of the glitch in either picoamps per second DAC when the signal is a digitally generated sine wave. or nanovolts per second, depending upon whether the glitch is measured as a current or voltage signal. Rev. D | Page 14 of 28 Data Sheet AD5444/AD5446 GENERAL DESCRIPTION CIRCUIT OPERATION DAC SECTION Unipolar Mode The AD5444/AD5446 are 12-bit and 14-bit current output Using a single op amp, the AD5444/AD5446 can easily be DACs consisting of segmented (4 bits), inverting R– 2R ladder configured to provide 2-quadrant multiplying operation or configurations. A simplified diagram for the 12-bit AD5444 a unipolar output voltage swing, as shown in Figure 38. is shown in Figure 37. RR R When an output amplifier is connected in unipolar mode, the V REF output voltage is given by 2R 2R 2R 2R 2R R S1 S2 S3 S12 D R V   V FB OUT REF n 2 I 1 OUT I 2 OUT where: DAC DATA LATCHES D is the fractional representation of the digital word loaded to AND DRIVERS the DAC: Figure 37. Simplified Ladder D = 0 to 4095 (12-bit AD5444) The feedback resistor (RFB) has a value of R. The value of R is D = 0 to 16383 (14-bit AD5446) typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If IOUT1 is n is the number of bits. kept at the same potential as GND, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the Note that the output voltage polarity is opposite to the V REF input resistance presented at V is always constant and nomi- REF polarity for dc reference voltages. nally of value R. The DAC output (I 1) is code-dependent, OUT This DAC is designed to operate with either negative or positive producing various resistances and capacitances. The external reference voltages. The V power pin is used by the internal DD amplifier choice should take into account the variation in digital logic only to drive the on and off states of the DAC impedance generated by the DAC on the amplifiers inverting switches. The DAC is also designed to accommodate ac refer- input node. ence input signals in the range of −10 V to +10 V. With a fixed Access is provided to the VREF, RFB, and both IOUT terminals of +10 V reference, the circuit shown in Figure 38 provides a the DAC, making the device extremely versatile and allowing it unipolar 0 V to −10 V output voltage swing. When V is an IN to be configured in several different operating modes. For ac signal, the circuit performs 2-quadrant multiplication. example, the device provides unipolar output mode, 4-quadrant Table 5 shows the relationship between digital code and multiplication in bipolar mode, and single-supply mode of expected output voltage for unipolar operation. operation. Note that a matching switch is used in series with the internal RFB. Power must be applied to VDD to achieve continuity Table 5. Unipolar Code when measuring RFB. Digital Input Analog Output (V) 1111 1111 1111 −V (4095/4096) REF 1000 0000 0000 −V (2048/4096) = −V /2 REF REF 0000 0000 0001 −VREF (1/4096) 0000 0000 0000 −VREF (0/4096) = 0 V DD R2 C1 V R DD FB I 1 OUT AD5444/ V REF V A1 REF AD5446 R1 I 2 OUT V = 0V TO –V OUT REF SYNC SCLK SDIN AGND MICROCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. Figure 38. Unipolar Operation Rev. D | Page 15 of 28 04464-029 04588-030 AD5444/AD5446 Data Sheet Bipolar Operation Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. In some applications, it may be necessary to generate a full 4-quadrant multiplying operation, or a bipolar output swing. Table 6. Bipolar Code This can easily be accomplished by using another external Digital Input Analog Output (V) amplifier and some external resistors, as shown in Figure 39. 1111 1111 1111 +V (2047/2048) REF In this circuit, the second amplifier (A2) provides a gain of 2. 1000 0000 0000 0 Biasing the external amplifier with an offset from the reference 0000 0000 0001 −V (2047/2048) REF voltage results in a full 4-quadrant multiplying operation. The 0000 0000 0000 −V (0/2048) REF transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is Stability incremented from code zero (V = −V ) to midscale OUT REF In the current-to-voltage (I-to-V) configuration, the I 1of the OUT (V − 0 V) to full scale (V = +V ) OUT OUT REF DAC and the inverting node of the op amp must be connected as closely as possible, and proper PCB layout techniques must D   V = V × − V   OUT REF REF n−1 be employed. Because every code change corresponds to a step  2  function, gain peaking can occur if the op amp has limited GBP where: and excessive parasitic capacitance exists at the inverting node. D is the fractional representation of the digital word loaded This parasitic capacitance introduces a pole into the open-loop to the DAC: response that can cause ringing or instability in the closed-loop applications circuit. D = 0 to 4095 (12-bit AD5444) D = 0 to 16383 (14-bit AD5446) An optional compensation capacitor (C1) can be added in parallel with R for stability, as shown in Figure 38 and FB n is the resolution of the DAC. Figure 39. Too small a value for C1 can produce ringing at When V is an ac signal, the circuit performs 4-quadrant IN the output, while too large a value can adversely affect the multiplication. settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation. R3 20kΩ V DD R2 R5 20kΩ C1 V R DD FB R4 R1 I 1 OUT 10kΩ AD5444/ V ±10V V A1 REF REF AD5446 A2 I 2 OUT SYNC SCLK SDIN V = –V TO +V OUT REF REF AGND NOTES MICROCONTROLLER 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 39. Bipolar Operation (4-Quadrant Multiplication) Rev. D | Page 16 of 28 04588-031 Data Sheet AD5444/AD5446 V = +5V DD SINGLE-SUPPLY APPLICATIONS ADR03 V V OUT IN Voltage Switching Mode of Operation GND Figure 40 shows the AD5444/AD5446 DACs operating in the +5V C1 V R DD FB voltage switching mode. The reference voltage (V ) is applied IN I 1 OUT –2.5V to the I 1 pin, I 2 is connected to AGND, and the output V OUT OUT REF I 2 OUT V = 0V TO +2.5V OUT voltage is available at the V terminal. In this configuration, REF GND –5V a positive reference voltage results in a positive output voltage, making single-supply operation possible. The output from NOTES the DAC is voltage at a constant impedance (the DAC ladder 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, resistance). Therefore, an op amp is necessary to buffer the IF A1 IS A HIGH SPEED AMPLIFIER. output voltage. The reference input no longer sees a constant Figure 41. Positive Voltage Output with Minimum Components input impedance but rather one that varies with code, so the ADDING GAIN voltage input should be driven from a low impedance source. In applications in which the output voltage is required to be V DD R1 R2 greater than V , gain can be added with an additional external IN amplifier, or it can be achieved in a single stage. It is important R V FB DD to take into consideration the effect of the temperature coeffi- V OUT V IN I 1 V REF OUT cients of the DAC’s thin film resistors. Simply placing a resistor in series with the R resistor can cause mismatches in the GND FB temperature coefficients and result in larger gain temperature coefficient errors. Instead, increase the gain of the circuit by NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. using the recommended configuration shown in Figure 42. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. R1, R2, and R3 should all have similar temperature coefficients, Figure 40. Single-Supply Voltage Switching Mode Operation but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains It is important to note that, with this configuration, V is lim- IN of greater than 1 are required. ited to low voltages, because the switches in the DAC ladder do V DD not have the same source-drain drive voltage. As a result, their on resistance differs, which degrades the integral linearity of the C1 DAC. In addition, V must not go negative by more than 0.3 V, IN V R DD FB or an internal diode turns on, exceeding the maximum ratings I 1 OUT R1 V V IN V REF OUT of the device. In this type of application, the full range of the I 2 OUT R3 multiplying capability of the DAC is lost. GND R2 + R3 GAIN = R2 R2 Positive Output Voltage R2R3 The output voltage polarity is opposite to the V polarity for R1 = REF NOTES R2 + R3 1. ADDITIONAL PINS OMITTED FOR CLARITY. dc reference voltages. To achieve a positive voltage output, an 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because Figure 42. Increasing Gain of Current Output DAC of the resistor’s tolerance errors. To generate a negative reference, DIVIDER OR PROGRAMMABLE GAIN ELEMENT the reference can be level-shifted by an op amp such that the Current-steering DACs are very flexible and lend themselves to V and GND pins of the reference become the virtual ground OUT many different applications. If this type of DAC is connected as and −2.5 V, respectively, as shown in Figure 41. the feedback element of an op amp and R is used as the input FB resistor, as shown in Figure 43, then the output voltage is inversely proportional to the digital input fraction, D. −n For D = 1 − 2 , the output voltage is −n V = −V /D = −V /(1 − 2 ) OUT IN IN Rev. D | Page 17 of 28 04588-032 04588-034 04588-033 AD5444/AD5446 Data Sheet V DD The input bias current of an op amp also generates an offset V IN at the voltage output as a result of the bias current flowing in the feedback resistor, R . Most op amps have input bias R V FB FB DD currents low enough to prevent any significant errors in I 1 V REF OUT 12-bit applications. GND Common-mode rejection of the op amp is important in voltage switching circuits because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate V OUT common-mode rejection for use at 8-bit, 10-bit, and 12-bit resolutions. NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY. Provided that the DAC switches are driven from true wideband Figure 43. Current-Steering DAC Used as a Divider low impedance sources (V and AGND), they settle quickly. IN or Programmable Gain Element Consequently, the slew rate and settling time of a voltage switching As D is reduced, the output voltage increases. For small values DAC circuit is determined largely by the output op amp. To of the digital fraction (D), it is important to ensure that the obtain minimum settling time in this configuration, it is impor- amplifier does not saturate and the required accuracy is met. tant to minimize capacitance at the V node (voltage output REF For example, an 8-bit DAC driven with the binary code 0x10 node in this application) of the DAC. This is done by using low (0001 0000), that is, 16 decimal, in the circuit of Figure 43, input, capacitance buffer amplifiers and careful board design. should cause the output voltage to be 16 × V . However, if the IN Most single-supply circuits include ground as part of the analog DAC has a linearity specification of ±0.5 LSB, then D can, in signal range, which, in turn, requires an amplifier that can handle fact, have a weight in the range of 15.5/256 to 16.5/256, so the rail-to-rail signals. A large range of single-supply amplifiers is possible output voltage is in the range 15.5 V to 16.5 V . This IN IN available from Analog Devices, Inc. (see Table 8 and Table 9 for is an error of 3%, even though the DAC itself has a maximum suitable suggestions). error of 0.2%. REFERENCE SELECTION DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an When selecting a reference for use with the AD5444/AD5446 current output DAC, pay attention to the output voltage tem- opposite current supplied from the op amp through the DAC. perature coefficient specification. This parameter affects not Because only a fraction (D) of the current into the V terminal REF only the full-scale error but can also affect the linearity (INL is routed to the I 1 terminal, the output voltage has to change, OUT and DNL) performance. The reference temperature coefficient as follows: should be consistent with the system accuracy specifications. Output Error Voltage due to DAC Leakage = (Leakage × R)/D For example, an 8-bit system required to hold its overall speci- where R is the DAC resistance at the V terminal. REF fication to within 1 LSB over the temperature range 0°C to 50°C For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain dictates that the maximum system drift with temperature should be less than 78 ppm/°C. (1/D) of 16, the error voltage is 1.6 mV. A 12-bit system with the same temperature range to overall AMPLIFIER SELECTION specification within 2 LSBs requires a maximum drift of The primary requirement for the current-steering mode is 10 ppm/°C. By choosing a precision reference with low output an amplifier with low input bias currents and low input offset temperature coefficient, this error source can be minimized. voltage. The input offset voltage of an op amp is multiplied by Table 7 suggests some of the dc references available from the variable gain (due to the code-dependent output resistance Analog Devices that are suitable for use with this range of of the DAC) of the circuit. A change in this noise gain between current output DACs. two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Rev. D | Page 18 of 28 04588-035 Data Sheet AD5444/AD5446 Table 7. Suitable Analog Devices Precision References Initial Tolerance Temperature Drift Part No. Output Voltage (V) Accuracy (%) Coefficient (ppm/°C) I (mA) Output Noise (µV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Analog Devices Precision Op Amps Part No. Supply Voltage (V) V (Max) (µV) I (Max) (nA) 0.1 Hz to 10 Hz Noise (µV p-p) Supply Current (µA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps BW @ ACL Slew Rate Part No. Supply Voltage (V) (Typ) (MHz) (Typ) (V/µs) V (Max) (µV) I (Max) (nA) Package OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP AD8021 ±2.25 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8 Rev. D | Page 19 of 28 AD5444/AD5446 Data Sheet SERIAL INTERFACE The AD5444/AD5446 have an easy-to-use, 3-wire interface that After the falling edge of the 16th SCLK pulse, bring SYNC high is compatible with SPI, QSPI, MICROWIRE, and DSP inter- to transfer data from the input shift register to the DAC register. face standards. Data is written to the device in 16-bit words. Daisy-Chain Mode This 16-bit word consists of two control bits, 12 data bits or Daisy-chain mode is the default power-on mode. To disable 14 data bits, as shown in Figure 44 and Figure 45. The AD5446 the daisy-chain function, write 01 to the control word. In daisy- uses all 14 bits of DAC data while AD5444 uses 12 bits and chain mode, the internal gating on the SCLK is disabled. The ignores the 2 LSBs. SCLK is continuously applied to the input shift register when Control Bit C1 and Control Bit C0 allow the user to load and SYNC is low. If more than 16 clock pulses are applied, the data update the new DAC code and to change the active clock edge. ripples out of the shift register and appears on the SDO line. By default, the shift register clocks data on the falling edge, but This data is clocked out on the rising edge of the SCLK (this this can be changed via the control bits. If changed, the DAC is the default; use the control word to change the active edge) core is inoperative until the next data frame. A power cycle and is valid for the next device on the falling edge (default). resets this back to the default condition. On-chip, power-on By connecting this line to the SDIN input on the next device in reset circuitry ensures the device powers on with zero scale the chain, a multidevice interface is constructed. Sixteen clock loaded to the DAC register and the I line. OUT pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16 N, where N is the Table 10. DAC Control Bits number of devices in the chain. C1 C0 Function Implemented 0 0 Load and update (power-on default) SYNC When the serial transfer to all devices is complete, 0 1 Disable SDO should be taken high. This prevents any further data from 1 0 No operation being clocked into the shift register. A burst clock containing 1 1 Clock data to shift register on rising edge the exact number of clock cycles can be used, and SYNC can be taken high some time later. After the rising edge of SYNC, data SYNC Function is automatically transferred from each device’s input register to SYNC is an edge-triggered input that acts as a frame synchroni- the addressed DAC. zation signal. Data can be transferred into the device only while When the control bits = 10, the device is in no operation mode. SYNC SYNC is low. To start the serial data transfer, should be This can be useful in daisy-chain applications where the user SYNC taken low, observing the minimum falling to the SCLK does not want to change the settings of a particular DAC in the falling edge setup time, t . To minimize the power consumption 4 chain. Simply write 10 to the control bits for that DAC and the of the device, the interface powers up fully only when the device following data bits are ignored. is being written to, that is, on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC. DB15 (MSB) DB0 (LSB) C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X DATA BITS CONTROL BITS Figure 44. AD5444 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C1 C0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DATA BITS CONTROL BITS Figure 45. AD5446 14-Bit Input Shift Register Contents Rev. D | Page 20 of 28 04588-038 04588-037 Data Sheet AD5444/AD5446 Table 11. SPORT Control Register Setup MICROPROCESSOR INTERFACING Name Setting Description Microprocessor interfacing to the AD5444/AD5446 DAC is TFSW 1 Alternate framing through a serial bus that uses standard protocol compatible INVTFS 1 Active low frame signal with microcontrollers and DSP processors. The communica- DTYPE 00 Right-justify data tions channel is a 3-wire interface consisting of a clock signal, a ISCLK 1 Internal serial clock data signal, and a synchronization signal. The AD5444/AD5446 TFSR 1 Frame every word requires a 16-bit word, with the default being data valid on the ITFS 1 Internal framing signal falling edge of SCLK, but this can be changed using the control SLEN 1111 16-bit data-word bits in the data-word. ADSP-BF5xx to AD5444/AD5446 Interface ADSP-21xx to AD5444/AD5446 Interface The ADSP-21xx family of DSPs is easily interfaced to the The ADSP-BF5xx family of processors has an SPI-compatible AD5444/AD5446 DAC without the need for extra glue logic. port that enables the processor to communicate with SPI- compatible devices. A serial interface between the ADSP-BF5xx Figure 46 is an example of an SPI interface between the DAC and the AD5444/AD5446 DAC is shown in Figure 48. In this and the ADSP-2191M. SCK of the DSP drives the serial clock configuration, data is transferred through the MOSI (master line, SCLK. SYNC is driven from one of the port lines, in this output/slave input) pin. SYNC is driven by the SPI chip select SPIxSEL case . pin, which is a reconfigured programmable flag pin. AD5444/ ADSP-2191* AD5446* ADSP-BF5xx* AD5444/AD5446* SYNC SPIxSEL SPIxSEL SYNC MOSI SDIN MOSI SDIN SCK SCLK SCLK SCK *ADDITIONAL PINS OMITTED FOR CLARITY. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 46. ADSP-2191M SPI to AD5444/AD5446 Interface Figure 48. ADSP-BF5xx to AD5444/AD5446 Interface A serial interface between the DAC and DSP SPORT is shown The ADSP-BF5xx processor incorporates channel synchronous in Figure 47. In this interface example, SPORT0 is used to trans- serial ports (SPORT). A serial interface between the DAC and fer data to the DAC shift register. Transmission is initiated by the DSP SPORT is shown in Figure 49. When the SPORT is writing a word to the Tx register after the SPORT has been enabled, initiate transmission by writing a word to the Tx register. enabled. In a write sequence, data is clocked out on each rising The data is clocked out on each rising edge of the DSPs serial edge of the DSP serial clock and clocked into the DAC input clock and clocked into the DAC input shift register on the shift register on the falling edge of its SCLK. The update of the falling edge of its SCLK. The DAC output is updated by using SYNC DAC output takes place on the rising edge of the signal. the transmit frame synchronization (TFS) line to provide a ADSP-2101/ AD5444/AD5446* SYNC signal. ADSP-2103/ ADSP-2191* TFS SYNC ADSP-BF5xx* AD5444/AD5446* DT SDIN TFS SYNC SCLK SCLK DT SDIN SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 47. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to AD5444/AD5446 Interface *ADDITIONAL PINS OMITTED FOR CLARITY Figure 49. ADSP-BF5xx to AD5444/AD5446 Interface Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC inter- face expects a t (SYNC falling edge to SCLK falling edge setup 4 time) of 13 ns minimum. See the ADSP-21xx User Manual for information on clock and frame sync frequencies for the SPORT register. Table 11 shows the setup for the SPORT control register. Rev. D | Page 21 of 28 04588-074 04588-082 04588-039 04588-040 AD5444/AD5446 Data Sheet 80C51/80L51 to AD5444/AD5446 Interface MC68HC11* AD5444/AD5446* A serial interface between the DAC and the 80C51/80L51 is PC7 SYNC shown in Figure 50. TxD of the 80C51/80L51 drives SCLK of SCLK SCK the DAC serial interface, while RxD drives the serial data line, SDIN MOSI SDIN. P1.1 is a bit-programmable pin on the serial port and SYNC is used to drive . When data is to be transmitted to the *ADDITIONAL PINS OMITTED FOR CLARITY switch, P1.1 is taken low. The 80C51/80L51 transmits data only Figure 51. MC68HC11 to AD5444/AD5446 Interface in 8-bit bytes; therefore, only eight falling clock edges occur in If the user wants to verify the data previously written to the the transmit cycle. To load data correctly to the DAC, P1.1 is input shift register, the SDO line can be connected to MISO of left low after the first eight bits are transmitted, and a second SYNC the MC68HC11, and, with low, the shift register clocks write cycle is initiated to transmit the second byte of data. data out on the rising edges of SCLK. Data on RxD is clocked out of the microcontroller on the rising MICROWIRE to AD5444/AD5446 Interface edge of TxD and is valid on the falling edge. As a result, no glue Figure 52 shows an interface between the DAC and any logic is required between the DAC and microcontroller inter- MICROWIRE-compatible device. Serial data is shifted out face. P1.1 is taken high following the completion of this cycle. on the falling edge of the serial clock, SK, and is clocked into The 80C51/80L51 provides the LSB of its SBUF register as the the DAC input shift register on the rising edge of SK, which first bit in the data stream. The DAC input register requires its corresponds to the falling edge of the DAC SCLK. data with the MSB as the first bit received. The transmit routine should take this into account. MICROWIRE* AD5444/AD5446* SK SCLK AD5444/AD5446* 8051* SO TxD SCLK SDIN CS SYNC RxD SDIN P1.1 SYNC *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 52. MICROWIRE to AD5444/AD5446 Interface Figure 50. 80C51/80L51 to AD5444/AD5446 Interface PIC16C6x/7x to AD5444/AD5446 Interface MC68HC11 Interface to AD5444/AD5446 Interface The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is Figure 51 is an example of a serial interface between the DAC done by writing to the synchronous serial port control register and the MC68HC11 microcontroller. The serial peripheral (SSPCON); see the PIC16/17 Microcontroller User Manual. interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock In this example, I/O port RA1 is used to provide a SYNC phase bit (CPHA) = 1. The SPI is configured by writing to the signal and enable the serial port of the DAC. This micro- SPI control register (SPCR); see the 68HC11 User Manual. SCK controller transfers only eight bits of data during each serial of the 68HC11 drives the SCLK of the DAC interface, the MOSI transfer operation; therefore, two consecutive write operations output drives the serial data line (SDIN) of the AD5444/AD5446. are required. Figure 53 shows the connection diagram. The SYNC signal is derived from a port line (PC7). When data PIC16C6x/7x* AD5444/AD5446* is being transmitted to the AD5444/AD5446, the SYNC line is SCLK SCK/RC3 taken low (PC7). Data appearing on the MOSI output is valid SDIN SDI/RC4 on the falling edge of SCK. Serial data from the 68HC11 is RA1 SYNC transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. *ADDITIONAL PINS OMITTED FOR CLARITY To load data to the DAC, PC7 is left low after the first eight bits Figure 53. PIC16C6x/7x to AD5444/AD5446 Interface are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. D | Page 22 of 28 04588-041 04588-044 04588-043 04588-042 Data Sheet AD5444/AD5446 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- A microstrip technique, by far the best, is not always possible tion of the power supply and ground return layout helps to with a double-sided board. In this technique, the component ensure the rated performance. The printed circuit boards on side of the board is dedicated to the ground plane, while signal which the AD5444/AD5446 are mounted should be designed traces are placed on the solder side. so the analog and digital sections are separated and confined to It is good practice to employ compact, minimum lead-length certain areas of the board. If the DACs are in systems in which PCB layout design. Leads to the input should be as short as multiple devices require a AGND-to-DGND connection, the possible to minimize IR drops and stray inductance. connection should be made at one point only. The star ground The PCB metal traces between V and R should also be REF FB point should be established as close as possible to the devices. matched to minimize gain error. To maximize high frequency The DAC should have ample supply bypassing of 10 µF in performance, the I-to-V amplifier should be located as close parallel with 0.1 µF on the supply located as close to the pack- to the device as possible. age as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on oppo- site sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. Rev. D | Page 23 of 28 AD5444/AD5446 Data Sheet OVERVIEW OF AD54xx AND AD55xx CURRENT OUTPUT DEVICES Table 12. 1 Part Number Resolution (Bits) Number of DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns pulse width CS AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. D | Page 24 of 28 Data Sheet AD5444/AD5446 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 54. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution (Bits) INL (LSB) Temperature Range Package Description Package Option Branding AD5444YRM 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D27 AD5444YRM-REEL 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D27 AD5444YRM-REEL7 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D27 AD5444YRMZ 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D6X AD5444YRMZ-REEL 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D6X AD5444YRMZ-REEL7 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D6X AD5446YRM 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D28 AD5446YRM-REEL 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D28 AD5446YRM-REEL7 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D28 AD5446YRMZ 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D7Z AD5446YRMZ-RL7 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D7Z EVAL-AD5446SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 25 of 28 091709-A AD5444/AD5446 Data Sheet NOTES Rev. D | Page 26 of 28 Data Sheet AD5444/AD5446 NOTES Rev. D | Page 27 of 28 AD5444/AD5446 Data Sheet NOTES ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04588-0-4/12(D) Rev. D | Page 28 of 28