ANALOG DEVICES AD5432

8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5426/AD5432/AD5443 FEATURES GENERAL DESCRIPTION 1 3 V to 5.5 V supply operation The AD5426/AD5432/AD5443 are CMOS 8-, 10-, and 12-bit 50 MHz serial interface current output digital-to-analog converters (DACs), respectively. 10 MHz multiplying bandwidth These devices operate from a 3 V to 5.5 V power supply, making 2.5 MSPS update rate them suitable for battery-powered applications and many other INL of ±1 LSB for 12-bit DAC applications. ±10 V reference input These DACs use a double buffered, 3-wire serial interface that is Low glitch energy < 2 nV-s compatible with SPI, QSPI™, MICROWIRE™, and most DSP Extended temperature range −40°C to +125°C interface standards. In addition, a serial data out pin (SDO) 10-lead MSOP package allows for daisy-chaining when multiple packages are used. Pin-compatible 8-, 10-, and 12-bit current output DACs Data readback allows the user to read the contents of the DAC Guaranteed monotonic register via the SDO pin. On power-up, the internal shift register 4-quadrant multiplication and latches are filled with 0s and the DAC outputs are at zero scale. Power-on reset with brownout detection As a result of manufacturing on a CMOS submicron process, Daisy-chain mode the parts offer excellent 4-quadrant multiplication characteristics Readback function with large signal multiplying bandwidths of 10 MHz. The applied 0.4 μA typical power consumption external reference input voltage, V , determines the full-scale REF APPLICATIONS output current. An integrated feedback resistor, R , provides FB Portable battery-powered applications temperature tracking and full-scale voltage output when combined Waveform generators with an external current to voltage precision amplifier. Analog processing The AD5426/AD5432/AD5443 DACs are available in small, Instrumentation 10-lead MSOP packages. Programmable amplifiers and attenuators The EVAL-AD5443SDZ/EVAL-AD5446SDZ/EVAL-AD5453SDZ Digitally controlled calibration evaluation board is available for evaluating DAC performance. For Programmable filters and oscillators more information, see the UG-327 evaluation board user guide. Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V V DD REF R AD5426/ R FB AD5432/ I 1 8-/10-/12-BIT OUT AD5443 R-2R DAC I 2 OUT DAC REGISTER POWER-ON RESET INPUT LATCH SYNC CONTROL LOGIC AND SCLK INPUT SHIFT REGISTER SDIN SDO GND Figure 1. 1 U.S. Patent No. 5,689,257. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03162-001 AD5426/AD5432/AD5443 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Operation ....................................................................... 15  Applications....................................................................................... 1  Single-Supply Applications ....................................................... 17  General Description ......................................................................... 1  Positive Output Voltage............................................................. 17  Functional Block Diagram .............................................................. 1  Adding Gain................................................................................ 18  Revision History ............................................................................... 2  DACs Used as a Divider or Programmable Gain Element ... 18  Specifications..................................................................................... 3  Reference Selection .................................................................... 18  Timing Characteristics ................................................................ 5  Amplifier Selection .................................................................... 18  Absolute Maximum Ratings............................................................ 6  Serial Interface ............................................................................ 20  ESD Caution.................................................................................. 6  PCB Layout and Power Supply Decoupling................................ 22  Pin Configuration and Function Descriptions............................. 7  Overview of AD54xx and AD55xx Devices ............................... 23  Typical Performance Characteristics ............................................. 8  Outline Dimensions....................................................................... 24  Terminology .................................................................................... 14  Ordering Guide .......................................................................... 24  Theory of Operation ...................................................................... 15  REVISION HISTORY 4/12—Rev. C to Rev. D Deleted Figure 62............................................................................ 26 Changed V = 2.5 V to V = 3 V ............................. Throughout 2/09—Rev. B to Rev. C DD DD Changes to General Description Section ...................................... 1 Changes to Low Power Serial Interface Section and Daisy- Deleted Microprocessor Interface Section, ADSP-21xx to Chain Mode Section....................................................................... 20 Updated Outline Dimensions....................................................... 28 AD5426/AD5432/AD5443 Interface Section, Figure 51, Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443 Interface Section, Figure 53 and Figure 54; Renumbered 11/08—Rev. A to Rev. B Sequentially ..................................................................................... 21 Changes to Ordering Guide .......................................................... 28 Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface 5/05—Rev. 0 to Rev. A Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/ Updated Format..................................................................Universal AD5443 Interface Section, Figure 56, MICROWIRE to Changes to Specifications.................................................................3 AD5426/AD5432/AD5443 Interface Section, Figure 57, Changes to Figure 42...................................................................... 16 Change to Figure 45 ....................................................................... 17 PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22 Deleted Evaluation Board for the AD5426/AD5432/AD5443 Change to Figure 46 ....................................................................... 18 Series of DACs Section, Operating the Evaluation Board Changes to Table 7, Table 8, and Table 9 ..................................... 19 Section, and Power Supplies Section............................................ 23 Additions to Microprocessor Interface Section.......................... 21 Deleted Figure 59 and Figure 60................................................... 24 Updated Outline Dimensions ....................................................... 24 2/04—Revision 0: Initial Version Changes to Ordering Guide .......................................................... 24 Deleted Figure 61............................................................................ 25 Rev. D | Page 2 of 24 Data Sheet AD5426/AD5432/AD5443 SPECIFICATIONS VDD = 3 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted; dc performance measured with OP177; ac performance with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5426 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic AD5432 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5443 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±10 mV 1 Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±10 nA Data = 0x0000, T = 25°C, I 1 A OUT ±20 nA Data = 0x0000, T = −40°C to 125°C, I 1 OUT 1 REFERENCE INPUT Reference Input Range ±10 V V Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C REF R Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C FB Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF 1 DIGITAL INPUT/OUTPUT Input High Voltage, VIH 1.7 V Input Low Voltage, V 0.6 V IL Output High Voltage, V V − 1 V V = 4.5 V to 5 V, I = 200 μA OH DD DD SOURCE V − 0.5 V V = 3 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 0.4 V VDD = 3 V to 3.6 V, ISINK = 200 μA Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF 1 DYNAMIC PERFORMANCE Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s Output Voltage Settling Time V = 10 V; R = 100 Ω, DAC latch alternately REF LOAD loaded with 0s and 1s Measured to ±16 mV of FS 50 100 ns Measured to ±4 mV of FS 55 110 ns Measured to ±1 mV of FS 90 160 ns Digital Delay 40 75 ns Interface delay time 10% to 90% Rise/Fall Time 15 30 ns Rise and fall time, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V = 0 V REF Multiplying Feedthrough Error DAC latch loaded with all 0s, VREF = ±3.5 70 dB 1 MHz 48 dB 10 MHz Rev. D | Page 3 of 24 AD5426/AD5432/AD5443 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Output Capacitance IOUT1 12 17 pF All 0s loaded 10 12 pF All 1s loaded I 2 22 25 pF All 0s loaded OUT 10 12 pF All 1s loaded Digital Feedthrough 0.1 nV-s SYNC Feedthrough to DAC output with high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Digital THD Clock = 1 MHz, V = 3.5 V, C = 1.8 pF REF COMP 50 kHz f 73 dB OUT 20 kHz f 74 dB OUT Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 75 dB 20 kHz f 76 dB OUT SFDR Performance (Narrow Band) Clock = 1 MHz, V = 3.5 V REF 50 kHz f 87 dB OUT 20 kHz fOUT 87 dB Intermodulation Distortion 78 dB Clock = 1 MHz, f1 = 20 kHz, f2 = 25 kHz, VREF = 3.5 V POWER REQUIREMENTS Power Supply Range 3.0 5.5 V IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 μA T = −40°C to +125°C , logic inputs = 0 V or V DD 1 Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization, not subject to production testing. Rev. D | Page 4 of 24 Data Sheet AD5426/AD5432/AD5443 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 3 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 3 V to 5.5 V 4.5 V to 5.5 V Unit Test Conditions/Comments fSCLK 50 50 MHz max Max clock frequency t1 20 20 ns min SCLK cycle time t2 8 8 ns min SCLK high time t 8 8 ns min SCLK low time 3 1 t 13 13 ns min SYNC falling edge to SCLK active edge setup time 4 t 5 5 ns min Data setup time 5 t6 3 3 ns min Data hold time t7 5 5 ns min SYNC rising edge to SCLK active edge t 30 30 ns min Minimum SYNC high time 8 2 t 80 45 ns typ SCLK active edge to SDO valid 9 120 65 ns max 1 Falling or rising edge as determined by control bits of serial word. 2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4. t 1 SCLK t t 2 3 t t 8 4 t 7 SYNC t 6 t 5 DIN DB15 DB0 ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram t 1 SCLK t t t 2 3 7 t t 4 8 t6 SYNC t 6 t 5 DB15 DB0 SDIN DB15 (N) DB0 (N) (N + 1) (N + 1) t 9 SDO DB15(N) DB0(N) ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain and Readback Modes Timing Diagram Rev. D | Page 5 of 24 03162-002 03162-003 AD5426/AD5432/AD5443 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 3. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect VREF, RFB to GND −12 V to +12 V device reliability. IOUT1, IOUT2 to GND −0.3 V to VDD + 0.3 V 1 Logic Inputs and Output −0.3 V to VDD + 0.3 V 200μAI OL Operating Temperature Range Extended Industrial (Y Version) −40°C to +125°C V + V OH (MIN) OL (MAX) TO OUTPUT PIN Storage Temperature Range −65°C to +150°C 2 C L Junction Temperature 150°C 20pF 10-lead MSOP θJA Thermal Impedance 206°C/W 200μAI OH Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C Figure 4. Load Circuit for SDO Timing Specifications 1 SYNC Overvoltages at SCLK, , and DIN are clamped by internal diodes. ESD CAUTION Rev. D | Page 6 of 24 03162-004 Data Sheet AD5426/AD5432/AD5443 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I 1 1 10 R OUT FB AD5426/ I 2 2 9 V OUT REF AD5432/ GND 3 8 V DD AD5443 SCLK 4 7 SDO TOP VIEW (Not to Scale) SDIN 5 6 SYNC Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 IOUT1 DAC Current Output. 2 I 2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. OUT 3 GND Digital Ground Pin. 4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz. 5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to rising edge. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial interface counts clocks, and data is latched to the shift register on the 16th active clock edge. 7 SDO Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge. 8 VDD Positive Power Supply Input. These parts can be operated from a supply of 3 V to 5.5 V. 9 V DAC Reference Voltage Input. REF 10 R DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. FB Rev. D | Page 7 of 24 03162-005 AD5426/AD5432/AD5443 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 T = 25°C T = 25°C A A V = 10V V = 10V REF REF 0.15 0.15 V = 5V V = 5V DD DD 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 6. INL vs. Code (8-Bit DAC) Figure 9. DNL vs. Code (8-Bit DAC) 0.5 0.5 T = 25°C A T = 25°C A V = 10V REF V = 10V 0.4 0.4 REF V = 5V DD V = 5V DD 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 600 800 10000 0 200 400 600 800 1000 CODE CODE Figure 7. INL vs. Code (10-Bit DAC) Figure 10. DNL vs. Code (10-Bit DAC) 1.0 1.0 T = 25°C T = 25°C A A V = 10V V = 10V 0.8 REF 0.8 REF V = 5V V = 5V DD DD 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 8. INL vs. Code (12-Bit DAC) Figure 11. DNL vs. Code (12-Bit DAC) Rev. D | Page 8 of 24 INL (LSB) iNL (LSB) INL (LSB) 03162-008 03162-007 03162-006 DNL (LSB) DNL (LSB) INL (LSB) 03162-011 03162-010 03162-009 Data Sheet AD5426/AD5432/AD5443 0.6 2.0 0.5 1.5 MAX INL 0.4 MAX INL 1.0 T = 25°C A 0.3 V = 0V REF 0.5 V = 3V DD 0.2 AD5443 T = 25°C A 0 MAX DNL V = 5V DD 0.1 AD5443 –0.5 0 –1.0 MIN INL –0.1 MIN INL MIN DNL –1.5 –0.2 –0.3 –2.0 23 45 67 89 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 REFERENCE VOLTAGE V (V) BIAS Figure 12. INL vs. Reference Voltage Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2 –0.40 4 T = 25°C T = 25°C A A MAX DNL V = 5V V = 2.5V DD REF 3 AD5443 V = 3V DD –0.45 AD5443 2 MAX INL –0.50 1 0 –0.55 –1 MIN DNL –0.60 –2 MIN INL –3 MIN DNL –0.65 –4 –0.70 –5 23 45 67 89 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 REFERENCE VOLTAGE V (V) BIAS Figure 13. DNL vs. Reference Voltage Figure 16. Linearity vs. VBIAS Voltage Applied to IOUT2 5 0.5 T = 25°C V = 10V A REF V = 0V 4 0.4 REF V = 3V AND 5V DD 3 0.3 V = 5V DD 2 0.2 1 0.1 GAIN ERROR 0 0 V = 3V DD OFFSET ERROR –1 –0.1 –2 –0.2 –3 –0.3 –4 –0.4 –5 –0.5 –60 –40 –20 0 20 40 60 80 100 120 140 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 TEMPERATURE (°C) V (V) BIAS Figure 14. Gain Error vs. Temperature Figure 17. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Rev. D | Page 9 of 24 ERROR (mV) DNL (LSB) INL (LSB) 03162-014 03162-013 03162-012 VOLTAGE (mV) LSB LSB 03162-017 03162-016 03162-015 AD5426/AD5432/AD5443 Data Sheet 0.5 0.7 T = 25°C T = 25°C A A V = 2.5V REF 0.4 V = 3V AND 5V DD 0.6 GAIN ERROR 0.3 0.5 0.2 V = 5V DD 0.1 0.4 OFFSET ERROR 0 0.3 –0.1 –0.2 0.2 –0.3 0.1 –0.4 V = 3V DD –0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1234 5 V (V) INPUT VOLTAGE (V) BIAS Figure 18. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Figure 21. Supply Current vs. Logic Input Voltage, SYNC (SCLK), DATA = 0 1.6 3 T = 25°C A V = 0V REF MAX INL 1.4 V = 5V DD 2 AD5443 1.2 1 I 1 V 5V OUT DD 1.0 MAX DNL 0 0.8 0.6 –1 MIN INL 0.4 I 1 V 3V OUT DD –2 0.2 MIN DNL –3 0 0.5 1.0 1.5 2.0 2.5 –40 –20 0 20 40 60 80 100 120 V (V) TEMPERATURE (°C) BIAS Figure 22. IOUT1 Leakage Current vs. Temperature Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2 0.50 4 T = 25°C A V = 2.5V REF 0.45 3 V = 5V DD AD5443 0.40 2 V = 5V DD 0.35 MAX DNL 1 ALL 0s 0.30 0 MAX INL ALL 1s 0.25 MIN DNL –1 0.20 V = 3V –2 DD 0.15 –3 ALL 1s ALL 0s 0.10 MIN INL –4 0.05 –5 0 0.5 1.0 1.5 2.0 –60 –40 –20 0 20 40 60 80 100 120 140 V (V) TEMPERATURE (°C) BIAS Figure 23. Supply Current vs. Temperature Figure 20. Linearity vs. VBIAS Voltage Applied to IOUT2 Rev. D | Page 10 of 24 LSB LSB VOLTAGE (mV) 03162-020 03162-019 03162-018 CURRENT (μA) I LEAKAGE (nA) CURRENT (mA) OUT 03162-023 03162-022 03162-021 Data Sheet AD5426/AD5432/AD5443 3.5 3 T = 25°C A V = ±0.15V, AD8038 C 1pF REF C AD5443 LOADING 010101010101 3.0 V = ±2V, AD8038 C 1pF REF C 0 2.5 V = ±3.51V, AD8038 C 1.8pF REF C V = ±2V, AD8038 C 1.47pF REF C 2.0 –3 V = ±0.15V, AD8038 C 1.47pF REF C 1.5 V = 5V CC 1 –6 V = 3V CC 0.5 T = 25°C A V = 5V DD AD8038 AMPLIFIER 0 –9 1 10 100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Supply Current vs. Update Rate Figure 27. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 6 0.060 LOADING V 5V, 0V REF T = 25°C ALL ON DD A 0 ZS TO FS NRG = 2.049nVs V = 0V DB11 REF –6 0.050 0x7FF TO 0x800 AD8038 AMPLIFIER DB10 –12 C = 1.8pF COMP DB9 –18 AD5443 0.040 DB8 –24 DB7 –30 V 3V, 0V REF DD DB6 0.030 NRG = 0.088nVs –36 DB5 0x800 TO 0x7FF –42 DB4 –48 0.020 DB3 –54 V 3V, 0V REF DD DB2 NRG = 1.877nVs –60 0.010 DB1 0x7FF TO 0x800 –66 DB0 –72 0 –78 T = 25°C A V = 5V –84 DD V 5V, 0V REF DD V = ±3.5V –0.010 –90 REF NRG = 0.119nVs, ALL OFF C = 1.8pF COMP –96 0x800 TO 0x7FF AD8038 AMPLIFIER –102 –0.020 1 10 100 1k 10k 100k 1M 10M 100M 0 50 100 150 200 250 300 FREQUENCY (Hz) TIME (ns) Figure 25. Reference Multiplying Bandwidth vs. Frequency and Code Figure 28. Midscale Transition VREF = 0 V 0.2 –1.70 T = 25°C V 5V, 3.5V REF DD A V = 3.5V NRG = 1.184nVs REF AD8038 AMPLIFIER 0x7FF TO 0x800 –1.71 C = 1.8pF COMP 0 AD5443 –1.72 V 3V, 3.5V REF DD –0.2 NRG = 1.433nVs 0x7FF TO 0x800 –1.73 –0.4 V 3V, 3.5V REF DD –1.74 NRG = 0.647nVs 0x800 TO 0x7FF T = 25°C A –0.6 V = 5V –1.75 DD V = ±3.5V REF C = 1.8pF V 5V, 3.5V REF, NRG = 0.364nVs, COMP DD AD8038 AMPLIFIER 0x800 TO 0x7FF –0.8 –1.76 1 10 100 1k 10k 100k 1M 10M 100M 0 50 100 150 200 250 300 FREQUENCY (Hz) TIME (ns) Figure 26. Reference Multiplying Bandwidth—All 1s Loaded Figure 29. Midscale Transition VREF = 3.5 V Rev. D | Page 11 of 24 GAIN (dB) GAIN (dB) I (mA) DD 03162-026 03162-025 03162-024 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) 03162-029 03162-028 03162-027 AD5426/AD5432/AD5443 Data Sheet 20 100 T = 25°C A V = 3V DD MCLK = 200kHz AMPLIFIER = AD8038 0 80 –20 MCLK = 500kHz MCLK = 1MHz 60 –40 –60 FULL SCALE 40 –80 ZERO SCALE 20 T = 25°C A –100 V = 3.5V REF AD8038 AMP AD5443 –120 0 1 10 100 1k 10k 100k 1M 10M 010 20 30 40 50 FREQUENCY (Hz) f (kHz) OUT Figure 30. Power Supply Rejection vs. Frequency Figure 33. Wideband SFDR vs. fOUT Frequency (AD5443) –60 80 T = 25°C A MCLK = 500kHz V = 3V DD V = 3.5V p-p REF –65 MCLK = 1MHz MCLK = 200kHz 60 –70 –75 40 –80 20 –85 T = 25°C A V = 3.5V REF AD8038 AMP AD5426 –90 0 1 10 100 1k 10k 100k 1M 0 10203040 50 FREQUENCY (Hz) f (kHz) OUT Figure 34. Wideband SFDR vs. fOUT Frequency (AD5426) Figure 31. THD and Noise vs. Frequency 0 1.8 T = 25°C A T = 25°C A V = 3.5V REF –10 1.6 AD8038 AMPLIFIER AD5443 –20 1.4 V IH –30 1.2 –40 1.0 –50 V IL 0.8 –60 0.6 –70 0.4 –80 –90 0.2 –100 0 0 50 100 150 200 250 300 350 400 450 500 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (Hz) VOLTAGE (V) Figure 35. Wideband SFDR fOUT = 50 kHz, Update = 1 MHz Figure 32. Threshold Voltages vs. Supply Voltage Rev. D | Page 12 of 24 THRESHOLD VOLTAGE (V) THD + N (dB) PSRR (dB) 03162-033 03162-031 03162-030 SFDR (dB) SFDR (dB) SFDR (dB) 03162-035 03162-034 03162-036 Data Sheet AD5426/AD5432/AD5443 0 0 T = 25°C T = 25°C A A V = 3.5V V = 3.5V REF REF –10 –10 AD8038 AMPLIFIER AD8038 AMPLIFIER AD5443 AD5443 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 50 100 150 200 250 300 350 400 450 500 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (Hz) FREQUENCY (Hz) Figure 36. Wideband SFDR fOUT = 20 kHz, Update = 1 MHz Figure 38. Narrowband (±50%) SFDR fOUT = 20 kHz, Update = 1 MHz 0 0 T = 25°C A T = 25°C A V = 3.5V REF V = 3.5V –10 REF –10 AD8038 AMPLIFIER AD8038 AMPLIFIER AD5443 AD5443 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 25 30 35 40 45 50 55 60 65 70 75 10 15 20 25 30 35 FREQUENCY (Hz) FREQUENCY (Hz) Figure 37. Narrowband (±50%) SFDR fOUT = 50 kHz, Update = 1 MHz Figure 39. Narrowband (±50%) IMD fOUT = 20 kHz, 25 kHz, Update = 1 MHz Rev. D | Page 13 of 24 SFDR (dB) SFDR (dB) 03162-038 03162-037 dB SFDR (dB) 03162-040 03162-039 AD5426/AD5432/AD5443 Data Sheet TERMINOLOGY Relative Accuracy Digital Feedthrough Relative accuracy or endpoint nonlinearity is a measure of the When the device is not selected, high frequency logic activity maximum deviation from a straight line passing through the on the device digital inputs may be capacitively coupled to show endpoints of the DAC transfer function. It is measured after up as noise on the IOUT pins and subsequently into the following adjusting for 0 and full scale and is normally expressed in LSBs circuitry. This noise is digital feedthrough. or as a percentage of full-scale reading. Multiplying Feedthrough Error Differential Nonlinearity This is the error due to capacitive feedthrough from the DAC Differential nonlinearity is the difference between the measured reference input to the DAC I 1 terminal, when all 0s are OUT change and the ideal 1 LSB change between any two adjacent loaded to the DAC. codes. A specified differential nonlinearity of −1 LSB maximum Total Harmonic Distortion (THD) over the operating temperature range ensures monotonicity. The DAC is driven by an ac reference. The ratio of the rms sum Gain Error of the harmonics of the DAC output to the fundamental value is Gain error or full-scale error is a measure of the output error the THD. Usually only the lower order harmonics are included, between an ideal DAC and the actual device output. For these such as second to fifth. DACs, ideal maximum output is V − 1 LSB. Gain error of the REF 2 2 2 2 (V + V + V + V ) 2 3 4 5 DACs is adjustable to 0 with external resistance. THD= 20 log V 1 Output Leakage Current Output leakage current is current that flows in the DAC ladder Digital Intermodulation Distortion switches when these are turned off. For the IOUT1 terminal, it Second-order intermodulation distortion (IMD) measurements can be measured by loading all 0s to the DAC and measuring are the relative magnitude of the fa and fb tones generated the I 1 current. Minimum current flows in the I 2 line OUT OUT digitally by the DAC and the second-order products at 2fa − fb when the DAC is loaded with all 1s. and 2fb − fa. Output Capacitance Spurious-Free Dynamic Range (SFDR) Capacitance from IOUT1 or IOUT2 to AGND. SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the mea- Output Current Settling Time sure of the difference in amplitude between the fundamental This is the amount of time it takes for the output to settle to a and the largest harmonically or nonharmonically related spur specified level for a full-scale input change. For these devices, it from dc to full Nyquist bandwidth (half the DAC sampling rate, is specified with a 100 Ω resistor to ground. or fS/2). Narrow band SFDR is a measure of SFDR over an The settling time specification includes the digital delay from arbitrary window size, in this case 50% of the fundamental. rising edge to the full-scale output charge. SYNC Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Rev. D | Page 14 of 24 Data Sheet AD5426/AD5432/AD5443 THEORY OF OPERATION The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit Note that the output voltage polarity is opposite to the VREF current output DACs consisting of a standard inverting R-2R polarity for dc reference voltages. ladder configuration. A simplified diagram for the 8-bit AD5426 is These DACs are designed to operate with either negative or shown in Figure 40. The matching feedback resistor, RFB, has a positive reference voltages. The VDD power pin is used by only the value of R. The value of R is typically 10 kΩ (minimum 8 kΩ internal digital logic to drive the DAC switches’ on and off states. and maximum 12 kΩ). If I 1 and I 2 are kept at the same OUT OUT These DACs are also designed to accommodate ac reference potential, a constant current flows in each ladder leg, regardless input signals in the range of −10 V to +10 V. of digital input code. Therefore, the input resistance presented With a fixed 10 V reference, the circuit shown in Figure 41 gives at VREF is always constant and nominally of value R. The DAC output (IOUT) is code-dependent, producing various resistances a unipolar 0 V to −10 V output voltage swing. When VIN is an ac and capacitances. External amplifier choice should take into signal, the circuit performs 2-quadrant multiplication. Table 5 account the variation in impedance generated by the DAC on shows the relationship between digital code and expected output the amplifiers inverting input node. voltage for unipolar operation (AD5426, 8-bit device). R R R V REF Table 5. Unipolar Code Table 2R 2R 2R 2R 2R Digital Input Analog Output (V) S1 S2 S3 S8 R 1111 1111 −VREF (255/256) R A FB I 1 1000 0000 −VREF (128/256) = −VREF/2 OUT I 2 OUT 0000 0001 −V (1/256) REF DAC DATA LATCHES 0000 0000 −V (0/256) = 0 REF AND DRIVERS Figure 40. Simplified Ladder V R2 DD Access is provided to the V , R , I 1, and I 2 terminals of REF FB OUT OUT the DAC, making the device extremely versatile and allowing it C1 V R DD FB to be configured in several different operating modes. For example, AD5426/ I 1 OUT A1 it can be configured to provide a unipolar output, 4-quadrant V V A1 AD5432/ REF REF R1 I 2 V = 0 OUT OUT AD5443 multiplication in bipolar or single-supply modes of operation. TO –V REF SYNC SCLK SDIN GND Note that a matching switch is used in series with the internal R feedback resistor. If users attempt to measure R , power FB FB MICROCONTROLLER AGND must be applied to V to achieve continuity. DD NOTES CIRCUIT OPERATION 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED Unipolar Mode IF A1 IS A HIGH SPEED AMPLIFIER. Using a single op amp, these devices can easily be configured to Figure 41. Unipolar Operation provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 41. When an output amplifier is connected in unipolar mode, the output voltage is given by D V =− V × OUT REF n 2 where D is the fractional representation of the digital word loaded to the DAC, and n is the number of bits. D = 0 to 255 (8-bit AD5426) = 0 to 1023 (10-bit AD5432) = 0 to 4095 (12-bit AD5443) Rev. D | Page 15 of 24 03162-041 03162-042 AD5426/AD5432/AD5443 Data Sheet Bipolar Operation Table 6. Bipolar Code Table Digital Input Analog Output (V) In some applications, it may be necessary to generate full 1111 1111 +VREF (127/128) 4-quadrant multiplying operation or a bipolar output swing. 1000 0000 0 This can easily be accomplished by using another external 0000 0001 −V (127/128) REF amplifier and some external resistors, as shown in Figure 42. 0000 0000 −V (128/128) REF In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference Stability voltage results in full 4-quadrant multiplying operation. The In the I-to-V configuration, the I of the DAC and the inverting OUT transfer function of this circuit shows that both negative and node of the op amp must be connected as close as possible and positive output voltages are created as the input data, D, which proper PCB layout techniques must be employed. Since every is incremented from code zero (VOUT = −VREF) to midscale code change corresponds to a step function, gain peaking may (VOUT = 0 V) to full scale (VOUT = +VREF). occur if the op amp has limited gain bandwidth product (GBP) D and there is excessive parasitic capacitance at the inverting node. ⎛ ⎞ V = V × − V ⎜ ⎟ OUT REF n− 1 REF This parasitic capacitance introduces a pole into the open-loop ⎝ 2 ⎠ response that can cause ringing or instability in closed-loop where D is the fractional representation of the digital word applications. loaded to the DAC and n is the resolution of the DAC. An optional compensation capacitor, C1, can be added in parallel D = 0 to 255 (8-bit AD5426) with RFB for stability, as shown in Figure 41 and Figure 42. Too = 0 to 1023 (10-bit AD5432) small a value of C1 can produce ringing at the output, while = 0 to 4095 (12-bit AD5443) too large a value can adversely affect the settling time. C1 should When VIN is an ac signal, the circuit performs 4-quadrant be found empirically, but 1 pF to 2 pF is generally adequate for multiplication. compensation. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-bit device). R3 20kΩ R5 V 20kΩ DD R2 C1 V R DD FB R4 AD5426/ I 1 10kΩ OUT A1 V A1 V REF REF AD5432/ I 2 OUT R1 A2 ±10V AD5443 SYNC SCLK SDIN GND V =–V OUT REF TO +V REF MICROCONTROLLER AGND NOTES 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 42. Bipolar Operation Rev. D | Page 16 of 24 03162-043 Data Sheet AD5426/AD5432/AD5443 V DD R1 R2 SINGLE-SUPPLY APPLICATIONS Current Mode Operation R V FB DD These DACs are specified and tested to guarantee operation A1 V OUT V I 1 in single-supply applications. In the current mode circuit of V IN OUT REF Figure 43, I 2 and hence I 1 is biased positive by an amount OUT OUT GND applied to V . BIAS V DD NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. C1 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED V R DD FB IF A1 IS A HIGH SPEED AMPLIFIER. I 1 OUT A1 V V A1 V OUT IN REF Figure 44. Single-Supply Voltage Switching Mode Operation I 2 OUT GND It is important to note that V is limited to low voltages because IN the switches in the DAC ladder no longer have the same source drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. A2 V BIAS Also, VIN must not go negative by more than 0.3 V or an internal diode turns on, exceeding the maximum ratings of the NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. device. In this type of application, the full range of multiplying 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. capability of the DAC is lost. Figure 43. Single-Supply Current Mode Operation POSITIVE OUTPUT VOLTAGE In this configuration, the output voltage is given by Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage VOUT = {D × (RFB/RDAC) × (VBIAS − VIN)} + VBIAS output, an applied negative reference to the input of the DAC As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095 is preferred over the output inversion through an inverting (AD5443), the output voltage varies from amplifier because of the resistor’s tolerance errors. To generate V = V to V = 2 V − V OUT BIAS OUT BIAS IN a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference V should be a low impedance source capable of sinking and BIAS become the virtual ground and −2.5 V, respectively, as shown sourcing all possible variations in current at the I 2 terminal OUT in Figure 45. without any problems. V = 5V DD ADR03 It is important to note that VIN is limited to low voltages because V V OUT IN the switches in the DAC ladder no longer have the same source GND drain drive voltage. As a result, their on resistance differs, which C1 degrades the linearity of the DAC. See Figure 15 to Figure 20. +5V V R DD FB Voltage Switching Mode of Operation I 1 OUT A1 V REF I 2 V = 0V Figure 44 shows these DACs operating in the voltage switching –2.5V OUT OUT TO +2.5V GND mode. The reference voltage, VIN, is applied to the IOUT1 pin, –5V IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference NOTES voltage results in a positive output voltage, making single- 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS supply operation possible. The output from the DAC is voltage A HIGH SPEED AMPLIFIER. at a constant impedance (the DAC ladder resistance), thus an Figure 45. Positive Voltage Output with Minimum of Components op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. Rev. D | Page 17 of 24 03162-044 03162-045 03162-046 AD5426/AD5432/AD5443 Data Sheet DAC leakage current is also a potential error source in divider ADDING GAIN circuits. The leakage current must be counterbalanced by an In applications where the output voltage is required to be greater opposite current supplied from the op amp through the DAC. than VIN, gain can be added with an additional external amplifier or Since only a fraction D of the current into the VREF terminal is it can be achieved in a single stage. It is important to consider the routed to the IOUT1 terminal, the output voltage has to change effect of temperature coefficients of the thin film resistors of the as follows: DAC. Simply placing a resistor in series with the R resistor causes FB mismatches in the temperature coefficients, resulting in larger Output Error Voltage due to DAC Leakage = (Leakage × R)/D gain temperature coefficient errors. Instead, the circuit shown where R is the DAC resistance at the V terminal. For a DAC REF in Figure 46 is a recommended method of increasing the gain of leakage current of 10 nA, R = 10 kΩ, and a gain (that is, 1/D) of 16, the circuit. R1, R2, and R3 should all have similar temperature the error voltage is 1.6 mV. coefficients, but they need not match the temperature coefficients V DD V of the DAC. This approach is recommended in circuits where IN gains of greater than 1 are required. R V FB DD V DD I 1 OUT V REF I 2 OUT C1 V R GND DD FB I 1 R1 OUT A1 V V V IN REF OUT I 2 OUT R3 GND V OUT GAIN = R2 + R3 R2 R2 R1 = R2R3 ADDITIONAL PINS OMITTED FOR CLARITY. R2 + R3 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. Figure 47. Current Steering DAC as a Divider or Programmable Gain Element 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. REFERENCE SELECTION Figure 46. Increasing Gain of Current Output DAC When selecting a reference for use with the AD5426 series of current output DACs, pay attention to the references output DACS USED AS A DIVIDER OR PROGRAMMABLE voltage temperature coefficient specification. This parameter not GAIN ELEMENT only affects the full-scale error, but can also affect the linearity (INL Current-steering DACs are very flexible and lend themselves to and DNL) performance. The reference temperature coefficient many different applications. If this type of DAC is connected as should be consistent with the system accuracy specifications. For the feedback element of an op amp and RFB is used as the input example, an 8-bit system required to hold its overall specification to resistor as shown in Figure 47, then the output voltage is inversely within 1 LSB over the temperature range 0°C to 50°C dictates proportional to the digital input fraction, D. that the maximum system drift with temperature should be less −n For D = 1 − 2 the output voltage is than 78 ppm/°C. A 12-bit system with the same temperature −N V = −V /D = −V /(1 − 2 ) range to overall specification within 2 LSBs requires a maximum OUT IN IN drift of 10 ppm/°C. By choosing a precision reference with low As D is reduced, the output voltage increases. For small values output temperature coefficient this error source can be minimized. of D, it is important to ensure that the amplifier does not saturate Table 7 suggests some references available from Analog Devices and also that the required accuracy is met. For example, an 8-bit that are suitable for use with this range of current output DACs. DAC driven with the binary code 0x10 (00010000), that is, 16 decimal, in the circuit of Figure 47 should cause the output AMPLIFIER SELECTION voltage to be 16 × VIN. However, if the DAC has a linearity The primary requirement for the current-steering mode is an specification of ±0.5 LSB, then D can in fact have the weight amplifier with low input bias currents and low input offset anywhere in the range 15.5/256 to 16.5/256 so that the possible voltage. The input offset voltage of an op amp is multiplied by output voltage will be in the range 15.5 V to 16.5 V —an error of IN IN the variable gain (due to the code-dependent output resistance +3% even though the DAC itself has a maximum error of 0.2%. of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. In general, the input offset voltage should be Rev. D | Page 18 of 24 03162-047 03162-048 Data Sheet AD5426/AD5432/AD5443 a fraction (~ <1/4) of an LSB to ensure monotonic behavior Provided the DAC switches are driven from true wideband low when stepping through codes. impedance sources (V and AGND), they settle quickly. IN Consequently, the slew rate and settling time of a voltage switching The input bias current of an op amp also generates an offset at DAC circuit is determined largely by the output op amp. the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low To obtain minimum settling time in this configuration, it is enough to prevent any significant errors in 12-bit applications. important to minimize capacitance at the VREF of the DAC. This is done by using low input capacitance buffer amplifiers and Common-mode rejection of the op amp is important in voltage careful board design. Most single-supply circuits include ground as switching circuits since it produces a code-dependent error at part of the analog signal range, which in turn requires an amplifier the voltage output of the circuit. Most op amps have adequate that can handle rail-to-rail signals,. There is a large range of common-mode rejection at an 8-, 10-, or 12-bit resolution. single-supply amplifiers available from Analog Devices. Table 7. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise μV p-p Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ A (MHz) Slew Rate (V/μs) V (Max) (μV) I (Max) (nA) Package CL OS B AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 100 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±2 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. D | Page 19 of 24 AD5426/AD5432/AD5443 Data Sheet DB15 (MSB) DB0 (LSB) SERIAL INTERFACE C3 C2 C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X XX The AD5426/AD5432/AD5443 have an easy to use 3-wire inter- CONTROL BITS DATA BITS face that is compatible with SPI/QSPI/MICROWIRE and DSP Figure 48. AD5426 8-Bit Input Shift Register Contents interface standards. Data is written to the device in 16 bit words. DB15 (MSB) DB0 (LSB) This 16-bit word consists of 4 control bits and either 8 , 10 , or 12 C3 C2 C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 XX data bits as shown in Figure 48, Figure 49, and Figure 50. The CONTROL BITS DATA BITS AD5443 uses all 12 bits of DAC data. The AD5432 uses 10 bits Figure 49. AD5432 10-Bit Input Shift Register Contents and ignores the 2 LSBs, while the AD5426 uses 8 bits and ignores DB15 (MSB) DB0 (LSB) the last 4 bits. C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Low Power Serial Interface CONTROL BITS DATA BITS To minimize the power consumption of the device, the interface Figure 50. AD5443 12-Bit Input Shift Register Contents powers up fully only when the device is being written to, that is, SYNC on the falling edge of . The SCLK and DIN input buffers Function SYNC are powered down on the rising edge of SYNC. The SYNC of SYNC is an edge-triggered input that acts as a frame synchro- the AD5426/AD5432/AD5443 needs to be synchronous with nization signal and chip enable. Data can be transferred into the the microprocessor control. Unfinished data frames are latched device only while SYNC is low. To start the serial data transfer, into the part and will affect the output. SYNC should be taken low observing the minimum SYNC DAC Control Bits C3 to C0 falling to SCLK falling edge setup time, t4. Control Bits C3 to C0 allow control of various functions of Daisy-Chain Mode the DAC, as seen in Table 10. Default settings of the DAC on Daisy-chain is the default power-on mode. To disable the daisy power-on are as follows: Data is clocked into the shift register chain function, write 1001 to the control word. In daisy-chain on falling clock edges and daisy-chain mode is enabled. mode, the internal gating on SCLK is disabled. The SCLK is Device powers on with zero-scale load to the DAC register continuously applied to the input shift register when SYNC is and I lines. OUT low. If more than 16 clock pulses are applied, the data ripples The DAC control bits allow the user to adjust certain features out of the shift register and appears on the SDO line. This data on power-on, for example, daisy-chaining may be disabled if is clocked out on the rising edge of SCLK (this is the default, use not in use, active clock edge may be changed to rising edge, and the control word to change the active edge) and is valid for the DAC output may be cleared to either zero scale or midscale. next device on the falling edge (default). By connecting this line The user may also initiate a readback of the DAC register to the D input on the next device in the chain, a multidevice IN contents for verification purposes. interface is constructed. Sixteen clock pulses are required for each device in the system. Therefore, the total number of clock Table 10. DAC Control Bits cycles must equal 16 N where N is the total number of devices C3 C2 C1 C0 Function Implemented in the chain. See the timing diagram in Figure 4. 0 0 0 0 No operation (power-on default) 0 0 0 1 Load and update When the serial transfer to all devices is complete, SYNC 0 0 1 0 Initiate readback should be taken high. This prevents any further data being 0 0 1 1 Reserved clocked into the input shift register. A burst clock containing 0 1 0 0 Reserved the exact number of clock cycles may be used and SYNC taken 0 1 0 1 Reserved high some time later. After the rising edge of SYNC, data is 0 1 1 0 Reserved automatically transferred from each device’s input shift register 0 1 1 1 Reserved to the addressed DAC. 1 0 0 0 Reserved When control bits = 0000, the device is in no operation mode. 1 0 0 1 Daisy-chain disable This may be useful in daisy-chain applications where the user 1 0 1 0 Clock data to shift register on rising edge does not want to change the settings of a particular DAC in the 1 0 1 1 Clear DAC output to zero scale chain. Simply write 0000 to the control bits for that DAC and 1 1 0 0 Clear DAC output to midscale the following data bits will be ignored. To re-enable the daisy- 1 1 0 1 Reserved chain mode, if disabled, a power recycle is required. 1 1 1 0 Reserved 1 1 1 1 Reserved Rev. D | Page 20 of 24 03162-049 03162-050 03162-051 Data Sheet AD5426/AD5432/AD5443 Standalone Mode After the falling edge of the 16th SCLK pulse, data is auto- matically transferred from the input shift register to the DAC. After power-on, write 1001 to the control word to disable daisy- For another serial transfer to take place, the counter must be chain mode. The first falling edge of SYNC resets a counter that reset by the falling edge of . SYNC counts the number of serial clocks, ensuring the correct number of bits are shifted in and out of the serial shift registers. A rising edge on during a write causes the write cycle to be aborted. SYNC Rev. D | Page 21 of 24 AD5426/AD5432/AD5443 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of Fast switching signals such as clocks should be shielded with the power supply and ground return layout helps to ensure the digital ground to avoid radiating noise to other parts of the rated performance. The printed circuit board on which the board and should never be run near the reference inputs. AD5426/AD5432/AD5443 is mounted should be designed so Avoid crossover of digital and analog signals. Traces on opposite that the analog and digital sections are separated and confined sides of the board should run at right angles to each other. This to certain areas of the board. If the DAC is in a system where reduces the effects of feedthrough through the board. A micro- multiple devices require an AGND-to-DGND connection, the strip technique is by far the best, but not always possible with a connection should be made at one point only. The star ground double-sided board. In this technique, the component side of the point should be established as close to the device as possible. board is dedicated to ground plane while signal traces are placed The DAC should have ample supply bypassing of 10 μF in parallel on the solder side. with 0.1 μF on the supply located as close to the package as It is good practice to employ compact, minimum lead length possible, ideally right up against the device. The 0.1 μF capacitor PCB layout design. Leads to the input should be as short as should have low effective series resistance (ESR) and effective possible to minimize IR drops and stray inductance. series inductance (ESI), like the common ceramic types that The PCB metal traces between V and R should also be REF FB provide a low impedance path to ground at high frequencies to matched to minimize gain error. To maximize on high frequency handle transient currents due to internal logic switching. Low performance, the I-to-V amplifier should be located as close to ESR, 1 μF to 10 μF tantalum or electrolytic capacitors should the device as possible. also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Rev. D | Page 22 of 24 Data Sheet AD5426/AD5432/AD5443 OVERVIEW OF AD54xx AND AD55xx DEVICES Table 11. Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width Rev. D | Page 23 of 24 AD5426/AD5432/AD5443 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 51. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution (Bit) INL (LSB) Temperature Range Package Description Package Option Branding AD5426YRM 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D1Q AD5426YRM-REEL 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D1Q AD5426YRM-REEL7 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D1Q AD5426YRMZ 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D6W AD5426YRMZ-REEL 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D6W AD5426YRMZ-REEL7 8 ±0.25 −40°C to +125°C 10-Lead MSOP RM-10 D6W AD5432YRM 10 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D1R AD5432YRM-REEL7 10 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D1R AD5432YRMZ 10 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D1R# AD5432YRMZ-REEL 10 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D1R# AD5432YRMZ-REEL7 10 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D1R# AD5443YRM 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S AD5443YRM-REEL 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S AD5443YRM-REEL7 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S AD5443YRMZ 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S# AD5443YRMZ-REEL 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S# AD5443YRMZ-REEL7 12 ±1 −40°C to +125°C 10-Lead MSOP RM-10 D1S# EVAL-AD5443EBZ Evaluation Board EVAL-AD5443SDZ Evaluation Board EVAL-AD5443-DBRDZ Evaluation Board 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03162-0-4/12(D) Rev. D | Page 24 of 24 091709-A