ANALOG DEVICES AD5429

Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface AD5429/AD5439/AD5449 FEATURES GENERAL DESCRIPTION 1 10 MHz multiplying bandwidth The AD5429/AD5439/AD5449 are CMOS, 8-, 10-, and 12-bit, INL of ±0.25 LSB @ 8 bits dual-channel, current output digital-to-analog converters (DAC), 16-lead TSSOP package respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other ±10 V reference input applications. 50 MHz serial interface As a result of being manufactured on a CMOS submicron process, 2.47 MSPS update rate these parts offer excellent 4-quadrant multiplication character- Extended temperature range: −40°C to +125°C 4-quadrant multiplication istics, with large signal multiplying bandwidths of 10 MHz. Power-on reset The applied external reference input voltage (V ) determines REF 0.5 μA typical current consumption the full-scale output current. An integrated feedback resistor Guaranteed monotonic (RFB) provides temperature tracking and full-scale voltage Daisy-chain mode output when combined with an external current-to-voltage Readback function precision amplifier. APPLICATIONS These DACs use a double-buffered, 3-wire serial interface that Portable battery-powered applications is compatible with SPI, QSPI™, MICROWIRE™, and most DSP Waveform generators interface standards. In addition, a serial data out (SDO) pin allows Analog processing daisy-chaining when multiple packages are used. Data readback Instrumentation applications allows the user to read the contents of the DAC register via the Programmable amplifiers and attenuators SDO pin. On power-up, the internal shift register and latches Digitally controlled calibration are filled with 0s, and the DAC outputs are at zero scale. Programmable filters and oscillators Composite video The AD5429/AD5439/AD5449 DACs are available in 16-lead Ultrasound TSSOP packages. The EVAL-AD5415/AD5449SDZ evaluation Gain, offset, and voltage trimming board is available for evaluating DAC performance. For more information, see the UG-297 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM V A REF RFB AD5429/AD5439/AD5449 R V DD R A FB SYNC I 1A OUT SHIFT INPUT DAC 8-/10-/12-BIT SCLK REGISTER REGISTER REGISTER R-2R DAC A I 2A OUT SDIN SDO LDAC CLR I 1B OUT INPUT DAC 8-/10-/12-BIT POWER-ON REGISTER REGISTER R-2R DAC B RESET I 2B OUT R B FB RFB R LDAC V B REF Figure 1. 1 U.S. Patent Number 5,689,257. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04464-001 AD5429/AD5439/AD5449 TABLE OF CONTENTS Features .............................................................................................. 1  Digital-to-Analog Converter .................................................... 15  Applications....................................................................................... 1  Circuit Operation ....................................................................... 15  General Description ......................................................................... 1  Single-Supply Applications ....................................................... 17  Functional Block Diagram .............................................................. 1  Adding Gain................................................................................ 18  Revision History ............................................................................... 2  Divider or Programmable Gain Element................................ 18  Specifications..................................................................................... 3  Reference Selection .................................................................... 19  Timing Characteristics ................................................................ 5  Amplifier Selection .................................................................... 19  Timing Diagrams.......................................................................... 5  Serial Interface ............................................................................ 20  Absolute Maximum Ratings............................................................ 7  Microprocessor Interfacing....................................................... 22  ESD Caution.................................................................................. 7  PCB Layout and Power Supply Decoupling ........................... 24  Pin Configuration and Function Descriptions............................. 8  Overview of AD54xx Devices....................................................... 25  Typical Performance Characteristics ............................................. 9  Outline Dimensions....................................................................... 26  Terminology .................................................................................... 14  Ordering Guide .......................................................................... 26  Theory of Operation ...................................................................... 15  REVISION HISTORY Changes to Absolute Maximum Ratings Section..........................7 6/11—Rev. C to Rev. D Changes to General Description Section .................................... 15 Changes to General Description .................................................... 1 Changes to Table 5.......................................................................... 15 Deleted Evaluation Board for the DAC Section ......................... 24 Changes to Table 6.......................................................................... 16 Changes to Ordering Guide .......................................................... 30 Changes to Single-Supply Applications Section......................... 17 4/10—Rev. B to Rev. C Changes to Divider or Programmable Gain Element Section.... 18 Added to Figure 4 ............................................................................. 6 Changes to Table 7 Through Table 10 ......................................... 20 3/08—Rev. A to Rev. B Added ADSP-BF5xx-to-AD5429/AD5439/AD5449 Added t and t Parameters to Table 2 ......................................... 5 13 14 Interface Section ........................................................................ 23 Changes to Figure 2.......................................................................... 5 Change to PCB Layout and Changes to Figure 3.......................................................................... 6 Power Supply Decoupling Section .......................................... 25 Changes to Figure 38...................................................................... 16 Changes to Power Supplies for the Evaluation Board Section.... 25 Changes to Ordering Guide .......................................................... 30 Changes to Table 13 ....................................................................... 29 Updated Outline Dimensions....................................................... 30 7/05—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 30 Changes to Features List .................................................................. 1 Changes to Specifications................................................................ 3 7/04—Revision 0: Initial Version Changes to Timing Characteristics................................................ 5 Rev. D | Page 2 of 28 AD5429/AD5439/AD5449 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5429 Resolution 8 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5439 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5449 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature ±5 ppm FSR/°C Coefficient Output Leakage Current ±5 nA Data = 0x0000, T = 25°C, I 1 A OUT ±15 nA Data = 0x0000, I 1 OUT REFERENCE INPUT Reference Input Range ±10 V V A, V B Input Resistance 9 11 13 kΩ Input resistance temperature coefficient = −50 ppm/°C REF REF VREFA-to-VREFB Input Resistance 1.6 2.5 % Typical = 25°C, maximum = 125°C Mismatch Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA V − 0.5 V V = 2.5 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 μA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying Bandwidth 10 MHz VREF = ±3.5 V p-p, DAC loaded all 1s Output Voltage Settling Time RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V, DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, VREF = 0 V Rev. D | Page 3 of 28 AD5429/AD5439/AD5449 1 Parameter Min Typ Max Unit Conditions Multiplying Feedthrough Error DAC latches loaded with all 0s, VREF = ±3.5 V 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Digital Feedthrough 3 5 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz f 61 dB OUT 50 kHz fOUT 66 dB SFDR Performance (Wide Band) AD5449, 65k codes, VREF = 3.5 V Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz fOUT 60 dB 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) AD5449, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50 kHz f 87 dB OUT Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion AD5449, 65k codes, VREF = 3.5 V f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 μA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD Power Supply Sensitivity 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization, not subject to production test. Rev. D | Page 4 of 28 AD5429/AD5439/AD5449 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 2 Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCLK 50 MHz max Maximum clock frequency t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t 8 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t6 4 ns min Data hold time t7 5 ns min SYNC rising edge to SCLK falling edge t 30 ns min Minimum SYNC high time 8 t 0 ns min SCLK falling edge to LDAC falling edge 9 t 12 ns min LDAC pulse width 10 t11 10 ns min SCLK falling edge to LDAC rising edge 3 t12 25 ns min SCLK active edge to SDO valid, strong SDO driver 60 ns min SCLK active edge to SDO valid, weak SDO driver t 12 ns min CLR pulse width 13 t 4.5 ns min SYNC rising edge to LDAC falling edge 14 Update Rate 2.47 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5. TIMING DIAGRAMS t 1 SCLK t t 2 3 t 4 t 8 t 7 SYNC t 6 t 5 DB0 DB15 SDIN t 10 t 9 1 LDAC t 11 2 LDAC 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram Rev. D | Page 5 of 28 04464-002 AD5429/AD5439/AD5449 t 1 SCLK t t 2 3 t 7 t 4 SYNC t 6 t 8 t 5 DB0 DB15 DB0 DB15 SDIN (N + 1) (N) (N) (N + 1) t 12 DB0 DB15 SDO (N) (N) NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram SCLK 16 32 SYNC DB15 DB0 DB15 DB0 SDIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB15 DB0 SDO SELECTED REGISTER DATA UNDEFINED CLOCKED OUT Figure 4. Readback Mode Timing Diagram 200μAI OL V (MIN) + V (MAX) TO OUTPUT OH OL PIN 2 C L 50pF 200μAI OH Figure 5. Load Circuit for SDO Timing Specifications Rev. D | Page 6 of 28 04464-004 04464-003 04464-059 AD5429/AD5439/AD5449 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 3. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect VREFx, RFBx to GND −12 V to +12 V device reliability. Only one absolute maximum rating may be IOUT1, IOUT2 to GND −0.3 V to +7 V applied at any one time. Input Current to Any Pin Except Supplies ±10 mA 1 Logic Inputs and Output −0.3 V to V + 0.3 V DD Operating Temperature Range ESD CAUTION Extended (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP, θJA Thermal Impedance 150°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 SYNC Overvoltages at SCLK, , and SDIN are clamped by internal diodes. Rev. D | Page 7 of 28 AD5429/AD5439/AD5449 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I 1A 1 16 I 1B OUT OUT I 2A 2 15 I 2B OUT OUT R A 3 14 R B FB FB AD5429/ V A 4 13 V B AD5439/ REF REF AD5449 GND 5 12 V DD TOP VIEW LDAC 6 11 CLR (Not to Scale) 7 10 SCLK SYNC 8 9 SDIN SDO NC = NO CONNECT Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 IOUT1A DAC A Current Output. 2 IOUT2A DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be biased to achieve single-supply operation. 3 R A DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external FB amplifier output. 4 VREFA DAC A Reference Voltage Input Pin. 5 GND Ground Pin. 6 LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode. 7 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 8 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to a rising edge. 9 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the next 16 opposite clock edges to the active clock edge. 10 SYNC Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 11 CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user to enable the hardware CLR pin as a clear-to-zero scale or midscale, as required. 12 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 13 VREFB DAC B Reference Voltage Input Pin. 14 R B DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external FB amplifier output. 15 I 2B OUT DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be biased to achieve single-supply operation. 16 IOUT1B DAC B Current Output. Rev. D | Page 8 of 28 04464-005 AD5429/AD5439/AD5449 TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 T = 25°C T = 25°C A A V = 10V V = 10V REF REF 0.15 0.15 V = 5V V = 5V DD DD 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 7. INL vs. Code (8-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 T = 25°C T = 25°C A A 0.4 0.4 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 8. INL vs. Code (10-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) 1.0 1.0 T = 25°C T = 25°C A A 0.8 0.8 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 9. INL vs. Code (12-Bit DAC) Figure 12. DNL vs. Code (12-Bit DAC) Rev. D | Page 9 of 28 INL (LSB) INL (LSB) INL (LSB) 04464-019 04464-018 04464-017 DNL (LSB) DNL (LSB) DNL (LSB) 04464-022 04464-021 04464-020 AD5429/AD5439/AD5449 0.6 8 T = 25°C A 0.5 7 0.4 6 MAX INL 0.3 5 V = 5V DD 0.2 4 T = 25°C A V = 5V 0.1 DD 3 0 MIN INL 2 –0.1 V = 3V DD 1 –0.2 V = 2.5V DD 0 –0.3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 34 5 6 789 10 INPUT VOLTAGE (V) REFERENCE VOLTAGE Figure 13. INL vs. Reference Voltage Figure 16. Supply Current vs. Logic Input Voltage –0.40 1.6 T = 25°C A V = 5V DD 1.4 –0.45 1.2 I 1 V = 5V OUT DD –0.50 1.0 –0.55 0.8 I 1 V = 3V OUT DD 0.6 –0.60 MIN DNL 0.4 –0.65 0.2 0 –0.70 27 34 5 68910 –40 –20 0 20 40 60 80 100 120 REFERENCE VOLTAGE TEMPERATURE (°C) Figure 14. DNL vs. Reference Voltage Figure 17. IOUT1 Leakage Current vs. Temperature 5 0.50 0.45 4 V = 5V V = 5V DD DD 3 0.40 0.35 2 ALL 0s 0.30 1 ALL 1s 0 0.25 V = 2.5V V = 2.5V DD DD 0.20 –1 –2 0.15 ALL 1s ALL 0s 0.10 –3 0.05 –4 V = 10V REF –5 0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Gain Error vs. Temperature Figure 18. Supply Current vs. Temperature Rev. D | Page 10 of 28 DNL (LSB) INL (LSB) GAIN ERROR (mV) 04464-037 04464-035 04464-036 SUPPLY CURRENT (µA) I 1 LEAKAGE (nA) OUT SUPPLY CURRENT (mA) 04464-038 04464-040 04464-039 AD5429/AD5439/AD5449 14 3 T = 25°C A T = 25°C A V = 5V DD LOADING ZS TO FS 12 V = 5V 0 DD 10 8 –3 6 V = 3V DD 4 V = ±2V, AD8038 C 1.47pF REF C –6 V = 2.5V V = ±2V, AD8038 C 1pF DD REF C V = ±0.15V, AD8038 C 1pF REF C 2 V = ±0.15V, AD8038 C 1.47pF REF C V = ±3.51V, AD8038 C 1.8pF REF C –9 0 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Supply Current vs. Update Rate Figure 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 6 0.045 T = 25°C ALL ON A T = 25°C 0x7FF TO 0x800 0 A LOADING DB11 V = 0V 0.040 REF –6 ZS TO FS AMP = AD8038 DB10 V = 5V DD –12 0.035 C = 1.8pF DB9 COMP –18 DB8 –24 0.030 DB7 –30 DB6 0.025 –36 V = 3V DD DB5 –42 0.020 DB4 –48 DB3 –54 0.015 DB2 0x800 TO 0x7FF –60 DB1 0.010 –66 DB0 V = 3V DD –72 0.005 T = 25°C A –78 V = 5V DD 0 –84 V = ±3.5V REF –90 ALL OFF C = 1.8pF –0.005 COMP –96 AMP = AD8038 V = 5V DD –102 –0.010 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code Figure 23. Midscale Transition, VREF = 0 V 0.2 –1.68 T = 25°C A 0x7FF TO 0x800 V = 3.5V –1.69 REF AMP = AD8038 V = 5V DD 0 C = 1.8pF COMP –1.70 –1.71 –0.2 –1.72 V = 3V DD –1.73 –0.4 V = 5V DD –1.74 V = 3V DD T = 25°C A –1.75 –0.6 V = 5V DD V =±3.5V REF –1.76 C = 1.8pF COMP 0x800 TO 0x7FF AMP = AD8038 –0.8 –1.77 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 21. Reference Multiplying Bandwidth—All 1s Loaded Figure 24. Midscale Transition, V = 3.5 V REF Rev. D | Page 11 of 28 I (mA) GAIN (dB) DD GAIN (dB) 04464-042 04464-043 04464-041 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) 04464-044 04464-045 04464-046 AD5429/AD5439/AD5449 90 20 T = 25°C A V = 3V DD 80 AMP = AD8038 0 MCLK = 5MHz 70 MCLK = 10MHz –20 60 –40 50 FULL SCALE MCLK = 25MHz 40 –60 ZERO SCALE 30 –80 20 –100 T = 25°C A 10 V = 3.5V REF AMP = AD8038 –120 0 1 100 1k 10k 100k 1M 10M 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz) f (kHz) OUT Figure 25. Power Supply Rejection Ratio vs. Frequency Figure 28. Wideband SFDR vs. fOUT Frequency –60 0 T = 25°C A T = 25°C A V = 5V DD V = 3V DD –10 AMP = AD8038 = 3.5V p-p V REF –65 65k CODES –20 –70 –30 –40 –75 –50 –60 –80 –70 –85 –80 –90 –90 0 2 4 6 8 10 12 1 10 100 1k 10k 100k 1M FREQUENCY (MHz) FREQUENCY (Hz) Figure 26. THD + Noise vs. Frequency Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz 100 0 T = 25°C A V = 5V DD MCLK = 1MHz –10 AMP = AD8038 65k CODES 80 –20 –30 60 MCLK = 200kHz –40 MCLK = 0.5MHz –50 40 –60 –70 –80 20 T = 25°C A –90 V = 3.5V REF AMP = AD8038 –100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) f (kHz) OUT Figure 27. Wideband SFDR vs. fOUT Frequency Figure 30. Wideband SFDR, f = 500 kHz, Clock = 10 MHz OUT Rev. D | Page 12 of 28 SFDR (dB) THD + N (dB) PSRR (dB) 04464-047 04464-049 04464-048 SFDR (dB) SFDR (dB) SFDR (dB) 04464-052 04464-051 04464-050 AD5429/AD5439/AD5449 0 0 T = 25°C T = 25°C  A A V = 5V V = 3V DD DD –10 –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (MHz) FREQUENCY (kHz) Figure 31. Wideband SFDR, f = 50 kHz, Clock = 10 MHz Figure 34. Narrow-Band IMD, f = 90 kHz, 100 kHz, Clock = 10 MHz OUT OUT 0 0 T = 25°C A T = 25°C A V = 3V DD V = 5V –10 DD –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 250 300 350 400 450 500 550 600 650 700 750 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) FREQUENCY (kHz) Figure 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz 20 300 T = 25°C  T = 25°C A A V = 3V ZERO SCALE LOADED TO DAC AMP = AD8038 DD AMP = AD8038 0 MIDSCALE LOADED TO DAC 250 65k CODES FULL SCALE LOADED TO DAC –20 200 –40 150 –60 100 –80 50 –100 –120 0 50 60 70 80 90 100 110 120 130 140 150 100 1k 10k 100k FREQUENCY (kHz) FREQUENCY (Hz) Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 36. Output Noise Spectral Density Rev. D | Page 13 of 28 SFDR (dB) SFDR (dB) SFDR (dB) 04464-055 04464-054 04464-053 OUTPUT NOISE (nV/ Hz) IMD (dB) IMD (dB) 04464-058 04464-057 04464-056 AD5429/AD5439/AD5449 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Crosstalk A measure of the maximum deviation from a straight line The glitch impulse transferred to the outputs of one DAC in passing through the endpoints of the DAC transfer function. response to a full-scale code change (all 0s to all 1s, or vice versa) It is measured after adjusting for zero and full scale and is typically in the input register of the other DAC. It is expressed in nV-sec. expressed in LSBs or as a percentage of the full-scale reading. Analog Crosstalk Differential Nonlinearity The glitch impulse transferred to the output of one DAC due to The difference in the measured change and the ideal 1 LSB a change in the output of another DAC. It is measured by change between two adjacent codes. A specified differential loading one of the input registers with a full-scale code change nonlinearity of −1 LSB maximum over the operating temperature (all 0s to all 1s, or vice versa) while keeping LDAC high and range ensures monotonicity. then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is Gain Error (Full-Scale Error) expressed in nV-sec. A measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is Channel-to-Channel Isolation V − 1 LSB. The gain error of the DACs is adjustable to zero REF The portion of input signal from the reference input of a DAC with an external resistance. that appears at the output of another DAC. It is expressed in dB. Output Leakage Current Total Harmonic Distortion (THD) The current that flows into the DAC ladder switches when they The DAC is driven by an ac reference. The ratio of the rms sum are turned off. For the IOUT1x terminal, it can be measured by of the harmonics of the DAC output to the fundamental value is loading all 0s to the DAC and measuring the IOUT1 current. the THD. Usually only the lower-order harmonics are included, Minimum current flows into the IOUT2x line when the DAC is such as the second to fifth harmonics. loaded with all 1s. 2 2 2 2 V +V +V +V 2 3 4 5 Output Capacitance THD= 20 log V 1 Capacitance from I 1 or I 2 to AGND. OUT OUT Intermodulation Distortion (IMD) Output Current Settling Time The DAC is driven by two combined sine wave references of The amount of time for the output to settle to a specified level Frequency fa and Frequency fb. Distortion products are produced for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground. at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 … Intermodulation terms are those for which m or n is not Digital-to-Analog Glitch Impulse equal to 0. The second-order terms include (fa + fb) and (fa − fb), The amount of charge injected from the digital inputs to the and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb), analog output when the inputs change state. This is normally and (fa − 2fb). IMD is defined as specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or RMS Sum of the Sum and Diff Distortion Products IMD= 20log voltage signal. RMS Amplitude of the Fundamental Digital Feedthrough Compliance Voltage Range When the device is not selected, high frequency logic activity The maximum range of (output) terminal voltage for which the on the digital inputs of the device is capacitively coupled through device provides the specified characteristics. the device and produces noise on the I pins and, subsequently, OUT on the circuitry that follows. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1x terminal when all 0s are loaded to the DAC. Rev. D | Page 14 of 28 AD5429/AD5439/AD5449 THEORY OF OPERATION When an output amplifier is connected in unipolar mode, the DIGITAL-TO-ANALOG CONVERTER output voltage is given by The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dual- n V =− V × D /2 channel, current output DACs consisting of a standard inverting OUT REF R-2R ladder configuration. Figure 37 shows a simplified diagram where: for a single channel of the AD5449. The feedback resistor, RFBA, D is the fractional representation of the digital word loaded to has a value of R. The value of R is typically 10 kΩ (with a the DAC. minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1A and D = 0 to 255 (AD5429) IOUT2A are kept at the same potential, a constant current flows = 0 to 1023 (AD5439) into each ladder leg, regardless of digital input code. Therefore, = 0 to 4095 (AD5449) the input resistance presented at V A is always constant. REF n is the number of bits. RR R V A REF With a fixed 10 V reference, the circuit shown in Figure 38 gives 2R 2R 2R 2R 2R a unipolar 0 V to −10 V output voltage swing. When VIN is an ac R S1 S2 S3 S12 signal, the circuit performs 2-quadrant multiplication. R A FB I 1A OUT Table 5 shows the relationship between digital code and the I 2A OUT expected output voltage for unipolar operation using the 8-bit DAC DATA LATCHES AD5429 DAC. AND DRIVERS Table 5. Unipolar Code Table Figure 37. Simplified Ladder Digital Input Analog Output (V) Access is provided to the V x, R x, I 1x, and I 2x termi- REF FB OUT OUT 1111 1111 −V (255/256) REF nals of the DACs, making the devices extremely versatile and 1000 0000 −V (128/256) = −V /2 REF REF allowing them to be configured in several operating modes, such 0000 0001 −V (1/256) REF as unipolar mode, bipolar output mode, or single-supply mode. 0000 0000 −VREF (0/256) = 0 CIRCUIT OPERATION Unipolar Mode Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 38. V DD R2 C1 V R A DD FB I 1A AD5429/ OUT V REF V x A1 REF AD5439/ R1 I 2A AD5449 OUT V = 0V TO –V OUT REF SYNC SCLK SDIN GND MICROCONTROLLER AGND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. 3. DAC B OMITTED FOR CLARITY. Figure 38. Unipolar Operation Rev. D | Page 15 of 28 04464-006 04464-007 AD5429/AD5439/AD5449 Bipolar Operation Stability In some applications, it may be necessary to generate full In the I-to-V configuration, the IOUT of the DAC and the inverting 4-quadrant multiplying operation or a bipolar output swing. node of the op amp must be connected as closely as possible, and This can easily be accomplished by using another external proper PCB layout techniques must be used. Because every code amplifier and three external resistors, as shown in Figure 39. change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (GBP) and When V is an ac signal, the circuit performs 4-quadrant IN there is excessive parasitic capacitance at the inverting node. multiplication. When connected in bipolar mode, the output This parasitic capacitance introduces a pole into the open-loop voltage is response, which can cause ringing or instability in the closed- n− 1 V =() V × D/ 2 − V OUT REF REF loop applications circuit. where: As shown in Figure 38 and Figure 39, an optional compensation capacitor, C1, can be added in parallel with RFBx for stability. D is the fractional representation of the digital word loaded to Too small a value of C1 can produce ringing at the output, the DAC. whereas too large a value can adversely affect the settling time. D = 0 to 255 (AD5429) C1 should be found empirically, but 1 pF to 2 pF is generally = 0 to 1023 (AD5439) adequate for the compensation. = 0 to 4095 (AD5449) n is the number of bits. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation with the AD5429. Table 6. Bipolar Code Digital Input Analog Output (V) 1111 1111 +V (255/256) REF 1000 0000 0 0000 0001 −VREF (255/256) 0000 0000 −VREF (256/256) R3 20kΩ V DD R2 R5 20kΩ C1 V R A DD FB R4 R1 I 1A OUT AD5429/ 10kΩ V ±10V V x A1 REF REF AD5439/ A2 I 2A R1 AD5449 OUT V = –V TO +V SYNC SCLK SDIN GND OUT REF REF AGND MICROCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. 4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY. Figure 39. Bipolar Operation Rev. D | Page 16 of 28 04464-008 AD5429/AD5439/AD5449 Note that V is limited to low voltages because the switches IN SINGLE-SUPPLY APPLICATIONS in the DAC ladder no longer have the same source-drain drive Voltage-Switching Mode voltage. As a result, their on resistance differs and degrades the Figure 40 shows the DACs operating in voltage-switching mode. integral linearity of the DAC. Also, VIN must not go negative by The reference voltage, V , is applied to the I 1A pin; I 2A IN OUT OUT more than 0.3 V, or an internal diode turns on, causing the device is connected to AGND; and the output voltage is available at the to exceed the maximum ratings. In this type of application, the VREFA terminal. In this configuration, a positive reference voltage full range of multiplying capability of the DAC is lost. results in a positive output voltage, making single-supply operation Positive Output Voltage possible. The output from the DAC is voltage at a constant The output voltage polarity is opposite to the V polarity for REF impedance (the DAC ladder resistance). Therefore, an op amp dc reference voltages. To achieve a positive voltage output, an is necessary to buffer the output voltage. The reference input applied negative reference to the input of the DAC is preferred no longer sees a constant input impedance; instead, it sees one over the output inversion through an inverting amplifier because that varies with code. Therefore, the voltage input should be of the resistor tolerance errors. To generate a negative reference, driven from a low impedance source. the reference can be level-shifted by an op amp such that the V OUT and GND pins of the reference become the virtual ground and −2.5 V, respectively, as shown in Figure 41. V DD R1 R2 R A V FB DD V IN I 1A OUT V 8-/10-/12-BIT OUT V A REF DAC I 2A OUT GND NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 40. Single-Supply Voltage-Switching Mode V = +5V DD ADR03 V V OUT IN GND +5V C1 R A V FB DD –2.5V I 1A OUT V A 8-/10-/12-BIT REF I 2A DAC OUT V = 0V TO +2.5V OUT GND –5V NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 41. Positive Voltage Output with Minimum Components Rev. D | Page 17 of 28 04464-009 04464-010 AD5429/AD5439/AD5449 As D is reduced, the output voltage increases. For small values of ADDING GAIN the Digital Fraction D, it is important to ensure that the amplifier In applications in which the output voltage must be greater than does not saturate and the required accuracy is met. For example, VIN, gain can be added with an additional external amplifier, or an 8-bit DAC driven with binary code of 0x10 (0001 0000)—that it can be achieved in a single stage. Consider the effect of temper- is, 16 decimal—in the circuit of Figure 43 should cause the output ature coefficients of the thin film resistors of the DAC. Simply voltage to be 16 × VIN. However, if the DAC has a linearity speci- placing a resistor in series with the RFB resistor causes mismatches fication of ±0.5 LSB, D can have a weight in the range of 15.5/256 in the temperature coefficients, resulting in larger gain temper- to 16.5/256, so that the possible output voltage is in the range of ature coefficient errors. Instead, the circuit in Figure 42 shows 15.5 V to 16.5 V . This range represents an error of 3%, even IN IN the recommended method of increasing the gain of the circuit. though the DAC itself has a maximum error of 0.2%. R1, R2, and R3 should have similar temperature coefficients, DAC leakage current is also a potential error source in divider but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits in which circuits. The leakage current must be counterbalanced by an gains of greater than 1 are required. opposite current supplied from the op amp through the DAC. Because only a fraction, D, of the current into the VREFx terminal DIVIDER OR PROGRAMMABLE GAIN ELEMENT is routed to the IOUT1 terminal, the output voltage changes as Current-steering DACs are very flexible and lend themselves follows: to many applications. If this type of DAC is connected as the Output Error Voltage Due to DAC Leakage = (Leakage × R)/D feedback element of an op amp and R A is used as the input FB where R is the DAC resistance at the V x terminal. resistor, as shown in Figure 43, the output voltage is inversely REF proportional to the digital input fraction, D. For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that −n is, 1/D) of 16, the error voltage is 1.6 mV. For D = 1 − 2 , the output voltage is − n V =−V / D=−V /() 1− 2 IN IN OUT V DD C1 V R A DD FB I 1A OUT R1 8-/10-/12-BIT V V IN V A OUT REF DAC I 2A OUT R3 GND R2 + R3 GAIN = R2 R2 R2R3 R1 = R2 + R3 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 42. Increasing Gain of Current Output DAC V DD V IN R A V FB DD I 1A OUT 8-/10-/12-BIT V A REF DAC I 2A OUT GND V OUT NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element Rev. D | Page 18 of 28 04464-012 04464-011 AD5429/AD5439/AD5449 voltage change is superimposed on the desired change in output REFERENCE SELECTION between the two codes and gives rise to a differential linearity When selecting a reference for use with the AD54xx series of error, which, if large enough, could cause the DAC to be non- current output DACs, pay attention to the reference output voltage monotonic. The input bias current of an op amp also generates temperature coefficient specification. This parameter affects not an offset at the voltage output as a result of the bias current flowing only the full-scale error, but it can also affect the linearity (INL and in the feedback resistor, RFB. Most op amps have input bias DNL) performance. The reference temperature coefficient should currents low enough to prevent significant errors in 12-bit be consistent with the system accuracy specifications. For example, applications. an 8-bit system required to hold its overall specification to within Common-mode rejection of the op amp is important in voltage- 1 LSB over the temperature range of 0°C to 50°C dictates that the switching circuits because it produces a code-dependent error maximum system drift with temperature should be less than at the voltage output of the circuit. Most op amps have adequate 78 ppm/°C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift common-mode rejection for use at 8-, 10-, and 12-bit resolution. of 10 ppm/°C. By choosing a precision reference with a low output If the DAC switches are driven from true wideband low impedance temperature coefficient, this error source can be minimized. sources (VIN and AGND), they settle quickly. Consequently, the Table 7 lists some references available from Analog Devices, Inc., slew rate and settling time of a voltage-switching DAC circuit that are suitable for use with this range of current output DACs. is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance at the AMPLIFIER SELECTION V node (the voltage output node in this application) of the REF The primary requirement for the current-steering mode is an DAC by using low input capacitance buffer amplifiers and careful amplifier with low input bias currents and low input offset voltage. board design. Because of the code-dependent output resistance of the DAC, Most single-supply circuits include ground as part of the analog the input offset voltage of an op amp is multiplied by the variable signal range, which, in turn, requires an amplifier that can handle gain of the circuit. A change in this noise gain between two rail-to-rail signals. Analog Devices offers a wide range of single- adjacent digital fractions produces a step change in the output supply amplifiers (see Table 8 and Table 9). voltage due to the amplifier input offset voltage. This output Table 7. Suitable Analog Devices Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Analog Devices Precision Op Amps Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) 0.1 Hz to 10 Hz Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) I (Max) (nA) Package B AD8065 5 to 24 145 180 1500 6000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8 Rev. D | Page 19 of 28 AD5429/AD5439/AD5449 SDO Control (SDO1 and SDO2) SERIAL INTERFACE The SDO bits enable the user to control the SDO output driver The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire strength, disable the SDO output, or configure it as an open-drain interface that is compatible with SPI, QSPI, MICROWIRE, and driver. The strength of the SDO driver affects the timing of t12, most DSP interface standards. Data is written to the device in and, when stronger, allows a faster clock cycle. 16-bit words. Each 16-bit word consists of four control bits and eight, 10, or 12 data bits, as shown in Figure 44 through Figure 46. Table 10. SDO Control Bits Low Power Serial Interface SDO2 SDO1 Function Implemented 0 0 Full SDO driver To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, 0 1 Weak SDO driver SYNC 1 0 SDO configured as open drain on the falling edge of . The SCLK and SDIN input buffers SYNC 1 1 Disable SDO output are powered down on the rising edge of . DAC Control Bit C3 to Control Bit C0 Daisy-Chain Control (DSY) Control Bit C3 to Control Bit C0 allow control of various functions DSY allows the enabling or disabling of daisy-chain mode. of the DAC, as shown in Table 11. The default settings of the DAC A 1 enables daisy-chain mode; a 0 disables daisy-chain mode. at power-on are such that data is clocked into the shift register When disabled, a readback request is accepted; SDO is auto- on falling clock edges and daisy-chain mode is enabled. The device matically enabled; the DAC register contents of the relevant powers on with a zero-scale load to the DAC register and I lines. OUT DAC are clocked out on SDO; and, when complete, SDO is The DAC control bits allow the user to adjust certain features at disabled again. power-on. For example, daisy-chaining can be disabled if not in Hardware CLR Bit (HCLR) use, an active clock edge can be changed to a rising edge, and DAC CLR The default setting for the hardware bit is to clear the registers output can be cleared to either zero scale or midscale. The user and DAC output to zero code. A 1 in the HCLR bit allows the can also initiate a readback of the DAC register contents for veri- CLR pin to clear the DAC outputs to midscale, and a 0 clears to fication. zero scale. Control Register (Control Bits = 1101) Active Clock Edge (SCLK) While maintaining software compatibility with single-channel The default active clock edge is a falling edge. Write a 1 to this current output DACs (AD5426/AD5432/AD5443), these DACs bit to clock data in on the rising edge, or a 0 to clock it in on the also feature additional interface functionality. Set the control bits falling edge. to 1101 to enter control register mode. Figure 47 shows the contents of the control register, the functions of which are described in the following sections. DB15 (MSB) DB0 (LSB) C3 C2 C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 CONTROL BITS DATA BITS Figure 44. AD5429 8-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C3 C2 C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 CONTROL BITS DATA BITS Figure 45. AD5439 10-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DATA BITS Figure 46. AD5449 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) 11 0 1 SDO2 SDO1 DSY HCLR SCLK XX X XX X X CONTROL BITS Figure 47. Control Register Loading Sequence Rev. D | Page 20 of 28 04464-016 04464-015 04464-014 04464-013 AD5429/AD5439/AD5449 When control bits = 0000, the device is in no operation mode. SYNC Function This may be useful in daisy-chain applications in which the user SYNC is an edge-triggered input that acts as a frame synchron- does not want to change the settings of a particular DAC in the ization signal and chip enable. Data can be transferred into the chain. Write 0000 to the control bits for that DAC; subsequent device only while SYNC is low. To start the serial data transfer, data bits are ignored. SYNC should be taken low, observing the minimum SYNC Standalone Mode falling edge to SCLK falling edge setup time, t4. After power-on, write 1001 to the control word to disable daisy- Daisy-Chain Mode SYNC chain mode. The first falling edge of resets the serial Daisy-chain mode is the default power-on mode. To disable the clock counter to ensure that the correct number of bits are daisy-chain function, write 1001 to the control word. In daisy- shifted in and out of the serial shift registers. A SYNC edge chain mode, the internal gating on SCLK is disabled. SCLK is during the 16-bit write cycle causes the device to abort the SYNC continuously applied to the input shift register when is current write cycle. low. If more than 16 clock pulses are applied, the data ripples After the falling edge of the 16th SCLK pulse, data is automat- out of the shift register and appears on the SDO line. This data ically transferred from the input shift register to the DAC. For is clocked out on the rising edge of SCLK (this is the default; use another serial transfer to take place, the counter must be reset the control word to change the active edge) and is valid for the SYNC by the falling edge of . next device on the falling edge of SCLK (default). By connecting this line to the SDIN input on the next device in the chain, LDAC Function a multidevice interface is constructed. For each device in the The LDAC function allows asynchronous and synchronous system, 16 clock pulses are required. Therefore, the total number updates to the DAC output. The DAC is asynchronously updated of clock cycles must equal 16n, where n is the total number of when this signal goes low. Alternatively, if this line is held perma- devices in the chain. See Figure 4. nently low, an automatic or synchronous update mode is selected, SYNC When the serial transfer to all devices is complete, should whereby the DAC is updated on the 16th clock falling edge when be taken high. This prevents additional data from being clocked the device is in standalone mode, or on the rising edge of SYNC into the input shift register. A burst clock containing the exact when the device is in daisy-chain mode. number of clock cycles can be used, after which SYNC can be Software LDAC Function taken high. After the rising edge of SYNC, data is automatically Load-and-update mode can also serve as a software update func- transferred from the input shift register of each device to the LDAC tion, irrespective of the voltage level on the pin. addressed DAC. Table 11. DAC Control Bits C3 C2 C1 C0 DAC Function Implemented 0 0 0 0 A and B No operation (power-on default) 0 0 0 1 A Load and update 0 0 1 0 A Initiate readback 0 0 1 1 A Load input register 0 1 0 0 B Load and update 0 1 0 1 B Initiate readback 0 1 1 0 B Load input register 0 1 1 1 A and B Update DAC outputs 1 0 0 0 A and B Load input registers 1 0 0 1 N/A Disable daisy-chain 1 0 1 0 N/A Clock data to shift register on rising edge 1 0 1 1 N/A Clear DAC output to zero scale 1 1 0 0 N/A Clear DAC output to midscale 1 1 0 1 N/A Control word 1 1 1 0 N/A Reserved 1 1 1 1 N/A No operation Rev. D | Page 21 of 28 AD5429/AD5439/AD5449 See the ADSP-21xx user manual at www.analog.com for details MICROPROCESSOR INTERFACING SYNC on clock and frame frequencies for the SPORT register. Microprocessor interfacing to the AD54xx family of DACs is Table 12 shows the setup for the SPORT control register. through a serial bus that uses standard protocol and is compatible with microcontrollers and DSP processors. The communication Table 12. SPORT Control Register Setup channel is a 3-wire interface consisting of a clock signal, a data Name Setting Description signal, and a synchronization signal. The AD5429/AD5439/ TFSW 1 Alternate framing AD5449 require a 16-bit word, with the default being data valid INVTFS 1 Active low frame signal on the falling edge of SCLK; however, this is changeable using DTYPE 00 Right-justify data the control bits in the data-word. ISCLK 1 Internal serial clock ADSP-21xx-to-AD5429/AD5439/AD5449 Interface TFSR 1 Frame every word ITFS 1 Internal framing signal The ADSP-21xx family of DSPs is easily interfaced to an AD5429/ SLEN 1111 16-bit data-word AD5439/AD5449 DAC without the need for extra glue logic. Figure 48 is an example of a serial peripheral interface (SPI) ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface between the DAC and the ADSP-2191. The MOSI (master output, The ADSP-BF5xx family of processors has an SPI-compatible port slave input) pin of the DSP drives the serial data line, SDIN. SYNC is driven from a port line, in this case SPIxSEL. that enables the processor to communicate with SPI-compatible devices. A serial interface between the BlackFin® processor and AD5429/AD5439/ ADSP-2191* the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In AD5449* this configuration, data is transferred through the MOSI pin. SYNC SPIxSEL SYNC SPIxSEL is driven by the pin, which is a reconfigured MOSI SDIN programmable flag pin. SCK SCLK AD5429/AD5439/ ADSP-BF5xx* AD5449* *ADDITIONAL PINS OMITTED FOR CLARITY. SPIxSEL SYNC Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface MOSI SDIN The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates SCK SCLK channel synchronous serial ports (SPORT). A serial interface between the DAC and DSP SPORT is shown in Figure 49. In this *ADDITIONAL PINS OMITTED FOR CLARITY. interface example, SPORT0 is used to transfer data to the DAC Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface shift register. Transmission is initiated by writing a word to the Tx register after SPORT has been enabled. In a write sequence, data A serial interface between the DAC and the DSP SPORT is shown is clocked out on each rising edge of the DSP serial clock and in Figure 51. When SPORT is enabled, initiate transmission by clocked into the DAC input shift register on the falling edge of writing a word to the Tx register. The data is clocked out on each its SCLK. Updating of the DAC output takes place on the rising rising edge of the DSP serial clock and clocked into the DAC SYNC input shift register on the falling edge of its SCLK. The DAC edge of the signal. output is updated by using the transmit frame synchronization AD5429/AD5439/ ADSP-2101/ (TFS) line to provide a SYNC signal. ADSP-2103/ AD5449* ADSP-2191* TFS SYNC AD5429/AD5439/ ADSP-BF5xx* AD5449* DT SDIN TFS SYNC SCLK SCLK DT SDIN SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to- AD5429/AD5439/AD5449 Interface *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame SYNC SYNC delay and frame setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t (SYNC falling edge to SCLK falling edge setup time) of 13 ns 4 minimum. Rev. D | Page 22 of 28 04464-028 04464-027 04464-034 04464-033 AD5429/AD5439/AD5449 80C51/80L51-to-AD5429/AD5439/AD5449 Interface valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges A serial interface between the DAC and the 80C51/80L51 is occurring in the transmit cycle. Data is transmitted MSB first. shown in Figure 52. TxD of the 80C51/80L51 drives SCLK of the DAC serial interface, and RxD drives the serial data line, SDIN. To load data to the DAC, leave PC7 low after the first eight bits P1.1 is a bit-programmable pin on the serial port and is used to are transferred and perform a second serial write operation to SYNC drive . When data is to be transmitted to the switch, P1.1 the DAC. PC7 is taken high at the end of this procedure. is taken low. The 80C51/80L51 transmit data in 8-bit bytes only; If the user wants to verify the data previously written to the input therefore, only eight falling clock edges occur in the transmit cycle. shift register, the SDO line can be connected to MISO of the To load data correctly to the DAC, P1.1 is left low after the first SYNC MC68HC11, and, with low, the shift register clocks data eight bits are transmitted, and then a second write cycle is initiated out on the rising edges of SCLK. to transmit the second byte of data. Data on RxD is clocked out MICROWIRE-to-AD5429/AD5439/AD5449 Interface of the microcontroller on the rising edge of TxD and is valid on Figure 54 shows an interface between the DAC and any the falling edge of TxD. As a result, no glue logic is required MICROWIRE-compatible device. Serial data is shifted out between the DAC and microcontroller interface. P1.1 is taken on the falling edge of the serial clock, SK, and is clocked into high following the completion of this cycle. The 80C51/80L51 the DAC input shift register on the rising edge of SK, which provide the LSB of the SBUF register as the first bit in the data corresponds to the falling edge of the DAC SCLK. stream. The DAC input register requires its data with the MSB as the first bit received. The transmit routine should take this MICROWIRE* AD5429/AD5439/ requirement into account. AD5449* SK SCLK AD5429/AD5439/ 80C51* SO SDIN AD5449* CS SYNC TxD SCLK RxD SDIN *ADDITIONAL PINS OMITTED FOR CLARITY. P1.1 SYNC Figure 54. MICROWIRE-to-AD5429/AD5439/AD5449 Interface PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 52. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is MC68HC11-to-AD5429/AD5439/AD5449 Interface done by writing to the synchronous serial port control register Figure 53 is an example of a serial interface between the DAC (SSPCON). See the PIC16/17 microcontroller user manual for and the MC68HC11 microcontroller. The SPI on the MC68HC11 more information. In this example, the I/O port, RA1, is used to is configured for master mode (MSTR) = 1, clock polarity bit provide a SYNC signal and enable the serial port of the DAC. This (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured microcontroller transfers only eight bits of data during each serial by writing to the SPI control register (SPCR); see the MC68HC11 transfer operation; therefore, two consecutive write operations user manual. The SCK of the MC68HC11 drives the SCLK of are required. Figure 55 shows the connection diagram. the DAC interface; the MOSI output drives the serial data line (SDIN) of the AD5429/AD5439/AD5449. PIC16C6x/7x* AD5429/AD5439/ AD5449* MC68HC11* AD5429/AD5439/ SCK/RC3 SCLK AD5449* SDI/RC4 SDIN PC7 SYNC RA1 SYNC SCK SCLK MOSI SDIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 55. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface The SYNC signal is derived from a port line (PC7). When data SYNC is being transmitted to the AD5429/AD5439/AD5449, the line is taken low (PC7). Data appearing on the MOSI output is Rev. D | Page 23 of 28 04464-030 04464-029 04464-032 04464-031 AD5429/AD5439/AD5449 Components, such as clocks, that produce fast-switching signals, PCB LAYOUT AND POWER SUPPLY DECOUPLING should be shielded with digital ground to avoid radiating noise In any circuit where accuracy is important, careful considera- to other parts of the board, and they should never be run near tion of the power supply and ground return layout helps to the reference inputs. ensure the rated performance. The printed circuit board on which the AD5429/AD5439/AD5449 is mounted should be Avoid crossover of digital and analog signals. Traces on opposite designed so that the analog and digital sections are separate sides of the board should run at right angles to each other. This and confined to certain areas of the board. If the DAC is in a layout reduces the effects of feedthrough on the board. A micro- strip technique is by far the best method, but its use is not always system where multiple devices require an AGND-to-DGND possible with a double-sided board. In this technique, the compo- connection, the connection should be made at one point only. nent side of the board is dedicated to the ground plane, and The star ground point should be established as close as possible signal traces are placed on the soldered side. to the device. The DAC should have ample supply bypassing of 10 μF in parallel It is good practice to use compact, minimum lead-length PCB with 0.1 μF on the supply, located as close as possible to the layout design. Leads to the input should be as short as possible package, ideally right up against the device. The 0.1 μF capacitor to minimize IR drops and stray inductance. should have low effective series resistance (ESR) and low effective The PCB metal traces between VREFx and RFBx should also be series inductance (ESI), such as the common ceramic types of matched to minimize gain error. To maximize high frequency capacitors that provide a low impedance path to ground at high performance, the I-to-V amplifier should be located as close as frequencies, to handle transient currents due to internal logic possible to the device. switching. Low ESR, 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Rev. D | Page 24 of 28 AD5429/AD5439/AD5449 OVERVIEW OF AD54xx DEVICES Table 13. 1 Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. D | Page 25 of 28 AD5429/AD5439/AD5449 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution INL (LSB) Temperature Range Package Description Package Option AD5429YRU 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRU-REEL 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRU-REEL7 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRUZ 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRUZ-REEL 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRUZ-REEL7 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRU 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRU-REEL 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRU-REEL7 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRUZ 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRUZ-REEL 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRUZ-REEL7 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU-REEL 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU-REEL7 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ-REEL 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ-REEL7 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD5449SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 26 of 28 AD5429/AD5439/AD5449 NOTES Rev. D | Page 27 of 28 AD5429/AD5439/AD5449 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04464-0-6/11(D) Rev. D | Page 28 of 28