ANALOG DEVICES AD5428

Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface Data Sheet AD5428/AD5440/AD5447 FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth 1 The AD5428/AD5440/AD5447 are CMOS, 8-, 10-, and 12-bit, INL of ±0.25 LSB @ 8 bits dual-channel, current output digital-to-analog converters (DACs), 20-lead and 24-lead TSSOP packages respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other ±10 V reference input applications. 21.3 MSPS update rate As a result of being manufactured on a CMOS submicron process, Extended temperature range: −40°C to +125°C they offer excellent 4-quadrant multiplication characteristics, 4-quadrant multiplication with large signal multiplying bandwidths of up to 10 MHz. Power-on reset 0.5 μA typical current consumption The DACs use data readback, allowing the user to read the Guaranteed monotonic contents of the DAC register via the DB pins. On power-up, the Readback function internal register and latches are filled with 0s, and the DAC AD7528 upgrade (AD5428) outputs are at zero scale. AD7547 upgrade (AD5447) The applied external reference input voltage (V ) determines REF the full-scale output current. An integrated feedback resistor (R ) FB APPLICATIONS provides temperature tracking and full-scale voltage output when Portable battery-powered applications combined with an external I-to-V precision amplifier. Waveform generators Analog processing The AD5428 is available in a small 20-lead TSSOP package, and Instrumentation applications the AD5440/AD5447 DACs are available in small 24-lead TSSOP Programmable amplifiers and attenuators packages. Digitally controlled calibration Programmable filters and oscillators 1 U.S. Patent Number 5,689,257. Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V A REF AD5428/AD5440/AD5447 R V R A DD FB DB0 DATA I A OUT INPUT INPUTS 8-/10-/12-BIT LATCH BUFFER R-2R DAC A DB7 DB9 DB11 AGND DAC A/B R R B CONTROL FB CS LOGIC I B R/W OUT 8-/10-/12-BIT LATCH R-2R DAC B DGND POWER-ON RESET V B REF Figure 1. AD5428/AD5440/AD5447 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04462-001 AD5428/AD5440/AD5447 Data Sheet TABLE OF CONTENTS Specifications..................................................................................... 3  Divider or Programmable Gain Element................................ 20  Timing Characteristics ................................................................ 5  Reference Selection .................................................................... 20  Absolute Maximum Ratings............................................................ 6  Amplifier Selection .................................................................... 20  ESD Caution.................................................................................. 6  Parallel Interface......................................................................... 22  Pin Configurations and Function Descriptions ........................... 7  Microprocessor Interfacing....................................................... 22  Typical Performance Characteristics ........................................... 10  PCB Layout and Power Supply Decoupling ........................... 23  Terminology .................................................................................... 15  Evaluation Board for the AD5447............................................ 23  General Description ....................................................................... 16  Power Supplies for the Evaluation Board................................ 23  DAC Section................................................................................ 16  Bill of Materials............................................................................... 27  Circuit Operation ....................................................................... 16  Overview of AD54xx Devices....................................................... 28  Single-Supply Applications ....................................................... 19  Outline Dimensions ....................................................................... 29  Adding Gain................................................................................ 19  Ordering Guide .......................................................................... 29  REVISION HISTORY Changes to General Description Section .................................... 16 8/11—Rev. B to Rev. C Changes to Figure 37...................................................................... 16 CS Changes to Pin Description, Table 6........................................ 9 Changes to Single-Supply Applications Section......................... 19 Changes to Figure 40 Through Figure 42.................................... 19 3/11—Rev. A to Rev. B Changes to Divider or Programmable Gain Element Section.... 20 Changes to Evaluation Board For the AD5447 Section ............ 23 Changes to Figure 43...................................................................... 20 Changes to Figure 47 Caption....................................................... 24 Changes to Figure 49...................................................................... 25 Changes to Table 9 Through Table 11 ......................................... 21 Changes to Microprocessor Interfacing Section ........................ 22 Change to U1 Description in Table 12......................................... 27 Added Figure 44 Through Figure 46 ........................................... 22 Change to Ordering Guide............................................................ 29 Added 8xC51-to-AD5428/AD5440/AD5447 7/05—Rev. 0 to Rev. A Interface Section ........................................................................ 22 Changed Pin DAC A/B to DAC A/B................................Universal Added ADSP-BF5xx-to-AD5428/AD5440/AD5447 Changes to Features List .................................................................. 1 Interface Section ........................................................................ 22 Changes to Specifications................................................................ 3 Changes to Power Supplies for the Evaluation Board Section.... 23 Changes to Timing Characteristics................................................ 5 Changes to Table 13 ....................................................................... 28 Change to Figure 2 ........................................................................... 5 Updated Outline Dimensions....................................................... 29 Change to Absolute Maximum Ratings Section........................... 6 Changes to Ordering Guide .......................................................... 29 Change to Figure 13, Figure 14, and Figure 18........................... 11 7/04—Revision 0: Initial Version Change to Figure 32 Through Figure 34 ..................................... 14 Rev. C | Page 2 of 32 Data Sheet AD5428/AD5440/AD5447 1 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5428 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5440 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5447 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±5 nA Data = 0x0000, T = 25°C A ±15 nA Data = 0x0000 REFERENCE INPUT Reference Input Range ±10 V V A, V B Input Resistance 8 10 13 kΩ Input resistance TC = –50 ppm/°C REF REF 1.6 2.5 % Typ = 25°C, max = 125°C VREFA-to-VREFB Input Resistance Mismatch Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, VIH 1.7 V VDD = 3.6 V to 5.5 V 1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5.5 V, I = 200 μA OH DD DD SOURCE VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5.5 V, ISINK = 200 μA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 μA Input Leakage Current, I 1 μA IL Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying BW 10 MHz V = ±3.5 V p-p, DAC loaded all 1s REF Output Voltage Settling Time R = 100 Ω, C = 15 pF, V = 10 V LOAD LOAD REF DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall times, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, VREF = 0 V Rev. C | Page 3 of 32 AD5428/AD5440/AD5447 Data Sheet Parameter Min Typ Max Unit Conditions Multiplying Feedthrough Error DAC latches loaded with all 0s, VREF = ±3.5 V 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Digital Feedthrough 1 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Digital THD Clock = 10 MHz, VREF = 3.5 V 100 kHz fOUT 61 dB 50 kHz f 66 dB OUT SFDR Performance (Wide Band) AD5447, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz fOUT 55 dB 100 kHz fOUT 63 dB 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz f 50 dB OUT 100 kHz fOUT 60 dB 50 kHz fOUT 62 dB SFDR Performance (Narrow Band) AD5447, 65k codes, VREF = 3.5 V Clock = 10 MHz 500 kHz f 73 dB OUT 100 kHz f 80 dB OUT 50k Hz fOUT 87 dB Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz f 75 dB OUT 50 kHz f 80 dB OUT Intermodulation Distortion AD5447, 65k codes, VREF = 3.5 V f1 = 40 kHz, f2 = 50 kHz 72 dB Clock = 10 MHz f1 = 40 kHz, f2 = 50 kHz 65 dB Clock = 25 MHz POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.7 μA TA = 25°C, logic inputs = 0 V or VDD 0.5 10 μA T = −40°C to +125°C, logic inputs = 0 V or V A DD Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design, not subject to production test. Rev. C | Page 4 of 32 Data Sheet AD5428/AD5440/AD5447 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Limit at TMIN, TMAX Unit Conditions/Comments Write Mode t 0 ns min R/W to CS setup time 1 t 0 ns min R/W to CS hold time 2 CS low time t3 10 ns min t 10 ns min Address setup time 4 t 0 ns min Address hold time 5 t6 6 ns min Data setup time t7 0 ns min Data hold time R/W high to CS low t8 5 ns min CS min high time t9 7 ns min Data Readback Mode t10 0 ns typ Address setup time t11 0 ns typ Address hold time t12 5 ns typ Data access time 25 ns max t 5 ns typ Bus relinquish time 13 10 ns max Update Rate 21.3 MSPS Consists of CS min high time, CS low time, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. t t t t 1 2 8 2 R/W t 9 t 3 CS t 5 t t t 4 10 11 DACA/DACB t t 8 12 t 13 t 7 DATA VALID DATA VALID DATA Figure 2. Timing Diagram 200μAI OL V + V TO OUTPUT OH (MIN) OL (MAX) PIN 2 C L 50pF 200μAI OH Figure 3. Load Circuit for Data Output Timing Specifications Rev. C | Page 5 of 32 04462-003 04462-002 AD5428/AD5440/AD5447 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed in Absolute Maximum Ratings may Parameter Rating cause permanent damage to the device. This is a stress rating V to GND –0.3 V to +7 V DD only; functional operation of the device at these or any other VREFA, VREFB, RFBA, RFBB to DGND –12 V to +12 V conditions above those listed in the operational sections of this IOUT1, IOUT2 to DGND –0.3 V to +7 V specification is not implied. Exposure to absolute maximum 1 Logic Inputs and Output –0.3 V to VDD + 0.3 V rating conditions for extended periods may affect device Operating Temperature Range reliability. Only one absolute maximum rating may be applied Automotive (Y Version) –40°C to +125°C at any one time. Storage Temperature Range –65°C to +150°C Junction Temperature 150°C ESD CAUTION 20-lead TSSOP θJA Thermal Impedance 143°C/W 24-lead TSSOP θJA Thermal Impedance 128°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 CS W Overvoltages at DBx, , and R/ are clamped by internal diodes. Rev. C | Page 6 of 32 Data Sheet AD5428/AD5440/AD5447 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 AGND 20 I B OUT 2 19 I A R B OUT FB 3 18 R A V B FB REF AD5428 4 17 V A V REF TOP VIEW DD (Not to Scale) 5 16 DGND R/W DAC A/B 6 15 CS DB7 7 14 DB0 (LSB) 8 DB6 13 DB1 9 DB5 12 DB2 10 DB4 11 DB3 Figure 4. Pin Configuration 20-Lead TSSOP (RU-20) Table 4. AD5428 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 20 IOUTA, IOUTB DAC Current Outputs. 3, 19 RFBA, RFBB DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external amplifier output. 4, 18 V A, V B DAC Reference Voltage Input Terminals. REF REF 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to14 DB7 to DB0 Parallel Data Bits 7 Through 0. 15 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. 16 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of the DAC register. 17 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. Rev. C | Page 7 of 32 04462-004 AD5428/AD5440/AD5447 Data Sheet AGND 1 24 I B OUT 2 I A 23 R B OUT FB 3 R A 22 V B FB REF 4 V A 21 V REF DD AD5440 5 TOP VIEW 20 R/W DGND (Not to Scale) 6 19 DAC A/B CS 7 18 NC DB9 DB8 8 17 NC DB7 9 16 DB0 (LSB) DB6 10 15 DB1 DB5 11 14 DB2 DB4 12 13 DB3 NC = NO CONNECT Figure 5. Pin Configuration 24-Lead TSSOP (RU-24) Table 5. AD5440 Pin Function Descriptions Pin No. Mnemonic Function AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to 1 achieve single-supply operation. 2, 24 I A, I B DAC Current Outputs. OUT OUT DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier 3, 23 R A, R B FB FB output. 4, 22 VREFA, VREFB DAC Reference Voltage Input Terminals. 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to16 DB9 to DB0 Parallel Data Bits 9 Through 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read CS 19 data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with R/W 20 CS to read back contents of the DAC register. 21 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD Rev. C | Page 8 of 32 04462-005 Data Sheet AD5428/AD5440/AD5447 AGND 1 24 I B OUT I A 2 23 R B OUT FB R A 3 22 V B FB REF V A 4 21 V REF DD AD5447 DGND 5 TOP VIEW 20 R/W (Not to Scale) 6 DAC A/B 19 CS 7 DB11 18 DB0 (LSB) 8 17 DB10 DB1 9 16 DB9 DB2 10 15 DB8 DB3 DB7 11 14 DB4 DB6 12 13 DB5 Figure 6. Pin Configuration 24-Lead TSSOP (RU-24) Table 6. AD5447 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 24 I A, I B DAC Current Outputs. OUT OUT 3, 23 R A, R B FB FB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier output. 4, 22 VREFA, VREFB DAC Reference Voltage Input Terminals. 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to 18 DB11 to DB0 Parallel Data Bits 11 Through 0. 19 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. 20 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent. Any changes on the data lines are reflected in the relevant DAC output. 21 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD Rev. C | Page 9 of 32 04462-006 AD5428/AD5440/AD5447 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 T = 25°C T = 25°C A A V = 10V V = 10V REF REF 0.15 0.15 V = 5V V = 5V DD DD 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 7. INL vs. Code (8-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 T = 25°C T = 25°C A A 0.4 0.4 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 8. INL vs. Code (10-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) 1.0 1.0 T = 25°C T = 25°C A A 0.8 0.8 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 9. INL vs. Code (12-Bit DAC) Figure 12. DNL vs. Code (12-Bit DAC) Rev. C | Page 10 of 32 INL (LSB) INL (LSB) INL (LSB) 04462-009 04462-008 04462-007 DNL (LSB) DNL (LSB) DNL (LSB) 04462-012 04462-011 04462-010 Data Sheet AD5428/AD5440/AD5447 0.6 8 0.5 T = 25°C A 7 0.4 MAX INL 6 0.3 5 V = 5V DD 0.2 T = 25°C A V = 5V 4 0.1 DD 0 3 MIN INL –0.1 2 V = 3V DD –0.2 1 V = 2.5V DD –0.3 2 34 5 6 789 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE INPUT VOLTAGE (V) Figure 13. INL vs. Reference Voltage Figure 16. Supply Current vs. Logic Input Voltage 1.6 –0.40 T = 25°C A 1.4 V = 5V DD –0.45 1.2 I 1 V = 5V OUT DD –0.50 1.0 0.8 –0.55 I 1 V = 3V OUT DD 0.6 –0.60 0.4 MIN DNL –0.65 0.2 0 –0.70 –40 –20 0 20 40 60 80 100 120 27 34 5 68910 TEMPERATURE (°C) REFERENCE VOLTAGE Figure 14. DNL vs. Reference Voltage Figure 17. IOUT1 Leakage Current vs. Temperature 5 0.50 0.45 4 V = 5V V = 5V DD DD 3 0.40 2 0.35 ALL 0s 1 0.30 ALL 1s 0 0.25 V = 2.5V V = 2.5V DD DD –1 0.20 –2 0.15 ALL 1s ALL 0s –3 0.10 V = 10V REF 0.05 –4 –5 0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Gain Error vs. Temperature Figure 18. Supply Current vs. Temperature Rev. C | Page 11 of 32 DNL (LSB) ERROR (mV) INL (LSB) 04462-015 04462-013 04462-014 CURRENT (μA) I 1 LEAKAGE (nA) OUT CURRENT (mA) 04462-022 04462-024 04462-023 AD5428/AD5440/AD5447 Data Sheet 14 3 T = 25°C A T = 25°C A LOADING ZS TO FS V = 5V DD 12 V = 5V DD 10 0 8 –3 6 V = 3V DD 4 V =±2V, AD8038 C 1.47pF V = 2.5V REF C DD –6 =±2V, AD8038 C 1pF V REF C 2 V =±0.15V, AD8038 C 1pF REF C V =±0.15V, AD8038 C 1.47pF REF C =±3.51V, AD8038 C 1.8pF V REF C 0 –9 1 10 100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Reference Multiplying Bandwidth vs. Frequency and Figure 19. Supply Current vs. Update Rate Compensation Capacitor 6 T = 25°C ALL ON 0.045 A 0 0x7FF TO 0x800 LOADING T = 25°C DB11 A –6 0.040 ZS TO FS V = 0V REF DB10 –12 V = 5V AMP = AD8038 DD DB9 0.035 –18 C = 1.8pF COMP DB8 –24 0.030 DB7 –30 DB6 –36 0.025 DB5 V = 3V DD –42 DB4 0.020 –48 DB3 –54 0.015 DB2 –60 0x800 TO 0x7FF DB1 –66 0.010 DB0 –72 V = 3V DD 0.005 T = 25°C A –78 V = 5V DD –84 0 V =±3.5V REF –90 C =1.8pF ALL OFF COMP –96 –0.005 AMP = AD8038 V = 5V –102 DD –0.010 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code Figure 23. Midscale Transition, VREF = 0 V –1.68 0.2 T = 25°C A 0x7FF TO 0x800 V = 3.5V REF –1.69 AMP = AD8038 V = 5V DD C = 1.8pF 0 COMP –1.70 –1.71 –0.2 –1.72 V = 3V DD –1.73 –0.4 V = 5V DD –1.74 V = 3V DD T = 25°C A –1.75 –0.6 V = 5V DD V =±3.5V REF –1.76 C = 1.8pF COMP 0x800 TO 0x7FF AMP = AD8038 –1.77 –0.8 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 21. Reference Multiplying Bandwidth—All 1s Loaded Figure 24. Midscale Transition, V = 3.5 V REF Rev. C | Page 12 of 32 GAIN (dB) I (mA) DD GAIN (dB) 04462-026 04462-027 04462-025 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) 04462-028 04462-042 04462-041 Data Sheet AD5428/AD5440/AD5447 90 20 T = 25°C A 80 V = 3V DD MCLK = 5MHz AMP = AD8038 0 70 MCLK = 10MHz 60 –20 50 –40 MCLK = 25MHz FULL SCALE 40 –60 ZERO SCALE 30 –80 20 T = 25°C A 10 V = 3.5V –100 REF AMP = AD8038 0 0 100 200 300 400 500 600 700 800 900 1000 –120 1 10 100 1k 10k 100k 1M 10M f (kHz) OUT FREQUENCY (Hz) Figure 25. Power Supply Rejection Ratio vs. Frequency Figure 28. Wideband SFDR vs. fOUT Frequency –60 0 T = 25°C A T = 25°C A V = 5V DD V = 3V DD –10 AMP = AD8038 V = 3.5V p-p –65 REF 65k CODES –20 –70 –30 –40 –75 –50 –80 –60 –70 –85 –80 –90 –90 0 2 4 6 8 10 12 1 10 100 1k 10k 100k 1M FREQUENCY (MHz) FREQUENCY (Hz) Figure 26. THD + Noise vs. Frequency Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz 100 0 T = 25°C A MCLK = 1MHz V = 5V DD –10 AMP = AD8038 80 65k CODES –20 –30 60 MCLK = 200kHz –40 MCLK = 0.5MHz –50 40 –60 –70 20 –80 T = 25°C A V = 3.5V REF –90 AMP = AD8038 0 –100 0 20 40 60 80 100 120 140 160 180 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 f (kHz) FREQUENCY (MHz) OUT Figure 27. Wideband SFDR vs. f Frequency OUT Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz Rev. C | Page 13 of 32 SFDR (dB) THD + N (dB) PSRR (dB) 04462-043 04462-045 04462-044 SFDR (dB) SFDR (dB) SFDR (dB) 04462048 04462-047 04462-046 AD5428/AD5440/AD5447 Data Sheet 0 0 T = 25°C T = 25°C  A A V = 5V V = 3V DD DD –10 –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (MHz) FREQUENCY (kHz) Figure 31. Wideband SFDR, f = 50 kHz, Clock = 10 MHz Figure 34. Narrow-Band IMD, f = 90 kHz, 100 kHz, Clock = 10 MHz OUT OUT 0 0 T = 25°C  T = 25°C A  A V = 3V V = 5V DD –10 –10 DD AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 250 300 350 400 450 500 550 600 650 700 750 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) FREQUENCY (kHz) Figure 32. Narrow-Band SFDR, f = 500 kHz, Clock = 25 MHz OUT Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz 20 300 T = 25°C T = 25°C  A A V = 3V ZERO SCALE LOADED TO DAC AMP = AD8038 DD AMP = AD8038 0 MIDSCALE LOADED TO DAC 250 65k CODES FULL SCALE LOADED TO DAC –20 200 –40 150 –60 100 –80 50 –100 0 –120 100 1k 10k 100k 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (kHz) FREQUENCY (Hz) Figure 36. Output Noise Spectral Density Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz Rev. C | Page 14 of 32 SFDR (dB) SFDR (dB) SFDR (dB) 04462-051 04462-050 04462-049 OUTPUT NOISE (nV/ Hz) IMD (dB) IMD (dB) 04462-53 04462-052 04462-054 Data Sheet AD5428/AD5440/AD5447 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Feedthrough A measure of the maximum deviation from a straight line When the device is not selected, high frequency logic activity passing through the endpoints of the DAC transfer function. It on the device’s digital inputs is capacitively coupled through the is measured after adjusting for zero and full scale and is device and produces noise on the IOUT pins and, subsequently, typically expressed in LSBs or as a percentage of the full-scale on the following circuitry. This noise is digital feedthrough. reading. Multiplying Feedthrough Error Differential Nonlinearity The error due to capacitive feedthrough from the DAC The difference in the measured change and the ideal 1 LSB reference input to the DAC I 1 terminal when all 0s are OUT change between two adjacent codes. A specified differential loaded to the DAC. nonlinearity of −1 LSB maximum over the operating Total Harmonic Distortion (THD) temperature range ensures monotonicity. The DAC is driven by an ac reference. The ratio of the rms sum Gain Error (Full-Scale Error) of the harmonics of the DAC output to the fundamental value is A measure of the output error between an ideal DAC and the the THD. Usually only the lower-order harmonics are included, actual device output. For these DACs, ideal maximum output is such as second to fifth harmonics. V – 1 LSB. The gain error of the DACs is adjustable to zero REF 2 2 2 2 with an external resistance. V +V +V +V 2 3 4 5 THD= 20 log V 1 Output Leakage Current The current that flows into the DAC ladder switches when they Digital Intermodulation Distortion are turned off. For the IOUT1 terminal, it can be measured by Second-order intermodulation distortion (IMD) measurements loading all 0s to the DAC and measuring the I 1 current. OUT are the relative magnitude of the fa and fb tones digitally generated Minimum current flows into the I 2 line when the DAC is OUT by the DAC and the second-order products at 2fa − fb and loaded with all 1s. 2fb − fa. Output Capacitance Spurious-Free Dynamic Range (SFDR) Capacitance from I 1 or I 2 to AGND. OUT OUT SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the Output Current Settling Time measure of difference in amplitude between the fundamental The amount of time for the output to settle to a specified level and the largest harmonic or nonharmonic spur from dc to full for a full-scale input change. For these devices, it is specified Nyquist bandwidth (half the DAC sampling rate, or fs/2). with a 100 Ω resistor to ground. Narrow-band SFDR is a measure of SFDR over an arbitrary Digital-to-Analog Glitch Impulse window size, in this case 50%, of the fundamental. Digital SFDR The amount of charge injected from the digital inputs to the is a measure of the usable dynamic range of the DAC when the analog output when the inputs change state. This is normally signal is a digitally generated sine wave. specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or voltage signal. Rev. C | Page 15 of 32 AD5428/AD5440/AD5447 Data Sheet GENERAL DESCRIPTION CIRCUIT OPERATION DAC SECTION Unipolar Mode The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit, Using a single op amp, these devices can easily be configured to dual-channel, current output DACs consisting of a standard provide 2-quadrant multiplying operation or a unipolar output inverting R-2R ladder configuration. Figure 37 shows a simplified voltage swing, as shown in Figure 38. When an output amplifier diagram for a single channel of the 8-bit AD5428. The feedback is connected in unipolar mode, the output voltage is given by resistor RFBA has a value of R. The value of R is typically 10 kΩ (with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1 n V =− V × D /2 OUT REF and AGND are kept at the same potential, a constant current flows into each ladder leg, regardless of digital input code. where: Therefore, the input resistance presented at V A is always REF D is the fractional representation of the digital word loaded to constant and nominally of value R. The DAC output (I ) is OUT the DAC. code-dependent, producing various resistances and D = 0 to 255 (8-bit AD5428) capacitances. When choosing an external amplifier, take into = 0 to 1023 (10-bit AD5440) account the variation in impedance generated by the DAC on = 0 to 4095 (12-bit AD5447) the amplifier’s inverting input node. n is the resolution of the DAC. RR R V REF Note that the output voltage polarity is opposite to the VREF 2R 2R 2R 2R 2R polarity for dc reference voltages. These DACs are designed to S1 S2 S3 S8 R R A operate with either negative or positive reference voltages. The FB I A OUT V power pin is only used by the internal digital logic to drive DD AGND the on and off states of the DAC switches. DAC DATA LATCHES AND DRIVERS These DACs are also designed to accommodate ac reference Figure 37. Simplified Ladder input signals in the range of –10 V to +10 V. With a fixed 10 V reference, the circuit in Figure 38 gives a Access is provided to the V , R , and I terminals of DAC A REF FB OUT unipolar 0 V to –10 V output voltage swing. When V is an ac IN and DAC B, making the devices extremely versatile and signal, the circuit performs 2-quadrant multiplication. allowing them to be configured in several operating modes, such as unipolar output mode, 4-quadrant multiplication Table 7 shows the relationship between digital code and the bipolar mode, or single-supply mode. Note that a matching expected output voltage for unipolar operation using the 8-bit switch is used in series with the internal RFBA feedback resistor. AD5428. If users attempt to measure RFBA, power must be applied to VDD Table 7. Unipolar Code to achieve continuity. Digital Input Analog Output (V) 1111 1111 –V (255/256) REF 1000 0000 –V (128/256) = –V /2 REF REF 0000 0001 –VREF (1/256) 0000 0000 –VREF (0/256) = 0 Rev. C | Page 16 of 32 04462-029 Data Sheet AD5428/AD5440/AD5447 V A IN (±10V) 1 R1 V A REF AD5428/AD5440/AD5447 R A 1 R FB R2 V DD 2 C1 I A OUT DB0 DATA 8-/10-/12-BIT INPUTS INPUT LATCH V A OUT R-2R DAC A BUFFER DB7 DB9 DB11 AGND AGND R B DAC A/B 1 FB R4 R CONTROL 2 CS C2 LOGIC I B OUT R/W 8-/10-/12-BIT LATCH V B OUT R-2R DAC B DGND AGND POWER-ON RESET V B REF 1 R3 V B IN (±10V) 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2 C1, C2 PHASE COMPENSATION (1pF TO 2pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION. Figure 38. Unipolar Operation Rev. C | Page 17 of 32 04462-030 AD5428/AD5440/AD5447 Data Sheet Bipolar Operation Table 8. Bipolar Code Digital Input Analog Output (V) In some applications, it may be necessary to generate full 4-quad- 1111 1111 +VREF (127/128) rant multiplying operation or a bipolar output swing. This can 1000 0000 0 easily be accomplished by using another external amplifier and 0000 0001 –V (127/128) REF some external resistors, as shown in Figure 39. In this circuit, the 0000 0000 –V (128/128) REF second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full Stability 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are In the I-to-V configuration, the IOUT of the DAC and the inverting created as the input data (D) is incremented from Code 0 (VOUT = node of the op amp must be connected as close as possible, and −VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). proper PCB layout techniques must be used. Because every code When connected in bipolar mode, the output voltage is given by change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (GBP) and n−1 V =() V × D/ 2 − V OUT REF REF there is excessive parasitic capacitance at the inverting node. where: This parasitic capacitance introduces a pole into the open-loop D is the fractional representation of the digital word loaded to response, which can cause ringing or instability in the closed- the DAC. loop applications circuit. D = 0 to 255 (AD5428) An optional compensation capacitor, C1, can be added in parallel = 0 to 1023 (AD5440) with R A for stability, as shown in Figure 38 and Figure 39. Too FB = 0 to 4095 (AD5447) small a value of C1 can produce ringing at the output, whereas n is the number of bits. too large a value can adversely affect the settling time. C1 should When VIN is an ac signal, the circuit performs 4-quadrant be found empirically, but 1 pF to 2 pF is generally adequate for multiplication. Table 8 shows the relationship between digital the compensation. code and the expected output voltage for bipolar operation using the 8-bit AD5428. V A IN (±10V) R5 1 R1 20kΩ 2 R6 20kΩ V A REF AD5428/AD5440/AD5447 2 R7 A2 10kΩ 1 RR R A2 V A OUT FB V DD 3 C1 R11 5kΩ I A OUT DATA DB0 INPUTS INPUT 8-/10-/12-BIT LATCH A1 BUFFER R-2R DAC A AGND DB7 DB9 DB11 AGND AGND DAC A/B R B 1 FB R4 R CONTROL CS LOGIC 3 C2 I B OUT R/W 8-/10-/12-BIT A3 LATCH R8 R-2R DAC B 20kΩ 2 R9 DGND 10kΩ AGND 2 A4 R10 POWER-ON 20kΩ V B RESET OUT V B REF R12 5kΩ 1 R3 AGND V B IN (±10V) 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V A = 0V WITH CODE 10000000 IN DAC A LATCH. OUT ADJUST R3 FOR V B = 0V WITH CODE 10000000 IN DAC B LATCH. OUT 2 MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3 C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER. Figure 39. Bipolar Operation (4-Quadrant Multiplication) Rev. C | Page 18 of 32 04462-031 Data Sheet AD5428/AD5440/AD5447 V = 5V DD SINGLE-SUPPLY APPLICATIONS ADR03 Voltage-Switching Mode V V OUT IN GND Figure 40 shows the DACs operating in voltage-switching +5V C1 mode. The reference voltage, V , is applied to the I A pin, IN OUT V R A DD FB and the output voltage is available at the V A terminal. In this REF 8-/10-/12-BIT I A OUT –2.5V V A REF DAC configuration, a positive reference voltage results in a positive AGND V = OUT 0V to 2.5V output voltage, making single-supply operation possible. The GND –5V output from the DAC is voltage at constant impedance (the DAC ladder resistance). Therefore, an op amp is necessary to NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. buffer the output voltage. The reference input no longer sees 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low Figure 41. Positive Voltage Output with Minimum Components impedance source. ADDING GAIN Note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source-drain drive In applications where the output voltage must be greater than voltage. As a result, their on resistance differs and degrades the V , gain can be added with an additional external amplifier, or IN integral linearity of the DAC. Also, VIN must not go negative by it can be achieved in a single stage. Consider the effect of temper- more than 0.3 V, or an internal diode turns on, causing the ature coefficients of the thin film resistors of the DAC. Simply device to exceed the maximum ratings. In this type of placing a resistor in series with the RFB resistor causes mismatches application, the full range of multiplying capability of the DAC in the temperature coefficients, resulting in larger gain temper- is lost. ature coefficient errors. Instead, the circuit in Figure 42 shows the recommended method for increasing the gain of the circuit. R1, R2, and R3 should have similar temperature coefficients, V DD but they need not match the temperature coefficients of the R1 R2 DAC. This approach is recommended in circuits where gains of greater than 1 are required. R A V FB DD V I A V IN OUT V OUT DD V A REF AGND GND C1 V R A DD FB R1 I A OUT 8-/10-/12-BIT V V IN OUT NOTES AGND V A DAC REF 1. ADDITIONAL PINS OMITTED FOR CLARITY. R3 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED GND R2 + R3 IF A1 IS A HIGH SPEED AMPLIFIER. GAIN = R2 R2 R2R3 Figure 40. Single-Supply Voltage-Switching Mode R = NOTES 1 R2 R3 + 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED Positive Output Voltage IF A1 IS A HIGH SPEED AMPLIFIER. The output voltage polarity is opposite to the V polarity for REF Figure 42. Increasing Gain of Current Output DAC dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor’s tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the V and GND pins of the reference become the virtual OUT ground and –2.5 V, respectively, as shown in Figure 41. Rev. C | Page 19 of 32 04462-033 04462-034 04462-035 AD5428/AD5440/AD5447 Data Sheet REFERENCE SELECTION DIVIDER OR PROGRAMMABLE GAIN ELEMENT When selecting a reference for use with the AD54xx series of Current-steering DACs are very flexible and lend themselves to current output DACs, pay attention to the reference’s output many applications. If this type of DAC is connected as the voltage temperature coefficient specification. This parameter not feedback element of an op amp and RFBA is used as the input only affects the full-scale error, but can also affect the linearity resistor, as shown in Figure 43, the output voltage is inversely (INL and DNL) performance. The reference temperature proportional to the digital input fraction, D. coefficient should be consistent with the system accuracy −n For D = 1 − 2 , the output voltage is specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range −n V =−V/ D=−V /() 1− 2 OUT IN IN 0° to 50°C dictates that the maximum system drift with temp- erature should be less than 78 ppm/°C. A 12-bit system with the V DD same temperature range to overall specification within 2 LSBs V IN requires a maximum drift of 10 ppm/°C. Choosing a precision R A reference with low output temperature coefficient minimizes this FB V DD I A OUT error source. Table 9 lists some references available from Analog V A REF AGND Devices that are suitable for use with these current output DACs. GND AMPLIFIER SELECTION The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset V OUT voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. A change in the noise gain between NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential As D is reduced, the output voltage increases. For small values linearity error, which, if large enough, could cause the DAC to of the digital fraction D, it is important to ensure that the be nonmonotonic. The input offset voltage should be <1/4 LSB amplifier does not saturate and that the required accuracy is to ensure monotonic behavior when stepping through codes. met. For example, an 8-bit DAC driven with the binary code 0x10 (0001 0000)—that is, 16 decimal—in the circuit of The input bias current of an op amp also generates an offset at Figure 43 should cause the output voltage to be 16 times V . the voltage output as a result of the bias current flowing in the IN feedback resistor, R . Most op amps have input bias currents However, if the DAC has a linearity specification of ±0.5 LSB, D FB low enough to prevent significant errors in 12-bit applications. can have a weight in the range of 15.5/256 to 16.5/256 so that the possible output voltage is in the range of 15.5 VIN to 16.5 VIN— Common-mode rejection of the op amp is important in voltage- an error of 3%, even though the DAC itself has a maximum switching circuits, because it produces a code-dependent error error of 0.2%. at the voltage output of the circuit. Most op amps have adequate DAC leakage current is also a potential error source in divider common-mode rejection for use at 8-, 10-, and 12-bit resolution. circuits. The leakage current must be counterbalanced by an Provided that the DAC switches are driven from true wideband, opposite current supplied from the op amp through the DAC. low impedance sources (V and AGND), they settle quickly. IN Because only a fraction, D, of the current into the VREF terminal Consequently, the slew rate and settling time of a voltage- is routed to the IOUT1 terminal, the output voltage changes as switching DAC circuit is determined largely by the output op follows: amp. To obtain minimum settling time in this configuration, Output Error Voltage Due to DAC Leakage=(Leakage× R)/D minimize capacitance at the VREF node (the voltage output node in this application) of the DAC by using low input capacitance where R is the DAC resistance at the VREF terminal. buffer amplifiers and careful board design. For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that Most single-supply circuits include ground as part of the analog is, 1/D) of 16, the error voltage is 1.6 mV. signal range, which in turns requires an amplifier that can handle rail-to-rail signals. Analog Devices offers a wide variety of single- supply amplifiers (see Table 10 and Table 11). Rev. C | Page 20 of 32 04462-040 Data Sheet AD5428/AD5440/AD5447 Table 9. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 10. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 11. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. C | Page 21 of 32 AD5428/AD5440/AD5447 Data Sheet 8xC51-to-AD5428/AD5440/AD5447 Interface PARALLEL INTERFACE Figure 45 shows the interface between the AD5428/AD5440/ Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or AD5447 and the 8xC51 family of DSPs. To facilitate external 12-bit parallel word format. Control lines CS and R/W allow data memory access, the address latch enable (ALE) mode is data to be written to or read from the DAC register. A write enabled. The low byte of the address is latched with this output event takes place when and R/ are brought low, data CS W pulse during access to the external memory. AD0 to AD7 are available on the data lines fills the shift register, and the rising the multiplexed low order addresses and data bus, and they edge of CS latches the data and transfers the latched data-word require strong internal pull-ups when emitting 1s. During to the DAC register. The DAC latches are not transparent; access to external memory, A8 to A15 are the high order therefore, a write sequence must consist of a falling and rising address bytes. Because these ports are open drain, they also edge on CS to ensure that data is loaded into the DAC register require strong internal pull-ups when emitting 1s. and its analog equivalent is reflected on the DAC output. A8 TO A15 ADDRESS BUS A read event takes place when R/ is held high and is W CS brought low. Data is loaded from the DAC register, goes back AD5428/ 1 into the input register, and is output onto the data line, where it 8051 AD5440/ 1 can be read back to the controller for verification or diagnostic AD5447 ADDRESS CS DECODER purposes. The input and DAC registers of these devices are not transparent; therefore, a falling and rising edge of is required CS WR R/W to load each data-word. DB0 TO DB11 8-BIT ALE MICROPROCESSOR INTERFACING LATCH ADSP-21xx-to-AD5428/AD5440/AD5447 Interface AD0 TO AD7 DATA BUS Figure 44 shows the AD5428/AD5440/AD5447 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A 1 ADDITIONAL PINS OMITTED FOR CLARITY. single wait state may be necessary to interface the AD5428/ Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface AD5440/AD5447 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface data memory wait state control register of the ADSP-21xx (see Figure 46 shows a typical interface between the AD5428/ the ADSP-21xx family’s user manual for details). AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The ADDR TO 0 ADDRESS BUS asynchronous memory write cycle of the processor drives the ADRR 13 digital inputs of the DAC. The AMSx line is actually four memory select lines. Internal ADDR lines are decoded into AD5428/ 1 ADSP-21xx AD5440/ AMS3–0, and then these lines are inserted as chip selects. The 1 ADDRESS AD5447 DMS CS rest of the interface is a standard handshaking operation. DECODER ADDR TO 1 ADDRESS BUS WR R/W ADRR 19 DB0 TO DB11 AD5428/ 1 ADSP-BF5xx AD5440/ 1 AD5447 ADDRESS AMSx DATA 0 TO CS DATA BUS DECODER DATA 23 1 ADDITIONAL PINS OMITTED FOR CLARITY. AWE R/W Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface DB0 TO DB11 DATA 0 TO DATA BUS DATA 23 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface Rev. C | Page 22 of 32 04462-055 04462-056 04462-057 Data Sheet AD5428/AD5440/AD5447 microstrip technique is by far the best method, but its use is not PCB LAYOUT AND POWER SUPPLY DECOUPLING always possible with a double-sided board. In this technique, In any circuit where accuracy is important, careful the component side of the board is dedicated to the ground consideration of the power supply and ground return layout plane, and signal traces are placed on the soldered side. helps to ensure the rated performance. The printed circuit board on which the AD5428/AD5440/AD5447 is mounted It is good practice to use compact, minimum lead length PCB should be designed so that the analog and digital sections are layout design. Leads to the input should be as short as possible separate and confined to certain areas of the board. If the DAC to minimize IR drops and stray inductance. is in a system where multiple devices require an AGND-to- The PCB metal traces between VREF and RFB should also be DGND connection, the connection should be made at one matched to minimize gain error. To maximize high frequency point only. The star ground point should be established as close performance, the I-to-V amplifier should be located as close as as possible to the device. possible to the device. These DACs should have ample supply bypassing of 10 μF in EVALUATION BOARD FOR THE AD5447 parallel with 0.1 μF on the supply located as close as possible to the package, ideally right up against the device. The 0.1 μF The evaluation board consists of an AD5447 DAC and a current-to-voltage amplifier, the AD8065. Included on the capacitor should have low effective series resistance (ESR) and evaluation board is a 10 V reference, the ADR01. An external low effective series inductance (ESI), like the common ceramic types of capacitors that provide a low impedance path to ground reference may also be applied via an SMB input. at high frequencies, to handle transient currents due to internal The evaluation kit consists of a CD-ROM with self-installing logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic PC software to control the DAC. The software simply allows the capacitors should also be applied at the supplies to minimize user to write a code to the device. transient disturbance and filter out low frequency ripple. POWER SUPPLIES FOR THE EVALUATION BOARD Components, such as clocks, that produce fast-switching signals The board requires ±12 V and +5 V supplies. The +12 V VDD should be shielded with digital ground to avoid radiating noise and −12 V VSS are used to power the output amplifier; the +5 V to other parts of the board, and they should never be run near is used to power the DAC (VDD1) and transceivers (VCC). the reference inputs. Both supplies are decoupled to their respective ground plane Avoid crossover of digital and analog signals. Traces on with 10 μF tantalum and 0.1 μF ceramic capacitors. opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A Rev. C | Page 23 of 32 AD5428/AD5440/AD5447 Data Sheet Figure 47. Schematic of AD5447 Evaluation Board Rev. C | Page 24 of 32 V 1 24 VCC LEBA 2 23 OEBA CEBA 3 15 P1–7 A0 B7 4 16 P1–6 A1 B6 5 DB0 18 DB0 P1–5 A2 B5 6 DB1 17 DB1 B4 P1–4 A3 7 19 DB2 16 DB2 P1–3 A4 B3 8 20 DB3 15 DB3 A5 B2 P1–2 DB4 9 21 14 DB4 A6 B1 10 22 DB5 13 DB5 A7 B0 11 14 DB6 12 DB6 CEAB LEAB 12 13 DB7 11 DB7 GND OEAB DB8 10 DB8 V D B9 9 DB9 DB10 8 DB10 DB11 7 DB11 V 6 DAC_A/B CS 19 CS 4 Y0 RW 20 R/W 2 P1–8 A0 5 24 Y1 1 5 VCC DGND LEBA 3 6 2 P1–9 A1 23 Y2 OEBA CEBA 15 3 1 ND 7 A0 B7 DG P1–36 E Y3 16 4 A1 B6 5 17 A2 B5 6 18 A3 B4 19 7 A4 B3 20 8 A5 B2 21 J3 9 A6 B1 22 10 A7 B0 11 14 CEAB LEAB 12 13 J4 GND OEAB P1–31 P1–1 P1–14 V 12 Y0 14 P2–3 A0 11 Y1 + 13 A1 10 Y2 P2–2 15 9 + E Y3 AGND P2–1 DGND V 1 V P2–4 + V P2–6 + P2–5 C1 V 1 CC DD 0.1μF C5 10μF U4 + U1 C6 AD5447 0.1μF 21 17 V DD C23 18 10μF C22 + 1.8pF V SS 23 C24 R B TP4 FB 0.1μF 24 2 4 I B J6 OUT 6 V– O/P B 3 V+ 7 U7 C25 74ABT543 3 CC R A 10μF FB 2 V C17 DD I A + OUT 0.1μF TP3 TP2 C2 DGND CC C26 U6-A 0.1μF 22 0.1μF V A REF 4 V B REF C9 U5 10μF AGND C7 + 1.8pF 1 J2 J5 V SS C10 TP1 0.1μF EXT EXT 2 4 J1 REF A REF B V– 6 O/P A V+ 3 7 A B U3 LK1 C11 V 10μF DD V DD + 3 4 +V V IN OUT C12 U2 C8 0.1μF 74ABT543 0.1μF C3 + C4 1 5 TRIM 10μF 0.1μF GND 2 U6-B DD C13 C14 0.1μF 10μF C15 C16 0.1μF 10μF DD SS P1–19 P1–20 P1–21 P1–22 C17 C18 P1–23 0.1μF 10μF CC P1–24 P1–25 P1–26 C19 C20 P1–27 P1–28 0.1μF 10μF P1–29 04464-037 P1–30 Data Sheet AD5428/AD5440/AD5447 Figure 48. Component-Side Artwork Figure 49. Silkscreen—Component-Side View (Top Layer) Rev. C | Page 25 of 32 04462-036 04462-038 AD5428/AD5440/AD5447 Data Sheet Figure 50. Solder-Side Artwork Rev. C | Page 26 of 32 04462-039 Data Sheet AD5428/AD5440/AD5447 BILL OF MATERIALS Table 12. Name/Position Part Description Value Tolerance (%) Stock Code C1 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C2 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C3 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C4 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C5 Tantalum capacitor—Taj series 10 μF 10 V 10 FEC 197-130 C6 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C7 NPO ceramic capacitor 1.8 pF 10 FEC 721-876 C8 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C9 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C10 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C11 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C12 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C13 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C14 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C15 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C16 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C17 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C18 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C19 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C20 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C21 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C22 NPO ceramic capacitor 1.8 pF 10 FEC 721-876 C23 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C24 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C25 Tantalum capacitor—Taj series 10 μF 20 V 10 FEC 197-427 C26 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 CS, DB0 to DB11 Red testpoint FEC 240-345 (Pack) J1 to J6 SMB socket FEC 310-682 J2 SMB socket FEC 310-682 J3 SMB socket FEC 310-682 J4 SMB socket FEC 310-682 J5 SMB socket FEC 310-682 J6 SMB socket FEC 310-682 LK1 3-pin header (2 × 2) FEC 511-791 and FEC 528-456 P1 36-pin Centronics connector FEC 147-753 P2 6-pin terminal block FEC 151-792 RW Red testpoint FEC 240-345 (Pack) TP1 to TP4 Red testpoint FEC 240-345 (Pack) U1 AD5447 AD5447YRU U2 ADR01 ADR01AR U3 AD8065 AD8065AR U4, U5 74ABT543 Fairchild 74ABT543CMTC U6 74139 CD74HCT139M U7 AD8065 AD8065AR Each Corner Rubber stick-on feet FEC 148-922 Rev. C | Page 27 of 32 AD5428/AD5440/AD5447 Data Sheet OVERVIEW OF AD54xx DEVICES Table 13. 1 Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. C | Page 28 of 32 Data Sheet AD5428/AD5440/AD5447 OUTLINE DIMENSIONS 7.90 7.80 7.70 6.60 6.50 6.40 24 13 4.50 20 11 4.40 4.50 4.30 4.40 6.40 BSC 4.30 1 12 6.40 BSC 1 10 PIN 1 0.65 PIN 1 1.20 BSC MAX 0.65 0.15 BSC 0.05 1.20 MAX 0.15 0.20 8° 0.75 0.05 0.09 0.75 0° 0.30 0.60 8° 0.20 0.60 SEATING 0.30 0.19 0.45 0° PLANE 0.45 0.09 COPLANARITY 0.19 SEATING 0.10 COPLANARITY 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 51. 20-Lead Thin Shrink Outline Package [TSSOP] Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) (RU-24) Dimensions shown in millimeters Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution INL (LSB) Temperature Range Package Description Package Option AD5428YRU 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5428YRU-REEL 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5428YRU-REEL7 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL7 8 ±0.5 –40 °C to +125°C 20-Lead TSSOP RU-20 AD5440YRU 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5440YRU-REEL 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5440YRU-REEL7 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ 10 ±0.5 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL7 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5447YRU 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5447YRU-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL7 12 ±1 –40 °C to +125°C 24-Lead TSSOP RU-24 EVAL-AD5447EBZ Evaluation Kit 1 Z = RoHS Compliant Part. Rev. C | Page 29 of 32 AD5428/AD5440/AD5447 Data Sheet NOTES Rev. C | Page 30 of 32 Data Sheet AD5428/AD5440/AD5447 NOTES Rev. C | Page 31 of 32 AD5428/AD5440/AD5447 Data Sheet NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04462-0-8/11(C) Rev. C | Page 32 of 32