ANALOG DEVICES AD5425

8-Bit, High Bandwidth Multiplying DAC with Serial Interface AD5425 FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation 1 The AD5425 is a CMOS, 8-bit, current output digital-to- 50 MHz serial interface analog converter that operates from a 2.5 V to 5.5 V power 9.5 MSPS update rate supply, making it suitable for battery-powered applications and INL of ±0.25 LSB many other applications. 10 MHz multiplying bandwidth This DAC utilizes a double buffered, 3-wire serial interface that ±10 V reference input is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP Low glitch energy: <2 nV-s Extended temperature range: −40°C to +125°C interface standards. An LDAC pin is also provided, which 10-lead MSOP package allows simultaneous updates in a multi-DAC configuration. On Guaranteed monotonic power-up, the internal shift register and latches are filled with 4-quadrant multiplication 0s and the DAC outputs are 0 V. Power-on reset with brownout detection As a result of manufacturing on a CMOS submicron process, LDAC function this DAC offers excellent 4-quadrant multiplication charac- 0.4 μA typical power consumption teristics with large signal multiplying bandwidths of 10 MHz. APPLICATIONS The applied external reference input voltage (V ) determines REF Portable battery-powered applications the full-scale output current. An integrated feedback resistor, Waveform generators RFB, provides temperature tracking and full-scale voltage output Analog processing when combined with an external I-to-V precision amplifier. Instrumentation applications The AD5425 is available in a small, 10-lead MSOP package. Programmable amplifiers and attenuators Digitally controlled calibration 1 U.S. Patent No. 5,969,657 Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V V DD REF R AD5425 R FB I 1 8-BIT OUT R-2R DAC I 2 OUT DAC REGISTER LDAC POWER-ON RESET INPUT LATCH SYNC CONTROL LOGIC AND SCLK INPUT SHIFT REGISTER SDIN GND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 03161-001 AD5425 TABLE OF CONTENTS Specifications..................................................................................... 3 Adding Gain................................................................................ 17 Timing Characteristics..................................................................... 5 DACs Used as a Divider or Programmable Gain Element ... 17 Absolute Maximum Ratings............................................................ 6 Reference Selection .................................................................... 17 ESD Caution.................................................................................. 6 Amplifier Selection .................................................................... 18 Pin Configuration and Function Descriptions............................. 7 Serial Interface ............................................................................ 19 Typical Performance Characteristics ............................................. 8 Microprocessor Interfacing....................................................... 19 Terminology .................................................................................... 13 PCB Layout and Power Supply Decoupling................................ 22 Theory of Operation ...................................................................... 14 Evaluation Board........................................................................ 22 Circuit Operation ....................................................................... 14 Operating the Evaluation Board .............................................. 22 Single-Supply Applications ....................................................... 16 Outline Dimensions ....................................................................... 27 Positive Output Voltage ............................................................. 16 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/05—Rev. 0 to Rev. A Updated Format................................................................ Universal Changes to Specifications Section.................................................3 Added Figure 18, Figure 20, Figure 21........................................10 Change to Table 7 ..........................................................................18 2/04—Revision 0: Initial Version Rev. A | Page 2 of 28 AD5425 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±10 nA Data = 0x0000, T = 25°C, I 1 A OUT ±20 nA Data = 0x0000, T = −40°C to +125°C, IOUT 1 1 REFERENCE INPUT Reference Input Range ±10 V VREF Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C RFB Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF 1 DIGITAL INPUT/OUTPUT Input High Voltage, V 1.7 V IH Input Low Voltage, V 0.6 V IL Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 μA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, I 1 μA IL Input Capacitance 4 10 pF 1 DYNAMIC PERFORMANCE Reference Multiplying Bandwidth 10 MHz V = ±3.5 V, DAC loaded all 1s REF Output Voltage Settling Time VREF = ±3.5 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±1 mV 90 160 ns Measured to ±4 mV 55 110 ns Measured to ±16 mV 50 100 ns Digital Delay 40 75 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry VREF = 0 V Multiplying Feedthrough Error DAC latch loaded with all 0s. VREF = ±3.5 V 70 dB 1 MHz 48 dB 10 MHz Output Capacitance IOUT1 12 17 pF All 0s loaded 25 30 pF All 1s loaded I 2 22 25 pF All 0s loaded OUT 10 12 pF All 1s loaded Digital Feedthrough 0.1 nV-s Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p; all 1s loaded, f = 1 kHz Rev. A | Page 3 of 28 AD5425 Parameter Min Typ Max Unit Conditions/Comments Digital THD Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF 50 kHz fOUT 70 dB 20 kHz fOUT 73 dB Output Noise Spectral Density 25 nV√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 2 MHz , V = 3.5 V REF 50 kHz f 67 dB OUT 20 kHz fOUT 68 dB SFDR Performance (Narrow Band) Clock = 2 MHz, VREF = 3.5 V 50 kHz fOUT 73 dB 20 kHz f 75 dB OUT Intermodulation Distortion 79 dB f = 20 kHz, f = 25 kHz, clock = 2 MHz, 1 2 VREF = 3.5 V POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 μA Logic inputs = 0 V or VDD, T = −40°C to +125°C Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 1 Guaranteed by design and characterization, not subject to production test. Rev. A | Page 4 of 28 AD5425 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter VDD = 2.5 V to 5.5 V Unit Conditions/Comments f 50 MHz max Maximum clock frequency SCLK t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time 2 SYNC falling edge to SCLK falling edge setup time t4 13 ns min t 5 ns min Data setup time 5 t 3 ns min Data hold time 6 t 5 ns min SYNC rising edge to SCLK falling edge 7 t 30 ns min Minimum SYNC high time 8 t 0 ns min SCLK falling edge to LDAC falling edge 9 LDAC pulse width t10 12 ns min SCLK falling edge to LDAC rising edge t11 10 ns min 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by control bits of serial word. t 1 SCLK t t 2 3 t t 8 4 t 7 SYNC t 6 t 5 DIN DB7 DB0 t 10 t 9 1 LDAC t 11 2 LDAC NOTES: 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Timing Diagram Rev. A | Page 5 of 28 03161-002 AD5425 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only and functional operation of the device at these or V , R to GND −12 V to +12 V REF FB any other conditions above those listed in the operational IOUT1, IOUT2 to GND −0.3 V to VDD + 0.3 V sections of this specification is not implied. Exposure to 1 Logic Input and Output −0.3 V to VDD + 0.3 V absolute maximum rating conditions for extended periods may Operating Temperature Range affect device reliability. Only one absolute maximum rating may Extended Industrial (Y Version) −40°C to +125°C be applied at any one time. Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 10-lead MSOP 206°C/W 1 SYNC LDAC θJA Thermal Impedance Overvoltages at SCLK, , DIN, and are clamped by internal diodes. Current should be limited to the maximum ratings given. Lead Temperature, Soldering 300°C (10 secs) IR Reflow, Peak Temperature 235°C (<20 secs) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 28 AD5425 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I 1 1 10 R OUT FB I 2 2 9 V OUT REF AD5425 GND 3 8 V DD TOP VIEW SCLK 4 7 LDAC (Not to Scale) SDIN 5 6 SYNC Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 I 1 DAC Current Output. OUT 2 I 2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. OUT 3 GND Digital Ground Pin. 4 SCLK Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input. This device can accommodate clock rates of up to 50 MHz. 5 SDIN Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on each falling edge of the following 8 clocks. 7 LDAC Load DAC Input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively; if this line is held permanently low, an automatic update mode is selected whereby the DAC is updated after 8 SCLK falling edges with SYNC low. 8 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD 9 VREF DAC Reference Voltage Input Terminal. 10 RFB DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output. Rev. A | Page 7 of 28 03161-003 AD5425 TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.4 T = 25°C T = 25°C A A V = 5V V = 10V REF DD 0.15 V = 5V DD 0.2 0.10 MIN DNL 0.05 0 0 –0.2 –0.05 MAX DNL –0.10 –0.4 –0.15 –0.20 –0.6 0 50 100 150 200 250 23 45 67 89 10 CODE REFERENCE VOLTAGE Figure 4. INL vs. Code (8-Bit DAC) Figure 7. DNL vs. Reference Voltage 0.20 1.6 T = 25°C A V = 10V REF 0.15 1.4 V = 5V DD 0.10 1.2 I 1 V 5V OUT DD 0.05 1.0 0 0.8 –0.05 0.6 –0.10 0.4 I 1 V 3V OUT DD –0.15 0.2 –0.20 0 0 50 100 150 200 250 –40 –20 0 20 40 60 80 100 120 CODE TEMPERATURE (°C) Figure 5. DNL vs. Code (8-Bit DAC) Figure 8. IOUT1 Leakage Current vs. Temperature 0.3 5 V = 10V T = 25°C REF A V = 5V DD 4 0.2 3 MAX INL V = 5V DD 2 0.1 1 0 0 V = 2.5V DD –1 MIN INL –0.1 –2 –3 –0.2 –4 –0.3 –5 23 45 67 89 10 –60 –40 –20 0 20 40 60 80 100 120 140 REFERENCE VOLTAGE TEMPERATURE (°C) Figure 6. INL vs. Reference Voltage Figure 9. Gain Error vs. Temperature Rev. A | Page 8 of 28 INL (LSB) INL (LSB) INL (LSB) xxxxx-xxx 03161-005 03161-004 ERROR (mV) I LEAKAGE (nA) DNL (LSB) OUT 03161-009 03161-008 xxxxx-xxx AD5425 0.5 2.5 T = 25°C V = 5V A DD V = 0V V = 3V DD REF V = 0V REF 2.0 0.3 GAIN ERROR 1.5 MAX INL MAX DNL 0.1 1.0 –0.1 MIN DNL 0.5 MIN INL OFFSET ERROR –0.3 0 –0.5 –0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.5 1.0 1.5 2.0 2.5 V (V) V (V) BIAS BIAS Figure 10. Linearity vs. VBIAS Voltage Applied to IOUT2 Figure 13. Gain and Offset Errors vs. Voltage Applied to IOUT2 1.4 10.0 T = 25°C T = 25°C A A V = 3V V = 5V DD DD 1.2 V = 0V V = 2.5V REF 8.0 REF 1.0 6.0 0.8 GAIN ERROR 4.0 0.6 0.4 2.0 OFFSET ERROR OFFSET ERROR 0.2 0 0 –2.0 –0.2 GAIN ERROR –0.4 –4.0 0.5 1.0 1.5 0 0.5 1.0 1.5 2.0 2.5 V (V) V (V) BIAS BIAS Figure 11. Gain and Offset Errors vs. V Voltage Applied to I 2 Figure 14. Gain and Offset Errors vs. V Voltage Applied to I 2 BIAS OUT BIAS OUT 0.5 1.0 V = 5V T = 25°C DD A V = 0V V = 5V REF 0.8 DD V = 2.5V REF 0.3 0.6 MIN INL BIAS 0.4 MAX INL MAX DNL MAX INL BIAS 0.1 0.2 0 –0.1 –0.2 MAX DNL BIAS MIN DNL MIN INL –0.4 MIN DNL BIAS –0.3 –0.6 –0.8 –0.5 –1.0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 V (V) V (V) BIAS BIAS Figure 12. Linearity vs. VBIAS Voltage Applied to IOUT2 Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2 Rev. A | Page 9 of 28 LSBs VOLTAGE(mV) LSBs 03161-012 03161-011 03161-010 LSBs VOLTAGE (mV) VOLTAGE (mV) 03161-015 03161-014 03161-013 AD5425 0.7 0.060 T = 25°C V 5V, 0V REF A DD T = 25°C A NRG = 2.049nVs V = 0V REF 0.050 07xFF TO 0x800 0.6 AD8038 AMPLIFIER C = 1.8pF COMP 0.040 0.5 V = 5V DD V 3V, 0V REF DD 0.030 NRG = 0.088nVs 0.4 0x800 TO 0x7FF 0.020 V 3V, 0V REF DD 0.3 NRG = 1.877nVs 0.010 0x7FF TO 0x800 0.2 0 V = 2.5V DD 0.1 V 5V, 0V REF DD –0.010 V = 3V NRG = 0.119nVs, DD 0x800 TO 0x7FF 0 –0.020 0 1234 5 0 50 100 150 200 250 300 INPUT VOLTAGE (V) TIME (ns) Figure 19. Midscale Transition, V = 3.5 V REF Figure 16. Supply Current vs. Input Voltage 1.8 6 T = 25°C T = 25°C A A ALL ON 0 LOADING DB11 1.6 –6 ZS TO FS DB10 –12 DB9 1.4 –18 DB8 V IH –24 DB7 1.2 –30 DB6 –36 DB5 1.0 –42 V DB4 IL –48 DB3 0.8 –54 DB2 –60 DB1 0.6 –66 DB0 –72 T = 25°C A 0.4 –78 V = 5V DD V = ±3.5V –84 REF INPUT 0.2 –90 ALL OFF C = 1.8pF COMP –96 AD8083 AMPLIFIER 0 –102 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1k 10k 100k 1M 10M 100M VOLTAGE (V) FREQUENCY (Hz) Figure 17. Threshold Voltages vs. Supply Voltage Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code 0.2 3 V = ±0.15V, AD8038 C 1pF REF C V = ±2V, AD8038 C 1pF REF C 0 0 V = ±3.51V, AD8038 C 1.8pF REF C –0.2 V = ±2V, AD8038 C 1.47pF REF C –3 V = ±0.15V, AD8038 C 1.47pF REF C –0.4 –6 T = 25°C A –0.6 V = 5V DD V = ±3.5V T = 25°C REF A C = 1.8pF V = 5V COMP DD AD8083 AMPLIFIER AD8038 AMPLIFIER –0.8 –9 1 10 100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. Reference Multiplying Bandwidth—All 1s Loaded Figure 21. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor Rev. A | Page 10 of 28 GAIN (dB) THRESHOLD VOLTAGE (V) CURRENT (mA) 03161-018 03161-017 03161-016 GAIN (dB) GAIN (dB) OUTPUT VOLTAGE (V) 03161-021 03161-020 03161-019 AD5425 –60 0 T = 25°C T = 25°C A A V = 3V V = 5V –10 DD DD V = 3.5V p-p V = 3.5V REF REF –65 –20 AD8038 AMPLIFIER –30 –70 –40 –50 –75 –60 –70 –80 –80 –90 –85 –100 –90 –110 1 10 100 1k 10k 100k 1M 0 200k 400k 600k 800k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. THD and Noise vs. Frequency Figure 25. Wideband SFDR, Clock = 2 MHz, fOUT = 20 kHz 20 0 T = 25°C V = 3V DD A V = 5V AMPLIFIER = AD8038 –10 DD V = 3.5V 0 REF –20 AD8038 AMPLIFIER –30 –20 –40 –40 –50 –60 –60 FULL SCALE –70 –80 –80 ZERO SCALE –90 –100 –100 –120 –110 1 10 100 1k 10k 100k 1M 10M 10k 12k 14k 16k 18k 20k 22k 24k 26k 28k 30k FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Power Supply Rejection vs. Frequency Figure 26. Narrowband SFDR, Clock = 2 MHz, fOUT = 20 kHz 0 0 T = 25°C A T = 25°C A V = 5V DD –10 V = 5V –10 DD V = 3.5V REF V = 3.5V REF AD8038 AMPLIFIER –20 –20 AD8038 AMPLIFIER –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 0 200k 400k 600k 800k 1M 25k 30k 35k 40k 45k 50k 55k 60k 65k 70k 75k FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Wideband SFDR, Clock = 2 MHz, f = 50 kHz OUT Figure 27. Narrowband SFDR, Clock = 2 MHz, fOUT = 50 kHz Rev. A | Page 11 of 28 SFDR (dB) POWER SUPPLY REJECTION THD + N (dB) 03161-024 03161-023 03161-022 SFDR (dB) SFDR (dB) SFDR (dB) 03161-027 03161-026 03161-025 AD5425 0 V = 5V DD V = 3.5V REF –10 AD8038 AMPLIFIER –20 –30 –40 –50 –60 –70 –80 –90 –100 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) Figure 28. Narrowband IMD (±50%) Clock = 2 MHz, f 1 = 20 kHz, f 2 = 25 kHz OUT OUT Rev. A | Page 12 of 28 IMD (dB) 03161-028 AD5425 TERMINOLOGY Relative Accuracy Digital Feedthrough Relative accuracy or endpoint nonlinearity is a measure of the When the device is not selected, high frequency logic activity maximum deviation from a straight line passing through the on the device digital inputs can be capacitively coupled to show endpoints of the DAC transfer function. It is measured after up as noise on the IOUT pins and subsequently into the following adjusting for zero and full scale and is normally expressed in circuitry. This noise is digital feedthrough. LSBs or as a percentage of full-scale reading. Multiplying Feedthrough Error Differential Nonlinearity This is the error due to capacitive feedthrough from the DAC Differential nonlinearity is the difference between the measured reference input to the DAC I 1 terminal, when all 0s are OUT change and the ideal 1 LSB change between any two adjacent loaded to the DAC. codes. A specified differential nonlinearity of −1 LSB maximum Total Harmonic Distortion (THD) over the operating temperature range ensures monotonicity. The DAC is driven by an ac reference. The ratio of the rms sum Gain Error of the harmonics of the DAC output to the fundamental value is Gain error or full-scale error is a measure of the output error the THD. Usually only the lower order harmonics are included, between an ideal DAC and the actual device output. For these such as second to fifth. DACs, ideal maximum output is V − 1 LSB. Gain error of the REF 2 2 2 2 DACs is adjustable to 0 with external resistance. (V +V +V +V ) 2 3 4 5 THD= 20 log V 1 Output Leakage Current Output leakage current is current that flows in the DAC ladder Digital Intermodulation Distortion switches when these are turned off. For the IOUT1 terminal, it Second-order intermodulation distortion (IMD) measurements can be measured by loading all 0s to the DAC and measuring are the relative magnitude of the fa and fb tones generated the I 1 current. Minimum current flows in the I 2 line OUT OUT digitally by the DAC and the second-order products at 2fa − fb when the DAC is loaded with all 1s. and 2fb − fa. Output Capacitance Spurious-Free Dynamic Range (SFDR) Capacitance from I 1 or I 2 to AGND. OUT OUT SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the mea- Output Current Settling Time sure of the difference in amplitude between the fundamental This is the amount of time it takes for the output to settle to a and the largest harmonically or nonharmonically related spur specified level for a full-scale input change. For these devices, it from dc to full Nyquist bandwidth (half the DAC sampling rate, is specified with a 100 Ω resistor to ground. or fS/2). Narrow band SFDR is a measure of SFDR over an The settling time specification includes the digital delay from arbitrary window size, in this case 50% of the fundamental. rising edge to the full-scale output charge. SYNC Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Rev. A | Page 13 of 28 AD5425 THEORY OF OPERATION The AD5425 is an 8-bit current output DAC consisting of a where D is the fractional representation of the digital word standard inverting R-2R ladder configuration. A simplified loaded to the DAC, in this case 0 to 255, and n is the number diagram is shown in Figure 29. The feedback resistor, RFB, has a of bits. value of R. The value of R is typically 10 kΩ (minimum 8 kΩ Note that the output voltage polarity is opposite to the VREF and maximum 12 kΩ). If I 1 and I 2 are kept at the same OUT OUT polarity for dc reference voltages. potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented This DAC is designed to operate with either negative or positive at V is always constant and nominally of value R. The DAC REF reference voltages. The V power pin is used by only the inter- DD output, IOUT, is code-dependent, producing various resistances nal digital logic to drive the DAC switches’ on and off states. and capacitances. When choosing the external amplifier, take into account the variation in impedance generated by the DAC This DAC is also designed to accommodate ac reference input on the amplifiers inverting input node. signals in the range of −10 V to +10 V. R R R With a fixed 10 V reference, the circuit shown in Figure 30 gives V REF a unipolar 0 V to −10 V output voltage swing. When VIN is an ac 2R 2R 2R 2R 2R signal, the circuit performs 2-quadrant multiplication. S1 S2 S3 S8 R R FB I 1 OUT Table 5 shows the relationship between digital code and the I 2 OUT expected output voltage for unipolar operation. DAC DATA LATCHES AND DRIVERS Table 5. Unipolar Code Table Digital Input Analog Output (V) Figure 29. Simplified Ladder 1111 1111 −V (255/256) REF Access is provided to the V , R , I 1, and I 2 terminals of REF FB OUT OUT 1000 0000 −VREF (128/256) = −VREF/2 the DAC, making the device extremely versatile and allowing it 0000 0001 −V (1/256) REF to be configured in several different operating modes, for exam- 0000 0000 −V (0/256) = 0 REF ple, to provide a unipolar output, bipolar output, or in single- supply modes of operation in unipolar mode or 4-quadrant V multiplication in bipolar mode. Note that a matching switch is R2 DD used in series with the internal R feedback resistor. If users FB C1 attempt to measure R , power must be applied to V to FB DD V R DD FB achieve continuity. I 1 OUT A1 V V A1 AD5425 REF REF R1 I 2 V = 0 OUT OUT CIRCUIT OPERATION TO –V REF SYNC SCLK SDIN GND Unipolar Mode Using a single op amp, this device can easily be configured to MICROCONTROLLER AGND provide 2-quadrant multiplying operation or a unipolar output NOTES: voltage swing, as shown in Figure 30. 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. When an output amplifier is connected in unipolar mode, the output voltage is given by Figure 30. Unipolar Operation D V =− V × OUT REF n 2 Rev. A | Page 14 of 28 03161-029 03161-030 AD5425 R3 20kΩ R5 V R2 20kΩ DD C1 V R DD FB R4 I 1 10kΩ OUT A1 V V A1 AD5425 REF REF I 2 OUT R1 A2 ±10V SYNC SCLK SDIN GND V =–V OUT REF TO +V REF MICROCONTROLLER AGND NOTES: 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0 V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 31. Bipolar Operation (4-Quadrant Multiplication) Bipolar Operation Stability In some applications, it may be necessary to generate full 4- In the I-to-V configuration, the IOUT of the DAC and the quadrant multiplying operation or a bipolar output swing. This inverting node of the op amp must be connected as closely as can be easily accomplished by using another external amplifier possible and proper PCB layout techniques must be employed. and some external resistors, as shown in Figure 31. In this Since every code change corresponds to a step function, gain circuit, the second amplifier, A2, provides a gain of 2. Biasing peaking can occur if the op amp has limited GBP and there is the external amplifier with an offset from the reference voltage, excessive parasitic capacitance at the inverting node. This results in full 4-quadrant multiplying operation. The transfer parasitic capacitance introduces a pole into the open-loop function of this circuit shows that both negative and positive response, which can cause ringing or instability in closed-loop output voltages are created as the input data, D, is incremented applications. from code zero (V = −V ) to midscale (V = 0 V ) to full OUT REF OUT An optional compensation capacitor, C1, can be added in scale (V = +V ). OUT REF parallel with R for stability, as shown in Figure 30 and Figure FB −1 n 31. Too small a value of C1 can produce ringing at V =() V × D/2 −V REF REF OUT the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to Where D is the fractional representation of the digital word 2 pF is generally adequate for compensation. loaded to the DAC and n is the resolution of the DAC. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. Table 6. Bipolar Code Table Digital Input Analog Output (V) 1111 1111 +VREF (127/128) 1000 0000 0 0000 0001 −V (127/128) REF 0000 0000 −VREF (128/128) Rev. A | Page 15 of 28 03161-031 AD5425 V DD R1 R2 SINGLE-SUPPLY APPLICATIONS Current Mode Operation R V FB DD In the current mode circuit of Figure 32, I 2 and hence I 1 OUT OUT A1 V I 1 A1 V IN OUT OUT is biased positive by an amount applied to V . In this V BIAS REF I 2 OUT configuration, the output voltage is given by GND VOUT = [D × (RFB/RDAC) × (VBIAS − VIN)] + VBIAS NOTES: As D varies from 0 to 255, the output voltage varies from 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. VOUT = VBIAS to VOUT = 2VBIAS − VIN V DD Figure 33. Single-Supply Voltage Switching Mode Operation It is important to note that V is limited to low voltage because IN C1 V R DD FB the switches in the DAC ladder no longer have the same source I 1 OUT A1 drain drive voltage. As a result, their on resistance differs, which A1 V V V OUT IN REF I 2 OUT degrades the linearity of the DAC. GND VIN must also not go negative by more than 0.3 V, otherwise an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of the DAC multiplying capability is lost. V BIAS NOTES: POSITIVE OUTPUT VOLTAGE 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE Note that the output voltage polarity is opposite to the V REF REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is Figure 32. Single-Supply Current Mode Operation preferred over the output inversion through an inverting V should be a low impedance source capable of sinking and BIAS amplifier because of the resistor tolerance errors. To generate a sourcing all possible variations in current at the I 2 terminal OUT negative reference, the reference can be level shifted by an without any problems. op amp such that the VOUT and GND pins of the reference become the virtual ground and −2.5 V respectively, as shown It is important to note that VIN is limited to low voltages because in Figure 34. the switches in the DAC ladder no longer have the same source- drain drive voltage. As a result, their on resistance differs and V = 5V DD ADR03 this degrades the linearity of the DAC. V V OUT IN GND Voltage Switching Mode of Operation +5V C1 V R DD FB Figure 33 shows this DAC operating in the voltage switching I 1 OUT –2.5V mode. The reference voltage VIN is applied to the IOUT1 pin, V REF I 2 IOUT2 is connected to AGND, and the output voltage is available OUT V = 0V TO +2.5V OUT GND at the VREF terminal. In this configuration, a positive reference –5V voltage results in a positive output voltage, making single- NOTES: supply operation possible. The output from the DAC is voltage 1 ADDITIONAL PINS OMITTED FOR CLARITY. 2 at a constant impedance (the DAC ladder resistance), thus an C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. op amp is necessary to buffer the output voltage. The reference input no longer sees constant input impedance, but one that Figure 34. Positive Voltage Output with Minimum of Components varies with code. So, the voltage input should be driven from a low impedance source. Rev. A | Page 16 of 28 03161-032 03161-033 04588-033 AD5425 V DD ADDING GAIN V IN In applications where the output voltage is required to be R V FB DD greater than VIN, gain can be added with an additional external I 1 V amplifier or it can be achieved in a single stage. It is important OUT REF to take into consideration the effect of temperature coefficients GND of the thin film resistors of the DAC. Simply placing a resistor in series with the R resistor causes mismatches in the temp- FB erature coefficients and results in larger gain temperature V OUT coefficient errors. Instead, the circuit of Figure 35 is a recom- mended method of increasing the gain of the circuit. R1, R2, NOTE: and R3 should all have similar temperature coefficients, but 1. ADDITIONAL PINS OMITTED FOR CLARITY. they need not match the temperature coefficients of the DAC. Figure 36. Current Steering DAC Used as a Divider or This approach is recommended in circuits where gains of Programmable Gain Element greater than 1 are required. DAC leakage current is also a potential error source in divider V DD circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. C1 V R DD FB Since only a fraction, D, of the current into the VREF terminal is I 1 OUT R1 A1 V routed to the IOUT1 terminal, the output voltage has to change V V IN REF OUT I 2 OUT R3 as follows: GND GAIN = R2 + R3 R2 Output Error Voltage Due to DAC Leakage = (Leakage × R)/D R2 R1 = R2R3 where R is the DAC resistance at the V terminal. For a DAC REF R2 + R3 NOTES: leakage current of 10 nA, R = 10 kΩ. With a gain (that is, 1/D) 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED of 16 the error voltage is 1.6 mV. IF A1 IS A HIGH SPEED AMPLIFIER. REFERENCE SELECTION Figure 35. Increasing the Gain of Current Output DAC When selecting a reference for use with the AD5425 current DACS USED AS A DIVIDER OR PROGRAMMABLE output DAC, pay attention to the reference’s output voltage GAIN ELEMENT temperature coefficient specification. This parameter not only Current steering DACs are very flexible and lend themselves to affects the full-scale error, but can also affect the linearity (INL many different applications. If this type of DAC is connected as and DNL) performance. The reference temperature coefficient the feedback element of an op amp and RFB is used as the input should be consistent with the system accuracy specifications. resistor as shown in Figure 36, then the output voltage is For example, an 8-bit system required to hold its overall inversely proportional to the digital input fraction, D. specification to within 1 LSB over the temperature range 0°C to 50°C dictates that the maximum system drift with temperature −n For D = 1 − 2 , the output voltage is should be less than 78 ppm/°C. A 12-bit system with the same −n temperature range to overall specification within 2 LSB requires V = −V /D = −V /(1 − 2 ) OUT IN IN a maximum drift of 10 ppm/°C. By choosing a precision As D is reduced, the output voltage increases. For small values reference with a low output temperature coefficient, this error of D, it is important to ensure that the amplifier does not satur- source can be minimized. Table 7 suggests some of the ate and that the required accuracy is met. For example, an 8-bit references available from Analog Devices that are suitable for DAC driven with the Binary Code 0x10 (00010000), that is, 16 use with this range of current output DACs. decimal, in the circuit of Figure 36, should cause the output voltage to be 16 × VIN. However, if the DAC has a linearity specification of ±0.5 LSB, then D can in fact have a weight anywhere in the range 15.5/256 to 16.5/256. Therefore, the possible output voltage is in the range of 15.5 V to 16.5 V — IN IN an error of 3%, even though the DAC itself has a maximum error of 0.2%. Rev. A | Page 17 of 28 03161-035 03161-036 AD5425 Common-mode rejection of the op amp is important in voltage AMPLIFIER SELECTION switching circuits, since it produces a code dependent error at The primary requirement for the current-steering mode is an the voltage output of the circuit. Most op amps have adequate amplifier with low input bias currents and low input offset vol- common-mode rejection for use at an 8-bit resolution. tage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of Provided the DAC switches are driven from true wideband low the DAC) of the circuit. A change in this noise gain between impedance sources (VIN and AGND), they settle quickly. Conse- two adjacent digital fractions produces a step change in the quently, the slew rate and settling time of a voltage switching output voltage due to the amplifier’s input offset voltage. This DAC circuit is determined largely by the output op amp. To output voltage change is superimposed on the desired change in obtain minimum settling time in this configuration, it is impor- output between the two codes and gives rise to a differential tant to minimize capacitance at the V node (voltage output REF linearity error, which if large enough, could cause the DAC to node in this application) of the DAC. This is done by using low be nonmonotonic. inputs capacitance buffer amplifiers and careful board design. The input bias current of an op amp also generates an offset at Most single-supply circuits include ground as part of the analog the voltage output as a result of the bias current flowing in the signal range, which in turns requires an amplifier that can . Most op amps have input bias currents feedback resistor, RFB handle rail-to-rail signals. There is a large range of single-supply low enough to prevent any significant errors. amplifiers available from Analog Devices. Table 7. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Precision ADI Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) VOS (Max) (μV) IBB (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable High Speed ADI Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IBB (Max) (nA) Package AD8065 5 to 24 145 180 1500 6000 SOIC-8, SOT-23,MSOP AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8 Rev. A | Page 18 of 28 AD5425 1 1 ADSP-2191 AD5425 SERIAL INTERFACE SPIxSEL SYNC The AD5425 has a simple 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. MOSI SDIN Data is written to the device in 8-bit words. This 8-bit word SCK SCLK consists of 8 data bits, as shown in Figure 37. DB7 (MSB) DB0 (LSB) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 ADDITIONAL PINS OMITTED FOR CLARITY. DATA BITS Figure 38. ADSP-2191 SPI-to-AD5425 Interface Figure 37. 8-Bit Input Shift Register Contents A serial interface between the DAC and DSP SPORT is shown in Figure 39. In this interface example, SPORT0 is used to SYNC is an edge-triggered input that acts as a frame synchro- transfer data to the DAC shift register. Transmission is initiated nization signal and chip enable. Data can be transferred into the by writing a word to the Tx register after the SPORT has been device only while is low. To start the serial data transfer, SYNC enabled. In a write sequence, data is clocked out on each rising SYNC should be taken low, observing the minimum SYNC edge of the DSP’s serial clock and clocked into the DAC input falling to SCLK falling edge setup time, t . 4 shift register on the falling edge of its SCLK. The update of the DAC output takes place on the rising edge of the SYNC signal. After loading eight data bits to the shift register, the line SYNC is brought high. The contents of the DAC register and the 1 ADSP-2101/ AD5425 output are updated by bringing LDAC low any time after the ADSP-2103/ 1 TFS SYNC 8-bit data transfer is complete, as seen in the timing diagram of ADSP-2191 Figure 2. can be tied permanently low if required. For LDAC DT SDIN another serial transfer to take place, the interface must be SCLK SCLK enabled by another falling edge of . SYNC Low Power Serial Interface 1 ADDITIONAL PINS OMITTED FOR CLARITY. To minimize the power consumption of the device, the interface fully powers up only when the device is being written to, that is, Figure 39. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5425 Interface on the falling edge of . The SCLK and SDIN input buffers SYNC Communication between two devices at a given clock speed is are powered down on the rising edge of SYNC. possible when the following specifications from one device to the other are compatible: frame sync delay and frame sync setup MICROPROCESSOR INTERFACING and hold, data delay and data setup and hold, and SCLK width. Microprocessor interfacing to this DAC is via a serial bus that The DAC interface expects a t (SYNC falling edge to SCLK 4 uses standard protocol compatible with microcontrollers and falling edge setup time) of 13 ns minimum. Consult the ADSP- DSP processors. The communications channel is a 3-wire inter- 21xx user manual for information on clock and frame sync face consisting of a clock signal, a data signal, and a synchro- frequencies for the SPORT register. nization signal. An pin is also included. The AD5425 LDAC Table 10. SPORT Control Register Setup requires an 8-bit word with the default being data valid on the Name Setting Description falling edge of SCLK, but this is changeable via the control bits TFSW 1 Alternate framing in the data-word. INVTFS 1 Active low frame signal ADSP-21xx-to AD5425 Interface DTYPE 00 Right-justify data The ADSP-21xx family of DSPs is easily interfaced to this ISCLK 1 Internal serial clock family of DACs without extra glue logic. Figure 38 shows an TFSR 1 Frame every word example of an SPI interface between the DAC and the ADSP- ITFS 1 Internal framing signal 2191. SCK of the DSP drives the serial data line, DIN. SYNC is SLEN 0111 8-bit data-word driven from one of the port lines, in this case . SPIxSEL Rev. A | Page 19 of 28 03161-037 03161-039 03161-038 AD5425 ADSP-BF5xx-to-AD5425 Interface 80C51/80L51-to-AD5425 Interface The ADSP-BF5xx family of processors has an SPI-compatible A serial interface between the DAC and the 8051 is shown in port that enables the processor to communicate with SPI- Figure 42. TxD of the 8051 drives SCLK of the DAC serial compatible devices. A serial interface between the ADSP-BF5xx interface, while RxD drives the serial data line, DIN. P3.3 is a bit- and the AD5425 DAC is shown in Figure 40. In this configura- programmable pin on the serial port that drives SYNC. When tion, data is transferred through the MOSI (master output/slave data is transmitted to the switch, P3.3 is taken low. The 80C51/ input) pin. is driven by the SPI chip select pin, which is a SYNC 80L51 transmits data in 8-bit bytes, which fits the AD5425 since reconfigured programmable flag pin. it only requires an 8-bit word. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the 1 1 ADSP-BF5xx AD5425 falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P3.3 is taken high at the SPIxSEL SYNC completion of this cycle. The 8051 provides the LSB of its SBUF MOSI SDIN register as the first bit in the data stream. The DAC input reg- SCK SCLK ister requires that the MSB is the first bit received. The transmit routine should take this into account. 1 ADDITIONAL PINS OMITTED FOR CLARITY. 1 1 8051 AD5425 TxD SCLK Figure 40. ADSP-BF5xx-to-AD5425 Interface The ADSP-BF5xx processor incorporates channel synchronous RxD SDIN serial ports (SPORT). A serial interface between the DAC and P1.1 SYNC the DSP SPORT is shown in Figure 41. When the SPORT is enabled, initiate transmission by writing a word to the Tx register. The data is clocked out on each rising edge of the DSP’s 1 ADDITIONAL PINS OMITTED FOR CLARITY. serial clock and clocked into the DAC’s input shift register on Figure 42. 80C51/80L51-to-AD5425 Interface the falling edge of its SCLK. The DAC output is updated by using the transmit frame synchronization (TFS) line to provide MC68HC11 Interface-to-AD5425 Interface a signal. SYNC Figure 43 shows an example of a serial interface between the DAC and the MC68HC11 microcontroller. The serial 1 1 ADSP-BF5xx AD5425 peripheral interface (SPI) on the MC68HC11 is configured for TFS SYNC master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by DT SDIN writing to the SPI control register (SPCR) (see the MC68HC11 SCLK SCLK user manual). SCK of the MC68HC11 drives the SCLK of the DAC interface, the MOSI output drives the serial data line, D , IN of the AD5425. The signal is derived from a port line, SYNC 1 ADDITIONAL PINS OMITTED FOR CLARITY. PC7. When data is being transmitted to the AD5425, the SYNC Figure 41. ADSP-BF5xx-to-AD5425 Interface line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the MC68HC11 is transmitted in 8-bit bytes with only 8 falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. PC7 is taken high at the end of the write. 1 1 MC68HC11 AD5425 PC7 SYNC SCK SCLK MOSI SDIN 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 43. 68HC11/68L11-to-AD5425 Interface Rev. A | Page 20 of 28 03161-041 03161-040 03161-043 03161-042 AD5425 MICROWIRE-to-AD5425 Interface PIC16C6x/7x-to-AD5425 Figure 44 shows an interface between the DAC and any The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is MICROWIRE™-compatible device. Serial data is shifted out on done by writing to the synchronous serial port control register the falling edge of the serial clock, SK, and is clocked into the (SSPCON) (see the PIC16/17 microcontroller user manual). In DAC input shift register on the rising edge of SK, which this example, I/O Port RA1 is being used to provide a SYNC corresponds to the falling edge of the DAC’s SCLK. signal and enable the DAC serial port. This microcontroller 1 1 AD5425 MICROWIRE transfers eight bits of data during each serial transfer operation. Figure 45 shows the connection diagram. SK SYNC SO SCLK 1 1 AD5425 PIC16C6x/7x CS SDIN SCK/RC3 SCLK SDI/RC4 SDIN 1 RA1 SYNC ADDITIONAL PINS OMITTED FOR CLARITY. Figure 44. MICROWIRE-to-AD5425 Interface 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 45. PIC16C6x/7x-to-AD5425 Interface Rev. A | Page 21 of 28 03161-044 03161-045 AD5425 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consider- It is good practice to employ compact, minimum lead length ation of the power supply and ground return layout helps to PCB layout design. Leads to the input should be as short as ensure the rated performance. The printed circuit board on possible to minimize IR drops and stray inductance. which the AD5425 is mounted should be designed so that the The PCB metal traces between VREF and RFB should also be analog and digital sections are separated and confined to matched to minimize gain error. To maximize high frequency certain areas of the board. If the DAC is in a system where performance, the I-to-V amplifier should be located as close to multiple devices require an AGND-to-DGND connection, the the device as possible. connection should be made at one point only. The star ground point should be established as close as possible to the device. EVALUATION BOARD The board consists of an 8-bit AD5425 and a current-to-voltage These DACs should have an ample supply bypassing of 10 μF in amplifier, the AD8065. Included on the evaluation board is a parallel with 0.1 μF on the supply and located as close to the 10 V reference, the ADR01. An external reference can also be package as possible—ideally up against the device. The 0.1 μF applied via an SMB input. capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as found in the common The evaluation kit consists of a CD-ROM with self-installing ceramic types that provide a low impedance path to ground at PC software to control the DAC. The software simply allows the high frequencies, to handle transient currents due to internal user to write a code to the device. logic switching. Low ESR, 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize OPERATING THE EVALUATION BOARD transient disturbance and to filter out low frequency ripple. Power Supplies The board requires ±12 V and 5 V supplies. The 12 V VDD and Fast switching signals such as clocks should be shielded with V are used to power the output amplifier, while the 5 V is used SS digital ground to avoid radiating noise to other parts of the to power the DAC (V ) and transceivers (V ). DD1 CC board and should never be run near the reference inputs. Both supplies are decoupled to their respective ground plane Avoid crossover of digital and analog signals. Traces on with 10 μF tantalum and 0.1 μF ceramic capacitors. opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the Link1 (LK1) is provided to allow selection between the on- board. A microstrip technique is by far the best, but not always board reference (ADR01) or an external reference applied possible with a double-sided board. In this technique, the through J2. Link2 should be connected to the LDAC position. component side of the board is dedicated to ground plane while signal traces are placed on the solder side. Rev. A | Page 22 of 28 4 AD5425 V DD1 R1 = 0Ω + C1 C2 SCLK 0.1μF 10μF C7 U1 SCLK J3 10μF 4 8 P1–3 SCLK V DD SDIN C5 V SDIN J4 4.7pF SS P1–2 5 SDIN R 10 FB C8 SYNC 0.1μF SYNC J5 V– TP1 P1–4 6 SYNC I 1 1 2 V OUT OUT SDO/LDAC 6 U3 AD8065AR LDAC J6 J1 3 P1–5 7 SDO/LDAC I 2 2 OUT 7 V+ C9 A LK2 V 10μF 3 REF B GND V DD V SDO REF P1–13 J2 V 9 REF C10 0.1μF P1–19 AD5425/AD5426/ P1–20 AD5432/AD5443 P1–21 LK1 P1–22 V DD P1–23 P1–24 P1–25 2 +V V 6 IN OUT P1–26 C3 C4 C5 U2 P1–27 10μF 0.1μF 0.1μF P1–28 ADR01AR V P1–29 DD 5 TRIM P1–30 GND P2–3 4 + C11 C12 0.1μF 10μF P2–2 AGND + C13 C14 0.1μF 10μF P2–1 V DD1 V SS P2–4 + C15 C16 0.1μF 10μF Figure 46. Schematic of the AD5425 Evaluation Board Rev. A | Page 23 of 28 + + 03161-046 AD5425 Figure 47. Component-Side Artwork P1 SCLK J3 C11 U3 SCLK J1 SDIN VOUT U1 J4 SDIN R1C6 SYNC C4 C1 C2 LK1 SYNC VREF U2 C3 SDO/LDAC J5 J2 VREF SDO/LDAC C16 C9 C14 J6 C15 C10 C13 P2 EVAL–AD5425EB Figure 48. Silkscreen—Component-Side View (Top Layer) Rev. A | Page 24 of 28 LK2 LDAC SDO VDD1 C8 VDD AGND TP1 VSS 03161-048 03161-047 AD5425 Figure 49. Solder-Side Artwork Rev. A | Page 25 of 28 03161-049 AD5425 Table 11. Overview of the AD54xx and AD55xx Devices Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width Rev. A | Page 26 of 28 AD5425 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.27 0.60 SEATING 0.23 0° 0.00 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 50. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Resolution INL Package Package Model (Bits) (LSBs) Temperature Range Description Branding Option AD5425YRM 8 ±0.25 −40°C to +125°C MSOP D1P RM-10 AD5425YRM-REEL 8 ±0.25 −40°C to +125°C MSOP D1P RM-10 AD5425YRM-REEL7 8 ±0.25 −40°C to +125°C MSOP D1P RM-10 EVAL-AD5425EB Evaluation Kit Rev. A | Page 27 of 28 AD5425 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03161-0-3/05(A) Rev. A | Page 28 of 28