ANALOG DEVICES AD5424

8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface Data Sheet AD5424/AD5433/AD5445 FEATURES GENERAL DESCRIPTION 1 2.5 V to 5.5 V supply operation The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit Fast parallel interface (17 ns write cycle) current output digital-to-analog converters (DACs), respectively. Update rate of 20.4 MSPS These devices operate from a 2.5 V to 5.5 V power supply, INL of ±1 LSB for 12-bit DAC making them suitable for battery-powered applications and 10 MHz multiplying bandwidth many other applications. These DACs utilize data readback, ±10 V reference input allowing the user to read the contents of the DAC register via Extended temperature range: –40°C to +125°C the DB pins. On power-up, the internal register and latches are 20-lead TSSOP and chip scale (4 mm × 4 mm) packages filled with 0s and the DAC outputs are at zero scale. 8-, 10-, and 12-bit current output DACs As a result of manufacturing with a CMOS submicron process, Upgrades to AD7524/AD7533/AD7545 they offer excellent 4-quadrant multiplication characteristics, Pin-compatible 8-, 10-, and 12-bit DACs in chip scale with large signal multiplying bandwidths of up to 10 MHz. Guaranteed monotonic The applied external reference input voltage (VREF) determines the 4-quadrant multiplication full-scale output current. An integrated feedback resistor (RFB) Power-on reset with brownout detection provides temperature tracking and full-scale voltage output Readback function when combined with an external I-to-V precision amplifier. 0.4 μA typical power consumption While these devices are upgrades of the AD5424/AD5433/ APPLICATIONS AD5445 in multiplying bandwidth performance, they have a Portable battery-powered applications latched interface and cannot be used in transparent mode. Waveform generators The AD5424 is available in small, 20-lead LFCSP and 16-lead Analog processing TSSOP packages, while the AD5433/AD5445 DACs are available Instrumentation applications in small, 20-lead LFCSP and TSSOP packages. Programmable amplifiers and attenuators Digitally controlled calibration The EVAL-AD5445SDZ evaluation board is available for Programmable filters and oscillators evaluating DAC performance. For more information, see the Composite video UG-333 evaluation board user guide. Ultrasound 1 Gain, offset, and voltage trimming U.S Patent No. 5,689,257. FUNCTIONAL BLOCK DIAGRAM V V DD REF R FB AD5424/ R AD5433/ I 1 OUT 8-/10-/12-BIT AD5445 R-2R DAC I 2 OUT POWER-ON DAC REGISTER RESET CS INPUT LATCH R/W GND DB0 DB7/DB9/DB11 DATA INPUTS Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03160-001 AD5424/AD5433/AD5445 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Operation ....................................................................... 18  Applications....................................................................................... 1  Bipolar Operation....................................................................... 19  General Description ......................................................................... 1  Single-Supply Applications ....................................................... 20  Functional Block Diagram .............................................................. 1  Positive Output Voltage............................................................. 20  Revision History ............................................................................... 2  Adding Gain................................................................................ 21  Specifications..................................................................................... 3  DACs Used as a Divider or Programmable Gain Element ... 21  Timing Characteristics..................................................................... 5  Reference Selection .................................................................... 22  Absolute Maximum Ratings............................................................ 6  Amplifier Selection .................................................................... 22  ESD Caution.................................................................................. 6  Parallel Interface......................................................................... 23  Pin Configurations and Function Descriptions ........................... 7  Microprocessor Interfacing....................................................... 23  Typical Performance Characteristics ........................................... 10  PCB Layout and Power Supply Decoupling................................ 24  Terminology................................................................................ 17  Outline Dimensions....................................................................... 25  Theory of Operation ...................................................................... 18  Ordering Guide .......................................................................... 26  REVISION HISTORY 12/12—Rev. B to Rev. C 3/05—Rev. 0 to Rev. A Changes to General Description Section ...................................... 1 Updated Format..................................................................Universal Added Note 2 to Table 1 .................................................................. 4 Changes to Specifications.................................................................4 Added EPAD Note to Table 4 and EPAD Note to Figure 4......... 7 Changes to Figure 49...................................................................... 17 Changes to Figure 50...................................................................... 18 Added EPAD Note to Table 5 and EPAD Note to Figure 6......... 8 Added EPAD Note to Table 6 and EPAD Note to Figure 8......... 9 Changes to Figure 51, Figure 52, and Figure 54 ......................... 19 Deleted the Evaluation Board for AD5424/AD5433/AD5445 Added Microprocessor Interfacing Section................................ 22 Section and Power Supplies for Evaluation Board Section....... 23 Added Figure 59 ............................................................................. 24 Deleted Figure 59; Renumbered Sequentially ............................ 24 Added Figure 60 ............................................................................. 25 Deleted Figure 60 and Figure 61................................................... 25 Changes to Ordering Guide .......................................................... 26 10/03—Initial Version: Revision 0 Deleted Figure 62 and Table 12; Renumbered Sequentially ..... 26 8/09—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 Rev. C | Page 2 of 28 Data Sheet AD5424/AD5433/AD5445 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions STATIC PERFORMANCE AD5424 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic AD5433 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5445 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±10 mV 1 Gain Error Temperature Coefficient ±5 ppm FSR/°C 1 Output Leakage Current ±10 nA Data = 0×0000, T = 25°C, I 1 A OUT ±20 nA Data = 0×0000, T = −40°C to +125°C, I 1 OUT 1 REFERENCE INPUT Reference Input Range ±10 V V Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C REF R Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C FB Input Capacitance Code Zero Scale 3 6 pF Code Full Scale 5 8 pF 1 DIGITAL INPUTS/OUTPUT Input High Voltage, VIH 1.7 V Input Low Voltage, V 0.6 V IL Output High Voltage, V V − 1 V V = 4.5 V to 5 V, I = 200 μA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 μA Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF 1 DYNAMIC PERFORMANCE Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s Output Voltage Settling Time V = ±3.5 V, R = 100 Ω, DAC latch REF LOAD alternately loaded with 0s and 1s Measured to ±16 mV of full scale 30 60 ns Measured to ±4 mV of full scale 35 70 ns Measured to ±1 mV of full scale 80 120 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall time, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V = 0 V REF Multiplying Feedthrough Error DAC latch loaded with all 0s, VREF = ±3.5 V 70 dB Reference = 1 MHz 48 dB Reference = 10 MHz Rev. C | Page 3 of 28 AD5424/AD5433/AD5445 Data Sheet Parameter Min Typ Max Unit Test Conditions Output Capacitance IOUT1 12 17 pF All 0s loaded 25 30 pF All 1s loaded I 2 22 25 pF All 0s loaded OUT 10 12 pF All 1s loaded Digital Feedthrough 1 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 81 dB VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Digital THD Clock = 10 MHz, VREF = 3.5 V 50 kHz f 65 dB OUT 2 Output Noise Spectral Density 25 nV√Hz @ 1 kHz SFDR Performance (Wide Band) AD5445, VREF = 3.5 V Clock = 10 MHz 500 kHz fOUT 55 dB 100 kHz f 63 dB OUT 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz fOUT 60 dB 50 kHz fOUT 62 dB SFDR Performance (Narrow Band) AD5445, V = 3.5 V REF Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50 kHz fOUT 82 dB Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz f 75 dB OUT 50 kHz fOUT 80 dB Intermodulation Distortion AD5445, VREF = 3.5 V Clock = 10 MHz f = 400 kHz, f = 500 kHz 65 dB 1 2 f = 40 kHz, f = 50 kHz 72 dB 1 2 Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz 51 dB f1 = 40 kHz, f2 = 50 kHz 65 dB POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD 0.4 5 μA Logic inputs = 0 V or V , T= −40°C to +125°C DD Power Supply Sensitivity 0.001 %/% ΔV = ±5% DD 1 Guaranteed by design, not subject to production test. 2 Specification measured with OP27. Rev. C | Page 4 of 28 Data Sheet AD5424/AD5433/AD5445 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter VDD = 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Test Conditions/Comments R/W to CS setup time t1 0 0 ns min t 0 0 ns min R/W to CS hold time 2 t 10 10 ns min CS low time (write cycle) 3 t4 6 6 ns min Data setup time t 0 0 ns min Data hold time 5 R/W high to CS low t6 5 5 ns min t7 9 7 ns min CS min high time t8 20 10 ns typ Data access time 40 20 ns max t9 5 5 ns typ Bus relinquish time 10 10 ns max 1 Guaranteed by design, not subject to production test. t t t 2 t 2 6 1 R/W t 7 t 3 CS t 4 t t 8 9 t 5 DATA DATA VALID DATA VALID Figure 2. Timing Diagram Rev. C | Page 5 of 28 03160-002 AD5424/AD5433/AD5445 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND –0.3 V to +7 V DD other conditions above those indicated in the operational V , R to GND –12 V to +12 V REF FB section of this specification is not implied. Exposure to absolute IOUT1, IOUT2 to GND –0.3 V to +7 V maximum rating conditions for extended periods may affect 1 Logic Inputs and Output –0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range Extended Industrial (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C ESD CAUTION Junction Temperature 150°C 16-Lead TSSOP θJA Thermal Impedance 150°C/W 20-Lead TSSOP θJA Thermal Impedance 143°C/W 20-Lead LFCSP θ Thermal Impedance 135°C/W JA Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 CS W Overvoltages at DBx, , and R/ , are clamped by internal diodes. Rev. C | Page 6 of 28 Data Sheet AD5424/AD5433/AD5445 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS I 1 1 16 R OUT FB 20 19 18 17 16 I 2 V OUT 2 15 REF 3 14 GND V DD GND 1 15 R/W PIN 1 DB7 4 13 R/W INDICATOR AD5424 DB7 CS 2 14 (Not to Scale) DB6 3 13 NC AD5424 DB6 CS 5 12 DB5 4 12 NC TOP VIEW DB4 5 11 NC DB5 6 11 DB0 (LSB) 7 10 DB4 DB1 6 78910 DB3 8 9 DB2 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 3. AD5424 Pin Configuration (TSSOP) Figure 4. AD5424 Pin Configuration (LFCSP) Table 4. AD5424 Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 19 IOUT1 DAC Current Output. 2 20 IOUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. 3 1 GND Ground. 4 to 11 2 to 9 DB7 to DB0 Parallel Data Bits 7 to 0. 10 to 13 NC No Internal Connection. 12 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. 13 15 R/W Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. 14 16 V Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DD 15 17 V DAC Reference Voltage Input Terminal. REF 16 18 RFB DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. Not applicable EPAD The exposed pad should be connected to ground. Rev. C | Page 7 of 28 03160-004 DB3 I 2 OUT DB2 I 1 OUT DB1 R FB DB0 V REF NC V DD 03160-005 AD5424/AD5433/AD5445 Data Sheet I 1 1 20 R OUT FB I 2 V 20 19 18 17 16 2 19 OUT REF GND 3 18 V DD GND 1 15 R/W PIN 1 4 DB9 17 R/W INDICATOR DB9 2 14 CS DB8 3 13 NC DB8 5 16 AD5433 CS AD5433 DB7 4 12 NC (Not to Scale) TOP VIEW DB6 5 11 DB7 6 15 NC DB0 DB6 7 14 NC 67 8910 DB5 8 13 DB0 (LSB) DB4 9 12 DB1 NOTES DB3 10 11 DB2 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE NC = NO CONNECT CONNECTED TO GROUND. Figure 5. AD5433 Pin Configuration (TSSOP) Figure 6. AD5433 Pin Configuration (LFCSP) Table 5. AD5433 Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 19 I 1 DAC Current Output. OUT 2 20 IOUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. 3 1 GND Ground. 4 to 13 2 to DB9 to Parallel Data Bits 9 to 0. 11 DB0 14, 15 12, 13 NC Not Internally Connected. 16 14 CS Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. 17 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. 18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 19 17 VREF DAC Reference Voltage Input Terminal. 20 18 R DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. FB Not applicable EPAD The exposed pad should be connected to ground. Rev. C | Page 8 of 28 03160-006 DB5 I 2 OUT DB4 I 1 OUT DB3 R FB DB2 V REF DB1 V DD 03160-007 Data Sheet AD5424/AD5433/AD5445 I 1 1 20 R OUT FB I 2 V OUT 2 19 REF 20 19 18 17 16 3 18 GND V DD GND R/W 1 PIN 1 15 DB11 4 17 R/W INDICATOR DB11 CS 2 14 DB10 DB10 3 13 DB0 5 16 CS AD5445 AD5445 DB9 4 12 DB1 (Not to Scale) TOP VIEW 6 DB9 15 DB0 (LSB) DB8 5 11 DB2 7 14 DB8 DB1 6 78910 DB7 8 13 DB2 DB6 9 12 DB3 NOTES DB5 10 11 DB4 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 7. AD5445 Pin Configuration (TSSOP) Figure 8. AD5445 Pin Configuration (LFCSP) Table 6. AD5445 Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 19 I 1 DAC Current Output. OUT 2 20 I 2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. OUT 3 1 GND Ground Pin. 4 to 15 2 to 13 DB11 to DB0 Parallel Data Bits 11 to 0. 16 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. 17 15 R/W Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. 18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 19 17 VREF DAC Reference Voltage Input Terminal. 20 18 RFB DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. Not applicable EPAD The exposed pad should be connected to ground. Rev. C | Page 9 of 28 03160-008 DB7 I 2 OUT DB6 I 1 OUT DB5 R FB DB4 V REF DB3 V DD 03160-009 AD5424/AD5433/AD5445 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 T = 25°C T = 25°C A A V = 10V V = 10V 0.15 REF REF 0.15 V = 5V V = 5V DD DD 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 9. INL vs. Code (8-Bit DAC) Figure 12. DNL vs. Code (8-Bit DAC) 0.5 0.5 T = 25°C T = 25°C A A 0.4 0.4 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 10. INL vs. Code (10-Bit DAC) Figure 13. DNL vs. Code (10-Bit DAC) 1.0 1.0 T = 25°C T = 25°C A A 0.8 0.8 V = 10V V = 10V REF REF V = 5V V = 5V DD DD 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 14. DNL vs. Code (12-Bit DAC) Figure 11. INL vs. Code (12-Bit DAC) Rev. C | Page 10 of 28 INL (LSB) INL (LSB) INL (LSB) 03160-012 03160-011 03160-010 DNL (LSB) DNL (LSB) DNL (LSB) 03160-015 03160-014 03160-013 Data Sheet AD5424/AD5433/AD5445 0.6 2.0 0.5 1.5 T = 25°C A 0.4 MAX INL V = 0V 1.0 REF V = 3V MAX INL DD 0.3 0.5 0.2 MAX DNL T = 25°C A 0 V = 5V DD 0.1 –0.5 0 MIN INL –1.0 MIN DNL –0.1 MIN INL –1.5 –0.2 –0.3 –2.0 27 34 5 68910 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 V (V) REFERENCE VOLTAGE BIAS Figure 15. INL vs. Reference Voltage, AD5445 Figure 18. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 –0.40 4 T = 25°C T = 25°C A A 3 V = 5V V = 2.5V REF DD –0.45 MAX DNL V = 3V DD 2 MAX INL –0.50 1 0 –0.55 –1 –0.60 –2 MIN DNL MIN INL MIN DNL –3 –0.65 –4 –0.70 –5 2 34 5 6 789 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 REFERENCE VOLTAGE V (V) BIAS Figure 16. DNL vs. Reference Voltage, AD5445 Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 5 0.5 T = 25°C 4 0.4 A V = 0V REF V = 3V AND 5V 3 0.3 DD V = 5V DD GAIN ERROR 0.2 2 1 0.1 0 0 V = 2.5V DD –0.1 –1 OFFSET ERROR –2 –0.2 –3 –0.3 V = 10V REF –4 –0.4 –5 –0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) V (V) BIAS Figure 20. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Figure 17. Gain Error vs. Temperature Rev. C | Page 11 of 28 DNL (LSB) ERROR (mV) INL (LSB) 03160-018 03160-016 03160-017 VOLTAGE (mV) LSB LSB 03160-021 03160-020 03160-019 AD5424/AD5433/AD5445 Data Sheet 0.5 8 0.4 7 0.3 6 0.2 GAIN ERROR 5 0.1 V = 5V DD 0 4 –0.1 OFFSET ERROR 3 –0.2 2 –0.3 T = 25°C A V = 3V DD V = 2.5V REF 1 –0.4 V = 3V AND 5V V = 2.5V DD DD –0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOLTAGE (V) V (V) BIAS Figure 21. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Figure 24. Supply Current vs. Logic Input Voltage (Driving DB0 to DB11, All Other Digital Inputs qt Supplies) 3 1.6 T = 25°C A MAX INL V = 0V REF 1.4 V = 5V DD 2 1.2 I V 5V OUT1 DD 1 1.0 MAX DNL I V 3V OUT1 DD 0 0.8 0.6 –1 0.4 –2 0.2 MIN INL MIN DNL –3 0 –40 –20 0 20 40 60 80 100 120 0.5 1.0 1.5 2.0 2.5 V (V) TEMPERATURE (°C) BIAS Figure 22. Linearity vs. V Voltage Applied to I 2, AD5445 Figure 25. I 1 Leakage Current vs. Temperature BIAS OUT OUT 4 0.50 T = 25°C A 3 V = 2.5V REF 0.45 V = 5V DD 0.40 2 MAX DNL V = 5V DD 0.35 1 ALL 0s 0.30 0 ALL 1s MAX INL 0.25 –1 0.20 V = 2.5V DD MIN DNL –2 0.15 ALL 1s ALL 0s –3 MIN INL 0.10 –4 0.05 –5 0 0.5 1.0 1.5 2.0 –60 –40 –20 0 20 40 60 80 100 120 140 V (V) BIAS TEMPERATURE (°C) Figure 23. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445 Figure 26. Supply Current vs. Temperature Rev. C | Page 12 of 28 LSB LSB VOLTAGE (mV) 03160-024 03160-023 03160-022 CURRENT (μA) I LEAKAGE (nA) CURRENT (mA) OUT 03160-027 03160-026 03160-025 Data Sheet AD5424/AD5433/AD5445 14 3 T = 25°C A T = 25°C A LOADING ZS TO FS V = 5V DD 12 AD5445 V = 5V DD 0 10 8 –3 6 V = 3V DD 4 –6 V = ±2V, AD8038 C 1.47pF REF C V = 2.5V DD V = ±2V, AD8038 C 1pF REF C 2 V = ±0.15V, AD8038 C 1pF REF C V = ±0.15V, AD8038 C 1.47pF REF C V = ±3.51V, AD8038 C 1.8pF REF C 0 –9 1 10 100 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Supply Current vs. Update Rate Figure 30. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 0.045 6 ALL ON 0x7FF TO 0x800 0 T = 25°C T = 25°C A A DB11 0.040 V = 0V –6 LOADING REF DB10 V = 5V DD AD8038 AMPLIFIER ZS TO FS –12 0.035 DB9 C = 1.8pF COMP –18 DB8 –24 0.030 DB7 –30 DB6 0.025 –36 V = 3V DB5 DD –42 0.020 DB4 –48 DB3 0.015 –54 DB2 0x800 TO 0x7FF –60 DB1 0.010 T = 25°C –66 A DB0 V = 3V DD V = 5V DD –72 0.005 V = ±3.5V REF –78 INPUT 0 –84 C = 1.8pF COMP –90 AD8038 AMPLIFIER ALL OFF –0.005 –96 AD5445 DAC V = 5V DD –102 –0.010 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code Figure 31. Midscale Transition, V = 0 V REF 0.2 –1.68 T = 25°C A 0x7FF TO 0x800 V = 3.5V –1.69 REF AD8038 AMPLIFIER V = 5V DD 0 C = 1.8pF COMP –1.70 –1.71 –0.2 –1.72 V = 3V DD –1.73 –0.4 V = 5V DD –1.74 T = 25°C A V = 3V DD V = 5V DD –1.75 –0.6 V = ±3.5V REF C = 1.8pF COMP –1.76 AD8038 AMPLIFIER 0x800 TO 0x7FF AD5445 DAC –0.8 –1.77 1 10 100 1k 10k 100k 1M 10M 100M 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) TIME (ns) Figure 29. Reference Multiplying Bandwidth—All 1s Loaded Figure 32. Midscale Transition, V = 3.5 V REF Rev. C | Page 13 of 28 GAIN (dB) GAIN (dB) I (mA) DD 03160-030 03160-029 03160-028 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) GAIN (dB) 03160-031 03160-033 03160-032 AD5424/AD5433/AD5445 Data Sheet 1.8 100 T = 25°C A MCLK = 1MHz 1.6 80 1.4 V IH 1.2 MCLK = 200kHz 60 1.0 V IL MCLK = 0.5MHz 0.8 40 0.6 0.4 T = 25°C 20 A V = 3.5V REF AD8038 AMPLIFIER 0.2 AD5445 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 20 40 60 80 100 120 140 160 180 200 VOLTAGE (V) f (kHz) OUT Figure 36. Wideband SFDR vs. f Frequency OUT Figure 33. Threshold Voltages vs. Supply Voltage 90 20 T = 25°C A 80 V = 3V DD 0 MCLK = 5MHz AMP = AD8038 70 MCLK = 10MHz –20 60 50 –40 MCLK = 25MHz 40 –60 30 FULL SCALE –80 20 T = 25°C ZERO SCALE A V = 3.5V REF –100 10 AD8038 AMPLIFIER AD5445 0 –120 0 100 200 300 400 500 600 700 800 900 1000 1 10 100 1k 10k 100k 1M 10M f (kHz) OUT FREQUENCY (Hz) Figure 37. Wideband SFDR vs. f Frequency OUT Figure 34. Power Supply Rejection vs. Frequency 0 –60 T = 25°C T = 25°C A A –10 V = 5V V = 3V DD DD AMP = AD8038 V = 3.5V p-p –65 REF AD5445 –20 65k CODES –30 –70 –40 –75 –50 –60 –80 –70 –85 –80 –90 –90 02 46 8 10 12 1 10 100 1k 10k 100k 1M FREQUENCY (MHz) FREQUENCY (Hz) Figure 38. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 35. THD and Noise vs. Frequency Rev. C | Page 14 of 28 THD + N (dB) PSRR (dB) THRESHOLD VOLTAGE (V) 03160-062 03160-035 03160-034 SFDR (dB) SFDR (dB) SFDR (dB) 03160-038 03160-037 03160-036 Data Sheet AD5424/AD5433/AD5445 0 20 T = 25°C T = 25°C A A –10 V = 3V V = 5V DD DD 0 AMP = AD8038 AMP = AD8038 –20 AD5445 AD5445 65k CODES 65k CODES –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –100 –90 –100 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (MHz) FREQUENCY (kHz) Figure 39. Wideband SFDR, f = 500 kHz, Clock = 10 MHz Figure 42. Narrow-Band SFDR, f = 100 kHz, MCLK = 25 MHz OUT OUT 0 0 T = 25°C T = 25°C A A = 5V –10 –10 V V = 3V DD DD AMP = AD8038 AMP = AD8038 AD5445 –20 AD5445 –20 65k CODES 65k CODES –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 200 250 300 350 400 450 500 550 600 650 700 FREQUENCY (MHz) FREQUENCY (kHz) Figure 40. Wideband SFDR, f = 50 kHz, Clock = 10 MHz Figure 43. Narrow-Band IMD, f = 400 kHz, 500 kHz, Clock = 10 MHz OUT OUT 0 0 T = 25°C T = 25°C A A –10 –10 V = 3V V = 3V DD DD AMP = AD8038 AMP = AD8038 –20 –20 AD5445 AD5445 65k CODES 65k CODES –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 250 300 350 400 450 500 550 600 650 700 750 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (kHz) FREQUENCY (kHz) Figure 41. Narrow-Band Spectral Response, f = 500 kHz, Clock = 25 MHz Figure 44. Narrow-Band IMD, f = 90 kHz, 100 kHz, Clock = 10 MHz OUT OUT Rev. C | Page 15 of 28 SFDR (dB) SFDR (dB) SFDR (dB) 03160-041 03160-040 03160-039 (dB) (dB) SFDR (dB) 03160-044 03160-043 03160-042 AD5424/AD5433/AD5445 Data Sheet 0 0 T = 25°C T = 25°C A A –10 –10 V = 5V V = 5V DD DD AMP = AD8038 AMP = AD8038 –20 –20 AD5445 AD5445 65k CODES 65k CODES –30 –30 –40 –40 –50 –50 –60 –60 MCLK 10MHz –70 V 5V –70 DD –80 –80 –90 –90 –100 –100 20 25 30 35 40 45 50 55 60 65 70 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 45. Narrow-Band IMD, f = 40 kHz, 50 kHz, Clock = 10 MHz Figure 47. Wideband IMD, f = 60 kHz, 50 kHz, Clock = 10 MHz OUT OUT 0 T = 25°C A –10 V = 5V DD AMP = AD8038 –20 AD5445 65k CODES –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) Figure 46. Wideband IMD, f = 90 kHz, 100 kHz, Clock = 25 MHz OUT Rev. C | Page 16 of 28 (dB) (dB) 03160-046 03160-045 (dB) 03160-047 Data Sheet AD5424/AD5433/AD5445 TERMINOLOGY Digital Feedthrough Relative Accuracy When the device is not selected, high frequency logic activity Relative accuracy or endpoint nonlinearity is a measure of the on the device digital inputs may be capacitively coupled maximum deviation from a straight line passing through the through the device to show up as noise on the I pins and OUT endpoints of the DAC transfer function. It is measured after subsequently in the following circuitry. This noise is called adjusting zero scale and full scale and is normally expressed in digital feedthrough. LSBs or as a percentage of full-scale reading. Multiplying Feedthrough Error Differential Nonlinearity This is the error due to capacitive feedthrough from the DAC Differential nonlinearity is the difference between the measured reference input to the DAC IOUT1 terminal when all 0s are change and the ideal 1 LSB change between any two adjacent loaded to the DAC. codes. A specified differential nonlinearity of –1 LSB maximum over the operating temperature range ensures monotonicity. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum Gain Error of the harmonics of the DAC output to the fundamental value is Gain error or full-scale error is a measure of the output error the THD. Usually only the lower order harmonics are included, between an ideal DAC and the actual device output. For these such as second to fifth. DACs, ideal maximum output is VREF – 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. 2 2 2 2 ( ) V +V +V +V 2 3 4 5 THD= 20 log Output Leakage Current V 1 Output leakage current is current that flows in the DAC ladder Digital Intermodulation Distortion switches when these are turned off. For the I 1 terminal, it OUT Second-order intermodulation distortion (IMD) measurements can be measured by loading all 0s to the DAC and measuring are the relative magnitude of the fa and fb tones generated the I 1 current. Minimum current flows in the I 2 line OUT OUT digitally by the DAC and the second-order products at 2fa − fb when the DAC is loaded with all 1s. and 2fb − fa. Output Capacitance Spurious-Free Dynamic Range (SFDR) Capacitance from IOUT1, or IOUT2, to AGND. SFDR is the usable dynamic range of a DAC before spurious Output Current Settling Time noise interferes or distorts the fundamental signal. It is measured This is the amount of time it takes for the output to settle to a by the difference in amplitude between the fundamental and the specified level for a full-scale input change. For these devices, it largest harmonically or nonharmonically related spur from dc is specified with a 100 Ω resistor to ground. to full Nyquist bandwidth (half the DAC sampling rate, or f /2). S The settling time specification includes the digital delay from Narrow-band SFDR is a measure of SFDR over an arbitrary the rising edge to the full-scale output change. CS window size, in this case, 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the Digital-to-Analog Glitch lmpulse signal is a digitally generated sine wave. The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA seconds or nV seconds, depending upon whether the glitch is measured as a current or voltage signal. Rev. C | Page 17 of 28 AD5424/AD5433/AD5445 Data Sheet THEORY OF OPERATION The AD5424, AD5433, and AD5445 are 8-, 10-, and 12-bit where D is the fractional representation of the digital word loaded current output DACs consisting of a standard inverting R-2R to the DAC and n is the resolution of the DAC. ladder configuration. A simplified diagram for the 8-bit AD5424 is D = 0 to 255 (8-bit AD5424) shown in Figure 48. The matching feedback resistor RFB has a = 0 to 1023 (10-bit AD5433) value of R. The value of R is typically 10 kΩ (minimum 8 kΩ = 0 to 4095 (12-bit AD5445) and maximum 12 kΩ). If I 1 and I 2 are kept at the same OUT OUT Note that the output voltage polarity is opposite to the V REF potential, a constant current flows in each ladder leg, regardless polarity for dc reference voltages. of digital input code. Therefore, the input resistance presented These DACs are designed to operate with either negative or positive at VREF is always constant and nominally of resistance value R. The DAC output (IOUT) is code-dependent, producing various reference voltages. The VDD power pin is only used by the internal resistances and capacitances. External amplifier choice should digital logic to drive the DAC switches’ on and off states. take into account the variation in impedance generated by the These DACs are also designed to accommodate ac reference DAC on the amplifiers inverting input node. input signals in the range of –10 V to +10 V. RR R V With a fixed 10 V reference, the circuit shown in Figure 49 gives REF 2R 2R 2R 2R 2R a unipolar 0 V to –10 V output voltage swing. When V is an ac IN S1 S2 S3 S8 R signal, the circuit performs 2-quadrant multiplication. R A FB I 1 OUT Table 7 shows the relationship between digital code and expected I 2 OUT output voltage for unipolar operation (AD5424, 8-bit device). DAC DATA LATCHES AND DRIVERS Table 7. Unipolar Code Table Figure 48. Simplified Ladder Digital Input Analog Output (V) Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of 1111 1111 –V (255/256) REF the DAC, making the device extremely versatile and allowing it 1000 0000 –VREF (128/256) = –VREF/2 to be configured in several different operating modes, for example, 0000 0001 VREF (1/256) to provide a unipolar output, 4-quadrant multiplication in bipolar 0000 0000 VREF (0/256) = 0 mode or in single-supply modes of operation. Note that a matching switch is used in series with the internal R feedback resistor. If FB V DD R2 users attempt to measure RFB, power must be applied to VDD to achieve continuity. C1 V R DD FB CIRCUIT OPERATION AD5424/ I 1 OUT V V A1 Unipolar Mode REF REF AD5433/ I 2 R1 OUT V = AD5445 OUT Using a single op amp, these devices can easily be configured to 0 TO –V REF R/W CS GND provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 49. AGND DATA When an output amplifier is connected in unipolar mode, the INPUTS output voltage is given by NOTES: 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. D 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED V =−V × OUT REF n IF A1 IS A HIGH SPEED AMPLIFIER. 2 Figure 49. Unipolar Operation Rev. C | Page 18 of 28 03160-048 03160-049 Data Sheet AD5424/AD5433/AD5445 R3 20kΩ V R2 DD R5 20kΩ V R C1 DD FB R4 R1 AD5424/ I 1 10kΩ OUT V REF V A1 REF AD5433/ ±10V I 2 OUT A2 AD5445 V =–V TO +V OUT REF REF GND R/W CS AGND DATA INPUTS NOTES: 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC. OUT 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 50. Bipolar Operation (4-Quadrant Multiplication) Stability BIPOLAR OPERATION In the I-to-V configuration, the I of the DAC and the inverting In some applications, it may be necessary to generate full OUT node of the op amp must be connected as closely as possible and 4-quadrant multiplying operation or a bipolar output swing. proper PCB layout techniques must be employed. Since every code This can be easily accomplished by using another external change corresponds to a step function, gain peaking may occur amplifier and some external resistors, as shown in Figure 50. if the op amp has limited GBP and there is excessive parasitic In this circuit, the second amplifier, A2, provides a gain of 2. capacitance at the inverting node. This parasitic capacitance Biasing the external amplifier with an offset from the reference introduces a pole into the open-loop response, which can cause voltage, results in full 4-quadrant multiplying operation. The ringing or instability in closed-loop applications. transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is An optional compensation capacitor, C1, can be added in parallel incremented from code zero (VOUT = –VREF) to midscale with R for stability, as shown in Figure 49 and Figure 50. Too FB (VOUT = 0 V) to full scale (VOUT = +VREF). small a value of C1 can produce ringing at the output, while too n−1 large a value can adversely affect the settling time. C1 should be V =() V × D/ 2 −V OUT REF REF found empirically, but 1 pF to 2 pF is generally adequate for where D is the fractional representation of the digital word compensation. loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-bit AD5424) = 0 to 1023 (10-bit AD5433) = 0 to 4095 (12-bit AD5445) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 8 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5424, 8-bit device). Table 8. Bipolar Code Table Digital Input Analog Output (V) 1111 1111 +VREF (127/128) 1000 0000 0 0000 0001 –V (127/128) REF 0000 0000 –V (128/128) REF Rev. C | Page 19 of 28 03160-050 AD5424/AD5433/AD5445 Data Sheet V DD SINGLE-SUPPLY APPLICATIONS R1 R2 Current Mode Operation R V FB DD The current mode circuit in Figure 51 shows a typical circuit for V IN I 1 A1 V OUT OUT operation with a single 2.5 V to 5 V supply. I 2 and therefore OUT V DAC REF I 2 OUT I 1 is biased positive by the amount applied to V . In this OUT BIAS GND configuration, the output voltage is given by NOTES: VOUT = [D × (RFB/RDAC) × (VBIAS − VIN)] + VBIAS 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED As D varies from 0 to 255 (AD5424), 0 to 1023 (AD5433), IF A1 IS A HIGH SPEED AMPLIFIER. or 0 to 4095 (AD5445), the output voltage varies from Figure 52. Single-Supply Voltage-Switching Mode Operation V = V to V = 2V − V OUT BIAS OUT BIAS IN It is important to note that V is limited to low voltages because IN V should be a low impedance source capable of sinking and BIAS the switches in the DAC ladder no longer have the same source- sourcing all possible variations in current at the I 2 terminal. OUT drain drive voltage. As a result, there on resistance differs, which V DD degrades the linearity of the DAC. See Figure 18 to Figure 23. Also, VIN must not go negative by more than 0.3 V; otherwise, an internal C1 V R DD FB diode turns on, exceeding the maximum ratings of the device. I 1 OUT In this type of application, the full range of multiplying capability V V IN REF DAC A1 I 2 OUT V OUT of the DAC is lost. GND POSITIVE OUTPUT VOLTAGE Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is V BIAS preferred over the output inversion through an inverting amplifier NOTES: because of the resistor tolerance errors. To generate a negative 1. ADDITIONAL PINS OMITTED FOR CLARITY reference, the reference can be level-shifted by an op amp such 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. that the VOUT and GND pins of the reference become the virtual ground and –2.5 V respectively, as shown in Figure 53. Figure 51. Single-Supply Current Mode Operation V = 5V DD It is important to note that V is limited to low voltages because IN ADR03 V V OUT IN the switches in the DAC ladder no longer have the same source- GND drain drive voltage. As a result, there on resistance differs and +5V C1 V R the linearity of the DAC degrades. DD FB I 1 OUT –2.5V Voltage Switching Mode of Operation V REF I 2 OUT V = 0V TO +2.5V OUT Figure 52 shows these DACs operating in the voltage-switching GND –5V mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available NOTES: 1 ADDITIONAL PINS OMITTED FOR CLARITY. at the VREF terminal. In this configuration, a positive reference 2 C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is a voltage at a Figure 53. Positive Voltage Output with Minimum of Components constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. Rev. C | Page 20 of 28 03160-051 03160-052 03160-053 Data Sheet AD5424/AD5433/AD5445 As D is reduced, the output voltage increases. For small values ADDING GAIN of D, it is important to ensure that the amplifier does not saturate In applications where the output voltage is required to be and that the required accuracy is met. greater than VIN, gain can be added with an additional external amplifier or it can be achieved in a single stage. It is important For example, in the circuit shown in Figure 55, an 8-bit DAC to consider the effect of the temperature coefficients of the thin driven with the binary code 0x10 (00010000), that is, 16 decimal, film resistors of the DAC. Simply placing a resistor in series with should cause the output voltage to be 16 × VIN. However, if the the R resistor causes mismatches in the temperature coefficients DAC has a linearity specification of ±0.5 LSB, then D can in fact FB have a weight anywhere in the range 15.5/256 to 16.5/256 so and results in larger gain temperature coefficient errors. Instead, that the possible output voltage falls in the range 15.5 V to the circuit shown in Figure 54 is a recommended method of IN 16.5 V —an error of 3% even though the DAC itself has a increasing the gain of the circuit. R1, R2, and R3 should have IN maximum error of 0.2%. similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is V DD V IN recommended in circuits where gains greater than 1 are required. R V FB DD V I 1 DD OUT V REF I 2 OUT GND C1 V R DD FB R1 I 1 8-/10-/12-BIT OUT V V IN OUT V DAC OUT V I 2 REF OUT R3 GND R2 + R3 GAIN = NOTE: R2 R2 ADDITIONAL PINS OMITTED FOR CLARITY NOTES: R2R3 R1 = 1. ADDITIONAL PINS OMITTED FOR CLARITY R2 + R3 Figure 55. Current-Steering DAC Used as a Divider or 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE Programmable Gain Element REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. DAC leakage current is also a potential error source in divider Figure 54. Increasing the Gain of the Current Output DAC circuits. The leakage current must be counterbalanced by an DACS USED AS A DIVIDER OR PROGRAMMABLE opposite current supplied from the op amp through the DAC. GAIN ELEMENT Since only a fraction, D, of the current into the V terminal is REF Current steering DACs are very flexible and lend themselves to routed to the I 1 terminal, the output voltage has to change OUT as follows: many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input Output Error Voltage due to DAC Leakage = (Leakage × R)/D resistor, as shown in Figure 55, then the output voltage is where R is the DAC resistance at the VREF terminal. inversely proportional to the digital input fraction, D. For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain –n For D = 1 – 2 the output voltage is (that is, 1/D) of 16, the error voltage is 1.6 mV. –n V = –V /D = –V /(1 − 2 ) OUT IN IN Rev. C | Page 21 of 28 03160-054 03160-055 AD5424/AD5433/AD5445 Data Sheet Table 9. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 10. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 11. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW at ACL (MHz) Slew Rate (V/μs) V (Max) (μV) I (Max) (nA) Package OS B AD8065 5 to 24 145 180 1500 6000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8 AMPLIFIER SELECTION REFERENCE SELECTION The primary requirement for the current-steering mode is an When selecting a reference for use with the AD5424/AD5433/ amplifier with low input bias currents and low input offset AD5445 family of current output DACs, pay attention to the voltage. The input offset voltage of an op amp is multiplied by reference’s output voltage temperature coefficient specification. the variable gain (due to the code dependent output resistance This parameter not only affects the full-scale error, but can also of the DAC) of the circuit. A change in the noise gain between affect the linearity (INL and DNL) performance. The reference two adjacent digital fractions produces a step change in the output temperature coefficient should be consistent with the system voltage due to the amplifier’s input offset voltage. This output accuracy specifications. For example, an 8-bit system required voltage change is superimposed on the desired change in output to hold its overall specification to within 1 LSB over the between the two codes and gives rise to a differential linearity temperature range 0°C to 50°C dictates that the maximum error, which, if large enough, could cause the DAC to be non- system drift with temperature should be less than 78 ppm/°C. monotonic. In general, the input offset voltage should be <1/4 A 12-bit system with the same temperature range to overall LSB to ensure monotonic behavior when stepping through codes. specification within 2 LSBs requires a maximum drift of The input bias current of an op amp also generates an offset at 10 ppm/°C. By choosing a precision reference with low output the voltage output as a result of the bias current flowing into the temperature coefficient this error source can be minimized. feedback resistor, RFB. Most op amps have input bias currents Table 9 suggests some references available from Analog Devices low enough to prevent significant errors in 12-bit applications. that are suitable for use with this range of current output DACs. Common-mode rejection of the op amp is important in voltage- switching circuits, since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common mode rejection for use at 8-, 10-, and 12-bit resolution. Rev. C | Page 22 of 28 Data Sheet AD5424/AD5433/AD5445 Provided the DAC switches are driven from true wideband 8xC51-to-AD5424/AD5433/AD5445 Interface low impedance sources (V and AGND), they settle quickly. IN Figure 57 shows the interface between the AD5424/AD5433/ Consequently, the slew rate and settling time of a voltage AD5445 and the 8xC51 family of DSPs. To facilitate external switching DAC circuit is determined largely by the output op data memory access, the address latch enable (ALE) mode is amp. To obtain minimum settling time in this configuration, it enabled. The low byte of the address is latched with this output is important to minimize capacitance at the VREF node (voltage pulse during access to external memory. AD0 to AD7 are the output node in this application) of the DAC. This is done by using multiplexed low order addresses and data bus and require low inputs capacitance buffer amplifiers and careful board design. strong internal pull-ups when emitting 1s. During access to external memory, A8 to A15 are the high order address bytes. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle Since these ports are open drained, they also require strong rail-to-rail signals. There is a large range of single-supply internal pull-ups when emitting 1s. amplifiers available from Analog Devices. A8 TO A15 ADDRESS BUS PARALLEL INTERFACE Data is loaded to the AD5424/AD5433/AD5445 in the format AD5424/ 8051* AD5433/ of an 8-, 10-, or 12-bit parallel word. Control lines and R/ CS W AD5445* ADDRESS CS allow data to be written to or read from the DAC register. A DECODER write event takes place when CS and R/W are brought low, data WR R/W available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word DB0 TO DB11 8-BIT ALE to the DAC register. The DAC latches are not transparent, thus LATCH a write sequence must consist of a falling and rising edge on CS AD0 TO AD7 DATA BUS to ensure that data is loaded to the DAC register and its analog equivalent is reflected on the DAC output. *ADDITIONAL PINS OMITTED FOR CLARITY A read event takes place when R/W is held high and CS is Figure 57. 8xC51-to-AD5424/AD5433/AD5445 Interface brought low. New data is loaded from the DAC register back to ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface the input register and out onto the data line where it can be read Figure 58 shows a typical interface between the AD5424/ back to the controller for verification or diagnostic purposes. AD5433/AD5445 and the ADSP-BF5xx family of DSPs. The MICROPROCESSOR INTERFACING asynchronous memory write cycle of the processor drives the ADSP-21xx-to-AD5424/AD5433/AD5445 Interface digital inputs of the DAC. The AMSx line is actually four memory Figure 56 shows the AD5424/AD5433/AD5445 interfaced to , these select lines. Internal ADDR lines are decoded into AMS3-0 the ADSP-21xx series of DSPs as a memory-mapped device. A lines are then inserted as chip selects. The rest of the interface is single wait state may be necessary to interface the AD5424/ a standard handshaking operation. AD5433/AD5445 to the ADSP-21xx, depending on the clock ADDR TO 1 ADDRESS BUS speed of the DSP. The wait state can be programmed via the ADRR 19 data memory wait state control register of the ADSP-21xx AD5424/ (see the ADSP-21xx family user’s manual for details). ADSP-BF5xx AD5433/ AD5445* ADDR TO 0 ADDRESS BUS ADDRESS AMSx ADRR CS 13 DECODER AD5424/ AWE R/W ADSP-21xx* AD5433/ AD5445* DB0 TO DB11 ADDRESS DMS CS DECODER WR R/W DATA 0 TO DATA BUS DATA 23 DB0 TO DB11 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 58. ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface DATA 0 TO DATA BUS DATA 23 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 56. ADSP21xx-to-AD5424/AD5433/AD5445 Interface Rev. C | Page 23 of 28 03160-056 03160-057 03160-063 AD5424/AD5433/AD5445 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of Fast switching signals such as clocks should be shielded with the power supply and ground return layout helps to ensure the digital ground to avoid radiating noise to other parts of the rated performance. The printed circuit board on which the board and should never be run near the reference inputs. AD5424/AD5433/AD5445 is mounted should be designed so Avoid crossover of digital and analog signals. Traces on opposite that the analog and digital sections are separated and confined sides of the board should run at right angles to each other. This to certain areas of the board. If the DAC is in a system where reduces the effects of feedthrough through the board. A micro- multiple devices require an AGND-to-DGND connection, the strip technique is by far the best, but not always possible with a connection should be made at one point only. The star ground double-sided board. In this technique, the component side of point should be established as close as possible to the device. the board is dedicated to the ground plane, while signal traces These DACs should have ample supply bypassing of 10 μF in are placed on the solder side. parallel with 0.1 μF on the supply, located as close to the package It is good practice to employ compact, minimum lead length as possible and ideally right up against the device. The 0.1 μF PCB layout design. Leads to the input should be as short as capacitor should have low effective series resistance (ESR) and possible to minimize IR drops and stray inductance. effective series inductance (ESI), like the common ceramic types The PCB metal traces between V and R should also be REF FB that provide a low impedance path to ground at high frequencies, matched to minimize gain error. To maximize high frequency to handle transient currents due to internal logic switching. Low performance, the I-to-V amplifier should be located as close to ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be the device as possible. applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Table 12. Overview of AD54xx and AD55xx Devices Part No. Resolution No. DACs INL(LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width Rev. C | Page 24 of 28 Data Sheet AD5424/AD5433/AD5445 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 59. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 8° 0.60 0.30 0° 0.45 COPLANARITY 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 60. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. C | Page 25 of 28 AD5424/AD5433/AD5445 Data Sheet 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 16 20 1 PIN 1 0.50 2.25 3.75 EXPOSED INDICATOR BSC BCS SQ PAD 2.10 SQ (BOTTOM VIEW) 1.95 5 10 6 11 0.75 0.25 MIN TOP VIEW 0.60 0.50 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.30 SEATING 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 61. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution (Bits) INL (LSB) Temperature Range Package Description Package Option AD5424YRU 8 ±0.25 −40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRU-REEL 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRU-REEL7 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ-REEL 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YRUZ-REEL7 8 ±0.25 –40°C to +125°C 16-Lead TSSOP RU-16 AD5424YCPZ 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5424YCPZ-REEL7 8 ±0.25 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5433YRU 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRU-REEL 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRU-REEL7 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ-REEL 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YRUZ-REEL7 10 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5433YCPZ 10 ±0.5 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 AD5445YRU 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRU-REEL 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRU-REEL7 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ-REEL 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YRUZ-REEL7 12 ±1 –40°C to +125°C 20-Lead TSSOP RU-20 AD5445YCPZ 12 ±1 –40°C to +125°C 20-Lead LFCSP_VQ CP-20-1 EVAL-AD5445EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 26 of 28 PIN 1 INDICATOR 012508-B Data Sheet AD5424/AD5433/AD5445 NOTES Rev. C | Page 27 of 28 AD5424/AD5433/AD5445 Data Sheet NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03160-0-12/11(C) Rev. C | Page 28 of 28