ANALOG DEVICES AD5415

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface Data Sheet AD5415 FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth 1 The AD5415 is a CMOS, 12-bit, dual-channel, current output On-chip 4-quadrant resistors allow flexible output ranges digital-to-analog converter. This device operates from a 2.5 V to INL of ±1 LSB 5.5 V power supply, making it suited to battery-powered appli- 24-lead TSSOP package cations and other applications. As a result of being manufactured 2.5 V to 5.5 V supply operation on a CMOS submicron process, this part offers excellent 4- ±10 V reference input quadrant multiplication characteristics, with large-signal 50 MHz serial interface multiplying bandwidths of 10 MHz. 2.47 MSPS update rate The applied external reference input voltage (V ) determines REF Extended temperature range: −40°C to 125°C the full-scale output current. An integrated feedback resistor (R ) FB 4-quadrant multiplication provides temperature tracking and full-scale voltage output when Power-on reset combined with an external current-to-voltage precision amplifier. 0.5 µA typical current consumption In addition, this device contains the 4-quadrant resistors necessary Guaranteed monotonic for bipolar operation and other configuration modes. Daisy-chain mode Readback function This DAC uses a double-buffered, 3-wire serial interface that is APPLICATIONS compatible with SPI®, QSPI™, MICROWIRE™, and most DSP Portable battery-powered applications interface standards. In addition, a serial data out pin (SDO) allows Waveform generators daisy-chaining when multiple packages are used. Data readback Analog processing allows the user to read the contents of the DAC register via the Instrumentation applications SDO pin. On power-up, the internal shift register and latches Programmable amplifiers and attenuators are filled with 0s, and the DAC outputs are at zero scale. Digitally controlled calibration The AD5415 DAC is available in a 24-lead TSSOP package. The Programmable filters and oscillators EVAL-AD5415/AD5449SDZ evaluation board is available for Composite video evaluating DAC performance. For more information, see the Ultrasound UG-296 evaluation board user guide. Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM R3A R2_3A R2A V A R1A REF R3 R2 2R 2R R R1 FB AD5415 2R 2R V DD R A FB SYNC I 1A OUT SHIFT INPUT DAC 12-BIT SCLK R-2R DAC A REGISTER REGISTER REGISTER I 2A SDIN OUT SDO LDAC I 1B OUT INPUT DAC 12-BIT REGISTER REGISTER R-2R DAC B I 2B OUT POWER-ON CLR RESET R B FB R1 R GND FB 2R R3 R2 2R 2R 2R R3B R2_3B R2B V B R1B REF Figure 1. 1 U.S. Patent Number 5,689,257. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.461.3113© 2004–2012 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 04461-001 AD5415 Data Sheet TABLE OF CONTENTS Specifications ..................................................................................... 3 Adding Gain ................................................................................ 17 Timing Characteristics ................................................................ 5 Divider or Programmable Gain Element ................................ 17 Absolute Maximum Ratings ............................................................ 7 Reference Selection .................................................................... 18 ESD Caution .................................................................................. 7 Amplifier Selection .................................................................... 18 Pin Configuration and Function Descriptions ............................. 8 Serial Interface ............................................................................ 20 Typical Performance Characteristics ............................................. 9 Microprocessor Interfacing ....................................................... 22 Terminology .................................................................................... 14 PCB Layout and Power Supply Decoupling ........................... 24 General Description ....................................................................... 15 Overview of AD54xx Devices ....................................................... 25 DAC Section ................................................................................ 15 Outline Dimensions ....................................................................... 26 Circuit Operation ....................................................................... 15 Ordering Guide .......................................................................... 26 Single-Supply Applications ....................................................... 16 REVISION HISTORY Change to Figure 32 ....................................................................... 15 5/12—Rev. C to Rev. D Changes to Table 5 and Table 6..................................................... 15 Changes SDO Control (SDO1 and SDO2) Section ................... 20 Change to Stability Section ........................................................... 16 6/11—Rev. B to Rev. C Changes to Voltage-Switching Mode of Operation Section ..... 16 Changes to General Description ................................................... 1 Change to Figure 35 ....................................................................... 16 Deleted Evaluation Board for the DAC Section and Power Changes to Divider or Programmable Gain Element Section .... 17 Supplies for the Evaluation Board Section .................................. 24 Changes to Figure 36 Through Figure 38.................................... 17 Changes to Ordering Guide .......................................................... 26 Changes to Table 7 Through Table 10 ......................................... 19 Added ADSP-BF5xx-to-AD5415 Interface Section ................... 22 4/10—Rev. A to Rev. B Change to 80C51/80L51-to-AD5415 Interface Section ............ 23 Added Figure 4 .................................................................................. 6 Change to MC68HC11-to-AD5415 Interface Section .............. 23 Change to Power Supplies for the Evaluation Board Section ... 24 7/05—Rev. 0 to Rev. A Changes to Table 13 ....................................................................... 28 Changes to Features List .................................................................. 1 Updated Outline Dimensions ....................................................... 29 Change to General Description ...................................................... 1 Changes to Ordering Guide .......................................................... 29 Changes to Specifications ................................................................ 3 Changes to Timing Characteristics ................................................ 5 7/04—Revision 0: Initial Version Change to Figure 8 and Figure 9..................................................... 9 Change to Figure 13 ....................................................................... 10 Change to Figure 27 Through Figure 29 ..................................... 12 Rev. D | Page 2 of 28 Data Sheet AD5415 1 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Bipolar Zero Code Error ±25 mV Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, IOUT1 ±15 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1 REFERENCE INPUT Reference Input Range ±10 V VREFA, VREFB Input Resistance 8 10 13 kΩ Input resistance TC = −50 ppm/°C V A-to-V B Input Resistance 1.6 2.5 % Typ = 25°C, max = 125°C REF REF Mismatch R1, R Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C FB R2, R3 Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C R2-to-R3 Resistance Mismatch 0.06 0.18 % Typ = 25°C, max = 125°C Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5.5 V, ISOURCE = 200 µA V − 0.5 V V = 2.5 V to 3.6 V, I = 200 µA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 µA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 µA DD SINK Input Leakage Current, IIL 1 µA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying BW 10 MHz VREF = ±3.5 V p-p, DAC loaded all 1s Output Voltage Settling Time RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns 10% to 90% Settling Time 15 30 ns Rise and fall times Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V = 0 V REF Multiplying Feedthrough Error DAC latches loaded with all 0s, V = ±3.5 V REF 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Rev. D | Page 3 of 28 AD5415 Data Sheet Parameter Min Typ Max Unit Conditions Digital Feedthrough 3 5 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V =3. 5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz fOUT 61 dB 50 kHz fOUT 66 dB SFDR Performance (Wide Band) VREF = 3.5 V Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz fOUT 65 dB Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz f 60 dB OUT 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) V = 3.5 V REF Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz f 80 dB OUT 50 kHz f 87 dB OUT Clock = 25 MHz 500 kHz fOUT 70 dB 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion V = 3.5 V REF f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 µA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD Power Supply Sensitivity 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization, not subject to production test. Rev. D | Page 4 of 28 Data Sheet AD5415 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 2 Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCLK 50 MHz max Maximum clock frequency t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t 8 ns min SCLK low time 3 SYNC falling edge to SCLK falling edge setup time t4 13 ns min t5 5 ns min Data setup time t6 4 ns min Data hold time t 5 ns min SYNC rising edge to SCLK falling edge 7 Minimum SYNC high time t8 30 ns min SCLK falling edge to LDAC falling edge t9 0 ns min pulse width t10 12 ns min LDAC t 10 ns min SCLK falling edge to LDAC rising edge 11 3 t12 25 ns min SCLK active edge to SDO valid, strong SDO driver 60 ns min SCLK active edge to SDO valid, weak SDO driver Update Rate 2.47 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 5. t 1 SCLK t t 2 3 t 4 t 8 t 7 SYNC t 6 t 5 DB15 DB0 DIN t 10 t 9 1 LDAC t 11 2 LDAC 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. NOTES ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram Rev. D | Page 5 of 28 04461-002 AD5415 Data Sheet t 1 SCLK t t 2 3 t 7 t 4 SYNC t 6 t 8 t 5 DB15 DB0 DB15 DB0 SDIN (N) (N) (N + 1) (N + 1) t 12 DB0 DB15 SDO (N) (N) NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON THE FALLING EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram SCLK 16 32 SYNC DB15 DB0 DB15 DB0 SDIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB15 DB0 SDO SELECTED REGISTER DATA UNDEFINED CLOCKED OUT Figure 4. Readback Mode Timing Diagram 200µA I OL V (MIN) + V (MAX) OH OL TO OUTPUT 2 PIN C L 50pF 200µA I OH Figure 5. Load Circuit for SDO Timing Specifications Rev. D | Page 6 of 28 04461-004 04461-003 04461-053 Data Sheet AD5415 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any VREF, RFB to GND −12 V to +12 V other conditions above those indicated in the operational IOUT1, IOUT2 to GND −0.3 V to +7 V section of this specification is not implied. Exposure to absolute Input Current to Any Pin Except Supplies ±10 mA maximum rating conditions for extended periods may affect 1 Logic Inputs and Output −0.3 V to V + 0.3 V DD device reliability. Operating Temperature Range Extended (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 24-Lead TSSOP, θJA Thermal Impedance 128°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 7 of 28 AD5415 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I 1A 1 24 I 1B OUT OUT 2 23 I 2A I 2B OUT OUT 3 22 R A R B FB FB 4 21 R1A R1B 5 20 R2A R2B AD5415 R2_3A 6 19 R2_3B TOP VIEW (Not to Scale) R3A 7 18 R3B V A 8 17 V B REF REF GND 9 16 V DD 10 15 LDAC CLR 11 14 SCLK SYNC 12 13 SDIN SDO Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 I 1A DAC A Current Output. OUT 2 IOUT2A DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 3 RFBA DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output. 4 to 7 R1A, R2A, DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with R2_3A, R3A minimum external components. 8 VREFA DAC A Reference Voltage Input Pin. 9 GND Ground Pin. 10 LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode. 11 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 12 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. 13 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin; they are clocked out on the next 16 opposite clock edges to the active clock edge. 14 SYNC Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and SDIN buffers, and the input shift register is enabled. Data is loaded into the shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 15 Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user CLR to enable the hardware CLR pin as a clear to zero scale or midscale as required. 16 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. 17 VREFB DAC B Reference Voltage Input Pin. 18 to 21 R3B, R2_3B, DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with R2B, R1B a minimum of external components. 22 RFBB DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external amplifier output. 23 IOUT2B DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 24 I 1B DAC B Current Output. OUT Rev. D | Page 8 of 28 04461-005 Data Sheet AD5415 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 –0.40 T = 25°C A T = 25°C A 0.8 V = 5V DD V = 10V REF V = 5V –0.45 DD 0.6 0.4 –0.50 0.2 0 –0.55 –0.2 –0.60 –0.4 MIN DNL –0.6 –0.65 –0.8 –1.0 –0.70 0 500 1000 1500 2000 2500 3000 3500 4000 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE Figure 7. INL vs. Code (12-Bit DAC) Figure 10. DNL vs. Reference Voltage 5 1.0 T = 25°C A 4 0.8 V = 10V REF V = 5V DD V = 5V DD 3 0.6 2 0.4 1 0.2 0 0 V = 2.5V DD –1 –0.2 –2 –0.4 –3 –0.6 V = 10V REF –4 –0.8 –5 –1.0 –60 –40 –20 0 20 40 60 80 100 120 140 0 500 1000 1500 2000 2500 3000 3500 4000 TEMPERATURE (°C) CODE Figure 11. Gain Error vs. Temperature Figure 8. DNL vs. Code (12-Bit DAC) 0.6 8 T = 25°C A 0.5 7 0.4 6 MAX INL 0.3 5 V = 5V DD 0.2 4 T = 25°C A V = 5V 0.1 DD 3 0 MIN INL 2 –0.1 V = 3V DD 1 –0.2 V = 2.5V DD 0 –0.3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 3 4 5 6 7 8 9 10 0 0.5 1.0 INPUT VOLTAGE (V) REFERENCE VOLTAGE Figure 12. Supply Current vs. Logic Input Voltage Figure 9. INL vs. Reference Voltage Rev. D | Page 9 of 28 INL (LSB) DNL (LSB) INL (LSB) 04461-008 04461-007 04461-006 DNL (LSB) ERROR (mV) CURRENT (mA) 04461-011 04461-010 04461-009 AD5415 Data Sheet 1.6 6 T = 25C ALL ON A 0 LOADING DB11 –6 1.4 ZS TO FS DB10 –12 DB9 –18 1.2 DB8 –24 I 1 V = 5V DB7 OUT DD –30 DB6 1.0 –36 DB5 –42 DB4 0.8 –48 DB3 –54 I 1 V = 3V OUT DD DB2 –60 0.6 DB1 –66 DB0 –72 0.4 T = 25C –78 A V = 5V DD –84 V =3.5V 0.2 REF –90 ALL OFF C =1.8pF COMP –96 AMP = AD8038 0 –102 –40 –20 0 20 40 60 80 100 120 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) TEMPERATURE (°C) Figure 13. I 1 Leakage Current vs. Temperature Figure 16. Reference Multiplying Bandwidth vs. Frequency and Code out 0.50 0.2 0.45 V = 5V DD 0.40 0 0.35 ALL 0s 0.30 –0.2 ALL 1s 0.25 V = 2.5V DD 0.20 –0.4 0.15 ALL 1s ALL 0s T = 25°C A 0.10 –0.6 V = 5V DD V =3.5V REF 0.05 C = 1.8pF COMP AMP = AD8038 0 –0.8 –60 –40 –20 0 20 40 60 80 100 120 140 1 10 100 1k 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 17. Reference Multiplying Bandwidth—All Ones Loaded Figure 14. Supply Current vs. Temperature 3 14 T = 25°C A T = 25°C A V = 5V DD LOADING ZS TO FS 12 V = 5V 0 DD 10 8 –3 6 V = 3V DD 4 V =2V, AD8038 C 1.47pF REF C –6 V = 2.5V V =2V, AD8038 C 1pF DD REF C V =0.15V, AD8038 C 1pF REF C 2 V =0.15V, AD8038 C 1.47pF REF C V =3.51V, AD8038 C 1.8pF REF C –9 0 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Supply Current vs. Update Rate Figure 18. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor Rev. D | Page 10 of 28 I (mA) CURRENT (A) I 1 LEAKAGE (nA) DD OUT 04461-014 04461-013 04461-012 GAIN (dB) GAIN (dB) GAIN (dB) 04461-017 04461-015 04461-016 Data Sheet AD5415 –60 0.045 0x7FF TO 0x800 T = 25°C T = 25°C A A 0.040 V = 0V V = 3V REF DD V = 5V DD AMP = AD8038 V = 3.5V p-p REF –65 0.035 C = 1.8pF COMP 0.030 –70 0.025 V = 3V DD 0.020 –75 0.015 0x800 TO 0x7FF 0.010 –80 V = 3V DD 0.005 0 –85 –0.005 V = 5V DD –0.010 –90 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) TIME (ns) Figure 19. Midscale Transition, V = 0 V Figure 22. THD and Noise vs. Frequency REF 100 –1.68 T = 25°C A 0x7FF TO 0x800 MCLK = 1MHz V = 3.5V –1.69 REF AMP = AD8038 V = 5V DD 80 C = 1.8pF COMP –1.70 –1.71 60 MCLK = 200kHz –1.72 MCLK = 0.5MHz V = 3V DD –1.73 40 V = 5V DD –1.74 V = 3V DD –1.75 20 T = 25°C A –1.76 V = 3.5V REF 0x800 TO 0x7FF AMP = AD8038 0 –1.77 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 f (kHz) TIME (ns) OUT Figure 20. Midscale Transition, V = 3.5 V REF Figure 23. Wideband SFDR vs. f Frequency OUT 20 90 T = 25C A V = 3V DD AMP = AD8038 80 0 MCLK = 5MHz 70 MCLK = 10MHz –20 60 –40 50 FULL SCALE MCLK = 25MHz –60 40 ZERO SCALE 30 –80 20 –100 T = 25°C A 10 V = 3.5V REF AMP = AD8038 –120 0 1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz) f (kHz) OUT Figure 21. Power Supply Rejection Ratio vs. Frequency Figure 24. Wideband SFDR vs. fOUT Frequency Rev. D | Page 11 of 28 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) PSRR (dB) 04461-020 04461-019 04461-018 SFDR (dB) SFDR (dB) THD + N (dB) 04461-023 04461-022 04461-021 AD5415 Data Sheet 0 0 T = 25°C T = 25°C � A A V = 5V V = 3V DD DD –10 –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 2 4 6 8 10 12 250 300 350 400 450 500 550 600 650 700 750 FREQUENCY (MHz) FREQUENCY (kHz) Figure 25. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 28. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz 20 0 T = 25°C T = 25°C � � A A V = 5V V = 3V DD DD –10 AMP = AD8038 AMP = AD8038 0 65k CODES 65k CODES –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –100 –90 –100 –120 50 60 70 80 90 100 110 120 130 140 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (kHz) FREQUENCY (MHz) Figure 29. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz Figure 26. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz 0 0 T = 25°C T = 25°C � A A V = 3V V = 5V DD –10 DD –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 –90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (kHz) FREQUENCY (MHz) Figure 27. Wideband SFDR, f = 50 kHz, Clock = 10 MHz Figure 30. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz OUT Rev. D | Page 12 of 28 SFDR (dB) SFDR (dB) SFDR (dB) 04461-026 04461-025 04461-024 (dB) SFDR (dB) SFDR (dB) 04461-028 04461-029 04461-027 Data Sheet AD5415 300 0 T = 25°C T = 25°C A � A ZERO SCALE LOADED TO DAC AMP = AD8038 V = 5V DD –10 AMP = AD8038 MIDSCALE LOADED TO DAC 250 65k CODES –20 FULL SCALE LOADED TO DAC –30 200 –40 150 –50 –60 100 –70 –80 50 –90 –100 0 100 1k 10k 100k 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) FREQUENCY (Hz) Figure 31. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz Figure 32. Output Noise Spectral Density Rev. D | Page 13 of 28 (dB) 04461-030 OUTPUT NOISE (nV/ Hz) 04461-031 AD5415 Data Sheet TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Multiplying Feedthrough Error A measure of the maximum deviation from a straight line The error due to capacitive feedthrough from the DAC passing through the endpoints of the DAC transfer function. It reference input to the DAC IOUT1 terminal when all 0s are is measured after adjusting for zero scale and full scale and is loaded to the DAC. normally expressed in LSB or as a percentage of the full-scale Digital Crosstalk reading. The glitch impulse transferred to the outputs of one DAC in Differential Nonlinearity response to a full-scale code change (all 0s to all 1s, or vice The difference in the measured change and the ideal 1 LSB versa) in the input register of the other DAC. It is expressed change between two adjacent codes. A specified differential in nV-sec. nonlinearity of −1 LSB maximum over the operating Analog Crosstalk temperature range ensures monotonicity. The glitch impulse transferred to the output of one DAC due to Gain Error (Full-Scale Error) a change in the output of another DAC. It is measured by A measure of the output error between an ideal DAC and the loading one of the input registers with a full-scale code change actual device output. For this DAC, ideal maximum output is LDAC (all 0s to all 1s, or vice versa) while keeping high and V − 1 LSB. The gain error of the DAC is adjustable to zero REF LDAC then pulsing low and monitoring the output of the DAC with an external resistance. whose digital code has not changed. The area of the glitch is expressed in nV-sec. Output Leakage Current The current that flows into the DAC ladder switches when they Channel-to-Channel Isolation are turned off. For the IOUT1 terminal, it can be measured by The portion of input signal from a DAC reference input that loading all 0s to the DAC and measuring the I 1 current. OUT appears at the output of another DAC. It is expressed in decibels. Minimum current flows into the I 2 line when the DAC is OUT Total Harmonic Distortion (THD) loaded with all 1s. The DAC is driven by an ac reference. The ratio of the rms sum Output Capacitance of the harmonics of the DAC output to the fundamental value is Capacitance from I 1 or I 2 to AGND. OUT OUT the THD. Usually only the lower-order harmonics are included, such as the second to fifth harmonics. Output Current Settling Time The amount of time for the output to settle to a specified level 2 2 2 2 V V V V 2 3 4 5 for a full-scale input change. For this device, it is specified with THD 20 log V 1 a 100 Ω resistor to ground. Intermodulation Distortion (IMD) Digital-to-Analog Glitch Impulse The DAC is driven by two combined sine wave references of The amount of charge injected from the digital inputs to the frequencies fa and fb. Distortion products are produced at sum analog output when the inputs change state. This is normally and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ... specified as the area of the glitch in either pA-sec or nV-sec, Intermodulation terms are those for which m or n is not equal depending on whether the glitch is measured as a current or to 0. The second-order terms include (fa + fb) and (fa − fb), and voltage signal. the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb), and Digital Feedthrough (fa − 2fb). IMD is defined as When the device is not selected, high frequency logic activity   rmssumof thesumanddiff distortionproducts on the device’s digital inputs is capacitively coupled through the IMD 20 log device and produces noise on the I pins and, subsequently, OUT rmsamplitudeof the fundamental on the following circuitry. This noise is digital feedthrough. Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics. Rev. D | Page 14 of 28 Data Sheet AD5415 GENERAL DESCRIPTION DAC SECTION When an output amplifier is connected in unipolar mode, the output voltage is given by The AD5415 is a 12-bit, dual-channel, current output DAC consisting of standard inverting R-2R ladder configuration. n VOUT = −VREF × D/2 Figure 33 shows a simplified diagram of a single channel of the AD5415. The feedback resistor RFB has a value of 2R. The value where: of R is typically 10 kΩ (with a minimum of 8 kΩ and a D is the fractional representation, in the range of 0 to 4,095, of maximum of 12 kΩ). If IOUT1 and IOUT2 are kept at the same the digital word loaded to the DAC. potential, a constant current flows into each ladder leg, n is the number of bits. regardless of the digital input code. Therefore, the input Note that the output voltage polarity is opposite the V REF resistance presented at V is always constant. REF polarity for dc reference voltages. This DAC is designed to RR R operate with either negative or positive reference voltages. The V A REF VDD power pin is only used by the internal digital logic to drive 2R 2R 2R 2R 2R the on and off states of the DAC switches. R S1 S2 S3 S12 R A FB I 1A OUT This DAC is also designed to accommodate ac reference input I 2A OUT signals in the range of −10 V to +10 V. DAC DATA LATCHES AND DRIVERS With a fixed 10 V reference, the circuit in Figure 34 gives a unipolar 0 V to −10 V output voltage swing. When VIN is an Figure 33. Simplified Ladder ac signal, the circuit performs 2-quadrant multiplication. Access is provided to the V , R , I 1, and I 2 terminals of REF FB OUT OUT Table 5 shows the relationship between digital code and the DAC, making the device extremely versatile and allowing it expected output voltage for unipolar operation. to be configured in several operating modes, such as unipolar output, bipolar output, or single-supply mode. Table 5. Unipolar Code Digital Input Analog Output (V) CIRCUIT OPERATION 1111 1111 1111 −VREF (4,095/4,096) Unipolar Mode 1000 0000 0000 −VREF (2,048/4,096) = −VREF/2 Using a single op amp, this device can easily be configured to 0000 0000 0001 −V (1/4,096) REF provide 2-quadrant multiplying operation or a unipolar output 0000 0000 0000 −V (0/4,096) = 0 REF voltage swing, as shown in Figure 34. V DD R1A R R1 FB 2R 2R R A FB R2A C1 I 1A R2 OUT AD5415 2R A1 12-BIT DAC A R2_3A R V = 0V TO –V OUT IN I 2A OUT R3 2R R3A AGND V A SYNC SCLK SDIN GND AGND REF AGND CONTROLLER NOTES 1. DAC B OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 34. Unipolar Operation Rev. D | Page 15 of 28 04461-032 04461-033 AD5415 Data Sheet V Bipolar Operation DD R1A R R1 FB 2R 2R R A In some applications, it may be necessary to generate full FB R2A V 4-quadrant multiplying operation or a bipolar output swing. IN C1 I 1A R2 OUT This can easily be accomplished by using another external 2R AD5415 A1 R2_3A 12-BIT DAC A R V = –V TO +V amplifier and the on-chip 4-quadrant resistors, as shown in OUT IN IN I 2A OUT R3 2R Figure 35. R3A A1 AGND V A SYNC SCLK SDIN GND REF When in bipolar mode, the output voltage is given by AGND n − 1 AGND µCONTROLLER V = (V × D/2 ) − V OUT REF REF NOTES 1. DAC B OMITTED FOR CLARITY. where: 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. D is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the DAC. Figure 35. Bipolar Operation n is the number of bits. SINGLE-SUPPLY APPLICATIONS When V is an ac signal, the circuit performs 4-quadrant Voltage-Switching Mode of Operation IN multiplication. Figure 36 shows the DAC operating in the voltage-switching mode. The reference voltage, VIN, is applied to the IOUT1A pin, Table 6 shows the relationship between digital code and the IOUT2A is connected to AGND, and the output voltage is expected output voltage for bipolar operation. available at the V A terminal. In this configuration, a positive REF Table 6. Bipolar Code reference voltage results in a positive output voltage, making Digital Input Analog Output (V) single-supply operation possible. The output from the DAC is 1111 1111 1111 +V (4,095/4,096) REF voltage at a constant impedance (the DAC ladder resistance). 1000 0000 0000 0 Therefore, an op amp is necessary to buffer the output voltage. 0000 0000 0001 −VREF (4,095/4,096) The reference input no longer sees a constant input impedance, 0000 0000 0000 −VREF (4,096/4,096) but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. Stability V DD R R 1 2 In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as R A V FB DD possible, and proper PCB layout techniques must be used. I 1A V OUT IN V OUT Because every code change corresponds to a step function, gain V A REF I 2A OUT peaking may occur if the op amp has limited gain bandwidth GND product (GBP) and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into NOTES the open-loop response, which can cause ringing or instability 1. SIMILAR CONFIGURATION FOR DACB 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED in the closed-loop applications circuit. IF A1 IS A HIGH SPEED AMPLIFIER. An optional compensation capacitor, C1, can be added in Figure 36. Single-Supply Voltage-Switching Mode parallel with RFBA for stability, as shown in Figure 34 and Figure 35. Too small a value of C1 can produce ringing at Note that V is limited to low voltages because the switches in IN the output, whereas too large a value can adversely affect the the DAC ladder no longer have the same source-drain drive settling time. C1 should be found empirically, but 1 pF to 2 pF voltage. As a result, their on resistance differs and degrades the is generally adequate for the compensation. integral linearity of the DAC. Also, VIN must not go negative by more than 0.3 V, or an internal diode turns on, causing the device to exceed the maximum ratings. In this type of application, the full range of multiplying capability of the DAC is lost. Rev. D | Page 16 of 28 04461-035 04461-034 Data Sheet AD5415 Positive Output Voltage DIVIDER OR PROGRAMMABLE GAIN ELEMENT The output voltage polarity is opposite to the VREF polarity for Current-steering DACs are very flexible and lend themselves to dc reference voltages. To achieve a positive voltage output, an many applications. If this type of DAC is connected as the applied negative reference to the input of the DAC is preferred feedback element of an op amp and R is used as the input FB over the output inversion through an inverting amplifier resistor, as shown in Figure 39, the output voltage is inversely because of the resistors’ tolerance errors. To generate a negative proportional to the digital input fraction, D. reference, the reference can be level-shifted by an op amp such −n that the V and GND pins of the reference become the virtual For D equal to 1 − 2 , the output voltage is OUT ground and −2.5 V, respectively, as shown in Figure 37. −n VOUT = −VIN/D = −VIN/(1 −2 ) V = 5V DD ADR03 V DD V V V OUT IN IN GND +5V C1 R A V FB DD V R A DD FB I 1A I 1A OUT OUT –2.5V V A REF 12-BIT DAC V A REF I 2A I 2A OUT V = 0 TO +2.5V OUT OUT GND GND –5V NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. V OUT 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. NOTES Figure 37. Positive Voltage Output with Minimum of Components 1. ADDITIONAL PINS OMITTED FOR CLARITY. ADDING GAIN Figure 39. Current-Steering DAC Used as a Divider or Programmable Gain Element In applications where the output voltage must be greater than VIN, gain can be added with an additional external amplifier, or it can As D is reduced, the output voltage increases. For small be achieved in a single stage. Consider the effect of temperature values of the digital fraction, D, it is important to ensure that coefficients of the thin film resistors of the DAC. Simply placing the amplifier does not saturate and that the required accuracy is a resistor in series with the R resistor causes mismatches in the FB met. For example, an 8-bit DAC driven with the binary code 0x10 temperature coefficients, resulting in larger gain temperature (0001 0000)—that is, 16 decimal—in the circuit of Figure 39 coefficient errors. Instead, the circuit in Figure 38 shows the should cause the output voltage to be 16 times V . However, if IN recommended method for increasing the gain of the circuit. the DAC has a linearity specification of ±0.5 LSB, D can have a R1, R2, and R3 should have similar temperature coefficients, weight in the range of 15.5/256 to 16.5/256, so that the possible but they need not match the temperature coefficients of the output voltage is in the range of 15.5 VIN to 16.5 VIN—an error of DAC. This approach is recommended in circuits where gains 3%, even though the DAC itself has a maximum error of 0.2%. of greater than 1 are required. DAC leakage current is also a potential source of errors in V DD divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the C1 V R A DD FB DAC. Because only a fraction, D, of the current into the V A REF I 1A OUT R1 terminal is routed to the I 1A terminal, the output voltage OUT V V V A 12-BIT DAC IN OUT REF I 2A OUT changes as follows: R3 GND R2 + R3 GAIN = R2 R2 Output Error Voltage Due to DAC Leakage = (Leakage × R)/D R2R3 R1 = R2 + R3 NOTES where R is the DAC resistance at the VREFA terminal. 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV. Figure 38. Increasing the Gain of the Current Output DAC Rev. D | Page 17 of 28 04461-037 04461-036 04461-038 AD5415 Data Sheet output between the two codes and gives rise to a differential REFERENCE SELECTION linearity error, which, if large enough, could cause the DAC to When selecting a reference for use with the AD54xx series of be nonmonotonic. current output DACs, pay attention to the reference’s output voltage temperature coefficient specification. This parameter The input bias current of an op amp also generates an offset at not only affects the full-scale error, but also can affect the the voltage output as a result of the bias current flowing in the linearity (INL and DNL) performance. The reference tempera- feedback resistor, RFB. Most op amps have input bias currents ture coefficient should be consistent with the system accuracy low enough to prevent significant errors in 12-bit applications. specifications. For example, an 8-bit system required to hold its Common-mode rejection of the op amp is important in overall specification to within 1 LSB over the temperature range voltage-switching circuits, because it produces a code- 0°C to 50°C dictates that the maximum system drift with dependent error at the voltage output of the circuit. Most op temperature should be less than 78 ppm/°C. A 12-bit system amps have adequate common-mode rejection for use at 12-bit with the same temperature range to overall specification within resolution. 2 LSB requires a maximum drift of 10 ppm/°C. Choosing a precision reference with a low output temperature coefficient Provided that the DAC switches are driven from true wideband minimizes this error source. Table 7 lists some of the references low impedance sources (VIN and AGND), they settle quickly. available from Analog Devices, Inc., that are suitable for use Consequently, the slew rate and settling time of a voltage- with this range of current output DACs. switching DAC circuit is largely determined by the output op amp. To obtain minimum settling time in this configuration, AMPLIFIER SELECTION minimize capacitance at the V node (the voltage output node REF The primary requirement for the current-steering mode is an in this application) of the DAC. This is done by using low input amplifier with low input bias currents and low input offset capacitance buffer amplifiers and careful board design. voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the Most single-supply circuits include ground as part of the analog variable gain of the circuit. A change in this noise gain between signal range, which in turn requires an amplifier that can two adjacent digital fractions produces a step change in the handle rail-to-rail signals. Analog Devices offers a wide range of output voltage due to the amplifier’s input offset voltage. This single-supply amplifiers, as listed in Table 8 and Table 9. output voltage change is superimposed on the desired change in Rev. D | Page 18 of 28 Data Sheet AD5415 Table 7. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (µV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) VOS (Max) (µV) IB (Max) (nA) Noise (µV p-p) Supply Current (µA) Package OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) VOS (Max) (µV) IB (Max) (nA) Package AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. D | Page 19 of 28 AD5415 Data Sheet SDO Control (SDO1 and SDO2) SERIAL INTERFACE The SDO bits enable the user to control the SDO output driver The AD5415 has an easy to use 3-wire interface that is strength, disable the SDO output, or configure it as an open- compatible with SPI, QSPI, MICROWIRE, and most DSP drain driver. The strength of the SDO driver affects the timing interface standards. Data is written to the device in 16-bit of t12 and, when stronger, allows a faster clock cycle to be used. words. Each 16-bit word consists of four control bits and Note that when the SDO output is disabled the daisy-chain 12 data bits, as shown in Figure 40. mode is also disabled. Low Power Serial Interface Table 10. SDO Control Bits To minimize the power consumption of the device, the interface SDO2 SDO1 Function only powers up fully when the device is being written to, that is, 0 0 Full SDO driver SYNC on the falling edge of . The SCLK and DIN input buffers 0 1 Weak SDO driver SYNC are powered down on the rising edge of . 1 0 SDO configured as open drain DAC Control Bits C3 to C0 1 1 Disable SDO output Control Bits C3 to C0 allow control of various functions of the DAC, as shown in Table 11. Default settings of the DAC at Daisy-Chain Control (DSY) power on are as follows. Data is clocked into the shift register DSY enables or disables daisy-chain mode. A 1 enables daisy- on falling clock edges, and daisy-chain mode is enabled. The chain mode; a 0 disables it. When disabled, a readback request device powers on with a zero-scale load to the DAC register and is accepted, SDO is automatically enabled, the DAC register I lines. The DAC control bits allow the user to adjust certain OUT contents of the relevant DAC are clocked out on SDO, and, features at power on. For example, daisy-chaining can be when complete, SDO is disabled again. disabled when not in use, an active clock edge can be changed CLR Hardware Bit (HCLR) to a rising edge, and DAC output can be cleared to either zero CLR scale or midscale. The user can also initiate a readback of the The default setting for the hardware pin is to clear the DAC register contents for verification purposes. registers and DAC output to zero code. A 1 in the HCLR bit clears the DAC outputs to midscale; a 0 clears them to zero scale. Control Register (Control Bits = 1101) Active Clock Edge (SCLK) While maintaining software compatibility with single-channel current output DACs (AD5426/AD5433/AD5443), this DAC The default active clock edge is the falling edge. Write a 1 to this also features additional interface functionality. Simply set the bit to clock data in on the rising edge; write a 0 to clock it in on control bits to 1101 to enter control register mode. Figure 41 the falling edge. shows the contents of the control register, the functions of which are described in the following sections. DB15 (MSB) DB0 (LSB) C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DATA BITS Figure 40. 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) 1 1 0 1 SDO1 SDO2 DSY HCLR SCLK X X X X X X X CONTROL BITS Figure 41. Control Register Loading Sequence Rev. D | Page 20 of 28 04461-040 04461-039 Data Sheet AD5415 Table 11. DAC Control Bits C3 C2 C1 C0 DAC Function 0 0 0 0 A and B No operation (power-on default) 0 0 0 1 A Load and update 0 0 1 0 A Initiate readback 0 0 1 1 A Load input register 0 1 0 0 B Load and update 0 1 0 1 B Initiate readback 0 1 1 0 B Load input register 0 1 1 1 A and B Update DAC outputs 1 0 0 0 A and B Load input registers 1 0 0 1 – Disable daisy-chain 1 0 1 0 – Clock data to shift register on rising edge 1 0 1 1 – Clear DAC output to zero scale 1 1 0 0 – Clear DAC output to midscale 1 1 0 1 – Control word 1 1 1 0 – Reserved 1 1 1 1 – No operation SYNC Function When control bits are 0000, the device is in no-operation mode. This might be useful in daisy-chain applications where the user SYNC is an edge-triggered input that acts as a frame synchroni- does not want to change the settings of a particular DAC in the zation signal and chip enable. Data can only be transferred into chain. Write 0000 to the control bits for that DAC, and subsequent the device while SYNC is low. To start the serial data transfer, data bits are ignored. SYNC should be taken low, observing the minimum SYNC falling to SCLK falling edge setup time, t . 4 Standalone Mode Daisy-Chain Mode After power on, writing 1001 to the control word disables daisy- SYNC chain mode. The first falling edge of resets the serial clock Daisy-chain mode is the default mode at power on. To disable counter to ensure that the correct number of bits are shifted in and the daisy-chain function, write 1001 to the control word. In out of the serial shift registers. A SYNC edge during the 16-bit daisy-chain mode, the internal gating on SCLK is disabled. write cycle causes the device to abort the current write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data After the falling edge of the 16th SCLK pulse, data is automati- ripples out of the shift register and appears on the SDO line. cally transferred from the input shift register to the DAC. For This data is clocked out on the rising edge of SCLK and is valid another serial transfer to take place, the counter must be reset for the next device on the falling edge of SCLK (default). By SYNC by the falling edge of . connecting this line to the SDIN input on the next device in the LDAC Function chain, a multidevice interface is constructed. For each device in the system, 16 clock pulses are required. Therefore, the total The LDAC function allows asynchronous and synchronous number of clock cycles must equal 16N, where N is the total updates to the DAC output. The DAC is asynchronously updated number of devices in the chain. (See Figure 5.) when this signal goes low. Alternatively, if this line is held per- manently low, an automatic or synchronous update mode is SYNC When the serial transfer to all devices is complete, should selected, whereby the DAC is updated on the 16th clock falling be taken high. This prevents additional data from being clocked edge when the device is in standalone mode, or on the rising into the input shift register. A burst clock containing the exact edge of SYNC when the device is in daisy-chain mode. number of clock cycles can be used, after which SYNC is taken Software LDAC Function high. After the rising edge of SYNC, data is automatically trans- ferred from each device’s input shift register to the addressed DAC. Load-and-update mode also functions as a software update LDAC function, irrespective of the voltage level on the pin. Rev. D | Page 21 of 28 AD5415 Data Sheet Table 12. SPORT Control Register Setup MICROPROCESSOR INTERFACING Name Setting Description Microprocessor interfacing to the AD5415 DAC is through a TFSW 1 Alternate framing serial bus that uses standard protocol compatible with micro- INVTFS 1 Active low frame signal controllers and DSP processors. The communication channel is DTYPE 00 Right-justify data a 3-wire interface consisting of a clock signal, a data signal, and ISCLK 1 Internal serial clock a synchronization signal. The AD5415 requires a 16-bit word, TFSR 1 Frame every word with the default being data valid on the falling edge of SCLK; ITFS 1 Internal framing signal however, this is changeable using the control bits in the data-word. SLEN 1111 16-bit data-word ADSP-21xx-to-AD5415 Interface The ADSP-21xx family of DSPs is easily interfaced to the ADSP-BF5xx-to-AD5415 Interface AD5415 DAC without the need for extra glue logic. Figure 42 The ADSP-BF5xx family of processors has an SPI-compatible is an example of an SPI interface between the DAC and the port that enables the processor to communicate with SPI- ADSP-2191. SCK of the DSP drives the serial data line, SDIN. compatible devices. A serial interface between the BlackFin® SYNC is driven from a port line, in this case SPIxSEL. processor and the AD5415 DAC is shown in Figure 44. In this configuration, data is transferred through the MOSI (master 1 ADSP-2191 1 AD5415 output, slave input) pin. is driven by the pin, SYNC SPIxSEL which is a reconfigured programmable flag pin. SPIxSEL SYNC MOSI SDIN 1 AD5415 1 SCK SCLK ADSP-BF5xx SPIxSEL SYNC 1 ADDITIONAL PINS OMITTED FOR CLARITY. MOSI SDIN SCK SCLK Figure 42. ADSP-2191 SPI-to-AD5415 Interface A serial interface between the DAC and DSP SPORT is shown 1 ADDITIONAL PINS OMITTED FOR CLARITY. in Figure 43. In this interface example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated Figure 44. ADSP-BF5xx-to-AD5415 Interface by writing a word to the Tx register after SPORT is enabled. In a The ADSP-BF5xx processor incorporates channel synchronous write sequence, data is clocked out on each rising edge of the serial ports (SPORT). A serial interface between the DAC and DSP’s serial clock and clocked into the DAC input shift register the DSP SPORT is shown in Figure 45. When SPORT is enabled, on the falling edge of its SCLK. The update of the DAC output initiate transmission by writing a word to the Tx register. The takes place on the rising edge of the SYNC signal. data is clocked out on each rising edge of the DSP’s serial clock and clocked into the DAC’s input shift register on the falling edge 1 ADSP-2101/ AD5415 of its SCLK. The DAC output is updated by using the transmit ADSP-2103/ 1 frame synchronization (TFS) line to provide a SYNC signal. ADSP-2191 TFS SYNC DT SDIN 1 AD5415 1 SCLK SCLK ADSP-BF5xx TFS SYNC 1 ADDITIONAL PINS OMITTED FOR CLARITY. DT SDIN SCLK SCLK Figure 43. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5415 Interface Communication between two devices at a given clock speed is 1 ADDITIONAL PINS OMITTED FOR CLARITY. possible when the following specifications are compatible: Figure 45. ADSP-BF5xx SPORT-to-AD5415 Interface frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns minimum. See the ADSP-21xx User Manual for information on clock and frame frequencies for the SYNC SPORT register. Table 12 shows the setup for the SPORT control register. Rev. D | Page 22 of 28 04461-042 04461-041 04461-051 04461-052 Data Sheet AD5415 80C51/80L51-to-AD5415 Interface 1 MC68HC11 1 AD5415 A serial interface between the DAC and the 80C51 is shown in PC7 SYNC Figure 46. TxD of the 80C51 drives SCLK of the DAC serial SCK SCLK interface, and RxD drives the serial data line, SDIN. P1.1 is a MOSI SDIN bit-programmable pin on the serial port and is used to drive . When data is to be transmitted to the switch, P1.1 is 1 SYNC ADDITIONAL PINS OMITTED FOR CLARITY. taken low. The 80C51/80L51 only transmits data in 8-bit bytes; Figure 47. MC68HC11-to-AD5415 Interface therefore, only eight falling clock edges occur in the transmit cycle. To load data correctly to the DAC, P1.1 is left low after If the user wants to verify the data previously written to the the first eight bits are transmitted, and a second write cycle is input shift register, the SDO line can be connected to MISO of initiated to transmit the second byte of data. Data on RxD is the MC68HC11, and, with SYNC low, the shift register clocks clocked out of the microcontroller on the rising edge of TxD data out on the rising edges of SCLK. and is valid on the falling edge of TxD. As a result, no glue logic MICROWIRE-to-AD5415 Interface is required between the DAC and microcontroller interface. Figure 48 shows an interface between the DAC and any P1.1 is taken high following the completion of this cycle. The MICROWIRE-compatible device. Serial data is shifted out on 80C51 provides the LSB of its SBUF register as the first bit in the falling edge of the serial clock, SK, and is clocked into the the data stream. The DAC input register requires its data with DAC input shift register on the rising edge of SK, which the MSB as the first bit received. The transmit routine should corresponds to the falling edge of the DAC’s SCLK. take this into account. 1 MICROWIRE 1 1 AD5415 1 AD5415 8051 SK SCLK TxD SCLK SO SDIN RxD SDIN CS SYNC P1.1 SYNC 1 ADDITIONAL PINS OMITTED FOR CLARITY. 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 48. MICROWIRE-to-AD5415 Interface Figure 46. 80C51/80L51-to-AD5415 Interface PIC16C6x/7x-to-AD5415 Interface MC68HC11-to-AD5415 Interface The PIC16C6x/7x synchronous serial port (SSP) is configured Figure 47 is an example of a serial interface between the DAC as an SPI master with the clock polarity bit (CKP) = 0. This is and the MC68HC11 microcontroller. The serial peripheral done by writing to the synchronous serial port control register interface (SPI) on the MC68HC11 is configured for master (SSPCON); see the PIC16/17 Microcontroller User Manual. In mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock this example, I/O port RA1 is used to provide a SYNC signal phase bit (CPHA) = 1. The SPI is configured by writing to the and enable the serial port of the DAC. This microcontroller SPI control register (SPCR); see the 68HC11 User Manual. SCK transfers only eight bits of data during each serial transfer of the 68HC11 drives the SCLK of the DAC interface; the MOSI operation; therefore, two consecutive write operations are output drives the serial data line (SDIN) of the DAC. required. Figure 49 shows the connection diagram. The signal is derived from a port line (PC7). When data SYNC 1 PIC16C6x/7x 1 is being transmitted to the AD5415, the line is taken low SYNC AD5415 SCK/RC3 SCLK (PC7). Data appearing on the MOSI output is valid on the SDIN SDI/RC4 falling edge of SCK. Serial data from the 68HC11 is transmitted RA1 SYNC in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data 1 ADDITIONAL PINS OMITTED FOR CLARITY. to the DAC, leave PC7 low after the first eight bits are transferred and perform a second serial write operation to the Figure 49. PIC16C6x/7x-to-AD5415 Interface DAC. PC7 is taken high at the end of this procedure. Rev. D | Page 23 of 28 04461-043 04461-046 04461-045 04461-044 AD5415 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING Components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise In any circuit where accuracy is important, careful considera- to other parts of the board, and they should never be run near tion of the power supply and ground return layout helps to the reference inputs. ensure the rated performance. The printed circuit board on which the AD5415 is mounted should be designed so that the Avoid crossover of digital and analog signals. Traces on analog and digital sections are separated and confined to opposite sides of the board should run at right angles to each certain areas of the board. If the DAC is in a system where other. This reduces the effects of feedthrough on the board. A multiple devices require an AGND-to-DGND connection, the microstrip technique is by far the best, but its use is not always connection should be made at one point only. The star ground possible with a double-sided board. In this technique, the point should be established as close as possible to the device. component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close as possible to It is good practice to use compact, minimum lead length PCB the package, ideally right up against the device. The 0.1 µF layout design. Leads to the input should be as short as possible capacitor should have low effective series resistance (ESR) and to minimize IR drops and stray inductance. low effective series inductance (ESI), like the common ceramic types of capacitors that provide a low impedance path to ground The PCB metal traces between VREF and RFB should also be at high frequencies, to handle transient currents due to internal matched to minimize gain error. To maximize high frequency logic switching. Low ESR 1 µF to 10 µF tantalum or electrolytic performance, the I-to-V amplifier should be located as close as capacitors should also be applied at the supplies to minimize possible to the device. transient disturbance and filter out low frequency ripple. Rev. D | Page 24 of 28 Data Sheet AD5415 OVERVIEW OF AD54XX DEVICES Table 13. 1 Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns pulse width CS AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. D | Page 25 of 28 AD5415 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 0.75 8° 0.30 0° 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 50. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution INL (LSB) Temperature Range Package Description Package Option AD5415YRU 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRU-REEL7 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRUZ 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRUZ-REEL 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRUZ-REEL7 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 EVAL-AD5415SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 26 of 28 Data Sheet AD5415 NOTES Rev. D | Page 27 of 28 AD5415 Data Sheet NOTES © 2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04461–0–5/12(D) Rev. D | Page 28 of 28