ANALOG DEVICES AD5405

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface AD5405 GENERAL DESCRIPTION FEATURES 1 10 MHz multiplying bandwidth The AD5405 is a CMOS, 12-bit, dual-channel, current output On-chip 4-quadrant resistors allow flexible output ranges digital-to-analog converter (DAC). This device operates from a INL of ±1 LSB 2.5 V to 5.5 V power supply, making it suited to battery-powered 40-lead LFCSP package and other applications. 2.5 V to 5.5 V supply operation As a result of manufacture with a CMOS submicron process, the ±10 V reference input device offers excellent 4-quadrant multiplication characteristics, 21.3 MSPS update rate with large signal multiplying bandwidths of up to 10 MHz. Extended temperature range: −40°C to 125°C 4-quadrant multiplication The applied external reference input voltage (V ) determines REF Power-on reset the full-scale output current. An integrated feedback resistor (R ) FB 0.5 μA typical current consumption provides temperature tracking and full-scale voltage output when Guaranteed monotonic combined with an external I-to-V precision amplifier. This device Readback function also contains the 4-quadrant resistors necessary for bipolar operation and other configuration modes. APPLICATIONS Portable battery-powered applications This DAC uses data readback, allowing the user to read the Waveform generators contents of the DAC register via the DB pins. On power-up, the Analog processing internal register and latches are filled with 0s, and the DAC Instrumentation applications outputs are at zero scale. Programmable amplifiers and attenuators Digitally controlled calibration The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package. Programmable filters and oscillators 1 U.S. Patent Number 5,689,257. Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V A R3A R2_3A R2A REF R1A R3 R2 2R 2R AD5405 R1 RFB 2R 2R V R A DD FB DATA DB0 I 1A OUT INPUTS INPUT 12-BIT LATCH BUFFER R-2R DAC A DB11 I 2A OUT DAC A/B CONTROL CS LOGIC R/W I 1B OUT 12-BIT LATCH R-2R DAC B I 2B LDAC OUT R B FB POWER-ON GND R1 RFB RESET R3 R2 2R 2R CLR 2R 2R R3B R2_3B R2B V B R1B REF Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2009 Analog Devices, Inc. All rights reserved. 04463-001 AD5405 TABLE OF CONTENTS Specifications ..................................................................................... 3  Divider or Programmable Gain Element ................................ 16  Timing Characteristics ................................................................ 5  Reference Selection .................................................................... 16  Absolute Maximum Ratings ............................................................ 6  Amplifier Selection .................................................................... 16  ESD Caution .................................................................................. 6  Parallel Interface ......................................................................... 18  Pin Configuration and Function Descriptions ............................. 7  Microprocessor Interfacing ....................................................... 18  Typical Performance Characteristics ............................................. 8  PCB Layout and Power Supply Decoupling ........................... 19  Terminology .................................................................................... 13  Evaluation Board for the DACs ................................................ 19  General Description ....................................................................... 14  Power Supplies for the Evaluation Board ................................ 19  DAC Section ................................................................................ 14  Overview of AD54xx Devices ....................................................... 22  Circuit Operation ....................................................................... 14  Outline Dimensions ....................................................................... 23  Single-Supply Applications ....................................................... 15  Ordering Guide .......................................................................... 23  Adding Gain ................................................................................ 15  REVISION HISTORY 12/09—Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Changes to Table 2 and Figure 2 ..................................................... 5 Changes to Table 4 and Figure 4 ..................................................... 7 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 7/05—Rev. 0 to Rev. A Changed Pin DAC A/B to DAC A/B ................................ Universal Changes to Features List .................................................................. 1 Changes to Specifications ................................................................ 3 Changes to Timing Characteristics ................................................ 5 Change to Absolute Maximum Ratings ......................................... 6 Change to Figure 7 and Figure 8..................................................... 8 Change to Figure 12 ......................................................................... 9 Change to Figure 26 Through Figure 28 ..................................... 11 Changes to General Description Section .................................... 14 Change to Figure 31 ....................................................................... 14 Changes to Table 5 Through Table 10 .......................................... 14 Changes to Figure 34 and Figure 35 ............................................. 15 Changes to Figure 36 and Figure 37 ............................................. 16 Changes to Microprocessor Interfacing Section ........................ 18 Added Figure 38 Through Figure 40............................................ 18 Change to Power Supplies for the Evaluation Board Section ... 19 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 7/04—Revision 0: Initial Version Rev. B | Page 2 of 24 AD5405 1 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Bipolar Zero-Code Error ±25 mV Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, IOUT1 ±15 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1 REFERENCE INPUT Reference Input Range ±10 V VREFA, VREFB Input Resistance 8 10 13 kΩ Input resistance TC = −50 ppm/°C V A-to-V B Input Resistance 1.6 2.5 % Typ = 25°C, max = 125°C REF REF Mismatch R1, R Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C FB R2, R3 Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C R2-to-R3 Resistance Mismatch 0.06 0.18 % Typ = 25°C, max = 125°C Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA V − 0.5 V V = 2.5 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 μA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, IIL 1 μA Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying BW 10 MHz VREF = ±3.5 V p-p, DAC loaded all 1s Output Voltage Settling Time RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Interface time delay 10% to 90% Settling Time 15 30 ns Rise and fall times Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V = 0 V REF Multiplying Feedthrough Error DAC latch loaded with all 0s, V = ±3.5 V REF 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Rev. B | Page 3 of 24 AD5405 Parameter Min Typ Max Unit Conditions Digital Feedthrough 1 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V = 3. 5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz f 61 dB OUT 50 kHz fOUT 66 dB SFDR Performance (Wideband) VREF = 3.5 V Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz fOUT 65 dB Clock = 25 MHz 500 kHz fOUT 50 dB 100 kHz f 60 dB OUT 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) V = 3.5 V REF Clock = 10 MHz 500 kHz fOUT 73 dB 100 kHz fOUT 80 dB 50 kHz f 87 dB OUT Clock = 25 MHz 500 kHz fOUT 70 dB 100 kHz fOUT 75 dB 50 kHz fOUT 80 dB Intermodulation Distortion V = 3.5 V REF f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 μA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 μA TA = −40°C to +125°C, logic inputs = 0 V or VDD Power Supply Sensitivity 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization, not subject to production test. Rev. B | Page 4 of 24 AD5405 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Limit at TMIN, TMAX Unit Conditions/Comments Write Mode t1 0 ns min R/W-to-CS setup time t2 0 ns min R/W-to-CS hold time t 10 ns min CS low time 3 t 10 ns min Address setup time 4 t 0 ns min Address hold time 5 t6 6 ns min Data setup time t7 0 ns min Data hold time t 5 ns min R/W high to CS low 8 t 7 ns min CS min high time 9 t 10 ns typ CS rising-to-LDAC falling time 14 t15 12 ns typ LDAC pulse width t16 10 ns typ CS rising-to-LDAC rising time t17 10 ns typ LDAC falling-to-CS rising time Data Readback Mode t 0 ns typ Address setup time 10 t 0 ns typ Address hold time 11 t12 5 ns typ Data access time 35 ns max t13 5 ns typ Bus relinquish time 10 ns max Update Rate 21.3 MSPS Consists of CS min high time, CS low time, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. t 8 t t t 2 2 1 R/W t 9 t 3 CS t t t 4 t 11 5 10 DACA/DACB t 6 t t t 12 13 7 DATA DATA VALID DATA VALID t t 14 15 1 LDAC t 17 t 16 2 LDAC 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Timing Diagram I 200μA OL V + V TO OH (MIN) OL (MAX) OUTPUT 2 C L PIN 50pF I 200μA OH Figure 3. Load Circuit for Data Timing Specifications Rev. B | Page 5 of 24 04463-003 04463-002 AD5405 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any VREFA, VREFB, RFBA, RFBB to GND −12 V to +12 V other conditions above those indicated in the operational IOUT1, IOUT2 to GND −0.3 V to +7 V section of this specification is not implied. Exposure to absolute 1 Logic Inputs and Output −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Operating Temperature Range device reliability. Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 40-lead LFCSP, θJA Thermal Impedance 30°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 LDAC CS W Overvoltages at DBx, , , and R/ are clamped by internal diodes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 24 AD5405 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS R1A 1 PIN 1 30 R1B R2A 2 INDICATOR 29 R2B R2_3A 3 28 R2_3B 4 R3A 27 R3B V A 5 REF 26 V B AD5405 REF DGND 6 TOP VIEW 25 V DD LDAC 7 (Not to Scale) 24 CLR DAC A/B 8 23 R/W NC 9 22 CS DB11 10 21 DB0 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 to 4 R1A, R2B, DAC A 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with R2_3B, R3A minimum of external components. 5, 26 V A, V B DAC Reference Voltage Input Terminals. REF REF 6 DGND Digital Ground Pin. 7 LDAC Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected whereby the DAC is updated on the rising edge of CS. 8 A Selects DAC A or B. Low selects DAC A, and high selects DAC B. DAC /B 9, 34 to 37 NC Not internally connected. 10 to 21 DB11 to DB0 Parallel Data Bits 11 through 0. 22 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Edge sensitive; when pulled high, the DAC data is latched. 23 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of DAC register. 24 CLR Active Low Control Input. Clears DAC output and input and DAC registers. 25 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 27 to 30 R3B, R2_3B, DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a R2B, R1B minimum of external components. 31, 40 R B, R A External Amplifier Output. FB FB 32 I 2B DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be OUT biased to achieve single-supply operation. 33 IOUT1B DAC B Current Outputs. 38 IOUT1A DAC A Current Outputs. 39 IOUT2A DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to achieve single-supply operation. EPAD Exposed pad must be connected to ground. Rev. B | Page 7 of 24 DB10 11 40 R A FB DB9 12 39 I 2A OUT DB8 13 38 I 1A OUT DB7 14 37 NC 36 NC DB6 15 DB5 16 35 NC 34 NC DB4 17 DB3 18 33 I 1B OUT 32 I 2B DB2 19 OUT 31 R B DB1 20 FB 04463-004 AD5405 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 –0.40 T = 25°C A T = 25°C A 0.8 V = 5V DD V = 10V REF V = 5V –0.45 DD 0.6 0.4 –0.50 0.2 0 –0.55 –0.2 –0.60 –0.4 MIN DNL –0.6 –0.65 –0.8 –1.0 –0.70 0 500 1000 1500 2000 2500 3000 3500 4000 27 34 5 68910 CODE REFERENCE VOLTAGE Figure 5. INL vs. Code (12-Bit DAC) Figure 8. DNL vs. Reference Voltage 1.0 5 T = 25°C A 0.8 4 V = 10V REF V = 5V V = 5V DD DD 0.6 3 0.4 2 0.2 1 0 0 V = 2.5V DD –0.2 –1 –0.4 –2 –0.6 –3 V = 10V –0.8 –4 REF –1.0 –5 0 500 1000 1500 2000 2500 3000 3500 4000 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 6. DNL vs. Code (12-Bit DAC) Figure 9. Gain Error vs. Temperature 0.6 8 T = 25°C A 0.5 7 0.4 6 MAX INL 0.3 5 V = 5V DD 0.2 T = 25°C A 4 V = 5V 0.1 DD 3 0 MIN INL 2 –0.1 V = 3V DD –0.2 1 V = 2.5V DD –0.3 0 2 34 5 6 789 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE INPUT VOLTAGE (V) Figure 7. INL vs. Reference Voltage Figure 10. Supply Current vs. Logic Input Voltage Rev. B | Page 8 of 24 INL (LSB) DNL (LSB) INL (LSB) 04463-032 04463-031 04463-030 DNL (LSB) ERROR (mV) CURRENT (mA) 04463-013 04463-033 04463-034 AD5405 1.6 6 T = 25°C ALL ON A 0 LOADING DB11 –6 1.4 ZS TO FS DB10 –12 DB9 –18 1.2 DB8 –24 I 1 V = 5V DB7 OUT DD –30 DB6 1.0 –36 DB5 –42 DB4 0.8 –48 DB3 –54 I 1 V = 3V OUT DD DB2 –60 0.6 DB1 –66 DB0 –72 0.4 T = 25°C A –78 V = 5V DD –84 V =±3.5V REF 0.2 –90 ALL OFF C =1.8pF COMP –96 AMP = AD8038 0 –102 –40 –20 0 20 40 60 80 100 120 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) TEMPERATURE (°C) Figure 14. Reference Multiplying Bandwidth vs. Frequency and Code Figure 11. IOUT1 Leakage Current vs. Temperature 0.50 0.2 0.45 V = 5V DD 0.40 0 0.35 ALL 0s 0.30 –0.2 ALL 1s 0.25 V = 2.5V DD –0.4 0.20 0.15 ALL 1s ALL 0s T = 25°C A 0.10 –0.6 V = 5V DD =±3.5V V REF 0.05 C = 1.8pF COMP AMP = AD8038 0 –0.8 –60 –40 –20 0 20 40 60 80 100 120 140 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) TEMPERATURE (°C) Figure 15. Reference Multiplying Bandwidth—All 1s Loaded Figure 12. Supply Current vs. Temperature 14 3 T = 25°C A T = 25°C A V = 5V DD LOADING ZS TO FS 12 V = 5V DD 0 10 8 –3 6 V = 3V DD 4 V =±2V, AD8038 C 1.47pF REF C –6 V = 2.5V V =±2V, AD8038 C 1pF DD REF C V =±0.15V, AD8038 C 1pF REF C 2 V =±0.15V, AD8038 C 1.47pF REF C V =±3.51V, AD8038 C 1.8pF REF C –9 0 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Reference Multiplying Bandwidth vs. Frequency Figure 13. Supply Current vs. Update Rate and Compensation Capacitor Rev. B | Page 9 of 24 I (mA) CURRENT (μA) I 1 LEAKAGE (nA) DD OUT 04463-038 04463-037 04463-036 GAIN (dB) GAIN (dB) GAIN (dB) 04463-015 04463-014 04463-029 AD5405 –60 0.045 0x7FF TO 0x800 T = 25°C T = 25°C A A 0.040 V = 0V V = 3V REF DD V = 5V DD AMP = AD8038 V = 3.5V p-p REF –65 0.035 C = 1.8pF COMP 0.030 –70 0.025 V = 3V DD 0.020 –75 0.015 0x800 TO 0x7FF 0.010 –80 V = 3V DD 0.005 0 –85 –0.005 V = 5V DD –0.010 –90 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) TIME (ns) Figure 17. Midscale Transition, V = 0 V Figure 20. THD and Noise vs. Frequency REF 100 –1.68 T = 25°C A 0x7FF TO 0x800 MCLK = 1MHz V = 3.5V –1.69 REF AMP = AD8038 V = 5V DD 80 C = 1.8pF COMP –1.70 –1.71 60 MCLK = 200kHz –1.72 MCLK = 0.5MHz V = 3V DD –1.73 40 V = 5V DD –1.74 V = 3V DD –1.75 20 T = 25°C A –1.76 V = 3.5V REF 0x800 TO 0x7FF AMP = AD8038 0 –1.77 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 f (kHz) TIME (ns) OUT Figure 18. Midscale Transition, V = 3.5 V REF Figure 21. Wideband SFDR vs. f Frequency OUT 20 90 T = 25°C A V = 3V DD 80 AMP = AD8038 0 MCLK = 5MHz 70 MCLK = 10MHz –20 60 –40 50 FULL SCALE MCLK = 25MHz 40 –60 ZERO SCALE 30 –80 20 –100 T = 25°C A 10 V = 3.5V REF AMP = AD8038 –120 0 1 100 1k 10k 100k 1M 10M 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (Hz) f (kHz) OUT Figure 19. Power Supply Rejection Ratio vs. Frequency Figure 22. Wideband SFDR vs. fOUT Frequency Rev. B | Page 10 of 24 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) PSRR (dB) 04463-026 04463-040 04463-039 SFDR (dB) SFDR (dB) THD + N (dB) 04463-028 04463-027 04463-041 AD5405 0 0 T = 25°C T = 25°C  A A V = 5V V = 3V DD DD –10 –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 0 2 4 6 8 10 12 250 300 350 400 450 500 550 600 650 700 750 FREQUENCY (MHz) FREQUENCY (kHz) Figure 23. Wideband SFDR, f = 100 kHz, Clock = 25 MHz Figure 26. Narrow-Band Spectral Response, f = 500 kHz, Clock = 25 MHz OUT OUT 0 20 T = 25°C T = 25°C A  A V = 5V V = 3V DD DD –10 AMP = AD8038 AMP = AD8038 0 65k CODES 65k CODES –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 –80 –100 –90 –100 –120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (kHz) FREQUENCY (MHz) Figure 27. Narrow-Band SFDR, f = 100 kHz, Clock = 25 MHz Figure 24. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz OUT 0 0 T = 25°C T = 25°C A A V = 3V V = 5V DD DD –10 –10 AMP = AD8038 AMP = AD8038 65k CODES 65k CODES –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 –90 70 75 80 85 90 95 100 105 110 115 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (kHz) Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz Rev. B | Page 11 of 24 SFDR (dB) SFDR (dB) SFDR (dB) 04463-020 04463-019 04463-018 (dB) SFDR (dB) SFDR (dB) 04463-023 04463-022 04463-021 AD5405 300 0 T = 25°C T = 25°C  A A ZERO SCALE LOADED TO DAC AMP = AD8038 V = 5V –10 DD AMP = AD8038 MIDSCALE LOADED TO DAC 250 65k CODES –20 FULL SCALE LOADED TO DAC –30 200 –40 –50 150 –60 100 –70 –80 50 –90 0 –100 100 1k 10k 100k 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) FREQUENCY (Hz) Figure 29. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz Figure 30. Output Noise Spectral Density Rev. B | Page 12 of 24 (dB) 04463-024 OUTPUT NOISE (nV/ Hz) 04463-025 AD5405 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Multiplying Feedthrough Error A measure of the maximum deviation from a straight line The error due to capacitive feedthrough from the DAC passing through the endpoints of the DAC transfer function. It reference input to the DAC IOUT1 terminal when all 0s are is measured after adjusting for zero and full scale and is normally loaded to the DAC. expressed in LSBs or as a percentage of the full-scale reading. Digital Crosstalk Differential Nonlinearity The glitch impulse transferred to the outputs of a DAC in The difference in the measured change and the ideal 1 LSB response to a full-scale code change (all 0s to all 1s, or vice change between two adjacent codes. A specified differential versa) in the input register of another DAC. It is expressed in nonlinearity of −1 LSB maximum over the operating temper- nV-sec. ature range ensures monotonicity. Analog Crosstalk Gain Error (Full-Scale Error) The glitch impulse transferred to the output of one DAC due to a A measure of the output error between an ideal DAC and the change in the output of another DAC. It is measured by loading actual device output. For this DAC, ideal maximum output is one of the input registers with a full-scale code change (all 0s to V − 1 LSB. The gain error of the DAC is adjustable to zero all 1s, or vice versa) while keeping LDAC high and then pulsing REF with an external resistance. LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-sec. Output Leakage Current The current that flows into the DAC ladder switches when they Channel-to-Channel Isolation are turned off. For the IOUT1 terminal, it can be measured by The portion of input signal from a DAC’s reference input that loading all 0s to the DAC and measuring the IOUT1 current. appears at the output of the other DAC. It is expressed in decibels. Minimum current flows into the I 2 line when the DAC is OUT Total Harmonic Distortion (THD) loaded with all 1s. The DAC is driven by an ac reference. The ratio of the rms sum Output Capacitance of the harmonics of the DAC output to the fundamental value is Capacitance from I 1 or I 2 to AGND. the THD. Usually only the lower-order harmonics are included, OUT OUT such as the second to the fifth harmonics. Output Current Settling Time The amount of time for the output to settle to a specified level 2 2 2 2 V + V + V + V 2 3 4 5 THD= 20 log for a full-scale input change. For this device, it is specified with V 1 a 100 Ω resistor to ground. Intermodulation Distortion (IMD) Digital-to-Analog Glitch Impulse The DAC is driven by two combined sine wave references The amount of charge injected from the digital inputs to the of frequencies fa and fb. Distortion products are produced analog output when the inputs change state. This is typically at sum and difference frequencies of mfa ± nfb, where m, n = 0, specified as the area of the glitch in either pA-sec or nV-sec, 1, 2, 3 ... Intermodulation terms are those for which m or n is depending on whether the glitch is measured as a current or not equal to 0. The second-order terms include (fa + fb) and voltage signal. (fa − fb), and the third-order terms are (2fa + fb), (2fa − fb), Digital Feedthrough (f + 2fa + 2fb), and (fa − 2fb). IMD is defined as When the device is not selected, high frequency logic activity (rms sum of the sum and diff distortion products) IMD= 20 log on the device’s digital inputs is capacitively coupled through the rms amplitude of the fundamental device and produces noise on the I pins and, subsequently, OUT on the following circuitry. This noise is digital feedthrough. Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics. Rev. B | Page 13 of 24 AD5405 GENERAL DESCRIPTION DAC SECTION When an output amplifier is connected in unipolar mode, the output voltage is given by The AD5405 is a 12-bit, dual-channel, current-output DAC n consisting of a standard inverting R-2R ladder configuration. V =−V × D 2 OUT REF Figure 31 shows a simplified diagram for a single channel of the AD5405. The feedback resistor RFBA has a value of 2R. The where: value of R is typically 10 kΩ (with a minimum of 8 kΩ and a D is the fractional representation, in the range of 0 to 4,095, of maximum of 13 kΩ). If IOUT1A and IOUT2A are kept at the same the digital word loaded to the DAC. potential, a constant current flows into each ladder leg, n is the resolution of the DAC. regardless of digital input code. Therefore, the input resistance With a fixed 10 V reference, the circuit shown in Figure 32 gives presented at V A is always constant. REF a unipolar 0 V to −10 V output voltage swing. When V is an ac IN signal, the circuit performs 2-quadrant multiplication. R R R V REFA 2R 2R 2R 2R 2R Table 5 shows the relationship between digital code and the S1 S2 S3 S12 R expected output voltage for unipolar operation. R A FB I OUT1A Table 5. Unipolar Code I OUT 2A Digital Input Analog Output (V) DAC DATA LATCHES AND DRIVERS 1111 1111 1111 −VREF (4,095/4,096) 1000 0000 0000 −VREF (2,048/4,096) = −VREF/2 Figure 31. Simplified Ladder Configuration 0000 0000 0001 −VREF (1/4,096) Access is provided to the V , R , I 1, and I 2 terminals of REF FB OUT OUT 0000 0000 0000 −V (0/4,096) = 0 REF the DAC, making the device extremely versatile and allowing it to be configured for several operating modes, such as unipolar output, bipolar output, or single-supply mode. Bipolar Operation In some applications, it may be necessary to generate full CIRCUIT OPERATION 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external Unipolar Mode amplifier, as shown in Figure 33. Using a single op amp, this DAC can easily be configured to provide 2-quadrant multiplying operation or a unipolar output V DD R1A R R1 FB voltage swing, as shown in Figure 32. 2R R A 2R FB R2A V C1 IN V DD R2 I 1A OUT R1A 2R AD5405 A1 R2_3A I 2A R1 R OUT FB 12-Bit DAC A V =–V TO +V OUT IN IN 2R 2R R A R FB R3 2R R3A C1 R2A A1 I 1A OUT R2 AGND AD5405 2R A1 V A REF GND I 2A 12-Bit DAC A OUT R2_3A AGND R V = 0V TO –V OUT IN R3 AGND 2R NOTES R3A 1. SIMILAR CONFIGURATION FOR DAC B. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. AGND AGND V A REF GND Figure 33. Bipolar Operation (4-Quadrant Multiplication) AGND When in bipolar mode, the output voltage is given by NOTES 1. SIMILAR CONFIGURATION FOR DAC B. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED n−1 V = (V × D 2 )− V IF A1 IS A HIGH SPEED AMPLIFIER. OUT REF REF Figure 32. Unipolar Operation where: D is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the DAC. n is the number of bits. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Rev. B | Page 14 of 24 04463-005 04463-006 04463-007 AD5405 Table 6 shows the relationship between the digital code and the Note that V is limited to low voltages because the switches in the IN expected output voltage for bipolar operation. DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs and degrades the integral Table 6. Bipolar Code linearity of the DAC. Also, VIN must not go negative by more Digital Input Analog Output (V) than 0.3 V, or an internal diode turns on, causing the device to 1111 1111 1111 +VREF (4,095/4,096) exceed the maximum ratings. In this type of application, the full 1000 0000 0000 0 range of multiplying capability of the DAC is lost. 0000 0000 0001 −V (4,095/4,096) REF 0000 0000 0000 −VREF (4,096/4,096) Positive Output Voltage Stability The output voltage polarity is opposite to the V polarity for REF dc reference voltages. To achieve a positive voltage output, an In the I-to-V configuration, the I of the DAC and the OUT applied negative reference to the input of the DAC is preferred inverting node of the op amp must be connected as close as over the output inversion through an inverting amplifier because possible, and proper PCB layout techniques must be used. of the resistor’s tolerance errors. To generate a negative reference, Because every code change corresponds to a step function, gain the reference can be level-shifted by an op amp such that the peaking may occur if the op amp has limited gain bandwidth V and GND pins of the reference become the virtual ground OUT product (GBP) and there is excessive parasitic capacitance at the and −2.5 V, respectively, as shown in Figure 35. inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability V = +5V DD in the closed-loop applications circuit. ADR03 V V OUT IN GND An optional compensation capacitor, C1, can be added in parallel +5V C 1 R A with RFBA for stability, as shown in Figure 32 and Figure 33. Too V FB DD I 1A –2.5V OUT small a value of C1 can produce ringing at the output, whereas V A 12-BIT DAC REF I 2A OUT V = 0V TO +2.5V OUT too large a value can adversely affect the settling time. C1 should GND –5V be found empirically, but 1 pF to 2 pF is generally adequate for the compensation. NOTES 1. SIMILAR CONFIGURATION FOR DAC B. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED SINGLE-SUPPLY APPLICATIONS IF A1 IS A HIGH SPEED AMPLIFIER. Voltage-Switching Mode of Operation Figure 35. Positive Voltage Output with Minimum Components Figure 34 shows the DAC operating in the voltage-switching ADDING GAIN mode. The reference voltage, VIN, is applied to the IOUT1A pin, In applications where the output voltage must be greater than IOUT2A is connected to AGND, and the output voltage is VIN, gain can be added with an additional external amplifier, or available at the VREFA terminal. In this configuration, a positive it can be achieved in a single stage. Consider the effect of temper- reference voltage results in a positive output voltage, making ature coefficients of the thin film resistors of the DAC. Simply single-supply operation possible. The output from the DAC is placing a resistor in series with the R resistor causes mismatches FB voltage at a constant impedance (the DAC ladder resistance). in the temperature coefficients, resulting in larger gain temper- Therefore, an op amp is necessary to buffer the output voltage. ature coefficient errors. Instead, the circuit of Figure 36 shows The reference input no longer sees a constant input impedance, the recommended method for increasing the gain of the circuit. but one that varies with code. Therefore, the voltage input R1, R2, and R3 should have similar temperature coefficients, should be driven from a low impedance source. but they need not match the temperature coefficients of the DAC. V DD This approach is recommended in circuits where gains of greater R R 1 2 than 1 are required. R A V FB DD V I 1A IN OUT V OUT V A REF I 2A OUT GND NOTES 1. SIMILAR CONFIGURATION FOR DAC B. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 34. Single-Supply Voltage-Switching Mode Rev. B | Page 15 of 24 04463-009 04463-010 AD5405 V DD Because only a fraction, D, of the current into the V terminal REF is routed to the I 1 terminal, the output voltage changes as OUT C1 follows: V R A DD FB R1 I 1A OUT V 12-BIT Output Error Voltage Due to DAC Leakage = (Leakage × R)/D IN V A V REF OUT DAC I 2A OUT R3 GND where R is the DAC resistance at the VREF terminal. GAIN = R2 + R3 R2 R2 For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that NOTES R1 = R2R3 is, 1/D) of 16, the error voltage is 1.6 mV. 1. SIMILAR CONFIGURATION FOR DAC B. R2 + R3 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. REFERENCE SELECTION When selecting a reference for use with the AD54xx series of Figure 36. Increasing Gain of Current Output DAC current output DACs, pay attention to the reference’s output voltage temperature coefficient specification. This parameter not DIVIDER OR PROGRAMMABLE GAIN ELEMENT only affects the full-scale error, but also can affect the linearity Current-steering DACs are very flexible and lend themselves to (INL and DNL) performance. The reference temperature coef- many applications. If this type of DAC is connected as the ficient should be consistent with the system accuracy specifica- feedback element of an op amp and RFBA is used as the input tions. For example, an 8-bit system required to hold its overall resistor, as shown in Figure 37, the output voltage is inversely specification to within 1 LSB over the temperature range 0°C to proportional to the digital input fraction, D. 50°C dictates that the maximum system drift with temperature −n should be less than 78 ppm/°C. A 12-bit system with the same For D = 1 − 2 , the output voltage is temperature range to overall specification within 2 LSBs requires −n a maximum drift of 10 ppm/°C. Choosing a precision reference V =− V D=− V() 1 − 2 OUT IN IN with low output temperature coefficient minimizes this error V DD source. V IN Table 7 lists some references available from Analog Devices that R A V FB DD are suitable for use with this range of current output DACs. 1A I OUT V A REF I 2A OUT AMPLIFIER SELECTION GND The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the V OUT variable gain of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the NOTES output voltage due to the amplifier’s input offset voltage. This 1. ADDITIONAL PINS OMITTED FOR CLARITY. output voltage change is superimposed on the desired change in Figure 37. Current-Steering DAC Used as a Divider or output between the two codes and gives rise to a differential Programmable Gain Element linearity error, which, if large enough, could cause the DAC to be nonmonotonic. As D is reduced, the output voltage increases. For small values of the digital fraction D, it is important to ensure that The input bias current of an op amp also generates an offset at the amplifier does not saturate and that the required accuracy is the voltage output as a result of the bias current flowing in the met. For example, an 8-bit DAC driven with the binary code 0x10 feedback resistor, R . Most op amps have input bias currents low FB (0001 0000)—that is, 16 decimal—in the circuit of Figure 37 enough to prevent significant errors in 12-bit applications. should cause the output voltage to be 16 times V . However, if IN the DAC has a linearity specification of ±0.5 LSB, D can have a Common-mode rejection of the op amp is important in weight in the range of 15.5/256 to 16.5/256 so that the possible voltage-switching circuits, because it produces a code- output voltage is in the range of 15.5 VIN to 16.5 VIN—an error dependent error at the voltage output of the circuit. Most of 3%, even though the DAC itself has a maximum error of 0.2%. op amps have adequate common-mode rejection for use at 12-bit resolution. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an Provided that the DAC switches are driven from true wideband, opposite current supplied from the op amp through the DAC. low impedance sources (V and AGND), they settle quickly. IN Rev. B | Page 16 of 24 04463-012 04463-011 AD5405 Consequently, the slew rate and settling time of a voltage- Most single-supply circuits include ground as part of the analog switching DAC circuit is determined largely by the output op signal range, which in turn requires an amplifier that can amp. To obtain minimum settling time in this configuration, handle rail-to-rail signals. Analog Devices offers a wide range of single-supply amplifiers, as listed in Table 8 and Table 9. minimize capacitance at the VREF node (the voltage output node in this application) of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. Table 7. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. B | Page 17 of 24 AD5405 8xC51-to-AD5405 Interface PARALLEL INTERFACE Figure 39 shows the interface between the AD5405 and the Data is loaded into the AD5405 in a 12-bit parallel word format. 8xC51 family of DSPs. To facilitate external data memory Control lines CS and R/W allow data to be written to or read access, the address latch enable (ALE) mode is enabled. The low from the DAC register. A write event takes place when and CS byte of the address is latched with this output pulse during R/W are brought low, data available on the data lines fills the access to the external memory. AD0 to AD7 are the multiplexed shift register, and the rising edge of latches the data and CS low order addresses and data bus; they require strong internal transfers the latched data-word to the DAC register. The DAC pull-ups when emitting 1s. During access to external memory, latches are not transparent; therefore, a write sequence must A8 to A15 are the high order address bytes. Because these ports consist of a falling and rising edge on CS to ensure that data is are open drained, they also require strong internal pull-ups loaded into the DAC register and that its analog equivalent is when emitting 1s. reflected on the DAC output. A read event takes place when A8 TO A15 ADDRESS BUS R/W is held high and CS is brought low. Data is loaded from the DAC register, goes back into the input register, and is output 1 onto the data line, where it can be read back to the controller for AD5405 1 8051 verification or diagnostic purposes. The input and DAC ADDRESS registers of these devices are not transparent; therefore, a falling CS DECODER and rising edge of CS is required to load each data-word. WR R/W MICROPROCESSOR INTERFACING DB0 TO DB11 8-BIT ALE ADSP-21xx-to-AD5405 Interface LATCH Figure 38 shows the AD5405 interfaced to the ADSP-21xx AD0 TO AD7 DATA BUS series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD5405 to the ADSP-21xx, 1 ADDITIONAL PINS OMITTED FOR CLARITY. depending on the clock speed of the DSP. The wait state can be Figure 39. 8xC51-to-AD5405 Interface programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family’s user manual for ADSP-BF5xx-to-AD5405 Interface details). Figure 40 shows a typical interface between the AD5405 and the ADDR TO 0 ADDRESS BUS ADSP-BF5xx family of DSPs. The asynchronous memory write ADRR 13 cycle of the processor drives the digital inputs of the DAC. The AMSx line is actually four memory select lines. Internal ADDR 1 AD5405 1 ADSP-21xx lines are decoded into AMS3–0; these lines are then inserted as ADDRESS DMS chip selects. The rest of the interface is a standard handshaking CS DECODER operation. WR R/W ADDR TO 1 ADDRESS BUS ADRR 19 DB0 TO DB11 1 AD5405 1 ADSP-BF5xx DATA 0 TO DATA BUS DATA 23 ADDRESS AMSx CS DECODER 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 38. ADSP21xx-to-AD5405 Interface AWE R/W DB0 TO DB11 DATA 0 TO DATA BUS DATA 23 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 40. ADSP-BF5xx-to-AD5405 Interface Rev. B | Page 18 of 24 04463-049 04463-050 04463-051 AD5405 possible with a double-sided board. In this technique, the PCB LAYOUT AND POWER SUPPLY DECOUPLING component side of the board is dedicated to the ground plane, In any circuit where accuracy is important, careful consider- and signal traces are placed on the soldered side. ation of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on It is good practice to use compact, minimum lead length PCB which the AD5405 is mounted should be designed so that the layout design. Leads to the input should be as short as possible analog and digital sections are separated and confined to to minimize IR drops and stray inductance. certain areas of the board. If the DAC is in a system where The PCB metal traces between VREF and RFB should also be multiple devices require an AGND-to-DGND connection, the matched to minimize gain error. To maximize high frequency connection should be made at one point only. The star ground performance, the I-to-V amplifier should be located as close as point should be established as close as possible to the device. possible to the device. These DACs should have ample supply bypassing of 10 μF in EVALUATION BOARD FOR THE DACS parallel with 0.1 μF on the supply located as close as possible to the package, ideally right up against the device. The 0.1 μF The evaluation board consists of a DAC and a current-to- capacitor should have low effective series resistance (ESR) and voltage amplifier, the AD8065. Included on the evaluation low effective series inductance (ESI), like the common ceramic board is a 10 V reference, the ADR01. An external reference may also be applied via an SMB input. types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal The evaluation kit consists of a CD-ROM with self-installing logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic PC software to control the DAC. The software simply allows the capacitors should also be applied at the supplies to minimize user to write a code to the device. transient disturbance and filter out low frequency ripple. POWER SUPPLIES FOR THE EVALUATION BOARD Components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise The board requires ±12 V and +5 V supplies. The +12 V V DD to other parts of the board, and they should never be run near and −12 V VSS are used to power the output amplifier; the +5 V is used to power the DAC (V ) and transceivers (V ). the reference inputs. DD1 CC Both supplies are decoupled to their respective ground plane Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each with 10 μF tantalum and 0.1 μF ceramic capacitors. other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best, but its use is not always Rev. B | Page 19 of 24 AD5405 Figure 41. Schematic of AD5405 Evaluation Board Figure 42. Component-Side Artwork Rev. B | Page 20 of 24 04463-045 04463-046 AD5405 Figure 43. Silkscreen—Component-Side View (Top Layer) Figure 44. Solder-Side Artwork Rev. B | Page 21 of 24 04463-048 04463-047 AD5405 OVERVIEW OF AD54xx DEVICES Table 10. 1 Part No. Resolution No. DACs INL (LSB) Interface Package Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40-1 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. B | Page 22 of 24 AD5405 OUTLINE DIMENSIONS 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 1 30 PIN 1 0.50 INDICATOR TOP 4.25 BSC 5.75 EXPOSED VIEW 4.10 SQ BSC SQ PAD 3.95 (BOT TOM VIEW) 0.50 0.40 21 10 20 11 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.02 NOM 1.00 THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.23 0.80 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution INL (LSB) Temperature Range Package Description Package Option AD5405YCP 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 AD5405YCP–REEL 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 AD5405YCP–REEL7 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 AD5405YCPZ 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 AD5405YCPZ–REEL 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 AD5405YCPZ–REEL7 12 ±1 −40°C to +125°C 40-Lead LFCSP_VQ CP-40-1 EVAL-AD5405EB Evaluation Kit 1 Z = RoHS Compliant Part. Rev. B | Page 23 of 24 072108-A AD5405 NOTES © 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04463–0–12/09(B) Rev. B | Page 24 of 24