ANALOG DEVICES AD5398

2 ® 120 mA, Current Sinking, 10-Bit, I C DAC AD5398 FEATURES FUNCTIONAL BLOCK DIAGRAM V 120 mA current sink DD 6 Available in 8-lead LFCSP package Available in 3 x 3 array WLCSP package POWER-ON REFERENCE RESET AD5398 2 2-wire (I C®-compatible) serial interface 10-bit resolution SDA 3 10-BIT Integrated current sense resistor 2 I C SERIAL 8 I CURRENT SINK INTERFACE OUTPUT DAC SCL 4 2.7 V to 5.5 V power supply Guaranteed monotonic over all codes R SENSE Power-down to 0.5 μA typical R 3.3Ω PD 1 Internal reference 5 2 7 Ultralow noise preamplifier DGND DGND AGND Power-down function Figure 1. Power-on reset CONSUMER APPLICATIONS GENERAL DESCRIPTION Lens autofocus The AD5398 is a single 10-bit DAC with 120 mA output Image stabilization current sink capability. It features an internal reference and Optical zoom operates from a single 2.7 V to 5.5 V supply. The DAC is Shutters 2 controlled via a 2-wire (I C-compatible) serial interface that Iris/exposure operates at clock rates up to 400 kHz. Neutral density (ND) filters Lens covers The AD5398 incorporates a power-on reset circuit, which Camera phones ensures that the DAC output powers up to 0 V and remains Digital still cameras there until a valid write takes place. It has a power-down feature that reduces the current consumption of the device to Camera modules 1 μA maximum. Digital video cameras/camcorders Camera-enabled devices The AD5398 is designed for autofocus, image stabilization, Security cameras and optical zoom applications in camera phones, digital still Web/PC cameras cameras, and camcorders. INDUSTRIAL APPLICATIONS The AD5398 also has many industrial applications, such as Heater control controlling temperature, light, and movement, over the range Fan control −40°C to +85°C without derating. Cooler (Peltier) control 2 Solenoid control The I C address range for the AD5398 is 0x18 to 0x1F Valve control inclusive. Linear actuator control Light control Current loop control Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05034-001 AD5398 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................6 Consumer Applications ................................................................... 1 Typical Performance Characteristics ..............................................8 Industrial Applications .................................................................... 1 Terminology.................................................................................... 10 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Serial Interface ............................................................................ 11 2 Revision History ............................................................................... 2 I C Bus Operation ...................................................................... 11 Specifications..................................................................................... 3 Data Format ................................................................................ 11 AC Specifications.......................................................................... 4 Power Supply Bypassing and Grounding................................ 12 Timing Specifications .................................................................. 4 Applications..................................................................................... 14 Absolute Maximum Ratings............................................................ 5 Outline Dimensions....................................................................... 15 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 15 REVISION HISTORY 12/05—Rev. A to Rev. B Inserted Figure 4 and Table 6.......................................................... 6 Inserted Figure 5............................................................................... 7 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 7/05—Rev. 0 to Rev. A Changes to Table 4............................................................................ 5 Deleted Figure 21............................................................................ 13 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 12/04—Revision 0: Initial Version Rev. B | Page 2 of 16 AD5398 SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Version Parameter Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with reduced performance Resolution 10 Bits 117 μA/LSB 2 Relative Accuracy ±1.5 ±4 LSB 2, 3 Differential Nonlinearity ±1 LSB Guaranteed monotonic over all codes 2, 4 Zero Code Error 0 1 5 mA All 0s loaded to DAC 2 Offset Error @ Code 16 0.5 mA 2 Gain Error ±0.6 % of FSR @ 25°C 4, 5 Offset Error Drift 10 μA/°C 2, 5 Gain Error Drift ±0.2 ±0.5 LSB/°C OUTPUT CHARACTERISTICS 4 Minimum Sink Current 3 mA Maximum Sink Current 120 mA V = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V but DD specified maximum sink current might not be achieved Output Current During PD 80 nA PD = 1 5 Output Compliance 0.6 VDD V Output voltage range over which max sink current is available Power-Up Time 20 μs To 10% of FS, coming out of power-down mode; V = 5 V DD 5 LOGIC INPUTS (PD) Input Current ±1 μA Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V INL DD Input High Voltage, V 0.7 V V V = 2.7 V to 5.5 V INH DD DD Pin Capacitance 3 pF 5 LOGIC INPUTS (SCL, SDA) Input Low Voltage, V −0.3 0.3 V V INL DD V + 0.3 Input High Voltage, VINH 0.7 VDD DD V Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD Input Hysteresis, VHYST 0.05 VDD V Digital Input Capacitance, C 6 pF IN 6 Glitch Rejection 50 ns Pulse width of spike suppressed POWER REQUIREMENTS V 2.7 5.5 V DD I (Normal Mode) I specification is valid for all DAC codes DD DD VDD = 2.7 V to 5.5 V 2.5 4 mA VIH = VDD, VIL = GND, VDD = 5.5 V VDD = 2.7 V to 4.5 V 2.3 3 mA VIH = VDD, VIL = GND, VDD = 4.5 V IDD (Power-Down Mode) 0.5 1 μA VIH = VDD, VIL = GND 1 Temperature range is as follows: B Version: −40°C to +85°C. 2 See the Terminology section. 3 Linearity is tested using a reduced code range: Codes 32 to 1023. 4 To achieve near zero output current, use the power-down feature. 5 Guaranteed by design and characterization; not production tested. 6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. Rev. B | Page 3 of 16 AD5398 AC SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted. Table 2. 1, 2 B Version Parameter Min Typ Max Unit Test Conditions/Comments Output Current Settling Time 250 μs VDD = 5 V, RL = 25 Ω, LL = 680 μH ¼ scale to ¾ scale change (0x100 to 0x300) Slew Rate 0.3 mA/μs Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry 3 Digital Feedthrough 0.06 nA-s 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section. TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. B Version 1 Parameter Unit Description Limit at TMIN, TMAX f 400 kHz max SCL clock frequency SCL t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t 0.6 μs min t , start/repeated start condition hold time 4 HD, STA t 100 ns min t , data setup time 5 SU, DAT 2 t6 0.9 μs max tHD, DAT, data hold time 0 μs min t7 0.6 μs min tSU, STA, setup time for repeated start t 0.6 μs min t , stop condition setup time 8 SU, STO t 1.3 μs min t , bus free time between a stop condition and a start condition 9 BUF t 300 ns max t rise time of both SCL and SDA when receiving 10 R, 0 ns min May be CMOS driven t11 250 ns max tF, fall time of SDA when receiving 300 ns max tF, fall time of both SCL and SDA when transmitting 3 20 + 0.1 C ns min b C 400 pF max Capacitive load for each bus line b 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD. SDA t t t 3 4 9 t t 10 11 SCL t t t t t t 2 t 7 1 8 4 6 5 START REPEATED STOP CONDITION START CONDITION CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. B | Page 4 of 16 05034-002 AD5398 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND –0.3 V to +7 V DD rating only; functional operation of the device at these or any V to DGND –0.3 V to V + 0.3 V DD DD other conditions above those listed in the operational sections AGND to DGND –0.3 V to +0.3 V of this specification is not implied. Exposure to absolute SCL, SDA to DGND –0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect PD to DGND –0.3 V to VDD + 0.3 V device reliability. Only one absolute maximum rating may be I to AGND –0.3 V to V + 0.3 V SINK DD applied at any one time. Operating Temperature Range Industrial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C Junction Temperature (TJ max) 150°C LFCSP Power Dissipation (TJ max − TA)/θJA 2 θ Thermal Impedance JA Mounted on 2-Layer Board 84°C/W Mounted on 4-Layer Board 48°C/W Lead Temperature, Soldering 3 Max Peak Reflow Temperature 260°C (±5°C) 1 Transient currents of up to 100 mA do not cause SCR latch-up. 2 To achieve the optimum θJA, it is recommended that the AD5398 is soldered on a 4-layer board. The AD5398 comes in an 8-lead LFCSP package with an exposed paddle that should be connected to the same potential as the AD5398 DGND pin. 3 As per Jedec J-STD-020C. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 16 AD5398 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PD 1 8 I SINK DGND 2 AD5398 7 AGND TOP VIEW SDA 3 6 V DD (Not to Scale) SCL 4 5 DGND Figure 3. 8-Lead LFSCP Pin Configuration Table 5. 8-Lead LFSCP Pin Function Description Pin No. Mnemonic Description 1 PD Power Down. Asynchronous power-down signal. 2 DGND Digital Ground Pin. 2 3 SDA I C Interface Signal. 2 4 SCL I C Interface Signal. 5 DGND Digital Ground Pin. 6 VDD Digital Supply Voltage. 7 AGND Analog Ground Pin. 8 ISINK Output Current Sink. 3 2 1 A B C VIEW FROM BALL SIDE Figure 4. 9-Ball WLCSP Pin Configuration Table 6. 9-Ball WLCSP Pin Function Description Ball Number Mnemonic Description A1 ISINK Output Current Sink. A2 NC No Connection. A3 PD Power Down. Asynchronous power-down signal. B1 AGND Analog Ground Pin. B2 DGND Digital Ground Pin. 2 B3 SDA I C Interface Signal. C1 DGND Digital Ground Pin. C2 VDD Digital Supply Voltage. 2 C3 SCL I C Interface Signal. Rev. B | Page 6 of 16 05034-021 05034-003 AD5398 1400μm PD 1 I SINK 8 AGND 7 DGND 2 1690μm SDA V 3 DD 6 SCL DGND 4 5 Figure 5. Metallization Photograph Dimensions shown in μm Contact Factory for Latest Dimensions Rev. B | Page 7 of 16 05034-023 AD5398 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 VERT = 50μs/DIV INL V = 3.8V DD TEMP = 25°C 1.5 1.0 0.5 3 0 HORIZ = 468μA/DIV –0.5 CH3 M50.0μs CODE Figure 6. Typical INL Plot Figure 9. Settling Time for a 4-LSB Step (VDD = 3.6 V) 0.6 DNL V = 3.8V DD VERT = 2μA/DIV 4.8μA p-p TEMP = 25°C 0.5 0.4 0.3 0.2 1 0.1 0 –0.1 –0.2 HORIZ = 2s/DIV –0.3 CH1 M2.0s CODE Figure 7. Typical DNL Plot Figure 10. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V) 92.0 0.14 I @ +25°C OUT 91.5 0.12 I @ –40°C OUT 91.0 0.10 90.5 I @ +85°C OUT 0.08 90.0 0.06 89.5 0.04 89.0 0.02 88.5 88.0 0 –6 –6 –6 –6 –6 –6 –6 53.5 100.0 150.0 200.0 250.0 300.0 333.1 TIME CODE Figure 8. ¼ to ¾ Scale Settling Time (VDD = 3.6 V) Figure 11. Sink Current vs. Code vs. Temperature (VDD = 3.6 V) Rev. B | Page 8 of 16 OUTPUT CURRENT (mA) DNL (LSB) INL (LSB) 0 0 56 56 112 112 168 168 224 224 280 280 336 336 392 392 448 448 504 504 560 560 616 616 672 672 728 728 784 784 840 840 896 896 952 952 1008 1008 1023 1023 05034-006 05034-005 05034-004 I (A) OUT 0 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 05034-008 05034-007 1023 05034-009 AD5398 2000 0.45 V = 3.6V DD 1800 0.40 1600 0.35 1400 0.30 V = 4.5V DD 1200 V = 3.8V DD 0.25 1000 0.20 800 0.15 600 0.10 400 0.05 200 0 0 –40–30–20–100 15 2535 455565 75 85 10 100 1k 10k 100k FREQUENCY TEMPERATURE (°C) Figure 12. AC Power Supply Rejection (VDD = 3.6 V) Figure 15. Zero Code Error vs. Supply Voltage vs. Temperature 3.5 1.5 V = 4.5V DD 3.0 1.0 POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V) DD DD 2.5 0.5 2.0 V = 3.8V DD 0 1.5 POSITIVE INL (V = 3.6V) DD 1.0 –0.5 0.5 NEGATIVE INL (V = 3.6V) DD –1.0 NEGATIVE INL (V = 3.8V) DD 0 –1.5 –0.5 V = 3.6V DD NEGATIVE INL (V = 4.5V) DD –1.0 –2.0 –40–30–20–100 15 2535 455565 75 85 –40–30–20–100 15 2535 455565 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. INL vs. Temperature vs. Supply Figure 16. Full-Scale Error vs. Temperature vs. Supply 1.0 0.8 0.6 POSITIVE DNL (V = 3.6V) DD 0.4 POSITIVE DNL (V = 4.5V) DD 0.2 0 POSITIVE DNL (V = 3.8V) = 3.8V) NEGATIVE DNL (V DD DD –0.2 –0.4 –0.6 NEGATIVE DNL (V = 4.5V) DD NEGATIVE DNL (V = 3.6V) DD –0.8 –1.0 –40–30–20–100 15 2535 455565 75 85 TEMPERATURE (°C) Figure 14. DNL vs. Temperature vs. Supply Rev. B | Page 9 of 16 DNL (LSB) INL (LSB) μA/V 05034-012 05034-011 05034-010 FS ERROR (mA) ZERO CODE ERROR (mA) 05034-096 05034-013 AD5398 TERMINOLOGY Relative Accuracy Gain Error Drift For the DAC, relative accuracy or integral nonlinearity is a This is a measurement of the change in gain error with changes measurement of the maximum deviation, in LSB, from a in temperature. It is expressed in LSB/°C. straight line passing through the endpoints of the DAC transfer Digital-to-Analog Glitch Impulse function. A typical INL vs. code plot is shown in Figure 6. Digital-to-analog glitch impulse is the impulse injected into the Differential Nonlinearity (DNL) analog output when the input code in the DAC register changes Differential nonlinearity is the difference between the measured state. It is normally specified as the area of the glitch in nA-s change and the ideal 1 LSB change between any two adjacent and is measured when the digital input code is changed by codes. A specified differential nonlinearity of ±1 LSB maximum 1 LSB at the major carry transition. ensures monotonicity. This DAC is guaranteed monotonic by Digital Feedthrough design. A typical DNL vs. code plot is shown in Figure 7. Digital feedthrough is a measurement of the impulse injected Zero-Code Error into the analog output of the DAC from the digital inputs of the Zero-code error is a measurement of the output error when DAC, but is measured when the DAC output is not updated. It zero code (0x0000) is loaded to the DAC register. Ideally, the is specified in nA-s and measured with a full-scale code change output is 0 mA. The zero-code error is always positive in the on the data bus, that is, from all 0s to all 1s and vice versa. AD5398 because the output of the DAC cannot go below 0 mA. Offset Error This is due to a combination of the offset errors in the DAC and Offset error is a measurement of the difference between ISINK output amplifier. Zero-code error is expressed in mA. (actual) and IOUT (ideal) in the linear region of the transfer Gain Error function, expressed in mA. Offset error is measured on the This is a measurement of the span error of the DAC. It is the AD5398 with Code 16 loaded into the DAC register. deviation in slope of the DAC transfer characteristic from the Offset Error Drift ideal, expressed as a percent of the full-scale range. This is a measurement of the change in offset error with a change in temperature. It is expressed in μV/°C. Rev. B | Page 10 of 16 AD5398 THEORY OF OPERATION The AD5398 is a fully integrated 10-bit DAC with 120 mA When the bus is idle, SCL and SDA are both high. The master output current sink capability and is intended for driving voice device initiates a serial bus operation by generating a start coil actuators in applications such as lens autofocus, image sta- condition, which is defined as a high-to-low transition on the bilization, and optical zoom. The circuit diagram is shown in SDA low while SCL is high. The slave device connected to the Figure 17. A 10-bit current output DAC coupled with Resistor R bus responds to the start condition and shifts in the next eight generates the voltage that drives the noninverting input of the data bits under control of the serial clock. These eight data bits operational amplifier. This voltage also appears across the R consist of a 7-bit address, plus a read/write bit, which is 0 if data SENSE resistor and generates the sink current required to drive the is to be written to a device, and 1 if data is to be read from a 2 voice coil. device. Each slave device on an I C bus must have a unique address. The address of the AD5398 is 0001100; however, Resistors R and RSENSE are interleaved and matched. Therefore, 0001101, 0001110, and 0001111 address the part because the the temperature coefficient and any nonlinearities over tem- last two bits are unused/don’t care (see Figure 19 and Figure 20). perature are matched and the output drift over temperature is Since the address plus R/W bit always equals eight bits of data, minimized. Diode D1 is an output protection diode. another way of looking at it is that the write address of the V AD5398 is 0001 1000 (0x18) and the read address is 0001 1001 BAT V DD (0x19). Again, Bit 6 and Bit 7 of the address are unused, and 6 therefore the write addresses can also be 0x1A, 0x1C, and 0x1E, VOICE POWER-ON REFERENCE COIL RESET AD5398 ACTUATOR and the read address can be 0x1B, 0x1D, and 0x1F (see Figure 19 and Figure 20). D1 SDA 3 10-BIT 2 I C SERIAL 8 CURRENT INTERFACE I At the end of the address data, after the R/W bit, the slave OUTPUT DAC SINK 4 SCL device that recognizes its own address responds by generating R SENSE an acknowledge (ACK) condition. This is defined as the slave R 3.3Ω PD 1 device pulling SDA low while SCL is low before the ninth clock 5 2 7 pulse, and keeping it low during the ninth clock pulse. Upon DGND DGND AGND receiving ACK, the master device can clock data into the Figure 17. Block Diagram Showing Connection to Voice Coil AD5398 in a write operation, or it can clock it out in a read operation. Data must change either during the low period of the SERIAL INTERFACE clock, because SDA transitions during the high period define a 2 start condition as described previously, or during a stop The AD5398 is controlled using the industry-standard I C condition as described in the Data Format section. 2-wire serial protocol. Data can be written to or read from the DAC at data rates up to 400 kHz. After a read operation, the 2 I C data is divided into blocks of eight bits, and the slave contents of the input register are reset to all zeros. generates an ACK at the end of each block. Since the AD5398 2 requires 10 bits of data, two data-words must be written to it I C BUS OPERATION when a write operation occurs, or read from it when a read 2 An I C bus operates with one or more master devices that operation occurs. At the end of a read or write operation, the generate the serial clock (SCL), and read/write data on the serial AD5398 acknowledges the second data byte. The master data line (SDA) to/from slave devices such as the AD5398. All generates a stop condition, defined as a low-to-high transition 2 devices on an I C bus have their SCL pin connected to the SDA on SDA while SCL is high, to end the transaction. 2 line and their SCL pin connected to the SCL line. I C devices can only pull the bus lines low; pulling high is achieved by pull- DATA FORMAT up resistors RP. The value of RP depends on the data rate, bus Data is written to the AD5398 high byte first, MSB first, and is 2 capacitance, and the maximum load current that the I C device shifted into the 16-bit input register. After all data is shifted in, can sink (3 mA for a standard device). data from the input register is transferred to the DAC register. V DD Because the DAC requires only 10 bits of data, not all bits of the R R P P SDA input register data are used. The MSB is reserved for an active- SCL high, software-controlled, power-down function. Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC data bits, Bit 9 to 2 2 2 I C MASTER I C SLAVE I C SLAVE Bit 0. Bit 3 to Bit 0 are unused. AD5398 DEVICE DEVICE DEVICE 2 During a read operation, data is read in the same bit order. Figure 18. Typical I C Bus Rev. B | Page 11 of 16 05034-016 05034-015 AD5398 1191 9 SCL 00 0 1 1 X X R/W PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5398 AD5398 AD5398 MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 19. Write Operation 1191 9 SCL 00 0 1 1 X X R/W SDA PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5398 AD5398 AD5398 MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 20. Read Operation 1 Table 7. Data Format Serial Data-Words High Byte Low Byte Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Function PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 PD = soft power-down; X = unused/don’t care; D9 to D0 = DAC data. POWER SUPPLY BYPASSING AND GROUNDING V BAT When accuracy is important in an application, it is beneficial to consider power supply and ground return layout on the PCB. VOICE COIL The PCB for the AD5398 should have separate analog and L C ACTUATOR digital power supply sections. Where shared AGND and DGND V C R C is necessary, the connection of grounds should be made at only TRACE one point, as close as possible to the AD5398. RESISTANCE R T V T 8 Special attention should be paid to the layout of the AGND I Q1 SINK return path and track between the voice coil motor and I to SINK minimize any series resistance. Figure 21 shows the output R SENSE V 3.3Ω DROP current sink of the AD5398 and illustrates the importance of reducing the effective series impedance of AGND, and the track 7 resistance between the motor and ISINK. The voice coil is AGND GROUND R modelled as inductor LC and resistor RC. The current through G RESISTANCE the voice coil is effectively a dc current that results in a voltage V G GROUND L G drop, V , when the AD5398 is sinking current; the effect of any C INDUCTANCE series inductance is minimal. The maximum voltage drop allowed across R is 400 mV, and the minimum drain to SENSE Figure 21. Effect of PCB Trace Resistance and Inductance source voltage of Q1 is 200 mV. This means that the AD5398 output has a compliance voltage of 600 mV. If VDROP falls below 600 mV, the output transistor, Q1, can no longer operate properly and ISINK might not be maintained as a constant. Rev. B | Page 12 of 16 05034-019 05034-018 05034-017 AD5398 For this reason it is important to minimize any series impedance As the current increases through the voice coil, V increases C on both the ground return path and interconnect between the and V decreases and eventually approaches the minimum DROP AD5398 and the motor. specified compliance voltage of 600 mV. The ground return path is modelled by the components RG and LG. The track The power supply of the AD5398 should be decoupled with resistance between the voice coil and the AD5398 is modelled as 0.1 μF and 10 μF capacitors. These capacitors should be kept as RT. The inductive effects of LG influence RSENSE and RC equally, physically close as possible, with the 0.1 μF capacitor serving as and because the current is maintained as a constant, it is not as a local bypass capacitor, and therefore should be located as close critical as the purely resistive component of the ground return as possible to the V pin. The 10 μF capacitor should be a DD path. When the maximum sink current is flowing through the tantalum bead-type; the 0.1 μF capacitor should be a ceramic motor, the resistive elements, R and R , might have an impact T G type with a low effective series resistance and effective series on the voltage headroom of Q1 and could, in turn, limit the inductance. The 0.1 μF capacitor provides a low impedance path maximum value of RC because of voltage compliance. to ground for high transient currents. For example: The power supply line should have as large a trace as possible to VBAT = 3.6 V provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals RG = 0.5 Ω should be shielded from other parts of the board by digital R = 0.5 Ω T ground. Avoid crossover of digital and analog signals if possible. I = 120 mA When traces cross on opposite sides of the board, ensure that SINK they run at right angles to each other to reduce feedthrough V = 600 mV (the compliance voltage) DROP effects through the board. The best board layout technique is to Then the largest value of resistance of the voice coil, RC, is use a multilayer board with ground and power planes, where the component side of the board is dedicated to the ground V −[V + (I ×R )+ (I ×R )] DROP SINK SINK G BAT T plane only and the signal traces are placed on the solder side. R = = C I SINK However, this is not always possible with a 2-layer board. 3.6 V−[600 mV+ 2×(120 mA×0.5 Ω)] The exposed paddle on the AD5398 should be soldered to = 24 Ω ground to ensure the best possible thermal performance. The 120 mA thermal impedance of the AD5398 LFCSP package is 48°C/W when soldered in a 4-layer board. It is defined in the Absolute Maximum Ratings section. Rev. B | Page 13 of 16 AD5398 APPLICATIONS The AD5398 is designed to drive both spring preloaded and 0.5 nonspring linear motors used in applications such as lens auto- focus, image stabilization, or optical zoom. The operation 0.4 principle of the spring-preloaded motor is that the lens position is controlled by the balancing of a voice coil and spring. Figure 22 0.3 shows the transfer curve of a typical spring preloaded linear motor for autofocus. The key points of this transfer function are displacement or stroke, which is the actual distance the lens 0.2 moves in mm, and the current through the motor in mA. START CURRENT 0.1 A start current is associated with spring-preloaded linear motors, which is effectively a threshold current that must be 0 exceeded for any displacement in the lens to occur. The start 0 10 20 30 40 50 60 70 80 90 100 110 120 current is usually 20 mA or greater; the rated stroke or SINK CURRENT (mA) displacement is usually 0.25 mm to 0.4 mm; and the slope of Figure 22. Spring Preloaded Voice Coil Stroke vs. Sink Current the transfer curve is approximately 10 μm/mA or less. The AD5398 is designed to sink up to 120 mA, which is more than adequate for available commercial linear motors or voice coils. Another factor that makes the AD5398 the ideal solution for these applications is the monotonicity of the device, which ensures that lens positioning is repeatable for the application of a given digital word. Figure 23 shows a typical application circuit for the AD5398. V V DD CC + + 0.1μF 10μF 10μF 0.1μF 6 POWER-DOWN VOICE POWER-ON RESET REFERENCE COIL RESET AD5398 1 ACTUATOR V DD R R P P SDA 10-BIT 3 2 I C SERIAL 8 CURRENT INTERFACE SCL OUTPUT DAC 4 2 2 2 R I C MASTER I C SLAVE I C SLAVE SENSE R DEVICE DEVICE DEVICE 3.3Ω 5 2 7 Figure 23. Typical Application Circuit Rev. B | Page 14 of 16 STROKE (mm) 05034-020 05034-022 AD5398 OUTLINE DIMENSIONS 0.65 0.59 1.575 0.53 1.515 SEATING 1.455 3 2 1 PLANE A 0.36 BALL 1 0.32 IDENTIFIER 1.750 0.28 1.690 B 1.630 C 0.50 BSC BALL PITCH TOP VIEW 0.28 BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.24 0.20 Figure 24. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9) Dimensions shown in millimeters 0.50 0.40 0.30 3.00 0.60 MAX PIN 1 BSC SQ INDICATOR 1 8 PIN 1 1.89 2.75 TOP 1.50 INDICATOR BSC SQ 1.74 VIEW REF 0.50 1.59 BSC 5 4 1.60 0.70 MAX 1.45 12° MAX 0.90 MAX 0.65 TYP 1.30 0.85 NOM 0.05 MAX 0.01 NOM SEATING 0.30 0.20 REF PLANE 0.23 0.18 Figure 25. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD5398BCBZ-REEL7 −40°C to +85°C 9-Ball Wafer Level Chip Scale (WLCSP) CB-9 1 AD5398BCPZ-REEL –40°C to +85°C 8-Lead LFCSP_VD CP-8-2 1 AD5398BCPZ-REEL7 –40°C to +85°C 8-Lead LFCSP_VD CP-8-2 1 AD5398BCPZ-WP –40°C to +85°C 8-Lead LFCSP_VD CP-8-2 AD5398ZCSURF –40°C to +150°C Die Form EVAL-AD5398EB Evaluation Board 1 Z = Pb-free part. Rev. B | Page 15 of 16 110405-0 AD5398 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05034-0-12/05(B) Rev. B | Page 16 of 16