ANALOG DEVICES AD5390

8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output Data Sheet AD5390/AD5391/AD5392 2 FEATURES I C-compatible interface Integrated functions AD5390: 16-channel, 14-bit voltage output DAC channel monitor AD5391: 16-channel, 12-bit voltage output DAC simultaneous output update via LDAC AD5392: 8-channel, 14-bit voltage output DAC clear function to user-programmable code Guaranteed monotonic amplifier boost mode to optimize slew rate INL user-programmable offset and gain adjust ±1 LSB max (AD5391) toggle mode enables square wave generation ±3 LSB max (AD5390-5/AD5392-5) thermal monitor ±4 LSB max (AD5390-3/AD5392-3) Robust 6.5 kV HBM and 2 kV FICDM ESD rating On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: −40°C to +85°C APPLICATIONS Rail-to-rail output amplifier Instrumentation and industrial control Power-down mode Power amplifier control Package types Level setting (ATE) 64-lead LFCSP (9 mm × 9 mm) Control systems 52-lead LQFP (10 mm × 10 mm) Microelectromechanical systems (MEMs) User interfaces Variable optical attenuators (VOAs) Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible Optical transceivers (MSA 300, XFP) (featuring data readback) FUNCTIONAL BLOCK DIAGRAM DV (×3) DGND (×3/×4) AV (×2) AGND (×2) DAC_GND (×2) REF_GND REFOUT/REFIN SIGNAL_GND (×2) DD DD 1.25V/2.5V AD5390 REFERENCE 2 SPI/I C INPUT DAC 14 14 14 14 REG REG DAC 0 DCEN/AD1 0 0 VOUT 0 14 m REG0 DIN/SDA 14 STATE c REG0 R R INTERFACE MACHINE SCLK/SCL CONTROL AND SYNC/AD0 LOGIC CONTROL INPUT 14 DAC 14 14 14 LOGIC REG REG DAC 1 SDO 1 1 VOUT 1 14 m REG1 VOUT 2 14 R c REG1 VOUT 3 R BUSY VOUT 4 PD INPUT 14 DAC 14 14 14 VOUT 5 REG REG DAC 6 CLR 6 6 VOUT 6 POWER-ON 14 RESET m REG6 RESET 14 R c REG6 R V 0 V 15 IN IN INPUT 14 DAC 14 14 14 REG REG DAC 7 7 7 VOUT 7 14 MON_IN1 m REG7 VOUT 8 MUX 14 R c REG7 R MON_IN2 ×2 VOUT 15 MON_OUT LDAC Figure 1. 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Trademarks and registered trademarks are the property of their respective owners. 03773-001 AD5390/AD5391/AD5392 Data Sheet TABLE OF CONTENTS 2 Features .............................................................................................. 1 I C Serial Interface ..................................................................... 26 2 Applications ....................................................................................... 1 I C Write Operation ....................................................................... 27 Functional Block Diagram .............................................................. 1 4-Byte Mode ................................................................................ 27 Revision History ............................................................................... 2 3-Byte Mode ................................................................................ 28 General Description ......................................................................... 3 2-Byte Mode ................................................................................ 29 Specifications ..................................................................................... 4 AD539x On-Chip Special Function Registers ........................ 30 AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 4 Control Register Write ............................................................... 32 AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 6 Hardware Functions ....................................................................... 34 AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 7 Reset Function ............................................................................ 34 AD5390-3/AD5391-3/AD5392-3 AC Characteristics............. 9 Asynchronous Clear Function .................................................. 34 Timing Characteristics ................................................................... 10 BUSY and LDAC Functions...................................................... 34 Serial SPI-, QSPI-, MICROWIRE-, and DSP-Compatible Power-On Reset .......................................................................... 34 Interface ....................................................................................... 10 Power-Down ............................................................................... 34 2 I C Serial Interface ...................................................................... 12 Microprocessor Interfacing ....................................................... 34 Absolute Maximum Ratings .......................................................... 13 Application Information ................................................................ 36 ESD Caution ................................................................................ 13 Power Supply Decoupling ......................................................... 36 Pin Configuraton and Function Descriptions ............................ 14 Typical Configuration Circuit .................................................. 36 Terminology .................................................................................... 17 AD539x Monitor Function ....................................................... 37 Typical Performance Characteristics ........................................... 18 Toggle Mode Function ............................................................... 37 Functional Description .................................................................. 22 Thermal Monitor Function ....................................................... 37 DAC Architecture ....................................................................... 22 Outline Dimensions ....................................................................... 39 Data Decoding ............................................................................ 23 Ordering Guide .......................................................................... 40 Interfaces .......................................................................................... 24 DSP-, SPI-, and MICROWIRE-Compatible Serial Interface ....................................................................................... 24 REVISION HISTORY 5/12—Rev. C to Rev. D Change order of Figure 41 and Figure 42 .................................... 36 Changes to Toggle Mode Function Section ................................ 37 Changes to Product Title and Features Section ............................ 1 Changes to Table 2 ............................................................................ 4 3/06—Rev. A to Rev. B Changes to Table 3 ............................................................................ 6 Changes to Figure 1 ........................................................................... 1 Changes to Table 4 ............................................................................ 7 Changes to Table 9 .......................................................................... 14 Changes to Table 5 ............................................................................ 9 Changes to Table 12 and Table 15 ................................................ 23 Changes to Table 6 .......................................................................... 10 Updated Outline Dimensions ....................................................... 39 Changes to Table 8 .......................................................................... 13 Changes to Ordering Guide .......................................................... 40 Changes to Figure 8 and Figure 10 ............................................... 14 10/04—Rev. 0 to Rev. A Changes to Table 9 .......................................................................... 16 Changes to Features .......................................................................... 1 Changes to Figure 17, Figure 18, Figure 19, And Figure 22 ...... 19 Changes to Table 1 ............................................................................. 3 Changes to Figure 23, Figure 24, Figure 25, and Figure 26 ....... 20 Changes to Table 2 ............................................................................. 4 Changes to Table 26 ........................................................................ 32 Changes to Table 3 ............................................................................. 6 Changes to Ordering Guide .......................................................... 40 Changes to Table 4 ............................................................................. 7 1/09—Rev. B to Rev. C Changes to Figure 36 ...................................................................... 35 Updated Format .................................................................. Universal Changes to Figure 37 ...................................................................... 36 Changes to Figure 33 ...................................................................... 27 Changes to Figure 38 ...................................................................... 36 Added Figure 34 and Renumbered Sequentially ........................ 27 Changes to Ordering Guide .......................................................... 41 Changes to Figure 34 ...................................................................... 28 4/04—Revision 0: Initial Version Changes to Table 28 ........................................................................ 33 Rev. D | Page 2 of 40 Data Sheet AD5390/AD5391/AD5392 GENERAL DESCRIPTION The AD5390/AD5391 are complete single-supply, 16-channel, The AD5390/AD5391/AD5392 contain a 3-wire serial interface 14-bit and 12-bit DACs, respectively. The AD5392 is a complete with interface speeds in excess of 30 MHz that are compatible single-supply, 8-channel, 14-bit DAC. The devices are available with SPI®, QSPI™, MICROWIRE™, and DSP interface standards 2 in either a 64-lead LFCSP or a 52-lead LQFP. All channels have and an I C-compatible interface supporting a 400 kHz data an on-chip output amplifier with rail-to-rail operation. All transfer rate. devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an An input register followed by a DAC register provides double- on-chip channel monitor function that multiplexes the analog buffering, allowing DAC outputs to be updated independently outputs to a common MON_OUT pin for external monitoring, or simultaneously using the input. Each channel has a LDAC and an output amplifier boost mode that optimizes the output programmable gain and offset adjust register, letting the user amplifier slew rate. fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel. Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio Model Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description Package Option AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 Rev. D | Page 3 of 40 AD5390/AD5391/AD5392 Data Sheet SPECIFICATIONS AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS AV = 4.5 V to 5.5 V; DV = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications T to T , DD DD MIN MAX unless otherwise noted. Table 2. 1 AD5390-5 1 1 Parameter AD5392-5 AD5391-5 Unit Test Conditions/Comments ACCURACY Resolution 14 12 Bits Relative Accuracy ±3 ±1 LSB max Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 4 mV max Offset Error ±4 ±4 mV max Measured at Code 32 in the linear region (AD5390-5/AD5392-5); measured at Code 8 in the linear region (AD5391-5) Offset Error TC ±5 ±5 µV/°C typ Gain Error 0.05 0.05 % FSR max At 25°C TMIN to TMAX ±0.06 ±0.06 % FSR max 2 Gain Temperature Coefficient 2 2 ppm FSR/°C typ 2 DC Crosstalk 1 1 LSB max REFERENCE INPUT/OUTPUT 2 Reference Input Reference Input Voltage 2.5 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 1 MΩ min Typically 100 MΩ Input Current ±1 ±1 µA max Typically ±30 nA Reference Range 1 V to AV /2 1 V to AV /2 V min/max DD DD 3 Reference Output Enabled via internal/external bit in control register; REF select bit in control register selects the reference voltage Output Voltage 2.495/2.505 2.495/2.505 V min/max At ambient, optimized for 2.5 V operation 1.22/1.28 1.22/1.28 V min/max At ambient when 1.25 V reference is selected Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C ±15 ±15 ppm max Temperature range: −40°C to +85°C Output Impedance 800 800 Ω typ 2 OUTPUT CHARACTERISTICS 4 Output Voltage Range 0/AVDD 0/AVDD V min/max Short-Circuit Current 40 40 mA max Load Current ±1 ±1 mA max Capacitive Load Stability R = ∞ 200 200 pF max L R = 5 kΩ 1000 1000 pF max L DC Output Impedance 0.6 0.6 Ω max MONITOR OUTPUT PIN Output Impedance 1000 1000 Ω typ Three-State Leakage Current 100 100 nA typ 2 LOGIC INPUTS DV = 2.7 V to 5.5 V DD V , Input High Voltage 2 2 V min IH VIL, Input Low Voltage DVDD > 3.6 V 0.8 0.8 V max DVDD ≤ 3.6 V 0.6 0.6 V max Input Current ±10 ±10 µA max Total for all pins, T = T to T A MIN MAX Pin Capacitance 10 10 pF max Rev. D | Page 4 of 40 Data Sheet AD5390/AD5391/AD5392 1 AD5390-5 1 1 Parameter AD5392-5 AD5391-5 Unit Test Conditions/Comments LOGIC INPUTS (SCL, SDA Only) V , Input High Voltage 0.7 × DV 0.7 × DV V min SMBus-compatible at DV < 3.6 V IH DD DD DD V , Input Low Voltage 0.3 × DV 0.3 × DV V max SMBus-compatible at DV < 3.6 V IL DD DD DD I , Input Leakage Current ±1 ±1 µA max IN VHYST, Input Hysteresis 0.05 × DVDD 0.05 × DVDD V min CIN, Input Capacitance 8 8 pF typ Glitch Rejection 50 50 ns max Input filtering suppresses noise spikes of <50 ns 2 LOGIC OUTPUTS (BUSY, SDO) Output Low Voltage 0.4 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA Output High Voltage DV − 1 DV − 1 V min DV = 5 V ± 10%, SDO only, sourcing 200 µA DD DD DD Output Low Voltage 0.4 0.4 V max DV = 2.7 V to 3.6 V, sinking 200 µA DD Output High Voltage DV − 0.5 DV − 0.5 V min DV = 2.7 V to 3.6 V SDO only, sourcing 200 µA DD DD DD High Impedance Leakage Current ±1 ±1 µA max High Impedance Output Capacitance 5 5 pF typ 2 LOGIC OUTPUT (SDA) VOL, Output Low Voltage 0.4 0.4 V max ISINK = 3 mA 0.6 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 ±1 µA max Three-State Output Capacitance 8 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 4.5/5.5 V min/max DV 2.7/5.5 2.7/5.5 V min/max DD 2 Power Supply Sensitivity ∆Midscale/∆AVDD −85 −85 dB typ AIDD 0.375 0.375 mA/channel Outputs unloaded, boost off, max 0.25 mA/channel typ AI 0.475 0.475 mA/channel Outputs unloaded, boost on, DD max 0.325 mA/channel typ DI 1 1 mA max V = DV , V = DGND DD IH DD IL AIDD (Power-Down) 20 20 µA max Typically 100 nA DIDD (Power-Down) 20 20 µA max Typically 1 µA Power Dissipation 35 35 mW max AD5390/AD5391 with outputs unloaded, AV = DV = 5 V, boost off DD DD 20 20 mW max AD5392 with outputs unloaded, AVDD = DVDD = 5 V, boost off 1 AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C. 2 Guaranteed by characterization, not production tested. 3 Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in performance accuracy. 4 Accuracy guaranteed from VOUT = 10 mV to AV − 50 mV. DD Rev. D | Page 5 of 40 AD5390/AD5391/AD5392 Data Sheet AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 3. 1 Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time ¼ scale to ¾ scale change settling to ±1 LSB AD5390/AD5392 3 µs typ Boost mode off, CR11 = 0 8 µs max Boost mode off, CR11 = 0 AD5391 3 µs typ Boost mode off, CR11 = 0 8 µs max Boost mode off, CR11 = 0 2 Slew rate 2.5 V/µs typ Boost mode on 1.5 V/µs typ Boost mode off Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See the Terminology section DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise (0.1 Hz to 10 Hz) 15 µV p-p typ External reference midscale loaded to DAC 40 µV p-p typ Internal reference midscale loaded to DAC Output Noise Spectral Density 1/2 @ 1 kHz 150 nV/(Hz) typ 1/2 @ 10 kHz 100 nV/(Hz) typ 1 Guaranteed by characterization, not production tested. 2 The slew rate can be adjusted via the current boost control bit in the DAC control register. Rev. D | Page 6 of 40 Data Sheet AD5390/AD5391/AD5392 AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 AD5390-3 1 1 Parameter AD5392-3 AD5391-3 Unit Test Conditions/Comments ACCURACY Resolution 14 12 Bits Relative Accuracy ±4 ±1 LSB max Differential Nonlinearity −1/+2 ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 4 mV max Offset Error ±4 ±4 mV max Measured at code 64 in the linear region Offset Error TC ±5 ±5 µV/°C typ Gain Error 0.05 0.05 % FSR max At 25°C ±0.1 ±0.1 % FSR max T to T MIN MAX 2 Gain Temperature Coefficient 2 2 ppm FSR/°C typ DC Crosstalk 1 1 LSB max REFERENCE INPUT/OUTPUT 2 Reference Input Reference Input Voltage 1.25 1.25 V ±1% for specified performance DC Input Impedance 1 1 MΩ min Typically 100 MΩ Input Current ±1 ±1 µA max Typically ±30 nA Reference Range 1 V to AV /2 1 V to AV /2 V min/max DD DD 3 Reference Output Enabled via internal/external bit in control register; REF select bit in control register selects the reference voltage Output Voltage 1.245/1.255 1.245/1.255 V min/max At ambient, optimized for 1.25 V operation 2.47/2.53 2.47/2.53 V min/max At ambient when 2.5 V reference is selected Reference TC ±10 ±10 ppm max Temperature range: 25°C to 85°C ±15 ±15 ppm max Temperature range: −40°C to +85°C Output Impedance 800 800 Ω typ 2 OUTPUT CHARACTERISTICS 4 Output Voltage Range 0/AVDD 0/AVDD V min/max Short-Circuit Current 40 40 mA max Load Current ±1 ±1 mA max Capacitive Load Stability R = ∞ 200 200 pF max L R = 5 kΩ 1000 1000 pF max L DC Output Impedance 0.6 0.6 Ω max 2 MONITOR OUTPUT PIN Output Impedance 1000 1000 Ω typ Three-State Leakage Current 100 100 nA typ 2 LOGIC INPUTS DV = 2.7 V to 5.5 V DD VIH, Input High Voltage 2 2 V min VIL, Input Low Voltage DVDD > 3.6 V 0.8 0.8 V max DVDD ≤ 3.6 V 0.6 0.6 V max Input Current ±10 ±10 µA max Total for all pins. T = T to T A MIN MAX Pin Capacitance 10 10 pF max Rev. D | Page 7 of 40 AD5390/AD5391/AD5392 Data Sheet 1 AD5390-3 1 1 Parameter AD5392-3 AD5391-3 Unit Test Conditions/Comments Logic Inputs (SCL, SDA Only) V , Input High Voltage 0.7 × DV 0.7 × DV V min SMBus-compatible at DV < 3.6 V IH DD DD DD V , Input Low Voltage 0.3 × DV 0.3 × DV V max SMBus-compatible at DV < 3.6 V IL DD DD DD I , Input Leakage Current ±1 ±1 µA max IN VHYST, Input Hysteresis 0.05 × DVDD 0.05 × DVDD V min Glitch Rejection 50 50 ns max Input filtering suppresses noise spikes <50 ns 2 Logic Outputs (BUSY, SDO) Output Low Voltage 0.4 0.4 V max DV = 2.7 V to 5.5 V, sinking 200 µA DD Output High Voltage DV − 0.5 DV − 0.5 V min DV = 2.7 V to 3.6 V, SDO only, sourcing 200 µA DD DD DD DVDD − 0.1 DVDD − 0.1 V min DVDD = 4.5 V to 5.5 V, SDO only, sourcing 200 µA High Impedance Leakage Current ±1 ±1 µA max High Impedance Output 5 5 pF typ Capacitance 2 Logic Output (SDA) VOL, Output Low Voltage 0.4 0.4 V max ISINK = 3 mA 0.6 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 ±1 µA max Three-State Output 8 8 pF typ Capacitance POWER REQUIREMENTS AV 2.7/3.6 2.7/3.6 V min/max DD DV 2.7/5.5 2.7/5.5 V min/max DD 2 Power Supply Sensitivity ∆Midscale/∆AVDD −85 −85 dB typ AIDD 0.375 0.375 mA/channel Outputs unloaded, boost off, max 0.25 mA/channel typ AI 0.475 0.475 mA/channel Outputs unloaded, boost on, DD max 0.325 mA/channel typ DIDD 1 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 20 20 µA max Typically 100 nA DI (Power-Down) 20 20 µA max Typically 1 µA DD Power Dissipation 21 21 mW max AD5390/AD5391 with outputs unloaded, AV = DV = 3 V, boost off DD DD 12 12 mW max AD5392 with outputs unloaded, AVDD = DVDD = 3 V, boost off 1 AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C. 2 Guaranteed by characterization, not production tested. 3 Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a degradation in performance accuracy. 4 Accuracy guaranteed from VOUT = 39 mV to AVDD − 50 mV. Rev. D | Page 8 of 40 Data Sheet AD5390/AD5391/AD5392 AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND. Table 5. 1 Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time ¼ scale to ¾ scale change settling to ±1 LSB AD5390/AD5392 3 µs typ Boost mode off, CR11 = 0 8 µs max Boost mode off, CR11 = 0 AD5391 3 µs typ Boost mode off, CR11 = 0 8 µs max Boost mode on, CR11 = 1 2 Slew Rate 2.5 V/µs typ Boost mode on 1.5 V/µs typ Boost mode off, CR11 = 0 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See the Terminology section DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test OUTPUT NOISE (0.1 Hz to 10 Hz) 15 µV p-p typ External reference midscale loaded to DAC 40 µV p-p typ Internal reference midscale loaded to DAC Output Noise Spectral Density 1/2 @ 1 kHz 150 nV/(Hz) typ 1/2 @ 10 kHz 100 nV/(Hz) typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit in the AD539x control registers. Rev. D | Page 9 of 40 AD5390/AD5391/AD5392 Data Sheet TIMING CHARACTERISTICS SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE DV = 2 V to 5.5 V; AV = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T to T , unless otherwise noted. DD DD MIN MAX 1 Table 6. 3-Wire Serial Interface 2, 3 Parameter Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 th t 13 ns min 24 SCLK falling edge to SYNC falling edge 5 4 t 33 ns min Minimum SYNC low time 6 t 10 ns min 7 Minimum SYNC high time t7 50 ns min Minimum SYNC high time in readback mode t8 5 ns min Data setup time t9 4.5 ns min Data hold time 4 th t 30 ns max 24 SCLK falling edge to BUSY falling edge 10 t 670 ns max BUSY pulse width low (single channel update) 11 4 th t 20 ns min 12 24 SCLK falling edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 2 μs max BUSY rising edge to DAC output response time t 0 ns min BUSY rising edge to LDAC falling edge 15 t 100 ns min LDAC falling edge to DAC output response time 16 t 8 µs typ DAC output settling time, AD5390/AD5392 17 t17 6 µs typ DAC output settling time, AD5391 t18 20 ns min CLR pulse width low t19 40 µs max CLR pulse activation time 5 t 20 ns max SCLK rising edge to SDO valid 20 4 t 5 ns min SCLK falling edge to SYNC rising edge 21 4 t 8 ns min 22 SYNC rising edge to SCLK rising edge 4 t23 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.2 V. CC 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. t 1 SCLK 24 48 t t t 22 3 2 t 7 t 21 SYNC t 4 t 8 t 9 DB23 DB0 DB23 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1 t 20 SDO DB23 DB0 t 23 UNDEFINED INPUT WORD FOR DAC N t 13 LDAC Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. D | Page 10 of 40 03773-002 Data Sheet AD5390/AD5391/AD5392 t 1 SCLK 24 24 1 2 t t 3 2 t t 4 5 SYNC t 7 t 6 t 8 t 9 DB23 DIN DB0 t 10 BUSY t 11 t t 12 13 1 LDAC t 17 t 14 VOUT 1 t 15 t 13 2 LDAC t 17 t 16 VOUT 2 t 18 CLR t 19 VOUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE DURING BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB0 DB23' DB0 DB23 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) I 200µA OL TO V OR OH (MIN) OUTPUT V C OL (MAX) PIN L 50pF I OH 200µA Figure 5. Load Circuit for Digital Output Timing Rev. D | Page 11 of 40 03773-003 03773-005 03773-006 AD5390/AD5391/AD5392 Data Sheet 2 I C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 2 1 Table 7. I C Serial Interface 2 Parameter Limit at T , T Unit Description MIN MAX FSCL 400 kHz max SCL clock frequency t 2.5 µs min SCL cycle time 1 t 0.6 µs min t , SCL high time 2 HIGH t3 1.3 µs min tLOW, SCL low time t4 0.6 µs min tHD, STA, start/repeated start condition hold time t5 100 ns min tSU, DAT, data setup time 3 t 0.9 µs max t , data hold time 6 HD DAT 0 µs min t , data hold time HD DAT t 0.6 µs min t , setup time for repeated start 7 SU STA t8 0.6 µs min tSU, STO stop condition setup time t9 1.3 µs min tBUF, bus free time between a stop and a start condition t10 300 ns max tF, fall time of SDA when transmitting 0 ns min t , rise time of SCL and SDA when receiving (CMOS-compatible) R t 300 ns max t , fall time of SDA when transmitting 11 F 0 ns min t , fall time of SDA when receiving (CMOS-compatible) F 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1 CB ns min tF, fall time of SCL and SDA when transmitting 4 C 400 pF max Capacitive load for each bus line B 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V MIN of the SCL signal) to bridge the undefined region of SCL’s falling edge. IH 4 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD. SDA t 9 t t t t 3 10 11 4 SCL t 4 t t t t t 6 2 5 7 t 8 1 REPEATED STOP START START CONDITION CONDITION CONDITION 2 Figure 6. I C Interface Timing Diagram Rev. D | Page 12 of 40 03773-007 Data Sheet AD5390/AD5391/AD5392 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Stresses above absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional Table 8. operation of the device at these or any other conditions above Parameter Rating those listed in the operational sections of this specification is AV to AGND −0.3 V to +7 V DD not implied. Exposure to absolute maximum rating conditions DVDD to DGND −0.3 V to +7 V for extended periods may affect device reliability. Digital Inputs to DGND −0.3 V to DVDD + 0.3 V Digital Outputs to DGND −0.3 V to DVDD + 0.3 V ESD CAUTION VREF to AGND −0.3 V to +7 V REFOUT to AGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V VOUTX to AGND −0.3 V to AVDD + 0.3 V ESD HBM 6.5 kV FICSM 2 kV Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 64-Lead LFCSP, θ 22°C/W JA 52-Lead LQFP, θ 38°C/W JA Reflow Soldering Peak Temperature 230°C Rev. D | Page 13 of 40 AD5390/AD5391/AD5392 Data Sheet PIN CONFIGURATON AND FUNCTION DESCRIPTIONS 52 51 50 49 48 47 46 45 44 43 42 41 40 CLR 1 39 LDAC NC 2 38 BUSY 1 PIN 1 NC 48 NC NC 3 37 RESET INDICATOR NC 2 47 BUSY NC 3 46 RESET REF_GND 4 36 NC PIN 1 4 45 NC NC INDICATOR REFOUT/REFIN 5 35 NC 5 NC 44 NC AD5390/ 6 34 6 SIGNAL_GND 1 NC NC 43 NC AD5391 REF_GND 7 42 NC AD5390/ DAC_GND 1 7 33 NC REFOUT/REFIN 8 41 NC TOP VIEW AD5391 32 AV 1 8 AV 2 DD DD SIGNAL_GND 1 9 40 NC (Not to Scale) 10 9 31 DAC_GND 1 39 NC VOUT 0 AGND 2 TOP VIEW 11 AV 1 38 NC DD (Not to Scale) VOUT 1 10 30 VOUT 15 VOUT 0 12 37 AV 2 DD 29 VOUT 2 11 VOUT 14 VOUT 1 13 36 AGND 2 VOUT 2 14 35 VOUT 15 12 28 VOUT 3 VOUT 13 VOUT 3 15 34 VOUT 14 VOUT 4 13 27 SIGNAL_GND 2 16 VOUT 4 33 VOUT 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NC = NO CONNECT NC = NO CONNECT Figure 7. AD5390/AD5391 LFCSP Pin Configuration Figure 9. AD5390/AD5391 LQFP Pin Configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 CLR 1 39 LDAC NC 2 38 BUSY 1 NC 48 NC PIN 1 NC 3 37 RESET 2 INDICATOR NC 47 BUSY PIN 1 NC 3 46 RESET REF_GND 4 36 NC INDICATOR NC 4 45 NC 35 REFOUT/REFIN 5 NC 5 NC 44 NC 6 SIGNAL_GND 1 6 34 NC NC 43 NC AD5392 REF_GND 7 42 NC DAC_GND 1 7 33 NC TOP VIEW AD5392 REFOUT/REFIN 8 41 NC (Not to Scale) 32 AV 1 8 NC SIGNAL_GND 1 9 DD 40 NC TOP VIEW 10 DAC_GND 1 39 NC 9 31 VOUT 0 NC (Not to Scale) 11 AV 1 38 NC DD VOUT 1 10 30 NC VOUT 0 12 37 NC VOUT 1 13 VOUT 2 11 29 NC 36 NC VOUT 2 14 35 NC 12 28 NC VOUT 3 15 VOUT 3 34 NC 13 27 SIGNAL_GND 2 VOUT 4 VOUT 4 16 33 NC 14 15 16 17 18 19 20 21 22 23 24 25 26 NC = NO CONNECT NC = NO CONNECT Figure 8. AD5392 LFCSP Pin Configuration Figure 10. AD5392 LQFP Pin Configuration Rev. D | Page 14 of 40 AGND 1 17 64 CLR AGND 1 17 64 CLR NC 18 63 DGND NC 18 63 DGND NC 19 62 SYNC/AD0 NC 19 62 SYNC/AD0 VOUT 5 20 61 DIN/SDA 61 DIN/SDA VOUT 5 20 VOUT 6 21 60 SCLK/SCL VOUT 6 21 60 SCLK/SCL VOUT 7 22 59 SDO VOUT 7 22 59 SDO 58 DV MON_IN 1 23 DD MON_IN 1 23 58 DV DD 57 DGND MON_IN 2 24 57 DGND MON_IN 2 24 56 DGND MON_OUT 25 56 DGND MON_OUT 25 55 DV VOUT 8 26 DD 55 DV TEST 26 DD 54 DV DD 54 DV VOUT 9 27 NC 27 DD VOUT 10 28 53 DGND 53 DGND NC 28 2 2 52 SPI/I C VOUT 11 29 52 SPI/I C NC 29 51 PD VOUT 12 30 51 PD NC 30 50 DCEN/AD1 DAC_GND 2 31 50 DCEN/AD1 DAC_GND 2 31 SIGNAL_GND 2 32 49 LDAC 49 LDAC SIGNAL_GND 2 32 03773-009 03773-008 AGND 1 DGND AGND 1 DGND VOUT 5 SYNC/AD0 VOUT 5 SYNC/AD0 VOUT 6 DIN/SDA VOUT 6 DIN/SDA VOUT 7 SCLK/SCL VOUT 7 SCLK/SCL MON_IN 1 SDO MON_IN 1 SDO MON_IN 2 DV DD MON_IN 2 DV DD MON_OUT DGND MON_OUT DGND TEST DV DD VOUT 8 DV DD NC DV DD DV VOUT 9 DD NC DGND VOUT 10 DGND 2 2 NC SPI/I C VOUT 11 SPI/I C PD PD NC VOUT 12 DCEN/AD1 DAC_GND 2 DCEN/AD1 DAC_GND 2 03773-011 03773-010 Data Sheet AD5390/AD5391/AD5392 Table 9. Pin Function Descriptions Mnemonic Function VOUT X Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND 1, Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together SIGNAL_GND 2 internally and should be connected to the AGND plane as close as possible to the AD539x. DAC_GND 1, Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs. DAC_GND 2 These pins should be connected to the AGND plane. AGND 1, AGND 2 Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AV 1, AV 2 Analog Supply Pins. Each group of eight channels has a separate AV pin. These pins should be decoupled with 0.1 uF DD DD DD ceramic capacitors and 10 µF tantalum capacitors. Operating range is 5 V ± 10%. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with 0.1 µF ceramic capacitors and 10 µF tantalum capacitors to DGND. REF_GND Ground Reference Point for the Internal Reference. Connect to AGND. REFOUT/REFIN The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled via the control register. The default for this pin is a reference input. MON_OUT Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of a 16-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. When the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs. MON_IN 1, Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the MON_IN 2 maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals. SYNC/AD0 Serial Interface Pin. This is the frame synchronization input signal for the serial interface. When taken low, the internal counter is enabled to count the required number of clocks before the addressed register is updated. 2 In I C mode, AD0 acts as a hardware address pin. 2 DCEN/AD1 Interface Control Pin. Operation is determined by the interface select bit SPI/I C. Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain operation to allow a number of devices to be cascaded together. 2 I C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for 2 this device on the I C bus. SDO Serial Data Output. Three-state CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 20 µs (AD5390/AD5391) and 15 µs (AD5392) while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 270 µs maximum. This falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. Rev. D | Page 15 of 40 AD5390/AD5391/AD5392 Data Sheet Mnemonic Function PD Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. 2 2 SPI/I C Interface Select Input Pin. When this input is low, I C mode is selected. When this input is high, SPI mode is selected. SCLK/SCL Interface Clock Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock speeds up to 50 MHz. 2 2 2 I C mode: In I C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I C mode is compatible with both 100 kHz and 400 kHz operating modes. DIN/SDA Interface Data Input Pin. 2 I C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK. SPI/ 2 2 2 SPI/I C = 0, I C mode: In I C mode, this pin is the serial data pin (SDA) operating as an open drain input/output. TEST Test pin (AD5392 only). This pin is used for production testing. For normal operation, this pin should not be connected. NC No Connect. These pins have no internal connection. Exposed Pad This pad should be connected to the ground plane. (LFCSP only) Rev. D | Page 16 of 40 Data Sheet AD5390/AD5391/AD5392 TERMINOLOGY Relative Accuracy or Endpoint Linearity (INL) DC Output Impedance A measure of the maximum deviation from a straight line The effective output source resistance. It is dominated by passing through the endpoints of the DAC transfer function. package lead resistance. It is measured after adjusting for zero-scale error and full-scale Output Voltage Settling Time error and is expressed in least significant bits (LSBs). The amount of time it takes for the output of a DAC to settle Differential Nonlinearity (DNL) to a specified level for a ¼ to ¾ full-scale input change. It is The difference between the measured change and the ideal measured from the rising edge of . BUSY 1 LSB change between any two adjacent codes. A specified Digital-to-Analog Glitch Energy differential nonlinearity of 1 LSB maximum ensures mono- The amount of energy injected into the analog output at the tonicity. major code transition. It is specified as the area of the glitch in Zero-Scale Error nV-s. It is measured by toggling the DAC register data between The error in the DAC output voltage when all 0s are loaded 0x1FFF and 0x2000. into the DAC register. Ideally, with all 0s loaded to the DAC DAC-to-DAC Crosstalk n−1 and m = all 1s, c = 2 , VOUT = 0 V. (Zero-Scale) The glitch impulse that appears at the output of one DAC due to Zero-scale error is a measure of the difference between VOUT both the digital change and subsequent analog output change at (actual) and VOUT (ideal) expressed in mV. It is mainly caused another DAC. The victim channel is loaded with midscale, and by offsets in the output amplifier. DAC-to-DAC crosstalk is specified in nV-s. Offset Error Digital Crosstalk A measure of the difference between VOUT (actual) and VOUT The glitch impulse transferred to the output of one converter (ideal) expressed in mV in the linear region of the transfer due to a change in the DAC register code of another converter function. Offset error is measured on the AD539x-5 with code is defined as the digital crosstalk and is specified in nV-s. 32 loaded in the DAC register and with code 64 loaded in the Digital Feedthrough DAC register on the AD539x-3. When the device is not selected, high frequency logic activity Gain Error on the device’s digital inputs can be capacitively coupled both The deviation in slope of the DAC transfer characteristic from across and through the device to show up as noise on the VOUT ideal and is expressed in % FSR with the DAC output unloaded. pins. It can also be coupled along the supply and ground lines. Gain error is specified in the linear region of the output range This noise is digital feedthrough. between VOUT = 10 mV and VOUT = AVDD − 50 mV. Output Noise Spectral Density DC Crosstalk This is a measure of internally generated random noise. Random The dc change in the output level of one DAC at midscale in noise is characterized as a spectral density (voltage per √Hz). response to a full-scale code (all 0s to all 1s and vice versa) and It is measured by loading all DACs to midscale and measuring 1/2 the output change of all other DACs. It is expressed in LSBs. noise at the output. It is measured in nV/(Hz) in a 1 Hz bandwidth at 10 kHz. Rev. D | Page 17 of 40 AD5390/AD5391/AD5392 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.00 AV = DV = 5.5V DD DD VREF = 2.5V 1.5 0.75 T = 25°C A 1.0 0.50 0.5 0.25 0 0 –0.5 –0.25 –1.0 –0.50 –1.5 –0.75 –2.0 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12288 16384 INPUT CODE INPUT CODE Figure 14. Typical AD5391-5 INL Plot Figure 11. AD5390-5/AD5392-5 Typical INL Plot 2.0 1.00 AV = DV = 3V DD DD VREF = 1.25V 1.5 0.75 T = 25°C A 1.0 0.50 0.5 0.25 0 0 –0.5 –0.25 –1.0 –0.50 –1.5 –0.75 –2.0 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12288 16384 INPUT CODE INPUT CODE Figure 12. AD5390-3/AD5392-3 INL Plot Figure 15. Typical AD5391-3 INL Plot 40 14 AV = 5.5V DD AV = 5V DD REFIN = 2.5V REFOUT = 2.5V T = 25°C A 35 TEMP. RANGE = 25°C TO 85°C 12 SAMPLE SIZE = 162 30 10 25 8 20 6 15 4 10 2 5 0 0 –2 –1 0 1 2 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 INL ERROR DISTRIBUTION (LSB) –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) Figure 13. AD5390/AD5392 INL Histogram Plot Figure 16. AD539x REFOUT Temperature Coefficient Rev. D | Page 18 of 40 INL ERROR (LSB) INL ERROR (LSB) NUMBER OF UNITS 03773-042 03773-041 03773-040 FREQUENCY INL ERROR (LSB) INL ERROR (LSB) 03773-045 03773-044 03773-043 Data Sheet AD5390/AD5391/AD5392 6 FULL SCALE 5 BUSY AV = DV = 5V DD DD VREF = 2.5V 3/4 SCALE 4 T = 25°C A MIDSCALE 3 2 1/4 SCALE VOUT 1 AV = DV = 5V ZERO SCALE DD DD VREF = 2.5V 0 T = 25°C A –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 CURRENT (mA) Figure 17. AD539x Exiting Soft Power-Down Figure 20. AD539x-5 Source and Sink Capability 0.20 AV = 5V DD VREF = 2.5V 0.15 T = 25°C A PD 0.10 ERROR AT ZERO SINKING CURRENT 0.05 0 –0.05 VOUT (V –VOUT) AT FULL-SCALE SOURCING CURRENT DD –0.10 AV = DV = 5V DD DD VREF = 2.5V –0.15 T = 25°C A –0.20 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 I /I (mA) SOURCE SINK Figure 18. AD539x Exiting Hardware Power-Down Figure 21. Headroom at Rails vs. Source/Sink Current 2.510 AV = DV = 5V DD DD VREF = 2.5V T = 25°C A 2.505 VDD 2.500 VOUT 2.995 2.990 0 2 4 6 8 10 12 TIME (µs) Figure 19. AD539x Power-Up Transient Figure 22. AD539x-5 Glitch Impulse Energy Rev. D | Page 19 of 40 03773-102 03773-101 03773-100 ERROR VOLTAGE (V) VOUT (V) VOLTAGE (V) 03773-050 03773-049 03773-103 AD5390/AD5391/AD5392 Data Sheet 1.260 DVDD = 5.5V V = DVDD IH 10 V = DGND IL T = 25°C A 1.255 8 6 1.250 4 1.245 2 0 1.240 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 10 12 DI (mA) DD TIME (µs) Figure 23. AD539x-3 Glitch Impulse Figure 26. AD539x DIDD Histogram 2.456 AV = DV = 5V DD DD VREF = 2.5V 2.455 T = 25°C A LDAC 14ns/SAMPLE NUMBER 2.454 2.453 2.452 VOUT 2.451 AV = DV = 5V DD DD 2.450 VREF = 2.5V T = 25°C A 2.449 0 50 100 150 200 250 300 350 400 450 500 550 SAMPLE NUMBER Figure 27. AD539x Adjacent Channel Crosstalk Figure 24. AD539x Slew Rate Boost Off 600 AV = 5V DD T = 25°C A REFOUT DECOUPLED 500 LDAC WITH 100nF CAPACITOR 400 300 REFOUT = 2.5V 200 VOUT REFOUT = 1.25V 100 AV = DV = 5V DD DD VREF = 2.5V T = 25°C A 0 100 1k 10k 100k FREQUENCY (Hz) Figure 25. AD539x Slew Rate Boost On Figure 28. AD539x REFOUT Noise Spectral Density Rev. D | Page 20 of 40 VOLTAGE (V) 03773-105 03773-106 03773-104 OUTPUT NOISE (nV/ Hz) AMPLITUDE (V) NUMBER OF UNITS 03773-057 03773-056 03773-107 Data Sheet AD5390/AD5391/AD5392 6 AV = DV = 3V AV = DV = 5V DD DD DD DD VREF = 1.25V T = 25°C A DAC LOADED WITH MIDSCALE T = 25°C 5 A EXTERNAL REFERENCE Y AXIS = 5µV/DIV 4 X AXIS = 100ms/DIV 3/4 SCALE FULL SCALE 3 MIDSCALE 2 1 0 ZERO SCALE 1/4 SCALE –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 CURRENT (mA) Figure 30. AD539x-3 Source and Sink Current Capability Figure 29. 0.1 Hz to 10 Hz Output Noise Plot Rev. D | Page 21 of 40 03773-058 VOUT (V) 03773-059 AD5390/AD5391/AD5392 Data Sheet FUNCTIONAL DESCRIPTION The digital input transfer function for each DAC can be DAC ARCHITECTURE represented as The AD5390/AD5391 are complete single-supply, 16-channel, n n−1 voltage output DACs offering a resolution of 14 bits and 12 bits, x2=((m+ 2)/2)×x1+(c− 2 ) respectively. The AD5392 is a complete single-supply, 8-channel, where: voltage output DAC offering 14-bit resolution. All devices are x2 is the data-word loaded to the resistor-string DAC. available in a 64-lead LFCSP and 52-lead LQFP, and feature x1 is the 12-bit and 14-bit data-word written to the DAC input serial interfaces. This family includes an internal select-able register. 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE buffered reference inputs (alternatively, an external reference on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB can be used to drive these inputs). All channels have an on-chip of the gain coefficient is zero. output amplifier with rail-to-rail output capable of driving a n = DAC resolution (n = 14 for the AD5390/AD5392 and 5 kΩ load in parallel with a 200 pF capacitance. n = 12 for the AD5391). The architecture of a single DAC channel consists of a 12-bit c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on and 14-bit resistor-string DAC followed by an output buffer the AD5390/AD5392 and 0x800 on the AD5391). amplifier operating at a gain of 2. This resistor-string architecture The complete transfer function for these devices can be guarantees DAC monotonicity. The 12-bit and 14-bit binary represented as digital code loaded to the DAC register determines at what n node on the string the voltage is tapped off before being fed to VOUT= 2×VREF×x2/2 the output amplifier. Each channel on these devices contains where: independent offset and gain control registers, allowing the user x2 is the data-word loaded to the resistor-string DAC. to digitally trim offset and gain. VREF is the reference voltage applied to the REFIN/REFOUT pin AVDD VREF on the DAC when an external reference is used (2.5 V for specified performance on the AD539x-5 products and 1.25 V on the x1 INPUT REG AD539x-3 products). DAC 14-BIT INPUT m REG x2 REG DAC DATA VOUT c REG R R Figure 31. Single-Channel Architecture These registers let the user calibrate out errors in the complete signal chain including the DAC using the internal m and c registers, which hold the correction factors. All channels are double-buffered, allowing synchronous updating of all channels using the pin. Figure 31 shows a block diagram of a LDAC single channel on the AD5390/AD5391/AD5392. Rev. D | Page 22 of 40 03773-018 Data Sheet AD5390/AD5391/AD5392 AD5391 DATA DECODING AD5390/AD5392 The AD5391 contains an internal 12-bit data bus. The input data is decoded depending on the value loaded to the REG1 and The AD5390/AD5392 contain an internal 14-bit data bus. REG0 bits of the input serial register. The input data from the The input data is decoded depending on the data loaded to serial input register is loaded into the addressed DAC input the REG1 and REG0 bits of the input serial register. This is register, offset (c) register, or gain (m) register. The format data shown in Table 10. and the offset (c) and gain (m) register contents are shown in Data from the serial input register is loaded into the addressed Table 14 to Table 16. DAC input register, offset (c) register, or gain (m) register. The Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1) format data, and the offset (c) and gain (m) register contents are shown in Table 11 to Table 13. DB11 to DB0 DAC Output (V) 1111 1111 1111 2 VREF × (4095/4096) Table 10. Register Selection 1111 1111 1110 2 VREF × (4094/4096) REG1 REG0 Register Selected 1000 0000 0001 2 VREF × (2049/4096) 1 1 Input data register (x1) 1000 0000 0000 2 V × (2048/4096) REF 1 0 Offset register (c) 0111 1111 1111 2 V × (2047/4096) REF 0 1 Gain register (m) 0000 0000 0001 2 V × (1/4096) REF 0 0 Special function registers (SFRs) 0000 0000 0000 0 Table 11. AD5390/AD5392 DAC Data Format Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0) (REG1 = 1, REG0 = 1) DB11 to DB0 Offset (LSB) DB13 to DB0 DAC Output (V) 1111 1111 1111 +2047 11 1111 1111 1111 2 VREF × (16383/16384) 1111 1111 1110 +2046 11 1111 1111 1110 2 VREF × (16382/16384) 1000 0000 0001 +1 10 0000 0000 0001 2 V × (8193/16384) REF 1000 0000 0000 +0 10 0000 0000 0000 2 V × (8192/16384) REF 0111 1111 1111 –1 01 1111 1111 1111 2 VREF × (8191/16384) 0000 0000 0001 –2047 00 0000 0000 0001 2 VREF × (1/16384) 0000 0000 0000 –2048 00 0000 0000 0000 0 Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1) Table 12. AD5390/AD5392 Offset Data Format DB11 to DB0 Gain Factor (REG1 = 1, REG0 = 0) 1111 1111 1110 1 DB13 to DB0 Offset (LSB) 1011 1111 1110 0.75 111111 1111 1111 +8191 0111 1111 1110 0.5 111111 1111 1110 +8190 0011 1111 1110 0.25 100000 0000 0001 +1 0000 0000 0000 0 100000 0000 0000 +0 011111 1111 1111 –1 000000 0000 0001 –8191 000000 0000 0000 –8192 Table 13. AD5390/AD5392 Gain Data Format (REG1 = 0, REG0 = 1) DB13 to DB0 Gain Factor 11 1111 1111 1110 1 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 00 1111 1111 1110 0.25 00 0000 0000 0000 0 Rev. D | Page 23 of 40 AD5390/AD5391/AD5392 Data Sheet INTERFACES The AD5390/AD5391/AD5392 contain a serial interface that Logic 1 pin to configure this mode of operation. The serial can be programmed to be DSP-, SPI-, and MICROWIRE- interface control pins are described in Table 17. 2 2 compatible, or I C-compatible. The SPI/I C pin is used to select Table 17. Serial Interface Control Pins the interface mode. Pin Description To minimize both the power consumption of the device and the SYNC, DIN, SCLK Standard 3-wire interface pins. on-chip digital noise, the interface fully powers up only when the DCEN Selects standalone mode or daisy-chain mode. device is being written to, that is, on the falling edge of SYNC. SDO Data out pin for daisy-chain mode. DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL INTERFACE Figure 2 to Figure 4 show timing diagrams for a serial write to The serial interface can be operated with a minimum of three the AD5390/AD5391/AD5392 in both standalone and daisy- wires in standalone mode or four wires in daisy-chain mode. chain mode. The 24-bit data-word format for the serial interface Daisy-chaining allows many devices to be cascaded together to is shown in Table 18 to Table 20. Descriptions of the bits follow 2 increase system channel count. The SPI/I C pin is tied to a in Table 21. Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration MSB LSB A W 0 0 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 /B R/ Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration MSB LSB A/B R/W 0 0 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration MSB LSB A W 0 0 0 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 /B R/ Table 21. Serial Input Register Configuration Bit Descriptions Bit Description A/B When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode disabled, this bit should be set to zero to select the A data register. R/W The read or write control bit. A3 to A0 Used to address the input channels. Select the register to which data is written, as outlined in Table 10. REG1 and REG0 DB13 to Contain the input data-word. DB0 X Don’t care condition. Rev. D | Page 24 of 40 Data Sheet AD5390/AD5391/AD5392 Standalone Mode The serial clock can be either a continuous or a gated clock. A continuous SCLK source can be used only if the can be SYNC By connecting the daisy-chain enable (DCEN) pin low, stand- held low for the correct number of clock cycles. In gated clock alone mode is enabled. The serial interface works with both a mode, a burst clock containing the exact number of clock cycles continuous and a noncontinuous serial clock. The first falling must be used and SYNC taken high after the final clock to latch edge of SYNC starts the write cycle and resets a counter that the data. counts the number of serial clocks to ensure that the correct number of bits is shifted into the serial shift register. Any Readback Mode further edges on SYNC (except for a falling edge) are ignored Readback mode is invoked by setting the R/W bit = 1 in the serial until 24 bits are clocked in. Once 24 bits have been shifted in, input register write sequence. With R/ = 1, Bit A3 to Bit A0 W the SCLK is ignored. For another serial transfer to take place, in association with Bits REG1 and REG0 select the register to the counter must be reset by the falling edge of . SYNC be read. The remaining data bits in the write sequence are don’t Daisy-Chain Mode care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed For systems that contain several devices, the SDO pin can be register. For a read of a single register, the NOP command can be used to daisy-chain the devices together. This daisy-chain mode used in clocking out the data from the selected register on SDO. can be useful in system diagnostics and for reducing the number of serial interface lines. The readback diagram in Figure 32 shows the readback sequence. For example, to read back the m register of Channel 0 on the By connecting the DCEN pin high, daisy-chain mode is AD539x, the following sequence should be implemented: enabled. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register First, write 0x404XXX to the AD539x input register. This when SYNC is low. If more than 24 clock pulses are applied, configures the AD539x for read mode with the m register of Channel 0 selected. Note that all data bits, DB13 to DB0, are the data ripples out of the shift register and appears on the don’t care bits. SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the Follow this with a second write, a NOP condition, and 0x000000. first device to the DIN input on the next device in the chain, During this write, the data from the m register is clocked out on a multidevice interface is constructed. For each device in the the DOUT line, that is, data clocked out contains the data from system, 24 clock pulses are required. Therefore, the total the m register in Bit DB13 to Bit DB0, and the top 10 bits con- number of clock cycles must equal 24N where N is the total tain the address information as previously written. In readback number of AD539x devices in the chain. mode, the signal must frame the data. Data is clocked out SYNC When the serial transfer to all devices is complete, SYNC is on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and taken high. This latches the input data in each device in the read operations of a readback, the first bit of data is clocked out daisy chain and prevents any further data from being clocked on the falling edge of . into the input shift register. SYNC If SYNC is taken high before 24 clocks are clocked into the part, it is considered a bad frame and the data is discarded. SCLK 24 48 SYNC DIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION SDO DB23 DB0 DB23 DB0 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 32. Readback Operation Rev. D | Page 25 of 40 03773-022 AD5390/AD5391/AD5392 Data Sheet 2 Repeated START Condition I C SERIAL INTERFACE 2 A repeated START (Sr) condition may indicate a change of data The AD5390/AD5391/AD5392 feature an I C-compatible direction on the bus. Sr may be used when the bus master is 2-wire interface consisting of a serial data line (SDA) and a 2 writing to several I C devices and does not want to relinquish serial clock line (SCL). SDA and SCL facilitate communication control of the bus. between the DACs and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagram. Acknowledge Bit (ACK) 2 The acknowledge bit (ACK) is the ninth bit attached to any 8-bit When selecting the I C operating mode by configuring the 2 2 data-word. An ACK is always generated by the receiving device. SPI/I C pin to Logic 0, the device is connected to the I C bus The AD539x devices generate an ACK when receiving an address as a slave device, that is, no clock is generated by the device. or data by pulling SDA low during the ninth clock period. The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1 (AD1)(AD0). The five MSBs are hard-coded and the two LSBs Monitoring the ACK allows for detection of unsuccessful data are determined by the state of the AD1 and AD0 pins. The transfers. An unsuccessful data transfer occurs if a receiving hardware configuration facility for the AD1 and AD0 pins device is busy or if a system fault has occurred. In the event of allows four of these devices to be configured on the bus. an unsuccessful data transfer, the bus master should reattempt 2 communication. I C Data Transfer AD539X Slave Addresses One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the A bus master initiates communication with a slave device by SCL clock pulse. Changes in SDA while SCL is high are control issuing a START condition followed by the 7-bit slave address. signals that configure START and STOP conditions. Both SDA When idle, the AD539x device waits for a START condition and SCL are pulled high by the external pull-up resistors when followed by its slave address. The LSB of the address word is 2 the I C bus is not busy. the read/write (R/W) bit. The AD539x devices are receive devices only and R/W = 0 when communicating with them. START and STOP Conditions After receiving the proper address 1010 1(AD1) (AD0), the A master device initiates communication by issuing a START AD539x issues an ACK by pulling SDA low for one clock cycle. condition. A START condition is a high-to-low transition on The AD539x has four user-programmable addresses determined SDA with SCL high. A STOP condition is a low-to-high trans- by the AD1 and AD0 bits. ition on SDA, while SCL is high. A START condition from the master signals the beginning of a transmission to the AD539x. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. Rev. D | Page 26 of 40 Data Sheet AD5390/AD5391/AD5392 2 I C WRITE OPERATION There are three specific modes in which data can be written to DAC to be addressed and is also acknowledged by the DAC. the AD539x family of DACs. Address Bits A3 to A0 address all channels on the AD5390/ AD5391. Address Bits A2 to A0 address all channels on the 4-BYTE MODE AD5392. Address Bit A3 is a zero on the AD5392. Two bytes When writing to the AD539x DACs, begin with an address byte of data are then written to the DAC, as shown in Figure 33. (R/W = 0), after which the DAC acknowledges that it is prepared A STOP condition follows. This lets the user update a single to receive data by pulling SDA low. The address byte is followed channel within the AD539x at any time and requires four bytes by the pointer byte. This addresses the specific channel in the of data to be transferred from the master. SCL 1 0 1 0 1 AD1 AD0 R/W A/B 0 0 0 A3 A2 A1 A0 SDA START ACK MSB ACK CONDITION BY BY ADDRESS BYTE POINTER BYTE BY CONVERTER CONVERTER MASTER SCL SDA REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ACK ACK STOP MOST SIGNIFICANT DATA BYTE BY LEAST SIGNIFICANT DATA BYTE BY CONDITION CONVERTER CONVERTER BY MASTER 2 Figure 33. AD5390/AD5392 4-Byte Mode I C Write Operation SCL AD1 AD0 R/W A/B 0 0 0 A3 A2 A1 A0 SDA 1 0 1 0 1 START ACK MSB ACK CONDITION BY BY ADDRESS BYTE POINTER BYTE BY CONVERTER CONVERTER MASTER SCL REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 SDA ACK ACK STOP MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY BY CONDITION CONVERTER CONVERTER BY MASTER 2 Figure 34. AD5391 4-Byte Mode I C Write Operation Rev. D | Page 27 of 40 03773-021 03773-023 AD5390/AD5391/AD5392 Data Sheet 3-BYTE MODE The 3-byte mode lets the user update more than one channel in on the AD5392. Address Bit A3 is a zero on the AD5392. This is a write sequence without having to write the device address byte then followed by the two data bytes. REG1 and REG0 determine each time. The device address byte is required only once and the register to be updated. subsequent channel updates require the pointer byte and the If a STOP condition is not sent following the data bytes, data bytes. In 3-byte mode, the user begins with an address byte another channel can be updated by sending a new pointer (R/ = 0) after which the DAC acknowledges that it is prepared W byte followed by the data bytes. This mode requires only three to receive data by pulling SDA low. The address byte is followed bytes to be sent to update any channel once the device has by the pointer byte; this addresses the specific channel in the been initially addressed and reduces the software overhead in DAC to be addressed and is also acknowledged by the DAC. updating the AD539x channels. A STOP condition at any time Address Bits A3 to A0 address all channels on the exits this mode. Figure 35 shows a typical configuration. AD5390/AD5391. Address Bits A2 to A0 address all channels SCL 1 0 1 0 1 AD1 AD0 R/W A/B 0 0 0 A3 A2 A1 A0 SDA START ACK MSB ACK CONDITION BY BY ADDRESS BYTE POINTER BYTE FOR CHANNEL N BY CONVERTER CONVERTER MASTER SCL REG1 REG0 MSB LSB MSB LSB SDA ACK ACK BY BY MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CONVERTER CONVERTER DATA FOR CHANNEL N SCL SDA 0 0 0 0 A3 A2 A1 A0 MSB ACK BY CONVERTER POINTER BYTE FOR CHANNEL NEXT CHANNEL SCL REG1 REG0 MSB LSB MSB LSB SDA ACK ACK STOP BY BY CONDITION MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CONVERTER CONVERTER BY MASTER DATA FOR CHANNEL NEXT CHANNEL 2 Figure 35. 3-Byte Mode I C Write Operation Rev. D | Page 28 of 40 03773-024 Data Sheet AD5390/AD5391/AD5392 2-BYTE MODE The 2-byte mode lets the user update channels sequentially The REG0 and REG1 bits in the data byte determine the register following initialization of this mode. The device address byte is to be updated. In this mode, following the initialization, only required only once and the address pointer is configured for the two data bytes are required to update a channel. The autoincrement or burst mode. channel address automatically increments from Address 0 to the final address and then returns to the normal 3-byte mode The user must begin with an address byte (R/ = 0), after W of operation. This mode allows transmission of data to all which the DAC acknowledges that it is prepared to receive data channels in one block and reduces the software overhead in by pulling SDA low. The address byte is followed by a specific configuring all channels. A STOP condition at any time exits pointer byte (0xFF), which initiates the burst mode of opera- this mode. Toggle mode of operation is not supported in tion. The address pointer initializes to Channel 0 and the data 2-byte mode. Figure 36 shows a typical configuration. following the pointer is loaded to Channel 0. The address pointer automatically increments to the next address. SCL 1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 SDA START ACK MSB ACK CONDITION BY BY ADDRESS BYTE POINTER BYTE BY CONVERTER CONVERTER MASTER SCL SDA REG1 REG0 MSB LSB MSB LSB ACK ACK MOST SIGNIFICANT DATA BYTE BY LEAST SIGNIFICANT DATA BYTE BY CONVERTER CONVERTER CHANNEL 0 DATA SCL REG1 REG0 MSB LSB MSB LSB SDA ACK ACK MOST SIGNIFICANT DATA BYTE BY LEAST SIGNIFICANT DATA BYTE BY CONVERTER CONVERTER CHANNEL 1 DATA SCL REG1 REG0 MSB LSB MSB LSB SDA ACK ACK STOP MOST SIGNIFICANT DATA BYTE BY LEAST SIGNIFICANT DATA BYTE BY CONDITION CONVERTER CONVERTER BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 36. 2-Byte Mode I C Write Operation Rev. D | Page 29 of 40 03773-025 AD5390/AD5391/AD5392 Data Sheet Soft Power-Down AD539x ON-CHIP SPECIAL FUNCTION REGISTERS REG1 = REG0 = 0, A3 to A0 = 1000 The AD539x family of parts contains a number of special DB13 to DB0 = Don’t Care function registers (SFRs) as shown in Table 22. SFRs are addressed with REG1 = 0 and REG0 = 0 and are decoded Executing this instruction performs a global power-down, using Address Bit A3 to Bit A0. which puts all channels into a low power mode, reducing analog current to 1 µA maximum and digital power consumption to Table 22. SFR Register Functions (REG1 = 0, REG0 = 0) 20 µA maximum. In power-down mode, the output amplifier R/ W A3 A2 A1 A0 Function can be configured as a high impedance output or can provide a X 0 0 0 0 NOP (no operation) 100 kΩ load to ground. The contents of all internal registers are 0 0 0 0 1 Write CLR code retained in power-down mode. 0 0 0 1 0 Soft CLR Soft Power-Up 0 1 0 0 0 Soft power-down REG1 = REG0 = 0, A3 to A0 =1001 0 1 0 0 1 Soft power-up DB13 to DB0 = Don’t Care 0 1 1 0 0 Control register write This instruction is used to power up the output amplifiers and 1 1 1 0 0 Control register read the internal references. The time to exit power-down mode is 0 1 0 1 0 Monitor channel 8 µs. The hardware power-down and software functions are 0 1 1 1 1 Soft reset internally combined in a digital OR function. Soft Reset SFR Commands REG1 = REG0 = 0, A5 to A0 = 001111 NOP (No Operation) DB13 to DB0 = Don’t Care REG1 = REG0 = 0, A3 to A0 = 0000 This instruction is used to implement a software reset. All Performs no operation, but is useful in readback mode to clock internal registers are reset to their default values, which out data on SDO for diagnostic purposes. BUSY outputs a low correspond to m at full scale and c at zero scale. The contents during a NOP operation. of the DAC registers are cleared, setting all analog outputs to Write CLR Code 0 V. The soft reset activation time is 135 µs maximum. REG1 = REG0 = 0, A3 to A0 = 0001 Monitor Channel DB13 to DB0 = Contain the CLR data REG1 = REG0 = 0, A3 to A0 = 01010 Bringing the CLR line low or exercising the soft clear function DB13 to DB8 = Contain data to address the channel to be loads the contents of the DAC registers with the data contained monitored in the user-configurable CLR register and sets VOUT 0 to A monitor function is provided on all devices. This feature, VOUT 15, accordingly. This can be very useful not only for consisting of a multiplexer addressed via the interface, allows setting up a specific output voltage in a clear condition but for any channel output to be routed to the MON_OUT pin for calibration purposes. For calibration, the user can load full scale monitoring using an external ADC. In addition to monitoring or zero scale to the clear code register and then issue a hardware all output channels, two external inputs are also provided, or software clear to load this code to all DACs, removing the allowing the user to monitor signals external to the AD539x. need for individual writes to all DACs. Default on power-up The channel monitor function must be enabled in the control is all zeros. register before any channels are routed to the MON_OUT pin. Soft CLR On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain the channel address for the monitored channel. On the AD5391 REG1 = REG0 = 0, A3 to A0 = 0010 12-bit part, DB11 to DB6 contain the channel address for the DB13 to DB0 = Don’t Care channel to be monitored. Selecting Address 63 three-states the Executing this instruction performs the CLR, which is MON_OUT pin. functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code The channel monitor decoding for the AD5390/AD5392 is register. The time taken to execute fully the SOFT CLR is shown in Table 23 and the monitor decoding for the AD5391 is 20 µs on the AD5390/AD5391 and 15 µs on the AD5392. It shown in Table 24. is indicated by the low time. BUSY Rev. D | Page 30 of 40 Data Sheet AD5390/AD5391/AD5392 Table 23. AD5390/AD5392 Channel Monitor Decoding MON_OUT MON_OUT REG1 REG0 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 to DB0 (AD5390) (AD5392) 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT 0 VOUT 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT 1 VOUT 1 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT 2 VOUT 2 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT 3 VOUT 3 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT 4 VOUT 4 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT 5 VOUT 5 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT 6 VOUT 6 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT 7 VOUT 7 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT 8 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT 9 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT 10 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT 11 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT 12 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT 13 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT 14 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT 15 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN 1 MON_IN 1 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN 2 MON_IN 2 0 0 1 0 1 0 1 1 1 1 1 1 X Three-state Three-state Table 24. AD5391 Channel Monitor Decoding REG1 REG0 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 to DB0 MON_OUT (AD5391) 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT 1 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT 2 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT 3 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT 4 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT 5 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT 6 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT 7 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT 8 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT 9 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT 10 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT 11 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT 12 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT 13 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT 14 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT 15 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN 1 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN 2 0 0 1 0 1 0 1 1 0 1 1 0 X Undefined 0 0 1 0 1 0 1 1 . . . . X Undefined 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 1 0 1 0 1 1 1 1 1 1 X Three-state Rev. D | Page 31 of 40 AD5390/AD5391/AD5392 Data Sheet CONTROL REGISTER WRITE Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0, A3 to A0 = 1100, and DB13 to DB0 contain the control register data. Table 25. AD5390/AD5392 Control Register Contents MSB LSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Table 26. AD5390 and AD5392 Bit Descriptions Bit Description CR13 Power-Down Status. This bit is used to configure the output amplifier state in power–down mode. CR13 = 1: Amplifier output is high impedance (default on power-up). CR13 = 0: Amplifier output is 100 kΩ to ground. CR12 REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows: CR12 = 1: Internal reference is 2.5 V (AD5390-2/AD5392-5 default). Recommended operating reference for AD539x-5. CR12 = 0: Internal reference is 1.25 V (AD5390-3/AD5392-3 default). Recommended operating reference for AD5390-3 and AD5392-3. CR11 Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is configured as follows: CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. CR10 Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference. CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12. CR10 = 0: External reference selected (default on power-up). CR9 Channel Monitor Enable (see Table 23). CR9 = 1: Monitor enabled (default on power-up). This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR9 = 0: Monitor disabled. When monitor is disabled, the MON_OUT pin is three-stated. CR8 Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the AD5390/AD5392. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be used to protect the device when the power dissipation of the device may be exceeded, if a number of output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature has dropped below 130°C. CR8 = 1: Thermal monitor enabled. CR8 = 0: Thermal monitor disabled (default on power-up). CR7 to CR4 Don’t Care. CR3 to CR2 Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in toggle mode on the AD5390 and AD5392, as follows: CR3 Group 1 Channel 8 to Channel 15 CR2 Group 0 Channel 0 to Channel 7 CR2 is the only active bit on the AD5392. Logic 1 written to any bit enables a group of channels and Logic 0 disables a group. LDAC is used to toggle between the two registers. CR1 to CR0 Don’t Care. Rev. D | Page 32 of 40 Data Sheet AD5390/AD5391/AD5392 Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0, A3 to A0 = 1100, and DB13 to DB0 contain the control register data. Table 27. AD5391 Control Register Contents MSB LSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Table 28. AD5391 Bit Descriptions Bit Description CR11 Power-Down Status. This bit is used to configure the output amplifier state in power-down mode. CR11 = 1: Amplifier output is high impedance (default on power-up). CR11 = 0: Amplifier output is 100 kΩ to ground. CR10 REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows: CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5. CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3. CR9 Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is configured as follows: CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. CR8 Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference. CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10. CR8 = 0: External reference selected (default on power-up). CR7 Channel Monitor Enable (see Table 24). CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated. CR6 Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the AD5391, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature has dropped below 130°C. CR6 = 1: Thermal monitor enabled. CR6 = 0: Thermal monitor disabled (default on power-up). CR5 to CR2 Don’t Care. CR1 to CR0 Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for each DAC. Control Register Bit CR1 and Bit CR0 are used to enable individual groups of eight channels for operation in toggle mode on the AD5391, as follows: CR1 Group 1 Channel 8 to Channel 15 CR0 Group 0 Channel 0 to Channel 7 Logic 1 written to any bit enables a group of channels and Logic 0 disables a group. LDAC is used to toggle between the two registers. Rev. D | Page 33 of 40 AD5390/AD5391/AD5392 Data Sheet HARDWARE FUNCTIONS RESET FUNCTION POWER-ON RESET Bringing the line low resets the contents of all internal The AD539x products contain a power-on reset generator RESET and state machine. The power-on reset resets all registers to a registers to their power-on reset state. RESET is a negative edge- predefined state, and the analog outputs are configured as high sensitive input. The default corresponds to m at full scale and impedance outputs. The pin goes low during the power- BUSY c at zero scale. The contents of all DAC registers are cleared by on reset sequence, preventing data writes to the device. setting the outputs to 0 V. This sequence takes 270 µs maximum. The falling edge of initiates the reset process. goes RESET BUSY POWER-DOWN low for the duration, returning high when RESET is complete. The AD539x products contain a global power-down feature that While is low, all interfaces are disabled and all BUSY LDAC puts all channels into a low power mode, reducing the analog pulses are ignored. When BUSY returns high, the part resumes power consumption to 1 µA maximum and the digital power normal operation, and the status of the pin is ignored RESET consumption to 20 µA maximum. In power-down mode, the until the next falling edge is detected. output amplifier can be configured as a high impedance output or to provide a 100 kΩ load to ground. The contents of all ASYNCHRONOUS CLEAR FUNCTION internal registers are retained in power-down mode. When CLR is negative-edge-triggered and BUSY goes low for the exiting power-down, the settling time of the amplifier elapses duration of the execution. Bringing the line low CLR CLR before the outputs settle to their correct value. clears the contents of the DAC registers to the data contained in MICROPROCESSOR INTERFACING the user-configurable CLR register and sets the analog outputs AD539x to MC68HC11 accordingly. This function can be used in system calibration The serial peripheral interface (SPI) on the MC68HC11 is to load zero scale and full scale to all channels together. The configured for master mode (MSTR = 1), clock polarity bit execution time for a CLR is 20 µs on the AD5390/AD5391 and (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is 15 µs on the AD5392. configured by writing to the SPI control register (SPCR)—see AND FUNCTIONS BUSY LDAC the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD539x, the MOSI output drives the serial data BUSY is a digital CMOS output indicating the status of the line (DIN) of the AD539x, and the MISO input is driven from AD539x devices. goes low during internal calculations BUSY DOUT. The SYNC signal is derived from a port line (PC7). When of x2 data. If LDAC is taken low while BUSY is low, this event data is being transmitted to the AD539x, the line is taken SYNC is stored. The user can hold the input permanently low LDAC low (PC7). Data appearing on the MOSI output is valid on the and, in this case, the DAC outputs update immediately falling edge of SCK. Serial data from the MC8HC11 is trans- after BUSY goes high. BUSY also goes low during a power-on mitted in 8-bit bytes with only eight falling clock edges reset and when a falling edge is detected on the pin. RESET occurring in the transmit cycle. During this time, all interfaces are disabled and any events DV DD on LDAC AD539x MC68HC11 are ignored. RESET The AD539x products contain an extra feature whereby a DAC register is not updated unless its x2 register has been written MISO SDO to since the last time LDAC was brought low. Normally, MOSI DIN when is brought low, the DAC registers are filled with LDAC SCK SCLK the contents of the x2 registers. However, these devices update PC7 SYNC the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk. 2 SPI/I C Figure 37. AD539x-MC68HC11 Interface Rev. D | Page 34 of 40 03773-026 Data Sheet AD5390/AD5391/AD5392 DV DD AD539x to PIC16C6x/7x AD539x The PIC16C6x/7x synchronous serial port (SSP) is configured 8xC51 as an SPI master with the clock polarity bit = 0. This is done RESET 2 by writing to the synchronous serial port control register SPI/I C (SSPCON)—see the PIC16/17 Microcontroller User Manual. DV DD In Figure 38, I/O port RA1 is used to pulse SYNC and enable the serial port of the AD539x. This microcontroller transfers RxD SDO only eight bits of data during each serial transfer operation; DIN therefore, three consecutive read/write operations are needed, TxD SCLK depending on the mode. Figure 38 shows the connection diagram. SYNC P1.1 DV DD Figure 39. AD539x to 8051 Interface AD539x PIC16C6x/7x AD539x to ADSP2101/ADSP2103 RESET Figure 40 shows a serial interface between the AD539x and 2 SPI/I C the ADSP2101/ADSP2103. The ADSP2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing SDI/RC4 SDO mode. The ADSP2101/ADSP2103 SPORT is programmed through the SPORT control register and should be configured SDO/RC5 DIN as follows: internal clock operation, active low framing, and SCK/RC3 SCLK 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. RA1 SYNC Figure 38. AD539x to PIC16C6x/7x Interface DV DD AD539x AD539x to 8051 ADSP2101/ ADSP2103 The AD539x requires a clock synchronized to the serial data. RESET 2 SPI/I C The 8051 serial interface must, therefore, be operated in Mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 39 shows how the 8051 is DR SDO DT DIN connected to the AD539x. Because the AD539x shifts data out SCK SCLK on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD539x TFS SYNC requires its data with the MSB first. Because the 8051 outputs RFS the LSB first, the transmit routine must take this into account. Figure 40. AD539x to ADSP2101/ADSP2103 Interface Rev. D | Page 35 of 40 03773-027 03773-029 03773-028 AD5390/AD5391/AD5392 Data Sheet APPLICATION INFORMATION Suitable external references for the AD539x-3 include the POWER SUPPLY DECOUPLING ADR280 1.2 V reference. The reference should be decoupled at In any circuit where accuracy is important, careful the REFOUT/ REFIN pin of the device with a 0.1 µF capacitor. consideration of the power supply and ground return layout AV DV DD DD helps to ensure the rated performance. The printed circuit 0.1µF board on which the AD539x is mounted should be designed so that the analog and digital sections are separated and confined 10µF 0.1µF ADR431/ to certain areas of the board. If the AD539x is in a system where ADR421 multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground AV DV DD DD point should be established as close as possible to the device. REFOUT/REFIN VOUT 0 For supplies with multiple pins (AV , AV ), it is recom- 0.1µF DD CC AD539x mended to tie those pins together. The AD539x should have REF_GND VOUT 15 ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible—ideally right DAC_GND SIGNAL_GND AGND DGND up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as Figure 41. Typical Configuration with External Reference the common ceramic types that provide a low impedance path Figure 42 shows a typical configuration when using the internal to ground at high frequencies, to handle transient currents due reference. On power-up, the AD539x defaults to an external to internal logic switching. reference; therefore, the internal reference needs to be configured The power supply lines of the AD539x should use as large a and turned on via a write to the AD539x control register. On the trace as possible to provide low impedance paths and reduce AD5390/AD5392, Control Register Bit CR12 lets the user choose the effects of glitches on the power supply line. Fast switching the reference voltage; Bit CR10 is used to select the internal signals such as clocks should be shielded with digital ground reference. It is recommended to use the 2.5 V reference when to avoid radiating noise to other parts of the board, and should AV = 5 V, and the 1.25 V reference when AV = 3 V. On the DD DD never run near the reference inputs. A ground line routed AD5391, Control Register Bit CR10 lets the user choose the ref- between the DIN and SCLK lines helps reduce crosstalk erence voltage; Bit CR8 is used to select the internal reference. between them (not required on a multilayer board, because AV DV DD DD there is a separate ground plane, but separating the lines helps). 0.1µF Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each 10µF 0.1µF other. This reduces the effects of feedthrough through the board. A micro-strip technique is by far the best, but not always AV DV DD DD possible with a double-sided board. In this technique, the REFOUT/REFIN VOUT 0 component side of the board is dedicated to ground plane, 0.1µF while signal traces are placed on the soldered side. AD539x REF_GND TYPICAL CONFIGURATION CIRCUIT VOUT 15 Figure 41 shows a typical configuration for the AD539x when DAC_GND SIGNAL_GND AGND DGND configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied together to a common AGND. AGND and DGND are Figure 42. Typical Configuration with Internal Reference. connected together at the AD539x device. On power-up, (Digital Connections Omitted for Clarity) the AD539x defaults to external reference operation. All The AD539x contains an internal power-on reset circuit with a AV lines are connected together and driven from the same DD 10 ms brown-out time. If the power supply ramp rate exceeds 5 V source. It is recommended to decouple close to the device 10 ms, the user should reset the AD539x as part of the initiali- with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this zation process to ensure the calibration data is loaded correctly application, the reference for the AD539x-5 is provided into the device. externally from either an ADR421 or ADR431 2.5 V reference. Rev. D | Page 36 of 40 03773-060 03773-061 Data Sheet AD5390/AD5391/AD5392 AD539x MONITOR FUNCTION The AD5390 contains a channel monitor function consisting 3. Load data to all B registers. of a multiplexer addressed via the interface, allowing any 4. Apply LDAC. channel output to be routed to this pin for monitoring using The is used to switch between the A and B registers in LDAC an external ADC. The channel monitor function must be determining the analog output. The first LDAC configures the enabled in the control register before any channels are routed to the MON_OUT pin. output to reflect the data in the A registers. This mode offers significant advantages if the user wants to generate a square Table 23 and Table 24 contain the decoding information wave at the output on all channels, as could be required to drive required to route any channel on the AD5390, AD5391, and a liquid-crystal-based, variable optical attenuator. AD5392 to the MON_OUT pin. Selecting Channel Address 63 three-states the MON_OUT pin. The AD539x family also Configuring the AD5390, for example, the user writes to the contains two monitor input pins called MON_IN 1 and control register and sets CR3 = 1 and CR2 = 1, enabling the two MON_IN 2. The user can connect external signals to these groups of eight for toggle mode operation. The user must then pins, which under software control can be multiplexed to load data to all 16 A registers and B registers. Toggling the LDAC MON_OUT for monitoring purposes. Figure 43 shows a typical sets the output values to reflect the data in the A and B registers, monitoring circuit implemented using a 12-bit SAR ADC in a and the frequency of the LDAC determines the frequency of the 6-lead SOT package. The external reference input is connected square wave output. The first loads the contents of the A LDAC to MON_IN 1 to allow it to be easily monitored. The controller registers to the DAC registers. Toggle mode is disabled via the output port selects the channel to be monitored, and the input control register; the first LDAC following the disabling of the port reads the converted data from the ADC. toggle mode updates the outputs with the data contained in the A registers. AV DD DIN DATA REFOUT/REFIN AD780/ OUTPUT PORT SYNC REGISTER ADR431 A SCLK AD5390 AV DD MON_IN1 DAC AD7476 CS 14-BIT DAC VOUT REGISTER SCLK INPUT PORT VOUT 0 MON_OUT VIN SDATA GND DATA INPUT INPUT REGISTER CONTROLLER AGND REGISTER DATA B VOUT 15 DAC_GND SIGNAL_GND LDAC A/B CONTROL INPUT Figure 44. Toggle Mode Function Figure 43. Typical Channel Monitoring Circuit THERMAL MONITOR FUNCTION TOGGLE MODE FUNCTION The AD539x family has a temperature shutdown function to The toggle mode function allows an output signal to be protect the chip in case multiple outputs are shorted. The short- generated using the LDAC control signal that switches between circuit current of each output amplifier is typically 40 mA. two DAC data registers. This function is configured using the Operating the AD539x at 5 V leads to a power dissipation of SFR control register, as follows: A write with REG1 = REG0 = 0, 200 mW/shorted amplifier. With five channels shorted, this A3 to A0 = 1100 specifies a control register write. The toggle leads to an extra watt of power dissipation. For the 52-lead mode function is enabled in groups of eight channels using Bit LQFP, the θJA is typically 44°C/W. CR3 and Bit CR2 in the AD5390/AD5392 control register and The thermal monitor is enabled by the user using CR8 in the using Bit CR1 and Bit CR0 in the AD5391 control register. (See AD5390/AD5392 control register and CR6 in the AD5391 the Control Register Write section.) Figure 44 shows a block control register. The output amplifiers on the AD539x are diagram of the toggle mode implementation. Each DAC automatically powered down if the die temperature exceeds channel on the AD539x contains an A and a B data register. approximately 130°C. After a thermal shutdown has occurred, Note that the B registers can be loaded only when toggle mode is enabled. the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130°C or by turning off the To configure the AD539x for toggle mode of operation, the thermal monitor function via the control register. sequence of events is as follows: 1. Enable toggle mode for the required channels via the control register. 2. Load data to all A registers. Rev. D | Page 37 of 40 03773-030 03773-031 AD5390/AD5391/AD5392 Data Sheet Power Amplifier Control 0.1µF Multistage power amplifier designs require a large number of 2.5V setpoints in the operation and control of the output stage. The 4R REFERENCE 2R AD539x are ideal for these applications because of their small ±10V R ±5V R RANGE VOUT 3 size (LFCSP) and the integration of 8 and 16 channels, offering VOUT 0 RANGE 12- and 14-bit resolution. Figure 45 shows a typical transmitter R 1/4 OP747/ 1/4 OP747/ R 4R 1/4 OP4177 AD539x-5 1/4 OP4177 2R architecture, in which the AD539x DACs can be used in the 0V TO 5V following control circuits: I control, average power control BIAS RANGE 0V TO 10V VOUT 1 (APC), peak power control (PPC), transmit gain control (TGC), RANGE VOUT 4 and audio level control (ALC). DACs are also required for 1/4 OP747/ 1/4 OP4177 variable voltage attenuators, phase shifter control, and dc- I SINK R VOUT 2 R 1/4 OP747/ setpoint control in the overall amplifier design. 1/4 OP4177 PHASE I BIAS SHIFT R1 Figure 46. Output Configurations for Process Control Applications Optical Transceivers POWER AUDIO 50Ω The AD539x-3 family of products are ideally suited to optical EXCITER AMPLIFIER SOURCE LOAD transceiver applications. In 300-pin MSA applications, for example, digital-to-analog converters are required to control the laser power, APD bias, and modulator amplitude. Diagnostic information is required as analog outputs from the module. The AD539x-3 products offer a combination of 8/16 channels, a resolution of 12/14 bits in a 64-lead LFCSP, and operate from a ALC PPC APC TGC supply voltage of 2.7 V to 5.5 V supply with internal reference. 2 The AD539x-3 parts also feature I C-compatible and SPI inter- Figure 45. Multistage Power Amplifier Control faces, making them ideal components for use in these applications. Process Control Applications Figure 47 shows a typical configuration in an optical transceiver The AD539x-5 family is ideal for process control applications application. because it offers a combination of 8 and 16 channels and 12-bit 3V CONTROLLER and 14-bit resolution. These applications generally require SDA SCL DV AV DD DD SDA output voltage ranges of 0 V to 5 V ± 5 V, 0 V to 10 V ± 10 V, 2 I C BUS SCL VLSRBIAS and current sink and source functions. The AD539x-5 products REFOUT/REFIN VLSRPWRMON PIN/APD IRXP operate from a single 5 V supply and, therefore, require external AND TIA VXLOPMON AD539x-3 signal conditioning to achieve the output ranges described here. AV REFIN DD IMODMON I BIAS Figure 46 shows configurations to achieve these output ranges. 10G LDD AIN 12-BIT AND IMPD MUX ADC IMOD LASER The key advantages of using AD539x-5 products in these IBIASMON AD7994 applications are small package size, pin compatibility with the TIAs ability to upgrade from 12 to 14 bits, integrated on-chip 2.5 V reference with 10 ppm/°C maximum temperature coefficient, Figure 47. Optical Transceiver using the AD539x-3 and excellent accuracy specifications. The AD539x-5 family contains an offset and gain register for each channel, so users can perform system-level calibration on a per-channel basis. Rev. D | Page 38 of 40 03773-032 03773-062 03773-033 Data Sheet AD5390/AD5391/AD5392 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 7.25 8.75 TOP VIEW BSC EXPOSED PAD 7.10 SQ BSC SQ (BOTTOM VIEW) 6.95 0.50 16 33 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 48. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters 12.20 12.00 SQ 0.75 11.80 1.60 0.60 MAX 0.45 52 40 39 1 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 13 27 3.5° 0.15 14 26 0° SEATING 0.05 0.10 PLANE 0.38 COPLANARITY VIEW A 0.65 0.32 BSC LEAD PITCH 0.22 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCC Figure 49. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters Rev. D | Page 39 of 40 051706-A 080108-C AD5390/AD5391/AD5392 ORDERING GUIDE Temperature Output Linearity Package Package 1 Model Range Resolution AV Channels Error (LSBs) Description Option DD AD5390BCPZ-3 −40°C to +85°C 14-bit 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP_VQ CP-64-3 AD5390BCPZ-3-REEL 14-bit 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5390BCPZ-3-REEL7 −40°C to +85°C 14-bit 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP_VQ CP-64-3 AD5390BCPZ-5 14-bit 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5390BCPZ-5-REEL −40°C to +85°C 14-bit 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP_VQ CP-64-3 AD5390BCPZ-5-REEL7 14-bit 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5390BSTZ-3 −40°C to +85°C 14-bit 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BSTZ-5 14-bit 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 −40°C to +85°C AD5391BCPZ-3 12-bit 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5391BCPZ-5 −40°C to +85°C 12-bit 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP_VQ CP-64-3 AD5391BCPZ-5-REEL 12-bit 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5391BCPZ-5-REEL7 −40°C to +85°C 12-bit 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP_VQ CP-64-3 AD5391BSTZ-3 12-bit 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 −40°C to +85°C AD5391BSTZ-5 −40°C to +85°C 12-bit 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5392BCPZ-3 −40°C to +85°C 14-bit 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP_VQ CP-64-3 AD5392BCPZ-5 14-bit 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP_VQ CP-64-3 −40°C to +85°C AD5392BSTZ-3 −40°C to +85°C 14-bit 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BSTZ-5 14-bit 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 −40°C to +85°C EVAL–AD5390EBZ Evaluation Board EVAL–AD5391EBZ Evaluation Board EVAL–AD5392EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03773-0-5/12(D) Rev. D | Page 40 of 40