ANALOG DEVICES AD5383

32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC AD5383 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User programmable offset and gain adjust Power-down mode Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitor User Interfaces APPLICATIONS Parallel Variable optical attenuators (VOA) Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, Level setting (ATE) featuring data readback) Optical microelectro-mechanical systems (MEMS) 2 I C-compatible Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DV (×3) AV (×4) DD DGND (×3) DD AGND (×4) DAC GND (×4) REFGND REFOUT/REFIN SIGNAL GND (×4) PD AD5383 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG 0 REG 0 V 0 OUT DB11/(DIN/SDA) 12 m REG 0 DB10/(SCLK/SCL) FIFO 12 2 DB9/(SPI/I C) R c REG 0 + DB8 R INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC + INPUT DAC DAC 1 DB0 CONTROL REG 1 REG 1 V 1 OUT LOGIC A4 12 V 2 m REG 1 OUT A0 12 c REG 1 R V 3 OUT R REG 0 V 4 OUT 12 12 12 12 V 5 INPUT DAC REG 1 OUT DAC 6 REG 6 REG 6 V 6 POWER-ON OUT RESET RESET 12 m REG 6 12 BUSY c REG 6 R R CLR 12 12 12 12 INPUT DAC V 0………V 31 OUT OUT DAC 7 REG 7 REG 7 V 7 OUT 12 MON_IN1 m REG 7 V 8 OUT 36-TO-1 12 MON_IN2 c REG 7 R MUX MON_IN3 R MON_IN4 V 31 OUT ×4 MON_OUT LDAC Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113© 2004–2010 Analog Devices, Inc. All rights reserved. 03734-001 AD5383 TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function .................................................. 25 Specif ica t ions ..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5383-5 Specifications ............................................................. 4 FIFO Operation in Parallel Mode ............................................ 25 AD5383-3 Specifications ............................................................. 6 Power-On Reset .......................................................................... 25 AC Characteristics ........................................................................ 7 Power-Down ............................................................................... 25 Timing Characteristics ..................................................................... 8 Interfaces.......................................................................................... 26 Serial Interface Timing ................................................................ 8 DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26 2 2 I C Serial Interface Timing ........................................................ 10 I C Serial Interface ..................................................................... 28 Parallel Interface Timing ........................................................... 11 Parallel Interface ......................................................................... 30 Absolute Maximum Ratings .......................................................... 13 Microprocessor Interfacing ....................................................... 31 ESD CAUTION .......................................................................... 13 Application Information ................................................................ 33 Pin Configuration and Function Descriptions ........................... 14 Power Supply Decoupling ......................................................... 33 Terminology .................................................................................... 17 Typical Configuration Circuit .................................................. 33 Typical Performance Characteristics ........................................... 18 Channel Monitor Function ....................................................... 34 Functional Description .................................................................. 21 Toggle Mode Function ............................................................... 34 DAC Architecture—General ..................................................... 21 Thermal Monitor Function ....................................................... 34 Data Decoding ............................................................................ 21 Optical Attenuators .................................................................... 35 On-Chip Special Function Registers (SFR) ............................ 22 Utilizing the FIFO ...................................................................... 36 SFR Commands .......................................................................... 22 Outline Dimensions ....................................................................... 37 Hardware Functions ....................................................................... 25 Ordering Guide .......................................................................... 37 Reset Function ............................................................................ 25 REVISION HISTORY 4/10—Rev. A to Rev. B Changes to Table 18 ........................................................................ 24 Updated Outline Dimensions ....................................................... 37 Changes to Ordering Guide .......................................................... 37 3/05—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Table 3 ............................................................................ 6 Change to Table 5 ............................................................................. 7 Change to Table 18 ......................................................................... 24 5/04—Revision 0: Initial Version Rev. B | Page 2 of 40 AD5383 GENERAL DESCRIPTION The AD5383 is a complete, single-supply, 32-channel, 12-bit An input register followed by a DAC register provides double DAC available in a 100-lead LQFP package. All 32 channels buffering, allowing the DAC outputs to be updated indepen- have an on-chip output amplifier with rail-to-rail operation. dently or simultaneously using the LDAC input. The AD5383 includes a programmable internal 1.25 V/2.5 V, Each channel has a programmable gain and offset adjust 10 ppm/°C reference; an on-chip channel monitor function that register that allows the user to fully calibrate any DAC channel. multiplexes the analog outputs to a common MON_OUT pin With boost off, power consumption is typically 0.25 mA/channel. for external monitoring; and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5383 Table 1 and Table 2 show additional products featuring high features channel count, low voltage, single-supply operation, and bipolar voltage output operation. • Double-buffered parallel interface with a 20 ns WR pulse width. • SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface with interface speeds in excess of 30 MHz. 2 • I C-compatible interface that supports a 400 kHz data transfer rate. Table 1. Other High Channel Count, Low Voltage, Single-Supply DAC Products in Portfolio Model Resolution AV Range Output Channels Linearity Error (LSB) Package Description Package Option DD AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64 Table 2. 40-Channel, Bipolar Voltage Output DAC Model Resolution Analog Supplies Output Channels Linearity Error (LSB) Package Package Option AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108 Rev. B | Page 3 of 40 AD5383 SPECIFICATIONS AD5383-5 SPECIFICATIONS AV = 4.5 V to 5.5 V; DV = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T to T , unless DD DD MIN MAX otherwise noted. Table 3. 1 Parameter AD5383-5 Unit Test Conditions/Comments ACCURACY Resolution 12 Bits 2 Relative Accuracy (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±4 mV max Offset Error ±4 mV max Measured at Code 32 in the linear region Offset Error TC ±5 μV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.06 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 μA max Typically ±30 nA Reference Range 1 to V/2 V min/max DD 4 Reference Output Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage Output Voltage 2.495/2.505 V min/max At ambient; optimized for 2.5 V operation; CR10 = 1 1.22/1.28 V min/max 1.25 V reference selected; CR10 = 0 Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C ±15 ppm/°C max Temperature range: −40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AV V min/max DD Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max R = 5 kΩ 1000 pF max L DC Output Impedance 0.5 Ω max MONITOR PIN Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DV = 2.7 V to 5.5 V DD V , Input High Voltage 2 V min IH V , Input Low Voltage 0.8 V max IL Input Current ±10 μA max Total for all pins; TA = TMIN to TMAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 μA max V , Input Hysteresis 0.05 DV V min HYST DD C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. B | Page 4 of 40 AD5383 1 Parameter AD5383-5 Unit Test Conditions/Comments 3 BUSY LOGIC OUTPUTS ( , SDO) V , Output Low Voltage 0.4 V max DV = 5 V ± 10%, sinking 200 μA OL DD V , Output High Voltage DV – 1 V min DV = 5 V ± 10%, sourcing 200 μA OH DD DD VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 μA VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage Current ±1 μA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 μA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AV 4.5/5.5 V min/max DD DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ΔMidscale/ΔΑVDD –85 dB typ AI 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 2 μA max Typically 200 nA DIDD (Power-Down) 20 μA max Typically 3 μA Power Dissipation 65 mW max Outputs unloaded, boost off, AV = DV = 5 V DD DD 1 AD5383-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5383-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5383 control register; operating the AD5383-5 with a 1.25 V reference leads to degraded accuracy specifications. Rev. B | Page 5 of 40 AD5383 AD5383-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter AD5383-3 Unit Test Conditions/Comments ACCURACY Resolution 12 Bits 2 Relative Accuracy (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 64 in the linear region Offset Error TC ±5 μV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.1 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 μA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max 4 Reference Output Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage Output Voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0 2.47/2.53 V min/max 2.5 V reference enabled; CR10 = 1 Reference TC ±10 ppm/°C typ Temperature range: +25°C to +85°C ±15 ppm/°C typ Temperature range: −40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AV V min/max DD Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max R = 5 kΩ 1000 pF max L DC Output Impedance 0.5 Ω max MONITOR PIN Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 3.6 V V , Input High Voltage 2 V min IH V Input Low Voltage 0.8 V max IL, Input Current ±10 μA max Total for all pins; TA = TMIN to TMAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 μA max V , Input Hysteresis 0.05 DV V min HYST DD C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. B | Page 6 of 40 AD5383 1 Parameter AD5383-3 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) VOL, Output Low Voltage 0.4 V max Sinking 200 μA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 μA High Impedance Leakage Current ±1 μA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 μA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ΔMidscale/ΔΑV –85 dB typ DD AI 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 2 μA max Typically 200 nA DIDD (Power-Down) 20 μA max Typically 1 μA Power Dissipation 39 mW max Outputs unloaded, boost off; AV = DV = 3 V DD DD 1 AD5383-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference leads to degraded accuracy specifications and limited input code range. 1 AC CHARACTERISTICS AV = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DV = 2.7 V to 5.5 V; AGND = DGND = 0 V. DD DD Table 5. Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2 Output Voltage Settling Time ¼ scale to ¾ scale change settling to ±1 LSB 6 μs typ 8 μs max 2 Slew Rate 2 V/μs typ Boost mode off, CR9 = 0 3 V/μs typ Boost mode on, CR9 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 μV p-p typ External reference, midscale loaded to DAC 40 μV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR9) in the AD5383 control register. Rev. B | Page 7 of 40 AD5383 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , unless otherwise DD DD MIN MAX noted. Table 6. 1, 2, 3 Parameter Limit at T , T Unit Description MIN MAX t1 33 ns min SCLK cycle time t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 13 ns min SYNC 24th SCLK falling edge to falling edge 4 t6 33 ns min Minimum SYNC low time t 10 ns min Minimum SYNC high time 7 t 50 ns min Minimum SYNC high time in readback mode 7A t 5 ns min Data setup time 8 t9 4.5 ns min Data hold time 4 t10 30 ns max BUSY 24th SCLK falling edge to falling edge t 670 ns max BUSY 11 pulse width low (single channel update) 4 t 20 ns min LDAC 12 24th SCLK falling edge to falling edge t 20 ns min 13 LDAC pulse width low t14 100 ns max BUSY rising edge to DAC output response time t15 0 ns min BUSY LDAC rising edge to falling edge t 100 ns min LDAC 16 falling edge to DAC output response time t 8 μs typ DAC output settling time, boost mode off 17 t18 20 ns min CLR pulse width low t19 35 μs max CLR pulse activation time 5 t20 20 ns max SCLK rising edge to SDO valid 5 t 5 ns min SYNC 21 SCLK falling edge to rising edge 5 t 8 ns min SYNC 22 rising edge to SCLK rising edge t23 20 ns min SYNC LDAC rising edge to falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of V ) and are timed from a voltage level of 1.2 V. r f CC 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. 200μA I OL V (MIN) OR OH TO OUTPUT PIN V (MAX) C OL L 50pF I 200μA OH Figure 2. Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain Mode) Rev. B | Page 8 of 40 03734-002 AD5383 t 1 24 24 SCLK t t 3 2 t t 4 5 t 6 SYNC t 7 t t 8 9 DB0 DIN DB23 t 10 t 11 BUSY t t 12 13 t 1 17 LDAC t 14 1 V OUT t 15 t 13 2 LDAC t 17 t 16 2 V OUT t 18 CLR t 19 V OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t 1 SCLK 24 48 t t t 3 2 21 t 7 t t 22 4 SYNC t t 8 9 DB23 DB0 DB23 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1 t 20 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 13 t 23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. B | Page 9 of 40 03734-003 03734-005 03734-004 AD5383 2 I C SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. 1, 2 Parameter Limit at TMIN, TMAX Unit Description FSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT 3 t6 0.9 μs max tHD,DAT, data hold time 0 μs min tHD,DAT, data hold time t 0.6 μs min t , setup time for repeated start 7 SU,STA t 0.6 μs min t , stop condition setup time 8 SU,STO t 1.3 μs min t , bus free time between a STOP and a START condition 9 BUF t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min t , fall time of SDA when receiving (CMOS-compatible) F 300 ns max t , fall time of SCL and SDA when receiving F 4 20 + 0.1 C ns min t , fall time of SCL and SDA when transmitting b F Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD. SDA t t t t t 9 3 10 11 4 SCL t t t t t 4 6 2 1 8 t t 5 7 START REPEATED STOP CONDITION START CONDITION CONDITION 2 Figure 6. I C-Compatible Serial Interface Timing Diagram Rev. B | Page 10 of 40 03734-006 AD5383 PARALLEL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 8. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description t0 4.5 ns min WR REG0, REG1, address to rising edge setup time t1 4.5 ns min WR REG0, REG1, address to rising edge hold time t 20 ns min CS 2 pulse width low t 20 ns min WR 3 pulse width low t 0 ns min 4 CS WR to falling edge setup time t5 0 ns min WR CS to rising edge hold time t6 4.5 ns min WR Data to rising edge setup time t 4.5 ns min WR 7 Data to rising edge hold time t 20 ns min WR 8 pulse width high 4 t9 700 ns min WR Minimum cycle time (single-channel write) 4 t10 30 ns max WR BUSY rising edge to falling edge 4, 5 t11 670 ns max BUSY pulse width low (single-channel update) t 30 ns min WR LDAC 12 rising edge to falling edge t 20 ns min LDAC 13 pulse width low t14 100 ns max BUSY rising edge to DAC output response time t15 20 ns min LDAC WR rising edge to rising edge t 0 ns min BUSY LDAC 16 rising edge to falling edge t 100 ns min LDAC 17 falling edge to DAC output response time t 8 μs max DAC output settling time 18 t19 20 ns min CLR pulse width low t20 35 μs max CLR pulse activation time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.2 V. R R DD 3 See Figure 7. 4 See Figure 29. 5 Measured with the load circuit of Figure 2. Rev. B | Page 11 of 40 AD5383 t t 0 1 REG0, REG1, A4..A0 t t 4 5 t 2 CS t 9 t t 3 8 WR t t t 15 6 7 DB11..DB0 t 10 t 11 BUSY t t 12 13 t 18 1 LDAC t 14 1 V OUT t 16 2 LDAC t 13 t 18 t 2 17 V OUT CLR t 19 t V 20 OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev. B | Page 12 of 40 03734-007 AD5383 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted . Table 9. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AV to AGND –0.3 V to +7 V DD rating only; functional operation of the device at these or any DV to DGND –0.3 V to +7 V DD other conditions above those listed in the operational sections Digital Inputs to DGND –0.3 V to DVDD + 0.3 V of this specification is not implied. Exposure to absolute SDA/SCL to DGND –0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Outputs to DGND –0.3 V to DVDD + 0.3 V device reliability. REFIN/REFOUT to AGND –0.3 V to AV + 0.3 V DD AGND to DGND –0.3 V to +0.3 V V x to AGND –0.3 V to AV + 0.3 V OUT DD Analog Inputs to AGND –0.3 V to AVDD + 0.3 V MON_IN Inputs to AGND –0.3 V to AVDD + 0.3 V MON_OUT to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (TJ Max) 150°C 100-Lead LQFP Package θ Thermal Impedance 44°C/W JA Reflow Soldering Peak Temperature 230°C 1 Transient currents of up to 100 mA will not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 13 of 40 AD5383 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 FIFO EN 75 RESET PIN 1 CLR 2 74 DB5 IDENTIFIER V 24 3 73 DB4 OUT 4 V 25 72 OUT DB3 5 V 26 71 DB2 OUT V 27 6 70 DB1 OUT 7 SIGNAL_GND4 69 DB0 8 DAC_GND4 68 NC 9 AGND4 67 NC AV 4 10 66 REG0 DD V 28 11 65 REG1 OUT V 29 12 64 OUT V 23 AD5383 OUT 13 V 30 63 V 22 OUT TOP VIEW OUT 14 V 31 (Not to Scale) 62 V 21 OUT OUT REF GND 15 61 V 20 OUT 16 REFOUT/REFIN 60 AV 3 DD 17 SIGNAL_GND1 59 AGND3 18 DAC_GND1 58 DAC_GND3 19 AV 1 57 SIGNAL_GND3 DD V 0 20 56 V 19 OUT OUT 21 V 1 55 OUT V 18 OUT 22 V 2 54 V 17 OUT OUT V 3 23 53 V 16 OUT OUT V 4 24 52 AV 2 OUT DD 25 AGND1 51 AGND2 Figure 8. 100-Lead LQFP Pin Configuration Table 10. Pin Function Descriptions Mnemonic Function VOUTx Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND(1 to 4) Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5383. DAC_GND(1 to 4) Each Group of Eight Channels Contains a DAC_GND Pin. This is the ground reference point for the internal 12-bit DAC. These pins shound be connected to the AGND plane. AGND(1 to 4) Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD(1 to 4) Analog Supply Pins. Each group of eight channels has a separate AV pin. These pins are connected together DD internally and should be decoupled with a 0.1 μF ceramic capacitor and a 10 μF tantalum capacitor. Operating range for the AD5383-5 is 4.5 V to 5.5 V; operating range for the AD5383-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with 0.1 μF ceramic and 10 μF tantalum capacitors to DGND. REF GND Ground Reference Point for the Internal Reference. REFOUT/REFIN The AD5383 Contains a Common REFOUT/REFIN Pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input. Rev. B | Page 14 of 40 26 NC 100 CS/(SYNC/AD0) 27 99 NC DB11/(DIN/SDA) NC 28 98 DB10/(SCLK/SCL) 2 NC 29 97 DB9/(SPI/I C) V 5 30 96 DB8 OUT V 6 31 95 DB7 OUT V 7 32 94 DB6 OUT NC 33 93 SDO(A/B) NC 34 92 DV DD 35 91 MON_IN1 DGND MON_IN2 36 90 DGND MON_IN3 37 89 NC MON_IN4 38 88 A4 39 NC 87 A3 40 86 MON_OUT A2 V 8 41 85 A1 OUT V 9 42 84 A0 OUT V 10 43 83 DV OUT DD 44 82 V 11 DV OUT DD V 12 45 81 DGND OUT DAC_GND2 46 80 SER/PAR SIGNAL_GND2 47 79 PD 48 V 13 78 WR (DCEN/AD1) OUT 49 77 LDAC V 14 OUT V 15 50 76 BUSY OUT 03734-008 AD5383 Mnemonic Function MON_OUT MON_OUT Monitor Output Pin. When the monitor function is enabled, this output acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31or any of the monitor input pins (MON_IN1 to MON_IN4) to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω, and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. MON_INx MON_IN Monitor Input Pins. The AD5383 contains four monitor input pins that allow the user to connect input signals within the maximum ratings of the device to these pins for monitoring purposes. Any of the signals applied to the MON_IN pins along with the 32 output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals. PAR Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied SER/ 2 2 SPI high, the serial interface mode is selected and Pin 97 ( /I C) is used to determine if the interface mode is SPI or I C. Parallel interface mode is selected when SER/PAR is low. CS SYNC Parallel Interface Mode. This pin acts as chip select input (level sensitive, active low). When low, the AD5383 is /( /AD0) selected. Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address 2 for the device on the I C bus. WR Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a /(DCEN/AD1) 2 daisy-chain enable in SPI mode, and as a hardware address pin in I C mode. WR CS Parallel Interface Write Input (Edge Sensitive). The rising edge of is used in conjunction with low and the address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction PAR with SER/ high to enable the SPI serial interface daisy-chain mode. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address 2 for this device on the I C bus. DB11 to DB0 Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5383. A4 to A0 Parallel Address Inputs. A4 to A0 are decoded to address one of the AD5383’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. REG1, REG0 Register Pins. In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. A Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a SDO/( /B) number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5383’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels contain two data registers. In normal mode, Data Register A is the default for data transfers. BUSY BUSY Digital CMOS Output. goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers in parallel mode (these are LDAC stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If is taken low BUSY BUSY BUSY while is low, this event is stored. also goes low during power-on reset, and when the pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input LDAC registers are transferred to the DAC registers and the DAC outputs are updated. If is taken low while BUSY is LDAC active and internal calculations are taking place, the event is stored and the DAC registers are updated when BUSY LDAC RESET goes inactive. However any events on during power-on reset or on are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated BUSY with the data contained in the CLR code register. is low for a duration of 35 μs while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 μs. The falling edge of RESET RESET BUSY RESET initiates the process and goes low for the duration, returning high when is complete. BUSY LDAC BUSY While is low, all interfaces are disabled and all pulses are ignored. When returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. Rev. B | Page 15 of 40 AD5383 Mnemonic Function PD Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode where the device consumes 2 μA analog supply current and 20 μA digital supply current. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or will provide a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. FIFO EN FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is 2 sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I C interface modes, the FIFO EN pin should be tied low. 2 SPI Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial DB9/( /I C) interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data (DIN) input. 2 When serial interface mode is selected (SER/PAR = 1) and this input is high I C mode is selected. In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input. DB10/(SCLK/SCL) Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial interface mode, this pin acts as a serial clock input. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 50 MHz. 2 2 2 I C Mode. In I C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I C mode is compatible with both 100 kHz and 400 kHz operating modes. DB11/(DIN/SDA) Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. 2 2 I C Mode. In I C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. NC No Connect. The user is advised not to connect any signal to these pins. Rev. B | Page 16 of 40 AD5383 TERMINOLOGY Relative Accuracy DC Output Impedance Relative accuracy, or endpoint linearity, is a measure of the DC output impedance is the effective output source resistance. maximum deviation from a straight line passing through the It is dominated by package lead resistance. endpoints of the DAC transfer function. It is measured after Output Voltage Settling Time adjusting for zero-scale error and full-scale error, and is Output voltage settling time is the amount of time it takes for expressed in LSB. the output of a DAC to settle to a specified level for a ¼ to ¾ Differential Nonlinearity BUSY full-scale input change, and is measured from the rising Differential nonlinearity is the difference between the measured edge. change and the ideal 1 LSB change between any two adjacent Digital-to-Analog Glitch Energy codes. A specified differential nonlinearity of 1 LSB maximum Digital-to-analog glitch energy is the amount of energy injected ensures monotonicity. into the analog output at the major code transition. It is Zero-Scale Error specified as the area of the glitch in nV-s. It is measured by Zero-scale error is the error in the DAC output voltage when all toggling the DAC register data between 0x1FFF and 0x2000. 0s are loaded into the DAC register. Ideally, with all 0s loaded to n – 1 DAC-to-DAC Crosstalk the DAC and m = all 1s, c = 2 DAC-to-DAC crosstalk is the glitch impulse that appears at the = 0 V VOUT(Zero-Scale) output of one DAC due to both the digital change and to the subsequent analog output change at another DAC. The victim Zero-scale error is a measure of the difference between VOUT channel is loaded with midscale. DAC-to-DAC crosstalk is (actual) and VOUT (ideal), expressed in mV. It is mainly due to specified in nV-s. offsets in the output amplifier. Digital Crosstalk Offset Error The glitch impulse transferred to the output of one converter Offset error is a measure of the difference between V (actual) OUT due to a change in the DAC register code of another converter is and V (ideal) in the linear region of the transfer function, OUT defined as the digital crosstalk and is specified in nV-s. expressed in mV. Offset error is measured on the AD5383-5 with Code 32 loaded into the DAC register, and on the Digital Feedthrough AD5383-3 with Code 64. When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both Gain Error across and through the device to show up as noise on the VOUT Gain Error is specified in the linear region of the output range pins. It can also be coupled along the supply and ground lines. between V = 10 mV and V = AV – 50 mV. It is the OUT OUT DD This noise is digital feedthrough. deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded. Output Noise Spectral Density Output noise spectral density is a measure of internally DC Crosstalk generated random noise. Random noise is characterized as a DC crosstalk is the dc change in the output level of one DAC at spectral density (voltage per √Hertz). It is measured by loading midscale in response to a full-scale code (all 0s to all 1s, and all DACs to midscale and measuring noise at the output. It is vice versa) and output change of all other DACs. It is expressed measured in nV/√Hz in a 1 Hz bandwidth at 10 kHz. in LSB. Rev. B | Page 17 of 40 AD5383 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 1.00 AV = 5V AV = 3V DD DD REFIN = 2.5V REFIN = 1.25V 0.75 0.75 T = 25°C T = 25°C A A 0.50 0.50 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 INPUT CODE INPUT CODE Figure 9. Typical AD5383-5 INL Plot Figure 12. Typical AD5383-3 INL Plot 2.539 1.254 AV = DV = 5V DD DD AV = DV = 3V DD DD 2.538 V = 2.5V REF V = 1.25V REF 1.253 2.537 T = 25°C A T = 25°C A 14ns/SAMPLE NUMBER 2.536 14ns/SAMPLE NUMBER 1.252 1 LSB CHANGE AROUND MIDSCALE 1 LSB CHANGE AROUND MIDSCALE 2.535 GLITCH IMPULSE = 10nV-s GLITCH IMPULSE = 5nV-s 2.534 1.251 2.533 2.532 1.250 2.531 1.249 2.530 2.529 1.248 2.528 2.527 1.247 2.526 2.525 1.246 2.524 2.523 1.245 0 50 100 150 200 250 300 350 400 450 500 550 0 50 100 150 200 250 300 350 400 450 500 550 SAMPLE NUMBER SAMPLE NUMBER Figure 10. AD5383-5 Glitch Impulse Figure 13. AD5383-3 Glitch Impulse AV = DV = 5V DD DD V = 2.5V REF T = 25°C A AV = DV = 5V DD DD V = 2.5V REF T = 25°C V A OUT V OUT Figure 11. Slew Rate with Boost Off Figure 14. Slew Rate with Boost On Rev. B | Page 18 of 40 AMPLITUDE (V) INL ERROR (LSB) 03734-011 03734-010 03734-009 AMPLITUDE (V) INL ERROR (LSB) 03734-014 03734-013 03734-012 AD5383 14 AV = 5.5V DD V = 2.5V REF T = 25°C A AV = DV = 5V DD DD 12 V = 2.5V REF T = 25°C A POWER SUPPLY RAMP RATE = 10ms 10 V OUT 8 6 4 AV DD 2 89 10 11 AI (mA) DD Figure 15. AI Histogram Figure 18. Power-Up Transient DD 40 DV = 5.5V DD V = DV IH DD 10 35 V = DGND IL T = 25°C A 30 8 25 6 20 15 4 10 2 5 0 0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 0.4 0.5 0.6 0.7 0.8 0.9 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 DI (mA) DD REFERENCE DRIFT (ppm/°C) Figure 16. DI Histogram Figure 19. REFOUT Temperature Coefficient DD PD WR BUSY AV = DV = 5V DD DD V = 2.5V REF T = 25°C A EXITS SOFT PD V OUT AV = DV = 5V TO MIDSCALE DD DD V = 2.5V REF V T = 25°C OUT A EXITS HARDWARE PD TO MIDSCALE Figure 17. Exiting Soft Power-Down Figure 20. Exiting Hardware Power-Down Rev. B | Page 19 of 40 NUMBER OF UNITS PERCENTAGE OF UNITS (%) 03734-017 03734-016 03734-015 FREQUENCY 03734-018 03734-019 03734-020 AD5383 6 6 AV = DV = 3V DD DD FULL-SCALE V = 1.25V REF T = 25°C A 5 5 AV = DV = 5V DD DD V = 2.5V 3/4 SCALE REF T = 25°C 4 4 A 3/4 SCALE FULL-SCALE 3 MIDSCALE 3 MIDSCALE 2 2 1/4 SCALE 1 1 ZERO-SCALE 0 0 ZERO-SCALE 1/4 SCALE –1 –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 –40 –20 –10 –5 –2 0 2 5 10 20 40 CURRENT (mA) CURRENT (mA) Figure 21. AD5383-5 Output Amplifier Source and Sink Capability Figure 24. AD5383-3 Output Amplifier Source and Sink Capability 0.20 2.456 AV = 5V DD AV = DV = 5V DD DD V = 2.5V REF V = 2.5V REF 0.15 T = 25°C A T = 25°C 2.455 A 14ns/SAMPLE NUMBER 0.10 2.454 ERROR AT ZERO SINKING CURRENT 0.05 2.453 0 2.452 –0.05 2.451 (V –V ) AT FULL-SCALE SOURCING CURRENT DD OUT –0.10 2.450 –0.15 –0.20 2.449 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 50 100 150 200 250 300 350 400 450 500 550 I /I (mA) SAMPLE NUMBER SOURCE SINK Figure 22. Headroom at Rails vs. Source/Sink Current Figure 25. Adjacent Channel DAC-to-DAC Crosstalk 600 AV = 5V AV = DV = 5V DD DD DD T = 25°C T = 25°C A A REFOUT DECOUPLED DAC LOADED WITH MIDSCALE 500 WITH 100nF CAPACITOR EXTERNAL REFERENCE Y AXIS = 5μV/DIV X AXIS = 100ms/DIV 400 300 REFOUT = 2.5V 200 AV = DV = 5V DD DD V = 2.5V REF T = 25°C REFOUT = 1.25V A 100 EXITS SOFT PD TO MIDSCALE 0 100 1k 10k 100k FREQUENCY (Hz) Figure 23. REFOUT Noise Spectral Density Figure 26. 0.1 Hz to 10 Hz Noise Plot Rev. B | Page 20 of 40 OUTPUT NOISE (nV/ Hz) ERROR VOLTAGE (V) V (V) OUT 03734-023 03734-022 03734-021 AMPLITUDE (V) V (V) OUT 03734-026 03734-025 03734-024 AD5383 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The complete transfer function for these devices can be represented as The AD5383 is a complete, single-supply, 32-channel voltage output DAC that offers 12-bit resolution. The part is available in n VOUT = 2 × VREF × x2/2 a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software where x2 is the data-word loaded to the resistor string DAC. selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used V is the internal reference voltage or the reference voltage REF to drive the buffered reference inputs; alternatively, an external externally applied to the DAC REFOUT/REFIN pin. For reference can be used to drive these inputs. Internal/external specified performance, an external reference voltage of 2.5 V is reference selection is via the CR8 bit in the control register; recommended for the AD5380-5 and 1.25 V for the AD5380-3. CR10 selects the reference magnitude if the internal reference is DATA DECODING selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ in parallel with a The AD5383 contains a 12-bit data bus, DB11 to DB0. Depending on the value of REG1 and REG0 (see Table 11), this 200 pF load. data is loaded into the addressed DAC input registers, offset (c) AV V DD REF registers, or gain (m) registers. The format data, offset (c), and gain (m) register contents are shown in Table 12 to Table 14. ×1 INPUT REG DAC 12-BIT Table 11. Register Selection INPUT DATA m REG ×2 REG DAC V OUT REG1 REG0 Register Selected c REG R 1 1 Input Data Register (x1) 1 0 Offset Register (c) R 0 1 Gain Register (m) 0 0 Special Function Registers (SFRs) Figure 27. Single-Channel Architecture The architecture of a single DAC channel consists of a 12-bit Table 12. DAC Data Format (REG1 = 1, REG0 = 1) resistor-string DAC followed by an output buffer amplifier DB11 to DB0 DAC Output (V) operating at a gain of 2. This resistor-string architecture 1111 1111 1111 2 V × (4095/4096) REF guarantees DAC monotonicity. The 12-bit binary digital code 1111 1111 1110 2 V × (4094/4096) REF loaded to the DAC register determines at which node on the 1000 0000 0001 2 VREF × (2049/4096) string the voltage is tapped off before being fed to the output 1000 0000 0000 2 VREF × (2048/4096) amplifier. Each channel on these devices contains independent 0111 1111 1111 2 VREF × (2047/4096) offset and gain control registers that allow the user to digitally 0000 0000 0001 2 V × (1/4096) REF trim offset and gain. These registers give the user the ability to 0000 0000 0000 0 calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers, which hold the Table 13. Offset Data Format (REG1 = 1, REG0 = 0) correction factors. All channels are double buffered, allowing DB11 to DB0 Offset (LSB) synchronous updating of all channels using the LDAC pin. 1111 1111 1111 +2048 Figure 27 shows a block diagram of a single channel on the 1111 1111 1110 +2047 AD5383. The digital input transfer function for each DAC can 1000 0000 0001 +1 be represented as 1000 0000 0000 0 0111 1111 1111 –1 n n – 1 x2 = [(m + 2)/ 2 × x1] + (c – 2 ) 0000 0000 0001 –2047 0000 0000 0000 –2048 where: x2 = the data-word loaded to the resistor string DAC. Table 14. Gain Data Format (REG1 = 0, REG0 = 1) x1 = the 12-bit data-word written to the DAC input register. m = the gain coefficient (default is 0xFFE). The gain coefficient DB11 to DB1 Gain Factor is written to the 11 most significant bits (DB11 to DB1) and the 1111 1111 1110 1 LSB (DB0) is 0. 1011 1111 1110 0.75 n = DAC resolution (n = 12 for AD5383). 0111 1111 1110 0.5 c = the12-bit offset coefficient (default is 0x800). 0011 1111 1110 0.25 0000 0000 0000 0 Rev. B | Page 21 of 40 03734-027 AD5383 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5383 contains a number of special function registers REG1 = REG0 = 0, A4 to A0 = 00010 (SFRs), as outlined in Table 15. SFRs are addressed with DB11 to DB0 = don’t care REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit A0. Executing this instruction performs the CLR, which is functionally CLR the same as that provided by the external pin. The DAC Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) outputs are loaded with the data in the CLR code register. It W A4 A3 A2 A1 A0 Function R/ takes 35 μs to fully execute the SOFT CLR, as indicated by the X 0 0 0 0 0 NOP (No Operation) BUSY low time. 0 0 0 0 0 1 Write CLR Code 0 0 0 0 1 0 Soft CLR Soft Power-Down 0 0 1 0 0 0 Soft Power-Down REG1 = REG0 = 0, A4 to A0 = 01000 0 0 1 0 0 1 Soft Power-Up DB11 to DB0 = don’t care 0 0 1 1 0 0 Control Register Write 1 0 1 1 0 0 Control Register Read Executing this instruction performs a global power-down 0 0 1 0 1 0 Channel Monitor feature that puts all channels into a low power mode that 0 0 1 1 1 1 Soft Reset reduces the analog supply current to 2 μA max, and the digital current to 20 μA. In power-down mode, the output amplifier SFR COMMANDS can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are NOP (No Operation) retained in power-down mode. No register can be written to REG1 = REG0 = 0, A4 to A0 = 00000 while in power-down. Soft Power-Up Performs no operation but is useful in serial readback mode to clock out data on D for diagnostic purposes. BUSY pulses OUT REG1 = REG0 = 0, A4 to A0 = 01001 low during a NOP operation. DB11 to DB0 = don’t care Write CLR Code This instruction is used to power up the output amplifiers and the internal reference. The time to exit power-down is 8 μs. The REG1 = REG0 = 0, A4 to A0 = 00001 hardware power-down and software function are internally DB11 to DB0 = contain the CLR data combined in a digital OR function. Bringing the CLR line low or exercising the soft clear function Soft RESET loads the contents of the DAC registers with the data con-tained REG1 = REG0 = 0, A4 to A0 = 01111 CLR in the user configurable register, and sets VOUT0 to VOUT31 DB11 to DB0 = don’t care accordingly. This can be very useful for setting up a specific This instruction is used to implement a software reset. All output voltage in a clear condition. It is also beneficial for internal registers are reset to their default values, which calibration purposes; the user can load full scale or zero scale to correspond to m at full scale and c at zero scale. The contents of the clear code register and then issue a hardware or software the DAC registers are cleared, setting all analog outputs to 0 V. clear to load this code to all DACs, removing the need for The soft reset activation time is 135 μs. individual writes to each DAC. Default on power-up is all zeros. Rev. B | Page 22 of 40 AD5383 Table 16. Control Register Contents MSB LSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Control Register Write/Read REG1 = REG0 = 0, A4 to A0 = 01100, R/W status determines if CR7 = 0: Monitor Disabled (default on power-up). When the monitor is disabled, the MON_OUT pin is three-stated. the operation is a write (R/W = 0) or a read (R/W = 1). DB11 to DB0 contains the control register data. CR6: Thermal Monitor Function. This function is used to monitor the AD5383’s internal die temperature when enabled. Control Register Contents The thermal monitor powers down the output amplifiers when CR11: Power-Down Status. This bit is used to configure the the temperature exceeds 130°C. This function can be used to output amplifier state in power down. protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously CR11 = 1. Amplifier output is high impedance (default on short-circuited. A soft power-up will re-enable the output power-up). amplifiers if the die temperature has dropped below 130°C. CR11 = 0. Amplifier output is 100 kΩ to ground. CR6 = 1: Thermal Monitor Enabled. CR10: REF Select. This bit selects the operating internal CR6 = 0: Thermal Monitor Disabled (default on power-up). reference for the AD5383. CR12 is programmed as follows: CR5 and CR4: Don’t Care. CR10 = 1: Internal reference is 2.5 V (AD5383-5 default), the recommended operating reference for AD5383-5. CR3 to CR0: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A CR10 = 0: Internal reference is 1.25 V (AD5383-3 default), and B registers for each DAC. Control Register Bits CR3 to CR0 the recommended operating reference for AD5383-3. are used to enable individual groups of eight channels for oper- ation in toggle mode. A Logic 1 written to any bit enables a CR9: Current Boost Control. This bit is used to boost the LDAC group of channels; a Logic 0 disables a group. is used to current in the output amplifier, thereby altering its slew rate. toggle between the two registers. Logic 1 enables a group of This bit is configured as follows: channels; Logic 0 disables a group of channels. CR9 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing Table 17. the power dissipation. CR Bit Group Channels CR3 3 24 to 31 CR9 = 0: Boost Mode Off (default on power-up). This CR2 2 16 to 23 reduces the bias current in the output amplifier and reduces CR1 1 8 to 15 the overall power consumption. CR0 0 0 to 7 CR8: Internal/External Reference. This bit determines if the Channel Monitor Function DAC uses its internal reference or an externally applied reference. REG1 = REG0 = 0, A4 to A0 = 01010 CR8 = 1: Internal Reference Enabled. The reference output DB11 to DB6 = Contain data to address the monitored channel. depends on data loaded to CR10. A channel monitor function is provided on the AD5383. This CR8 = 0: External Reference Selected (default on power up). feature, which consists of a multiplexer addressed via the interface, allows any channel output or signals connected to the CR7: Channel Monitor Enable (see Channel Monitor MON_IN pins to be routed to the MON_OUT pin for Function). monitoring using an external ADC. The channel monitor function must be enabled in the control register before any CR7= 1: Monitor Enabled. This enables the channel monitor channels are routed to MON_OUT. On the AD5383, DB11 to function. After a write to the monitor channel in the SFR DB6 contain the channel address for the monitored channel. register, the selected channel output is routed to the Selecting Channel Address 63 three-states MON_OUT. MON_OUT pin. Rev. B | Page 23 of 40 AD5383 Table 18. Channel Monitor Decoding REG1 REG0 A4 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 to DB0 MON_OUT 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4 0 0 0 1 0 1 0 0 0 0 1 0 1 X V 5 OUT 0 0 0 1 0 1 0 0 0 0 1 1 0 X V 6 OUT 0 0 0 1 0 1 0 0 0 0 1 1 1 X V 7 OUT 0 0 0 1 0 1 0 0 0 1 0 0 0 X V 8 OUT 0 0 0 1 0 1 0 0 0 1 0 0 1 X V 9 OUT 0 0 0 1 0 1 0 0 0 1 0 1 0 X V 10 OUT 0 0 0 1 0 1 0 0 0 1 0 1 1 X V 11 OUT 0 0 0 1 0 1 0 0 0 1 1 0 0 X V 12 OUT 0 0 0 1 0 1 0 0 0 1 1 0 1 X V 13 OUT 0 0 0 1 0 1 0 0 0 1 1 1 0 X V 14 OUT 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26 0 0 0 1 0 1 0 0 1 1 0 1 1 X V 27 OUT 0 0 0 1 0 1 0 0 1 1 1 0 0 X V 28 OUT 0 0 0 1 0 1 0 0 1 1 1 0 1 X V 29 OUT 0 0 0 1 0 1 0 0 1 1 1 1 0 X V 30 OUT 0 0 0 1 0 1 0 0 1 1 1 1 1 X V 31 OUT 0 0 0 1 0 1 0 1 0 0 0 0 0 X Undefined 0 0 0 1 0 1 0 1 0 0 0 0 1 X Undefined 0 0 0 1 0 1 0 1 0 0 0 1 0 X MON_IN1 0 0 0 1 0 0 1 0 0 0 1 1 X MON_IN2 0 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN3 0 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State REG1 REG0 A4 A3 A2 A1 A0 000 101 0 V 0 OUT V 1 OUT AD5383 V 30 OUT CHANNEL V 31 MONITOR OUT MON_IN1 DECODING MON_OUT MON_IN2 MON_IN3 MON_IN4 CHANNEL ADDRESS DB11–DB6 Figure 28. Channel Monitor Decoding Rev. B | Page 24 of 40 03734-028 AD5383 HARDWARE FUNCTIONS FIFO OPERATION IN PARALLEL MODE RESET FUNCTION The AD5383 contains a FIFO to optimize operation when RESET Bringing the line low resets the contents of all internal operating in parallel interface mode. The FIFO Enable (level RESET registers to their power-on reset state. is a negative edge- sensitive, active high) is used to enable the internal FIFO. When sensitive input. The default corresponds to m at full scale and to connected to DVDD, the internal FIFO is enabled, allowing the c at zero scale. The contents of the DAC registers are cleared, user to write to the device at full speed. FIFO is only available in setting VOUT0 to VOUT31 to 0 V. This sequence takes 270 μs max. parallel interface mode. The status of the FIFO EN pin is The falling edge of RESET initiates the reset process; BUSY goes sampled on power-up, and after a CLR or RESET, to determine low for the duration, returning high when RESET is complete. 2 if the FIFO is enabled. In either serial or I C interface modes, BUSY LDAC While is low, all interfaces are disabled and all FIFO EN should be tied low. Up to 128 successive instructions BUSY pulses are ignored. When returns high, the part resumes can be written to the FIFO at maximum speed in parallel mode. RESET normal operation and the status of the pin is ignored When the FIFO is full, any further writes to the device are until the next falling edge is detected. ignored. Figure 29 shows a comparison between FIFO mode and non-FIFO mode in terms of channel update time. Figure 29 ASYNCHRONOUS CLEAR FUNCTION also outlines digital loading time. CLR Bringing the line low clears the contents of the DAC 25 registers to the data contained in the user-configurable CLR register and sets V 0 to V 31 accordingly. This function can OUT OUT WITHOUT FIFO be used in system calibration to load zero scale and full scale to 20 (CHANNEL UPDATE TIME) all channels. The execution time for a CLR is 32 μs. 15 BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the 10 AD5383. The value of x2, the internal data loaded to the DAC WITH FIFO (CHANNEL UPDATE TIME) data register, is calculated each time the user writes new data to the corresponding x1, c, or m registers. During the calculation 5 WITH FIFO BUSY BUSY of x2, the output goes low. While is low, the user (DIGITAL LOADING TIME) can continue writing new data to the x1, m, or c registers, but 0 1 4 7 10131619222528 313437 40 no DAC output updates can take place. The DAC outputs are NUMBER OF WRITES LDAC LDAC updated by taking the input low. If goes low while Figure 29. Channel Update Rate (FIFO vs. Non-FIFO) BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. The user may hold POWER-ON RESET the LDAC input permanently low, in which case the DAC The AD5383 contains a power-on reset generator and state outputs update immediately after BUSY goes high. BUSY also machine. The power-on reset resets all registers to a predefined goes low during power-on reset and when a falling edge is state and configures the analog outputs as high impedance. The RESET detected on the pin. During this time, all interfaces are BUSY pin goes low during the power-on reset sequencing, LDAC disabled and any events on are ignored. The AD5383 preventing data writes to the device. contains an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time POWER-DOWN LDAC was brought low. Normally, when LDAC is brought low, The AD5383 contains a global power-down feature that puts all the DAC registers are filled with the contents of the x2 registers. channels into a low power mode and reduces the analog power However, the AD5383 will only update the DAC register if the consumption to 2 μA maximum and digital power consumption x2 data has changed, thereby removing unnecessary digital to 20 μA maximum. In power-down mode, the output amplifier crosstalk. can be configured as high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values. Rev. B | Page 25 of 40 TIME (μs) 03734-029 AD5383 INTERFACES The AD5383 contains both parallel and serial interfaces. Figure 3 and Figure 5 show timing diagrams for a serial write to Furthermore, the serial interface can be programmed to be the AD5383 in standalone and daisy-chain modes. The 24-bit 2 SPI-, DSP-, MICROWIRE-, or I C-compatible. The SER/PAR data-word format for the serial interface is shown in Table 19. pin selects parallel and serial interface modes. In serial mode, A /B. When toggle mode is enabled, this pin selects whether the 2 2 SPI the /I C pin is used to select DSP, SPI, MICROWIRE, or I C data write is to the A or B register. With toggle disabled, this bit interface mode. should be set to zero to select the A data register. The devices use an internal FIFO memory to allow high speed W R/ is the read or write control bit. successive writes in parallel interface mode. The user can con- tinue writing new data to the device while write instructions are A4 to A0 address the input channels. being executed. The BUSY signal indicates the current status of REG1 and REG0 select the register to which data is written, as the device, going low while instructions in the FIFO are being shown in Table 11. executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO DB11 to DB0 contain the input data-word. is full, any further writes to the device are ignored. X is a don’t care condition. To minimize both the power consumption of the device and the Standalone Mode on-chip digital noise, the active interface only powers up fully when the device is being written to, that is, on the falling edge By connecting the DCEN (daisy-chain enable) pin low, stand- of WR or the falling edge of SYNC. alone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL SYNC edge of starts the write cycle and resets a counter that INTERFACES counts the number of serial clocks to ensure that the correct The serial interface can be operated with a minimum of three number of bits are shifted into the serial shift register. Any wires in standalone mode or four wires in daisy-chain mode. further edges on SYNC, except for a falling edge, are ignored Daisy-chaining allows many devices to be cascaded together to until 24 bits are clocked in. Once 24 bits have been shifted in, increase system channel count. The SER/PAR pin must be tied the SCLK is ignored. In order for another serial transfer to take 2 high and the SPI/I C pin (Pin 97) should be tied low to enable SYNC place, the counter must be reset by the falling edge of . the DSP-/SPI-/MICROWIRE-compatible serial interface. In serial interface mode, the user does not need to drive the parallel input data pins. The serial interface’s control pins are: SYNC , DIN, SCLK—Standard 3-wire interface pins. DCEN—Selects standalone mode or daisy-chain mode. SDO—Data out pin for daisy-chain mode. Table 19. 40-Channel, 12-Bit DAC Serial Input Register Configuration MSB LSB A/B R/W 0 A4 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X Rev. B | Page 26 of 40 AD5383 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin may be W Readback mode is invoked by setting the R/ bit = 1 in the used to daisy-chain several devices together. This daisy-chain W serial input register write. With R/ = 1, Bits A4 to A0, in mode can be useful in system diagnostics and in reducing the association with Bits REG1 and REG0, select the register to be number of serial interface lines. read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO By connecting the DCEN (daisy-chain enable) pin high, daisy- output will contain the data from the previously addressed chain mode is enabled. The first falling edge of SYNC starts the register. For a read of a single register, the NOP command can write cycle. The SCLK is continuously applied to the input shift be used in clocking out the data from the selected register on register when SYNC is low. If more than 24 clock pulses are SDO. Figure 30 shows the readback sequence. For example, to applied, the data ripples out of the shift register and appears on read back the m register of Channel 0 on the AD5383, the the SDO line. This data is clocked out on the rising edge of following sequence should be implemented. First, write SCLK and is valid on the falling edge. By connecting the SDO 0x404XXX to the AD5383 input register. This configures the of the first device to the DIN input on the next device in the AD5383 for read mode with the m register of Channel 0 chain, a multidevice interface is constructed. Twenty-four clock selected. Note that Data Bits DB11 to DB0 are don’t cares. pulses are required for each device in the system. Therefore, the Follow this with a second write, a NOP condition, 0x000000. total number of clock cycles must equal 24N, where N is the During this write, the data from the m register is clocked out on total number of AD538x devices in the chain. the D line, that is, data clocked out will contain the data from OUT the m register in Bits DB11 to DB0, and the top 10 bits contain SYNC When the serial transfer to all devices is complete, is the address information as previously written. In readback taken high. This latches the input data in each device in the SYNC mode, the signal must frame the data. Data is clocked out daisy-chain and prevents any further data from being clocked on the rising edge of SCLK and is valid on the falling edge of into the input shift register. the SCLK signal. If the SCLK idles high between the write and If SYNC is taken high before 24 clocks are clocked into the part, read operations of a readback operation, the first bit of data is SYNC this is considered a bad frame and the data is discarded. clocked out on the falling edge of . The serial clock may be either a continuous or a gated clock. A SYNC continuous SCLK source can only be used if can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must SYNC be used and must be taken high after the final clock to latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23 DB0 DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 30. Serial Readback Operation Rev. B | Page 27 of 40 03734-030 AD5383 2 I C SERIAL INTERFACE AD5383 Slave Addresses 2 The AD5383 features an I C-compatible, 2-wire interface A bus master initiates communication with a slave device by consisting of a serial data line (SDA) and a serial clock line issuing a START condition followed by the 7-bit slave address. (SCL). SDA and SCL facilitate communication between the When idle, the AD5383 waits for a START condition followed AD5383 and the master at rates up to 400 kHz. Figure 6 shows by its slave address. The LSB of the address word is the read/ the 2-wire interface timing diagram that incorporates three 2 W different modes of operation. In selecting the I C operating write (R/ ) bit. The AD5383 is a receive-only device; when W mode, first configure serial operating mode (SER/PAR = 1) and communicating with the AD5383, R/ = 0. After receiving the 2 2 proper address 10101 (AD1) (AD0), the AD5383 issues an ACK then select I C mode by configuring the SPI/I C pin to a 2 by pulling SDA low for one clock cycle. Logic 1. The device is connected to the I C bus as a slave device (that is, no clock is generated by the AD5383). The AD5383 has The AD5383 has four different user-programmable addresses a 7-bit slave address 10101 (AD1) (AD0). The 5 MSBs are hard- determined by the AD1 and AD0 bits. coded and the 2 LSBs are determined by the state of the AD1 Write Operation and AD0 pins. The facility to hardware-configure AD1 and AD0 allows four of these devices to be configured on the bus. There are three specific modes in which data can be written to 2 the AD5383 DAC. I C Data Transfer One data bit is transferred during each SCL clock cycle. The 4-Byte Mode data on SDA must remain stable during the high period of the When writing to the AD5383 DACs, the user must begin with SCL clock pulse. Changes in SDA while SCL is high are control W an address byte (R/ = 0) after which the DAC acknowledges signals that configure START and STOP conditions. Both SDA that it is prepared to receive data by pulling SDA low. The and SCL are pulled high by the external pull-up resistors when 2 the I C bus is not busy. address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the START and STOP Conditions DAC. Two bytes of data are then written to the DAC, as shown A master device initiates communication by issuing a START in Figure 31. A STOP condition follows. This allows the user to condition. A START condition is a high-to-low transition on update a single channel within the AD5383 at any time and SDA with SCL high. A STOP condition is a low-to-high requires four bytes of data to be transferred from the master. transition on SDA while SCL is high. A START condition from the master signals the beginning of a transmission to the 3-Byte Mode AD5383. The STOP condition frees the bus. If a repeated In 3-byte mode, the user can update more than one channel in a START condition (Sr) is generated instead of a STOP condition, write sequence without having to write the device address byte the bus remains active. each time. The device address byte is only required once; sub- Repeated START Conditions sequent channel updates require the pointer byte and the data A repeated START (Sr) condition may indicate a change of data bytes. In 3-byte mode, the user begins with an address byte direction on the bus. Sr may be used when the bus master is W (R/ = 0), after which the DAC acknowledges that it is 2 writing to several I C devices and wants to maintain control of prepared to receive data by pulling SDA low. The address byte is the bus. followed by the pointer byte. This addresses the specific channel in the DAC to be addressed and is also acknowledged by the Acknowledge Bit (ACK) DAC. This is then followed by the two data bytes. REG1 and The acknowledge bit (ACK) is the ninth bit attached to any REG0 determine the register to be updated. 8-bit data-word. ACK is always generated by the receiving device. The AD5383 devices generate an ACK when receiving If a STOP condition does not follow the data bytes, another an address or data by pulling SDA low during the ninth clock channel can be updated by sending a new pointer byte followed period. Monitoring ACK allows for detection of unsuccessful by the data bytes. This mode only requires three bytes to be sent data transfers. An unsuccessful data transfer occurs if a receiving to update any channel once the device has been initially addressed, device is busy or if a system fault has occurred. In the event of and reduces the software overhead in updating the AD5383 an unsuccessful data transfer, the bus master should reattempt channels. A STOP condition at any time exits this mode. Figure 32 communication. shows a typical configuration. Rev. B | Page 28 of 40 AD5383 SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 0 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB SDA ACK BY ACK BY STOP AD538x AD538x COND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE BY MASTER 2 Figure 31. 4-Byte, I C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 0 A4A3 A2A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 0 A4 A3A2A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP COND AD538x AD538x BY MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" 2 Figure 32. 3-Byte, I C Write Operation Rev. B | Page 29 of 40 03734-032 03734-031 AD5383 PARALLEL INTERFACE 2-Byte Mode The SER/PAR pin must be tied low to enable the parallel Following initialization of 2-byte mode, the user can interface and disable the serial interfaces. Figure 7 shows the sequentially update channels. The device address byte is only timing diagram for a parallel write. The parallel interface is required once, and the address pointer is configured for auto- controlled by the following pins: increment or burst mode. CS Pin The user must begin with an address byte (R/W = 0), after Active low device select pin. which the DAC acknowledges that it is prepared to receive data WR Pin by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. WR CS On the rising edge of , with low, the addresses on The address pointer initializes to Channel 0, the data following Pin A4 to Pin A0 are latched; data present on the data bus is the pointer is loaded to Channel 0, and the address pointer loaded into the selected input registers. automatically increments to the next address. REG0, REG1 Pins The REG0 and REG1 pins determine the destination register The REG0 and REG1 bits in the data byte determine which of the data being written to the AD5383. See Table 11. register is updated. In this mode, following the initializa-tion, only the two data bytes are required to update a channel. The Pins A4 to A0 channel address automatically increments from Address 0 to Each of the 32 DAC channels can be addressed individually. Channel 31 and then returns to the normal 3-byte mode of Pins DB11 to DB0 operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in The AD5383 accepts a straight 12-bit parallel word on DB11 configuring all channels. A STOP condition at any time exits to DB0, where DB11 is the MSB and DB0 is the LSB. this mode. Toggle mode is not supported in 2-byte mode. Figure 33 shows a typical configuration. SCL SDA 1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND ACK BY MSB ACK BY BY MASTER CONVERTER CONVERTER ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY CONVERTER CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP CONVERTER CONVERTER COND MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 33. 2-Byte, I C Write Operation Rev. B | Page 30 of 40 03734-033 AD5383 MICROPROCESSOR INTERFACING Parallel Interface When data is being transmitted to the AD5383, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid The AD5383 can be interfaced to a variety of 16-bit microcon- on the falling edge of SCK. Serial data from the 68HC11 is trollers or DSP processors. Figure 35 shows the AD5383 family transmitted in 8-bit bytes with only eight falling clock edges interfaced to a generic 16-bit microcontroller/DSP processor. The occurring in the transmit cycle. lower address lines from the processor are connected to A0 to A4 on the AD5383. The upper address lines are decoded to DV MC68HC11 DD AD5383 CS LDAC provide a , signal for the AD5383. The fast interface SER/PAR timing of the AD5383 allows direct interface to a wide variety of RESET microcontrollers and DSPs, as shown in Figure 35. MISO SDO MOSI DIN AD5383 to MC68HC11 SCK SCLK The serial peripheral interface (SPI) on the MC68HC11 is PC7 SYNC 2 SPI/I C configured for master mode (MSTR = 1), the clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see Figure 34. AD5383-to-MC68HC11 Interface the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5383, the MOSI output drives the serial data line (DIN) of the AD5383, and the MISO input is driven from SYNC DOUT. The signal is derived from a port line (PC7). μCONTROLLER/ AD5383 DSP PROCESSOR* D15 REG1 REG0 D11 DATA BUS D0 D0 CS UPPER BITS OF ADDRESS ADDRESS BUS DECODE LDAC A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 R/W WR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 35. AD5383-to-Parallel Interface Rev. B | Page 31 of 40 03734-035 03734-034 AD5383 DV AD5383 to PIC16C6x/7x 8XC51 DD AD5383 SER/PAR The PIC16C6x/7x synchronous serial port (SSP) is configured RESET as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). RxD SDO See the PIC16/17 Microcontroller User Manual. In this example DIN TxD SCLK I/O, Port RA1 is being used to pulse SYNC and enable the serial P1.1 SYNC 2 port of the AD5383. This microcontroller transfers only eight SPI/I C bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed Figure 37. AD5383-to-8051 Interface depending on the mode. Figure 36 shows the connection diagram. AD5383 to ADSP-2101/ADSP-2103 DV Figure 38 shows a serial interface between the AD5383 and the PIC16C6X/7X DD AD5383 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR be set up to operate in SPORT transmit alternate framing mode. RESET SDI/RC4 SDO The ADSP-2101/ADSP-2103 SPORT is programmed through SDO/RC5 DIN the SPORT control register and should be configured as follows: SCK/RC3 SCLK internal clock operation, active low framing, and 16-bit word RA1 SYNC 2 SPI/I C length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Figure 36. AD5383-to-PIC16C6x/7x Interface DV ADSP-2101/ DD AD5383 ADSP-2103 SER/PAR AD5383 to 8051 RESET The AD5383 requires a clock synchronized to the serial data. DR SDO DT DIN Therefore, the 8051 serial interface must be operated in Mode 0. SCK SCLK In this mode, serial data enters and exits through RxD, and a TFS SYNC shift clock is output on TxD. Figure 37 shows how the 8051 is RFS 2 SPI/I C connected to the AD5383. Because the AD5383 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5383 Figure 38. AD5383-to-ADSP-2101/ADSP-2103 Interface requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. Rev. B | Page 32 of 40 03734-036 03734-038 03734-037 AD5383 APPLICATION INFORMATION an ADR421 or ADR431 2.5 V reference. Suitable external POWER SUPPLY DECOUPLING references for the AD5383-3 include the ADR280 1.2 V In any circuit where accuracy is important, careful considera- reference. The reference should be decoupled at the tion of the power supply and ground return layout helps to REFOUT/REFIN pin of the device with a 0.1 μF capacitor. ensure the rated performance. The printed circuit board on AV DV DD DD which the AD5383 is mounted should be designed so that the 0.1μF analog and digital sections are separated and confined to certain areas of the board. If the AD5383 is in a system where 10μF 0.1μF multiple devices require an AGND-to-DGND connection, the ADR431/ ADR421 connection should be made at one point only, a star ground point established as close to the device as possible. AV DV DD DD For supplies with multiple pins (AV , DV ), these pins should REFOUT/REFIN V 0 DD DD OUT be tied together. The AD5383 should have ample supply bypas- 0.1μF AD5383-5 sing of 10 μF in parallel with 0.1 μF on each supply, located as REFGND close to the package as possible and ideally right up against the V 31 OUT DAC SIGNAL device. The 10 μF capacitors are the tantalum bead type. The GND GND AGND DGND 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at Figure 39. Typical Configuration with External Reference high frequencies, to handle transient currents due to internal logic switching. Figure 40 shows a typical configuration when using the internal reference. On power-up, the AD5383 defaults to an external The power supply lines of the AD5383 should use as large a reference; therefore, the internal reference needs to be trace as possible to provide low impedance paths and reduce the configured and turned on via a write to the AD5383 control effects of glitches on the power supply line. Fast switching register. Control Register Bit CR10 allows the user to choose the signals such as clocks should be shielded with digital ground to reference value; Bit CR 8 is used to select the internal reference. avoid radiating noise to other parts of the board, and should It is recommended to use the 2.5 V reference when AVDD = 5 V, never be run near the reference inputs. A ground line routed and the 1.25 V reference when AVDD = 3 V. between the DIN and SCLK lines will help reduce crosstalk between them (this is not required on a multilayer board AV DV DD DD because there will be a separate ground plane, but separating 0.1μF the lines will help). It is essential to minimize noise on the VIN and REFIN lines. 10μF 0.1μF Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each AV DV DD DD other. This reduces the effects of feedthrough through the REFOUT/REFIN V 0 OUT board. A micro-strip technique is by far the best, but is not 0.1μF AD5383 always possible with a double-sided board. In this technique, REFGND the component side of the board is dedicated to the ground V 31 OUT plane while signal traces are placed on the solder side. DAC SIGNAL GND GND AGND DGND TYPICAL CONFIGURATION CIRCUIT Figure 39 shows a typical configuration for the AD5383-5 when Figure 40. Typical Configuration with Internal Reference configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins are Digital connections have been omitted for clarity. The AD5383 tied together to a common AGND. AGND and DGND are contains an internal power-on reset circuit with a 10 ms connected together at the AD5383 device. On power-up, the brownout time. If the power supply ramp rate exceeds 10 ms, AD5383 defaults to external reference operation. All AV lines DD the user should reset the AD5383 as part of the initialization are connected together and driven from the same 5 V source. It process to ensure the calibration data gets loaded correctly into is recommended to decouple close to the device with a 0.1 μF the device. ceramic and a 10 μF tantalum capacitor. In this application, the reference for the AD5383-5 is provided externally from either Rev. B | Page 33 of 40 03734-040 03734-039 AD780/ ADR431 AD5383 CHANNEL MONITOR FUNCTION LDAC The is used to switch between the A and B registers in The AD5383 contains a channel monitor function that consists LDAC determining the analog output. The first configures the of a multiplexer addressed via the interface, allowing any chan- output to reflect data in the A registers. This mode offers signi- nel output to be routed to this pin for monitoring using an ficant advantages if the user wants to generate a square wave at external ADC. The channel monitor function must be enabled the output of all 32 channels, as might be required to drive a in the control register before any channels are routed to liquid crystal-based variable optical attenuator. In this case, the MON_OUT. Table 18 contains the decoding information user writes to the control register and enables the toggle func- needed to route any channel to MON_OUT. To three-state tion by setting CR3 to CR2 = 1, thus enabling the four groups of MON_OUT, select Channel Address 63. Figure 41 shows a eight for toggle mode operation. The user must then load data typical monitoring circuit using a 12-bit SAR ADC in a 6-lead LDAC to all 32 A and B registers. Toggling sets the output SOT-23 package. The controller output port selects the channel values to reflect the data in the A and B registers. The frequency to be monitored, and the input port reads the converted data of the LDAC determines the frequency of the square wave from the ADC. output. TOGGLE MODE FUNCTION Toggle mode is disabled via the control register. The first LDAC The toggle mode function allows an output signal to be generated following the disabling of the toggle mode updates the outputs LDAC using the control signal that switches between two DAC with the data contained in the A registers. data registers. This function is configured using the SFR control THERMAL MONITOR FUNCTION register as follows. A write with REG1 = REG0 = 0 and A4 to A0 = 01100 specifies a control register write. The toggle mode The AD5383 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. The short function is enabled in groups of eight channels using Bit CR3 to circuit current of each output amplifier is typically 40 mA. Bit CR0 in the control register. See the AD5383 Control Operating the AD5383 at 5 V results in power dissipation of Register Write/Read section. Figure 42 shows a block diagram 200 mW per shorted amplifier. With five channels shorted, this of toggle mode implementation. Each of the 32 DAC channels on the AD5383 contain an A and B data register. Note that the amounts to an extra watt of power dissipation. For the 100-lead B registers can only be loaded when toggle mode is enabled. LQFP, the θJA is typically 44°C/W. The sequence of events when configuring the AD5383 for The thermal monitor is enabled by the user via CR6 in the toggle mode is: control register. The output amplifiers on the AD5383 are automatically powered down if the die temperature exceeds 1. Enable toggle mode for the required channels via the approximately 130°C. After a thermal shutdown has occurred, control register. the user can re-enable the part by executing a soft power-up if 2. Load data to A registers. the temperature has dropped below 130°C or by turning off the thermal monitor function via the control register. 3. Load data to B registers. LDAC 4. Apply . AVCC AVCC REFOUT/REFIN DIN SYNC OUTPUT PORT SCLK MON_IN1 AVCC MON_IN2 AD7476 CS MON_OUT V SCLK INPUT PORT IN SDATA V 0 OUT AD5383 GND CONTROLLER V 31 AGND OUT DAC_GND SIGNAL_GND Figure 41. Typical Channel Monitoring Circuit Rev. B | Page 34 of 40 03734-041 AD5383 DATA REGISTER A DAC 12-BIT DAC V OUT REGISTER DATA INPUT INPUT REGISTER DATA REGISTER B LDAC A/B CONTROL INPUT Figure 42. Toggle Mode Function ADD DROP PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM DWDM ATTENUATOR IN OUT FIBRE AWG FIBRE AWG 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) ADG731 N:1 MULTIPLEXER AD5383, (32:1 MUX) 32-CHANNEL, 12-BIT DAC AD7671 CONTROLLER 16-BIT ADC (0-5V, 1MSPS) Figure 43. OADM Using the AD5383 as Part of an Optical Attenuator OPTICAL ATTENUATORS ance amplifier and ADC in a closed-loop control system. The Based on its high channel count, high resolution, monotonic AD5383 controls the optical attenuator for each wavelength, behavior, and high level of integration, the AD5383 is ideally ensuring that the power is equalized in all wavelengths before targeted at optical attenuation applications used in dynamic being multiplexed onto the fiber. This prevents information loss gain equalizers, variable optical attenuators (VOA), and optical and saturation from occurring at amplification stages further add-drop multiplexers (OADM). In these applications, each along the fiber. wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimped- Rev. B | Page 35 of 40 03734-043 03734-042 AD5383 UTILIZING THE FIFO systems, as many as 320 channels need to be updated within The AD5383 FIFO mode optimizes total system update rates in 25 μs to 30 μs. 320 channels require the use of 10 AD5383s. applications where a large number of channels need to be With FIFO mode enabled, the data write cycle time is 40 ns; updated. FIFO mode is only available when parallel interface therefore, each group consisting of 32 channels can be fully mode is selected. The FIFO EN pin is used to enable the FIFO. loaded in 1.28 μs. In FIFO mode, a complete group of 32 The status of FIFO EN is sampled during the initialization channels updates in 11.5 μs. The time taken to update all 320 sequence. Therefore, the FIFO status can only be changed by channels is 11.5 μs + 9 × 1.28 μs = 23 μs. Figure 44 shows the resetting the device. In a telescope that provides for the cancel- FIFO operation scheme. lation of atmospheric distortion, for example, a large number of channels need to be updated in a short period of time. In such GROUP A GROUP B GROUP C GROUP D GROUP E GROUP F GROUP G GROUP H GROUP I GROUP J CHNLS 0-31 CHNLS 32-63 CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS 64-95 96-127 128-159 160-191 192-223 224-255 256-287 288-319 FIFO DATA LOAD GROUP A FIFO DATA LOAD FIFO DATA LOAD 1.28μs 1.28μs 1.28μs GROUP B GROUP J OUTPUT UPDATE OUTPUT UPDATE 11.5μs 11.5μs TIME FOR GROUP A TIME FOR GROUP J OUTPUT UPDATE 11.5μs TIME FOR GROUP B TIME TO UPDATE 320 CHANNELS = 23μs Figure 44. Using FIFO Mode 320 Channels Updated in Under 25 μs Rev. B | Page 36 of 40 03734-044 AD5383 OUTLINE DIMENSIONS 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 76 1 75 0.60 0.45 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 25 51 0.15 0° 26 50 SEATING 0.05 0.08 PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 BSC VIEW A 0.17 LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 45. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1) Dimensions shown in millimeters ORDERING GUIDE Temperature AVDD Output Linearity Package Package 1 Model Resolution Range Range Channels Error Description Option AD5383BSTZ-3 12 Bits –40°C to +85°C 2.7 V to 3.6 V 32 ±1 LSB 100-Lead LQFP ST-100-1 AD5383BSTZ-5 12 Bits –40°C to +85°C 4.5 V to 5.5 V 32 ±1 LSB 100-Lead LQFP ST-100-1 1 Z = RoHS Compliant Part. Rev. B | Page 37 of 40 051706-A AD5383 NOTES Rev. B | Page 38 of 40 AD5383 NOTES Rev. B | Page 39 of 40 AD5383 NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03734–0–4/10(B) Rev. B | Page 40 of 40