ANALOG DEVICES AD5382

32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC AD5382 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±4 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User-programmable offset and gain adjust Power-down mode Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitor User interfaces: Parallel APPLICATIONS Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, Variable optical attenuators (VOAs) featuring data readback) Level setting (ATE) 2 I C-compatible Optical micro-electro-mechanical systems (MEMS) Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3) AVDD (×4) AGND (×4) DAC_GND (×4) REFGND REFOUT/REFIN SIGNAL_GND (×4) PD AD5382 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 14 14 14 14 INPUT DAC SDO DAC 0 REG0 REG0 VOUT0 DB13/(DIN/SDA) 14 m REG0 DB12/(SCLK/SCL) FIFO 14 2 DB11/(SPI/I C) c REG0 R + DB10 R INTERFACE STATE CONTROL MACHINE 14 14 14 14 LOGIC + INPUT DAC DAC 1 DB0 CONTROL REG1 REG1 VOUT1 LOGIC 14 A4 VOUT2 m REG1 A0 14 R c REG1 VOUT3 R REG0 VOUT4 14 14 14 14 INPUT DAC VOUT5 REG1 DAC 6 REG6 REG6 VOUT6 POWER-ON RESET RESET 14 m REG6 BUSY 14 c REG6 R R CLR 14 14 14 14 INPUT DAC VOUT0………VOUT31 DAC 7 REG7 REG7 VOUT7 14 MON_IN1 m REG7 VOUT8 36-TO-1 14 MON_IN2 R c REG7 MUX MON_IN3 R MON_IN4 VOUT31 ×4 MON_OUT LDAC Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113© 2004–2010 Analog Devices, Inc. All rights reserved. 03733-001 AD5382 TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function .................................................. 25 Specif ica t ions ..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5382-5 Specifications ............................................................. 4 FIFO Operation in Parallel Mode ............................................ 25 AD5382-3 Specifications ............................................................. 6 Power-On Reset .......................................................................... 25 AC Characteristics ........................................................................ 7 Power-Down ............................................................................... 25 Timing Characteristics ..................................................................... 8 AD5382 Interfaces .......................................................................... 26 SPI-, QSPI-, MICROWIRE-, or DSP-Compatible Serial DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26 Interface ......................................................................................... 8 2 I C Serial Interface ..................................................................... 28 2 I C Serial Interface ...................................................................... 10 Parallel Interface ......................................................................... 30 Parallel Interface ......................................................................... 11 Microprocessor Interfacing ....................................................... 31 Absolute Maximum Ratings .......................................................... 13 Application Information ................................................................ 33 ESD Caution ................................................................................ 13 Power Supply Decoupling ......................................................... 33 Pin Configuration and Function Descriptions ........................... 14 Typical Configuration Circuit .................................................. 33 Terminology .................................................................................... 17 Monitor Function ....................................................................... 34 Typical Performance Characteristics ........................................... 18 Toggle Mode Function ............................................................... 34 Functional Description .................................................................. 21 Thermal Monitor Function ....................................................... 35 DAC Architecture—General ..................................................... 21 AD5382 in a MEMS-Based Optical Switch ............................ 35 Data Decoding ............................................................................ 21 Optical Attenuators .................................................................... 36 On-Chip Special Function Registers (SFR) ............................ 22 Outline Dimensions ....................................................................... 37 SFR Commands .......................................................................... 22 Ordering Guide .......................................................................... 37 Hardware Functions ....................................................................... 25 Reset Function ............................................................................ 25 REVISION HISTORY 4/10—Rev. A to Rev. B Changes to Table 18 ........................................................................ 24 Changes to Ordering Guide .......................................................... 37 3/05—Rev. 0 to Rev. A Changes to Specifications ................................................................ 4 Changes to Figure 43 ...................................................................... 35 5/04—Revision 0: Initial Version Rev. B | Page 2 of 40 AD5382 GENERAL DESCRIPTION 2 interface speeds in excess of 30 MHz and an I C®-compatible The AD5382 is a complete, single-supply, 32-channel, 14-bit interface that supports a 400 kHz data transfer rate. DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. An input register followed by a DAC register provides double The AD5382 includes an internal software-selectable 1.25 V/ buffering, allowing the DAC outputs to be updated indepen- 2.5 V, 10 ppm/°C reference, an on-chip channel monitor dently or simultaneously using the LDAC input. function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output Each channel has a programmable gain and offset adjust amplifier boost mode that allows optimization of the amplifier register that allows the user to fully calibrate any DAC slew rate. channel. Power consumption is typically 0.25 mA/channel when operating with boost mode disabled. The AD5382 contains a double-buffered parallel interface, which features a 20 ns WR pulse width, an SPI-, QSPI-, MICROWIRE-, DSP-compatible serial interface with Table 1. Other High Channel Count, Low Voltage, Single Supply DACs in Product Portfolio Model Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description Package Option AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64 Table 2. 40-Channel Bipolar Voltage Output DACs Model Resolution Analog Output Channels Linearity Error (LSB) Package Package Option Supplies AD5379ABC 14 Bits ±11.4 V to 40 ±3 108-Lead CSPBGA BC-108 ±16.5 V AD5378ABC 14 Bits ±11.4 V to 32 ±3 108-Lead CSPBGA BC-108 ±16.5 V Rev. B | Page 3 of 40 AD5382 SPECIFICATIONS AD5382-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications T to T , MIN MAX unless otherwise noted. Table 3. 1 Parameter AD5382-5 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy (INL) ±4 LSB max Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 32 in the linear region Offset Error TC ±5 μV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.06 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2xREFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 μA max Typically ±30 nA 1 to Reference Range V min/max AVDD/2 4 Reference Output Enabled via CR10 in the AD5382 control register; CR12 selects the reference voltage Output Voltage 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation 1.22/1.28 V min/max 1.25 V reference selected; CR12 = 0 Reference TC ±10 ppm/°C max Temperature Range: +25°C to +85°C ±15 ppm/°C max Temperature Range: –40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability R = ∞ 200 pF max L R = 5 kΩ 1000 pF max L DC Output Impedance 0.5 Ω max MONITOR PIN Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 5.5 V V , Input High Voltage 2 V min IH VIL, Input Low Voltage 0.8 V max Input Current ±10 μA max Total for all pins, TA = TMIN to TMAX Pin Capacitance 10 pF max Rev. B | Page 4 of 40 AD5382 1 Parameter AD5382-5 Unit Test Conditions/Comments LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V I , Input Leakage Current ±1 μA max IN V , Input Hysteresis 0.05 DVDD V min HYST C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns 3 LOGIC OUTPUTS (BUSY, SDO) VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 μA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 μA VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 μA V , Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 μA OH High Impedance Leakage Current ±1 μA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 μA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AI 0.375 mA/channel max Outputs unloaded, boost off. 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded, boost on. 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 2 μA max Typically 200 nA DI (Power-Down) 20 μA max Typically 3 μA DD Power Dissipation 65 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V 1 AD5382-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications. Rev. B | Page 5 of 40 AD5382 AD5382-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter AD5382-3 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy (INL) ±4 LSB max Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 256 in the linear region Offset Error TC ±5 μV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.1 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 μA max Typically ±30 nA 1 to Reference Range V min/max AVDD/2 Enabled via CR10 in the AD5382 control register, 4 Reference Output CR12 selects the reference voltage Output Voltage 1.245/1.255 V min/max At ambient; CR12 = 0; optimized for 1.25 V operation 2.47/2.53 V min/max 2.5 V reference selected; CR12 = 1 Reference TC ±10 ppm/°C max Temperature Range: +25°C to +85°C ±15 ppm/°C max Temperature Range: –40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max DC Output Impedance 0.5 Ω max MONITOR PIN (MON OUT) Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 3.6 V V , Input High Voltage 2 V min IH V Input Low Voltage 0.8 V max IL, Input Current ±10 μA max Total for all pins, T = T to T A MIN MAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY) V , Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V IH VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 μAmax VHYST, Input Hysteresis 0.05 DVDD V min C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. B | Page 6 of 40 AD5382 1 Parameter AD5382-3 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) VOL, Output Low Voltage 0.4 V max Sinking 200 μA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 μA High Impedance Leakage Current ±1 μA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 μA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AI 0.375 mA/channel max Outputs unloaded; boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded; boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD VIL = DGND AIDD (Power-Down) 2 μA max DIDD (Power-Down) 20 μA max Power Dissipation 39 mW max Outputs unloaded; boost off; AVDD = DVDD = 3 V 1 AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications. 1 AC CHARACTERISTICS AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND= 0 V. Table 5. Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2 Output Voltage Settling Time 1/4 scale to 3/4 scale change settling to ±1 LSB 8 μs typ 10 μs max 2 Slew Rate 2 V/μs typ Boost mode off, CR11 = 0 3 V/μs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 μV p-p typ External reference, midscale loaded to DAC 40 μV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density at 1 kHz 150 nV/√Hz typ at 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5382 control register. Rev. B | Page 7 of 40 AD5382 TIMING CHARACTERISTICS SPI-, QSPI-, MICROWIRE-, OR DSP-COMPATIBLE SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , MIN MAX unless otherwise noted. Table 6. 1, 2, 3 Parameter Limit at T , T Unit Description MIN MAX t1 33 ns min SCLK cycle time t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 13 ns min 24th SCLK falling edge to SYNC falling edge 4 t6 33 ns min Minimum SYNC low time t 10 ns min Minimum SYNC high time 7 t 50 ns min Minimum SYNC high time in readback mode 7A t 5 ns min Data setup time 8 t9 4.5 ns min Data hold time 4 t10 30 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) 4 t 20 ns min 24th SCLK falling edge to LDAC falling edge 12 t 20 ns min LDAC pulse width low 13 t 100 ns max 14 BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t 8 μs typ DAC output settling time 17 t 20 ns min CLR pulse width low 18 t 35 μs max CLR pulse activation time 19 5 t20 20 ns max SCLK rising edge to SDO valid 5 t21 5 ns min SCLK falling edge to SYNC rising edge 5 t22 8 ns min SYNC rising edge to SCLK rising edge t 20 ns min SYNC rising edge to LDAC falling edge 23 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of V ) and are timed from a voltage level of 1.2 V. r f CC 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. 200μA I OL V (MIN) OR OH TO OUTPUT PIN V (MAX) C OL L 50pF 200μA I OH Figure 2. Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain Mode) Rev. B | Page 8 of 40 03733-002 AD5382 t 1 24 24 SCLK t t 3 2 t t 4 5 t 6 SYNC t t t 7 8 9 DB0 DIN DB23 t 10 t 11 BUSY t t 12 13 t 1 17 LDAC t 14 VOUT1 t 15 t 13 2 LDAC t 17 t 16 VOUT2 t 18 CLR t 19 VOUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t 1 SCLK 24 48 t t 3 2 t 21 t 7 t t 22 4 SYNC t t 8 9 DB23 DB0 DB23 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 20 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 13 t 23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. B | Page 9 of 40 03733-003 03733-005 03733-004 AD5382 2 I C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. 1, 2 Parameter Limit at TMIN, TMAX Unit Description FSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT 3 t6 0.9 μs max tHD,DAT, data hold time 0 μs min tHD,DAT, data hold time t 0.6 μs min t , setup time for repeated start 7 SU,STA t 0.6 μs min t , stop condition setup time 8 SU,STO t 1.3 μs min t , bus free time between a stop and a start condition 9 BUF t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min t , fall time of SDA when receiving (CMOS-compatible) F 300 ns max t , fall time of SCL and SDA when receiving F 4 20 + 0.1C ns min t , fall time of SCL and SDA when transmitting b F Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V min of the SCL signal) in order to bridge the undefined region of IH SCL’s falling edge. 4 C is the total capacitance, in pF, of one bus line. t and t are measured between 0.3 DV and 0.7 DV . b R F DD DD SDA t t t t t 9 3 10 11 4 SCL t t t t t 4 6 2 1 8 t t 5 7 START REPEATED STOP CONDITION START CONDITION CONDITION 2 Figure 6. I C-Compatible Serial Interface Timing Diagram Rev. B | Page 10 of 40 03733-006 AD5382 PARALLEL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications Tmin to Tmax, unless otherwise noted. Table 8. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description t0 4.5 ns min REG0, REG1, address to WR rising edge setup time t1 4.5 ns min REG0, REG1, address to WR rising edge hold time t2 20 ns min CS pulse width low t 20 ns min WR pulse width low 3 t 0 ns min CS to WR falling edge setup time 4 t 0 ns min 5 WR to CS rising edge hold time t6 4.5 ns min Data to WR rising edge setup time t7 4.5 ns min Data to WR rising edge hold time t8 20 ns min WR pulse width high 4 t 700 ns min Minimum WR cycle time (single-channel write) 9 4 t 30 ns max WR rising edge to BUSY falling edge 10 4, 5 t11 670 ns max BUSY pulse width low (single-channel update) t12 30 ns min WR rising edge to LDAC falling edge t13 20 ns min LDAC pulse width low t 100 ns max BUSY rising edge to DAC output response time 14 t 20 ns min LDAC rising edge to WR rising edge 15 t 0 ns min rising edge to LDAC falling edge 16 BUSY t17 100 ns min LDAC falling edge to DAC output response time t18 8 μs typ DAC output settling time t19 20 ns min CLR pulse width low t 35 μsmax CLR pulse activation time 20 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.2 V. R R DD 3 See Figure 7. 4 See Figure 29. 5 Measured with the load circuit of Figure 2. Rev. B | Page 11 of 40 AD5382 t t 0 1 REG0, REG1, A4...A0 t t 4 5 t 2 CS t 9 t t 3 8 WR t t t 15 6 7 DB13...DB0 t 10 t 11 BUSY t t 12 13 t 18 1 LDAC t 14 VOUT1 t 16 2 LDAC t 13 t 18 t 17 VOUT2 CLR t 19 t VOUT 20 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev. B | Page 12 of 40 03733-007 AD5382 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 9. rating only; functional operation of the device at these or any Parameter Rating other conditions above those listed in the operational sections AVDD to AGND –0.3 V to +7 V of this specification is not implied. Exposure to absolute DVDD to DGND –0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Inputs to DGND –0.3 V to DVDD + 0.3 V device reliability. SDA/SCL to DGND –0.3 V to + 7 V Digital Outputs to DGND –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND –0.3 V to AVDD + 0.3 V AGND to DGND –0.3 V to +0.3 V VOUTx to AGND –0.3 V to AVDD+ 0.3 V Analog Inputs to AGND –0.3 V to AVDD + 0.3 V MON_IN Inputs to AGND –0.3 V to AVDD + 0.3 V MON_OUT to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (TJ max) 150°C 100-lead LQFP Package θ Thermal Impedance 44°C/W JA Reflow Soldering Peak Temperature 230°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 13 of 40 AD5382 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 FIFO EN 75 RESET PIN 1 CLR 2 74 DB7 IDENTIFIER VOUT24 3 73 DB6 4 VOUT25 72 DB5 5 VOUT26 71 DB4 VOUT27 6 70 DB3 7 SIGNAL_GND4 69 DB2 8 DAC_GND4 68 DB1 9 AGND4 67 DB0 AVDD4 10 66 REG0 VOUT28 11 65 REG1 VOUT29 12 64 VOUT23 AD5382 13 VOUT30 63 VOUT22 TOP VIEW 14 VOUT31 (Not to Scale) 62 VOUT21 REFGND 15 61 VOUT20 16 REFOUT/REFIN 60 AVDD3 17 SIGNAL_GND1 59 AGND3 18 DAC_GND1 58 DAC_GND3 19 AVDD1 57 SIGNAL_GND3 VOUT0 20 56 VOUT19 VOUT1 21 55 VOUT18 22 VOUT2 54 VOUT17 VOUT3 23 53 VOUT16 VOUT4 24 52 AVDD2 25 AGND1 51 AGND2 Figure 8. 100-Lead LQFP Pin Configuration Table 10. Pin Function Descriptions Mnemonic Function VOUTx Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND(1–4) Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5382. DAC_GND(1–4) Ground Reference point for the Internal 14-Bit DAC. Each group of eight channels contains a DAC_GND pin. These pins shound be connected to the AGND plane. AGND(1–4) Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD(1–4) Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are internally shorted and should be decoupled with a 0.1 μF ceramic capacitor and a 10 μF tantalum capacitor. Operating range for the AD5382-5 is 4.5 V to 5.5 V; operating range for the AD5382-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with 0.1 μF ceramic and 10 μF tantalum capacitors to DGND. REFGND Ground Reference Point for the Internal Reference. REFOUT/REFIN Reference Output when the Internal Reference is Selected. The AD5382 contains a common REFOUT/REFIN pin. If the application requires an external reference, it can be applied to this pin, and the internal reference can be disabled via the control register. The default for this pin is a reference input. Rev. B | Page 14 of 40 NC 26 100 CS/(SYNC/AD0) 27 99 NC DB13/(DIN/SDA) NC 28 98 DB12/(SCLK/SCL) 2 NC 29 97 DB11/(SPI/I C) VOUT5 30 96 DB10 VOUT6 31 95 DB9 32 94 VOUT7 DB8 NC 33 93 SDO(A/B) NC 34 92 DVDD 35 MON_IN1 91 DGND 36 90 MON_IN2 DGND MON_IN3 37 89 NC MON_IN4 38 88 A4 NC 39 87 A3 MON_OUT 40 86 A2 VOUT8 41 85 A1 VOUT9 42 84 A0 VOUT10 43 83 DVDD 82 VOUT11 44 DVDD VOUT12 45 81 DGND DAC_GND2 46 80 SER/PAR SIGNAL_GND2 47 79 PD VOUT13 48 78 WR (DCEN/AD1) 49 77 VOUT14 LDAC VOUT15 50 76 BUSY 03733-008 AD5382 Mnemonic Function MON_OUT Monitor Output. When the monitor function is enabled, this pin acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31 or any of the monitor input pins (MON_IN1 to MON_IN4) to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. MON_INx Monitor Input Pins. The AD5382 contains four monitor input pins that allow the user to connect input signals, within the maximum ratings of the device, to these pins for monitoring purposes. Any of the signals applied to the MON_IN pins, along with the 32 output channels, can be switched to the MON_OUT pin via software. For example, an external ADC can be used to monitor these signals. SER/PAR Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied 2 2 high, the serial interface mode is selected and Pin 97 (SPI/I C) is used to determine if the interface mode is SPI or I C. Parallel interface mode is selected when SER/PAR is low. CS/(SYNC/AD0) In parallel interface mode, this pin acts as the chip select input (level sensitive, active low). When low, the AD5382 is selected. In serial interface mode, this is the frame synchronization input signal for the serial clocks before the addressed register is updated. 2 In I C mode, this pin acts as a hardware address pin used in conjunction with AD1 to determine the software address 2 for the device on the I C bus. WR/(DCEN/AD1) Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a 2 daisy-chain enable in SPI mode and as a hardware address pin in I C mode. Parallel Interface Write Input (Edge Sensitive). The rising edge of WR is used in conjunction with CS low, and the address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction with SER/PAR high to enable the SPI serial interface daisy-chain mode. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address 2 for this device on the I C bus. DB13–DB0 Parallel Data Bus. DB13 is the MSB and DB0 is the LSB of the input data-word on the AD5382. A4–A0 Parallel Address Inputs. A4 to A0 are decoded to address one of the AD5382’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. REG1, REG0 In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. SDO/(A/B) Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. In parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5382’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels contain two data registers. In normal mode, Data Register A is the default for data transfers. BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the RESET pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated CLR with the data in the CLR code register. BUSY is low for 35 μs while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 270 μs. The falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation, and the status of the RESET pin is ignored until the next falling edge is detected. Rev. B | Page 15 of 40 AD5382 Mnemonic Function PD Power Down (Level Sensitive, Active High). PD is used to place the device in to low power mode where the device consumes 2 μA AIDD and 20 μA DIDD. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. FIFO EN FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is available only in parallel interface mode. The status of the FIFO EN pin is 2 sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I C interface modes, the FIFO EN pin should be tied low. 2 DB11/(SPI/I C) Multifunction Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. In serial interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB13 is the serial data (DIN) input. 2 When serial interface mode is selected (SER/PAR = 1) and this input is high, I C mode is selected. In this mode, DB12 is the serial clock (SCL) input and DB13 is the serial data (SDA) input. DB12/(SCLK/SCL) Multifunction Input Pin. In parallel interface mode, this pin acts as DB12 of the parallel input data-word. In serial interface mode, this pin acts as a serial clock input. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 50 MHz. 2 2 2 I C Mode. In I C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I C mode is compatible with both 100 kHz and 400 kHz operating modes. DB13/(DIN/SDA) Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB13 of the parallel input data-word. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. 2 2 I C Mode. In I C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. NC No Connect. The user is advised not to connect any signals to these pins. Rev. B | Page 16 of 40 AD5382 TERMINOLOGY DC Output Impedance Relative Accuracy Relative accuracy or endpoint linearity is a measure of the This is the effective output source resistance. It is dominated by maximum deviation from a straight line passing through the package lead resistance. endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is Output Voltage Settling Time expressed in LSB. This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change, Differential Nonlinearity and is measured from the rising edge. BUSY Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Digital-to-Analog Glitch Energy codes. A specified differential nonlinearity of 1 LSB maximum This is the amount of energy injected into the analog output at ensures monotonicity. the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data Zero-Scale Error between 0x1FFF and 0x2000. Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to DAC-to-DAC Crosstalk n – 1 the DAC and m = all 1s, c = 2 DAC-to-DAC crosstalk is the glitch impulse that appears at the = 0 V output of one DAC due to both the digital change and to the VOUT(Zero-Scale) subsequent analog output change at another DAC. The victim Zero-scale error is a measurement of the difference between channel is loaded with midscale. DAC-to-DAC crosstalk is VOUT (actual) and VOUT (ideal), expressed in mV. It is mainly specified in nV-s. due to offsets in the output amplifier. Digital Crosstalk Offset Error The glitch impulse transferred to the output of one converter Offset error is a measurement of the difference between VOUT due to a change in the DAC register code of another converter is (actual) and VOUT (ideal) in the linear region of the transfer defined as the digital crosstalk and is specified in nV-s. function, expressed in mV. Offset error is measured on the AD5382-5 with Code 32 loaded into the DAC register, and on Digital Feedthrough the AD5382-3 with Code 64. When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both Gain Error across and through the device to show up as noise on the Gain error is specified in the linear region of the output range VOUT pins. It can also be coupled along the supply and ground between VOUT= 10 mV and VOUT = AVDD – 50 mV. It is the lines. This noise is digital feedthrough. deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded. Output Noise Spectral Density This is a measurement of internally generated random noise. DC Crosstalk Random noise is characterized as a spectral density (voltage per This is the dc change in the output level of one DAC at midscale √Hz). It is measured by loading all DACs to midscale and in response to a full-scale code (all 0s to all 1s, and vice versa) measuring noise at the output. It is measured in nV/√Hz in a and output change of all other DACs. It is expressed in LSB. 1 Hz bandwidth at 10 kHz. Rev. B | Page 17 of 40 AD5382 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 AVDD = DVDD = 5.5V AVDD = DVDD = 3V V = 2.5V V = 1.25V REF REF 1.5 1.5 T = 25°C T = 25°C A A 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 INPUT CODE INPUT CODE Figure 9. Typical AD5382-5 INL Plot Figure 12. Typical AD5382-3 INL Plot 2.539 1.254 AVDD = DVDD = 5V AVDD = DVDD = 3V 2.538 V = 2.5V REF V = 1.25V REF 1.253 2.537 T = 25°C A T = 25°C A 14ns/SAMPLE NUMBER 2.536 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE 1.252 2.535 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 10nV-s GLITCH IMPULSE = 5nV-s 2.534 1.251 2.533 2.532 1.250 2.531 2.530 1.249 2.529 1.248 2.528 2.527 1.247 2.526 2.525 1.246 2.524 2.523 1.245 0 50 100 150 200 250 300 350 400 450 500 550 0 50 100 150 200 250 300 350 400 450 500 550 SAMPLE NUMBER SAMPLE NUMBER Figure 10. AD5382-5 Glitch Impulse Figure 13. AD5382-3 Glitch Impulse AVDD = DVDD = 5V V = 2.5V REF T = 25°C A AVDD = DVDD = 5V V = 2.5V REF T = 25°C VOUT A VOUT Figure 11. Slew Rate with Boost Off Figure 14. Slew Rate with Boost On Rev. B | Page 18 of 40 AMPLITUDE (V) INL ERROR (LSB) 03733-011 03733-010 03733-009 AMPLITUDE (V) INL ERROR (LSB) 03733-014 03733-013 03733-012 AD5382 14 AVDD = 5.5V V = 2.5V REF AVDD = DVDD = 5V T = 25°C A V = 2.5V REF 12 T = 25°C A POWER SUPPLY RAMP RATE = 10ms 10 8 6 4 2 89 10 11 AI (mA) DD Figure 18. Power-Up Transient Figure 15. AIDD Histogram 14 DVDD = 5.5V AVDD = 5.5V V = DVDD REFIN = 2.5V IH 10 V = DGND T =25°C IL 12 A T = 25°C A 10 8 8 6 6 4 4 2 2 0 0 0.4 0.5 0.6 0.7 0.8 0.9 –2 –1 0 1 2 DI (mA) DD INL ERROR DISTRIBUTION (LSB) Figure 16. DIDD Histogram Figure 19. INL Error Distribution PD WR BUSY AVDD = DVDD = 5V V = 2.5V REF T = 25°C A EXITS SOFT PD VOUT TO MIDSCALE AVDD = DVDD = 5V V = 2.5V REF VOUT T = 25°C A EXITS HARDWARE PD TO MIDSCALE Figure 17. Exiting Soft Power-Down Figure 20. Exiting Hardware Power-Down Rev. B | Page 19 of 40 NUMBER OF UNITS PERCENTAGE OF UNITS (%) 03733-017 03733-016 03733-015 NUMBER OF UNITS 03733-020 03733-018 03733-019 AD5382 6 6 AVDD = DVDD = 3V FULL SCALE V = 1.25V REF T = 25°C A 5 5 AVDD = DVDD = 5V V = 2.5V 3/4 SCALE REF T = 25°C 4 4 A 3/4 SCALE FULL SCALE 3 MIDSCALE 3 MIDSCALE 2 2 1/4 SCALE 1 1 ZERO SCALE 0 0 ZERO SCALE 1/4 SCALE –1 –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 –40 –20 –10 –5 –2 0 2 5 10 20 –40 CURRENT (mA) CURRENT (mA) Figure 21. AD5382-5 Output Amplifier Source and Sink Capability Figure 24. AD5382-3 Output Amplifier Source and Sink Capability 0.20 2.456 AVDD = 5V AVDD = DVDD = 5V V = 2.5V REF V = 2.5V REF 0.15 T = 25°C A T = 25°C 2.455 A 14ns/SAMPLE NUMBER 0.10 2.454 ERROR AT ZERO SINKING CURRENT 0.05 2.453 0 2.452 –0.05 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT 2.451 –0.10 2.450 –0.15 –0.20 2.449 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 50 100 150 200 250 300 350 400 450 500 550 SAMPLE NUMBER I /I (mA) SOURCE SINK Figure 22. Headroom at Rails vs. Source/Sink Current Figure 25. Adjacent Channel DAC-to-DAC Crosstalk 600 AVDD = 5V T = 25°C A REFOUT DECOUPLED 500 AVDD = DVDD = 5V WITH 100nF CAPACITOR T = 25°C A DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE 400 Y AXIS = 5μV/DIV X AXIS = 100ms/DIV 300 REFOUT = 2.5V 200 REFOUT = 1.25V AV = DV = 5V DD DD 100 V = 2.5V REF T = 25°C A EXITS SOFT PD 0 TO MIDSCALE 100 1k 10k 100k FREQUENCY (Hz) Figure 23 REFOUT Noise Spectral Density Figure 26. 0.1 Hz to 10 Hz Noise Plot Rev. B | Page 20 of 40 OUTPUT NOISE (nV/ Hz) ERROR VOLTAGE (V) VOUT (V) 03733-023 03733-022 03733-021 AMPLITUDE (V) VOUT (V) 03733-026 03733-025 03733-024 AD5382 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The complete transfer function for these devices can be represented as The AD5382 is a complete, single-supply, 32-channel voltage output DAC that offers 14-bit resolution. The part is available n VOUT = 2 × VREF × x2/2 in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software- where: selectable, 1.25 V/2.5 V, 10 ppm/°C reference, which can be x2 is the data-word loaded to the resistor string DAC, and used to drive the buffered reference inputs; alternatively, an V is the internal reference voltage, or the reference voltage REF external reference can be used to drive these inputs. Internal/ externally applied to the DAC REFOUT/REFIN pin. For speci- external reference selection is via the CR10 bit in the control fied performance, an external reference voltage of 2.5 V is register; CR12 selects the reference magnitude if the internal recommended for the AD5380-5, and 1.25 V for the AD5380-3. reference is selected. All channels have an on-chip output DATA DECODING amplifier with rail-to-rail output capable of driving 5 kΩ in The AD5382 contains a 14-bit data bus, DB13–DB0. Depend- parallel with a 200 pF load. ing on the value of REG1 and REG0 (see Table 11), this data is VREF AVDD loaded into the addressed DAC input registers (x1), offset (c) registers, or gain (m) registers. The format data, offset (c), and ×1 INPUT REG gain (m) register contents are shown in Table 12 to Table 14. DAC 14-BIT INPUT DATA m REG ×2 REG DAC VOUT Table 11. Register Selection c REG R REG1 REG0 Register Selected R 1 1 Input Data Register (x1) 1 0 Offset Register (c) 0 1 Gain Register (m) Figure 27. Single-Channel Architecture 0 0 Special Function Registers (SFRs) The architecture of a single DAC channel consists of a 14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guar- Table 12. DAC Data Format (REG1 = 1, REG0 = 1) antees DAC monotonicity. The 14-bit binary digital code loaded DB13 to DB0 DAC Output (V) to the DAC register determines at what node on the string the 11 1111 1111 1111 2 V × (16383/16384) REF voltage is tapped off before being fed to the output amplifier. 11 1111 1111 1110 2 V × (16382/16384) REF Each channel on these devices contains independent offset and 10 0000 0000 0001 2 VREF × (8193/16384) gain control registers that allow the user to digitally trim offset 10 0000 0000 0000 2 VREF × (8192/16384) and gain. These registers give the user the ability to calibrate out 01 1111 1111 1111 2 VREF × (8191/16384) errors in the complete signal chain, including the DAC, using 00 0000 0000 0001 2 V × (1/16384) REF the internal m and c registers, which hold the correction factors. 00 0000 0000 0000 0 All channels are double buffered, allowing synchronous updating of all channels using the pin. Figure 27 shows a LDAC Table 13. Offset Data Format (REG1 = 1, REG0 = 0) block diagram of a single channel on the AD5382. The digital DB13 to DB0 Offset (LSB) input transfer function for each DAC can be represented as 11 1111 1111 1111 +8191 n n – 1 x2 = [(m + 2)/2 × x1] + (c – 2 ) 11 1111 1111 1110 +8190 10 0000 0000 0001 +1 where: 10 0000 0000 0000 0 x2 is the data-word loaded to the resistor string DAC. 01 1111 1111 1111 –1 x1 is the 14-bit data-word written to the DAC input register. 00 0000 0000 0001 –8191 m is the gain coefficient (default is 0x3FFE on the AD5382). 00 0000 0000 0000 –8192 The gain coefficient is written to the 13 most significant bits (DB13 to DB1) and LSB (DB0) is a zero. n = DAC resolution (n = 14 for AD5382). c is the14-bit offset coefficient (default is 0x2000). Rev. B | Page 21 of 40 03733-027 AD5382 Soft Clear Table 14. Gain Data Format (REG1 = 0, REG0 = 1) DB13 to DB0 Gain Factor REG1 = REG0 = 0, A4–A0 = 00010 11 1111 1111 1110 1 DB13–DB0 = Don’t Care 10 1111 1111 1110 0.75 Executing this instruction performs a software clear, which is 01 1111 1111 1110 0.5 functionally the same as that provided by the external pin. 00 0111 1111 1110 0.25 CLR 00 0000 0000 0000 0 The DAC outputs are loaded with the data in the Clear Code. register (Table 15). It takes 35 μs to fully execute the Soft Clear and is indicated by the BUSY low time. ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5382 contains a number of special function registers Soft Power-Down (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0, A4–A0 = 01000 REG1 = REG0 = 0 and are decoded using Address Bits A4 to A0. DB13–DB0 = Don’t Care Executing this instruction performs a global power-down Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) feature that puts all channels into a low power mode that R/W A4 A3 A2 A1 A0 Function reduces the analog supply current to 2 μA max and the digi- X 0 0 0 0 0 NOP (No Operation) tal current to 20 μA max. In power-down mode, the output 0 0 0 0 0 1 Write Clear Code amplifier can be configured as a high impedance output or 0 0 0 0 1 0 Soft Clear provide a 100 kΩ load to ground. The contents of all internal 0 0 1 0 0 0 Soft Power-Down registers are retained in power-down mode. No register can 0 0 1 0 0 1 Soft Power-Up be written to while in power-down. 0 0 1 1 0 0 Control Register Write 1 0 1 1 0 0 Control Register Read Soft Power-Up 0 0 1 0 1 0 Monitor Channel REG1 = REG0 = 0, A4–A0 = 01001 0 0 1 1 1 1 Soft Reset DB13–DB0 = Don’t Care This instruction is used to power up the output amplifiers and SFR COMMANDS the internal reference. The time to exit power-down is 8 μs. NOP (No Operation) The hardware power-down and software functions are internally combined in a digital OR function. REG1 = REG0 = 0, A4–A0 = 00000 Soft RESET Performs no operation but is useful in serial readback mode to REG1 = REG0 = 0, A4–A0 = 01111 clock out data on DOUT for diagnostic purposes. BUSY pulses DB13–DB0 = Don’t Care low during a NOP operation. This instruction is used to implement a software reset. Write Clear Code All internal registers are reset to their default values, which correspond to m at full scale and c at zero. The contents of REG1 = REG0 = 0, A4–A0 = 00001 the DAC registers are cleared, setting all analog outputs to 0 V. DB13–DB0 = Contain the clear code data The soft reset activation time is 135 μs max. Bringing the line low or exercising the soft clear function CLR loads the contents of the DAC registers with the data contained in the user-configurable Clear register, and sets VOUT0 to VOUT31 accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hard-ware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default on power-up is all zeros. Rev. B | Page 22 of 40 AD5382 Table 16. Control Register Contents MSB LSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Control Register Write/Read REG1 = REG0 = 0, A4–A0 = 01100, R/W status determines CR8: Thermal Monitor Function. This function is used to monitor the AD5382’s internal die temperature when enabled. if the operation is a write (R/ = 0) or a read (R/ = 1). W W The thermal monitor powers down the output amplifiers when DB13 to DB0 contain the control register data. the temperature exceeds 130°C. This function can be used to Control Register Contents protect the device when power dissipation may be exceeded if a CR13: Power-Down Status. This bit is used to configure the number of output channels are simultaneously short-circuited. output amplifier state in power-down. A soft power-up re-enables the output amplifiers if the die temperature drops below 130°C. CR13 = 1. Amplifier output is high impedance (default on power-up). CR8 = 1: Thermal Monitor Enabled. CR13 = 0. Amplifier output is 100 kΩ to ground. CR8 = 0: Thermal Monitor Disabled (default on power-up). CR12: REF Select. This bit selects the operating internal CR7 and CR6: Don’t Care. reference for the AD5382. CR5 to CR2: Toggle Function Enable. This function allows the CR12 = 1: Internal reference is 2.5 V (AD5382-5 default), the user to toggle the output between two codes loaded to the A recommended operating reference for AD5382-5. and B register for each DAC. Control Register Bits CR5 to CR2 are used to enable individual groups of eight channels for CR12 = 0: Internal reference is 1.25 V (AD5382-3 default), operation in toggle mode. A Logic 1 written to any bit enables a the recommended operating reference for AD5382-3. group of channels; a Logic 0 disables a group. LDAC is used to toggle between the two registers. Table 17 shows the decoding CR11: Current Boost Control. This bit is used to boost the for toggle contains Channels 24 to 31, CR5 = 1 enables these current in the output amplifier, thereby altering its slew rate. channels. CR11 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing Table 17. the power dissipation. CR Bit Group Channels CR5 3 24–31 CR11 = 0: Boost Mode Off (default on power-up). This CR4 2 16–23 reduces the bias current in the output amplifier and reduces CR3 1 8–15 the overall power consumption. CR2 0 0–7 CR10: Internal/External Reference. This bit determines if the DAC uses its internal reference or an externally CR1 and CR0: Don’t Care. applied reference. Channel Monitor Function REG1 = REG0 = 0, A4–A0 = 01010 CR10 = 1: Internal Reference Enabled. The reference output depends on data loaded to CR12. DB13–DB8 = Contain data to address the monitored channel CR10 = 0: External Reference Selected (default on power-up). A channel monitor function is provided on the AD5382. CR9: Channel Monitor Enable (see Channel Monitor Function) This feature, which consists of a multiplexer addressed via the interface, allows any channel output or the signals connected CR9 = 1: Monitor Enabled. This enables the channel monitor to the MON_IN inputs to be routed to the MON_OUT pin for function. After a write to the monitor channel in the SFR monitoring using an external ADC. The channel monitor func- register, the selected channel output is routed to the tion must be enabled in the control register before any channels MON_OUT pin. are routed to MON_OUT. On the AD5382, DB13 to DB8 contain the channel address for the monitored channel. CR9 = 0: Monitor Disabled (default on power-up). When the Selecting channel address 63 three-states MON_OUT. monitor is disabled, MON_OUT is three-stated. Rev. B | Page 23 of 40 AD5382 Table 18. AD5382 Channel Monitor Decoding REG1 REG0 A4 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7–DB0 MON_OUT 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4 0 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT5 0 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT6 0 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT7 0 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT8 0 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT9 0 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT10 0 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT11 0 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT12 0 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT13 0 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT14 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26 0 0 0 1 0 1 0 0 1 1 0 1 1 X VOUT27 0 0 0 1 0 1 0 0 1 1 1 0 0 X VOUT28 0 0 0 1 0 1 0 0 1 1 1 0 1 X VOUT29 0 0 0 1 0 1 0 0 1 1 1 1 0 X VOUT30 0 0 0 1 0 1 0 0 1 1 1 1 1 X VOUT31 0 0 0 1 0 1 0 1 0 0 0 0 0 X Undefined 0 0 0 1 0 1 0 1 0 0 0 0 1 X Undefined 0 0 0 1 0 1 0 1 0 0 0 1 0 X MON_IN1 0 0 0 1 0 0 1 0 0 0 1 1 X MON_IN2 0 0 0 1 0 1 0 1 0 0 1 0 0 X MON_IN3 0 0 0 1 0 1 0 1 0 0 1 0 1 X MON_IN4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State REG1 REG0 A4 A3 A2 A1 A0 000 101 0 VOUT0 VOUT1 AD5382 VOUT30 CHANNEL VOUT31 MONITOR MON_IN1 DECODING MON_OUT MON_IN2 MON_IN3 MON_IN4 CHANNEL ADDRESS DB13–DB8 Figure 28. Channel Monitor Decoding Rev. B | Page 24 of 40 03733-028 AD5382 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the line low resets the contents of all internal The AD5382 contains a FIFO to optimize operation when RESET operating in parallel interface mode. The FIFO EN pin (level registers to their power-on reset state. Reset is a negative edge- sensitive, active high) is used to enable the internal FIFO. When sensitive input. The default corresponds to m at full scale and connected to DVDD, the internal FIFO is enabled, allowing the to c at zero scale. The contents of the DAC registers are cleared, user to write to the device at full speed. FIFO is only available in setting VOUT0 to VOUT31 to 0 V. This sequence takes 270 μs parallel interface mode. The status of the FIFO EN pin is sam- max. The falling edge of RESET initiates the reset process; pled on power-up, and after a CLEAR or RESET, to determine if BUSY goes low for the duration, returning high when RESET is 2 the FIFO is enabled. In either serial or I C interface mode, FIFO complete. While is low, all interfaces are disabled and all BUSY EN should be tied low. Up to 128 successive instructions can be LDAC pulses are ignored. When BUSY returns high, the part written to the FIFO at maximum speed in parallel mode. When resumes normal operation and the status of the RESET pin is the FIFO is full, further writes to the device are ignored. Figure ignored until the next falling edge is detected. 29 shows a comparison between FIFO mode and non-FIFO mode in terms of channel update time. Figure 29 also shows ASYNCHRONOUS CLEAR FUNCTION digital loading time. Bringing the line low clears the contents of the DAC CLR registers to the data contained in the user-configurable CLR 25 register and sets VOUT0 to VOUT31 accordingly. This func- tion can be used in system calibration to load zero scale and WITHOUT FIFO 20 full scale to all channels. The execution time for a CLR is 35 μs. (CHANNEL UPDATE TIME) AND FUNCTIONS BUSY LDAC 15 BUSY is a digital CMOS output that indicates the status of the AD5382. The value of x2, the internal data loaded to the DAC 10 WITH FIFO data register, is calculated each time the user writes new data to (CHANNEL UPDATE TIME) the corresponding x1, c, or m register. During the calculation of 5 x2, the BUSY output goes low. While BUSY is low, the user can WITH FIFO (DIGITAL LOADING TIME) continue writing new data to the x1, m, or c register, but no 0 DAC output updates can take place. The DAC outputs are 1 4 7 10 13 16 19 22 25 28 31 34 37 40 updated by taking the input low. If goes low while LDAC LDAC NUMBER OF WRITES BUSY is active, the LDAC event is stored and the DAC outputs Figure 29. Channel Update Rate (FIFO vs. Non-FIFO) update immediately after goes high. The user may hold BUSY POWER-ON RESET the LDAC input permanently low, in which case the DAC The AD5382 contains a power-on reset generator and a state outputs update immediately after goes high. also BUSY BUSY machine. The power-on reset resets all registers to a predefined goes low during power-on reset and when a falling edge is state and configures the analog outputs as high impedance. detected on the RESET pin. During this time, all interfaces are The BUSY pin goes low during the power-on reset sequencing, disabled and any events on LDAC are ignored. preventing data writes to the device. The AD5382 contains an extra feature whereby a DAC register POWER-DOWN is not updated unless its x2 register has been written to since the last time was brought low. Normally, when is The AD5382 contains a global power-down feature, which puts LDAC LDAC all channels into a low power mode and reduces the analog brought low, the DAC registers are filled with the contents of power consumption to 2 μA max and digital power consump- the x2 registers. However, the AD5382 updates the DAC register tion to 20 μA max. In power-down mode, the output amplifier only if the x2 data changes, thereby removing unnecessary can be configured as a high impedance output or provide a 100 digital crosstalk. kΩ load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier elapses before the outputs settle to their correct values. Rev. B | Page 25 of 40 TIME (μs) 03733-029 AD5382 AD5382 INTERFACES The AD5382 contains both parallel and serial interfaces. Figure 3 and Figure 5 show timing diagrams for a serial write to Furthermore, the serial interface can be programmed to the AD5382 in standalone and daisy-chain modes. The 24-bit 2 be either SPI-, DSP-, MICROWIRE-, or I C-compatible. The data-word format for the serial interface is shown in Table 19. SER/PAR pin selects parallel and serial interface modes. A/B. When toggle mode is enabled, this pin selects whether the 2 In serial mode, the /I C pin is used to select DSP, SPI, SPI data write is to the A or B register. With toggle disabled, this bit 2 MICROWIRE, or I C interface mode. should be set to 0 to select the A data register. The device uses an internal FIFO memory to allow high speed R/W is the read or write control bit. successive writes in parallel interface mode. The user can con- tinue writing new data to the device while write instructions are A4–A0 are used to address the input channels. being executed. The signal indicates the current status of BUSY REG1 and REG0 select the register to which data is written, as the device, going low while instructions in the FIFO are being shown in Table 11. executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO DB13–DB0 contain the input data-word. is full, further writes to the device are ignored. X is a don’t care condition. To minimize both the power consumption of the device and Standalone Mode the on-chip digital noise, the active interface powers up fully when only the device is being written to, that is, on the falling By connecting the DCEN (daisy-chain enable) pin low, stand- edge of WR or the falling edge of SYNC. alone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL edge of SYNC starts the write cycle and resets a counter that INTERFACES counts the number of serial clocks to ensure that the correct The serial interface can be operated with a minimum of three number of bits are shifted into the serial shift register. Any wires in standalone mode or four wires in daisy-chain mode. further edges on except for a falling edge are ignored SYNC Daisy chaining allows many devices to be cascaded together to until 24 bits are clocked in. Once 24 bits are shifted in, the increase system channel count. The SER/PAR pin must be tied SCLK is ignored. For another serial transfer to take place, the 2 high and the /I C pin (Pin 97) should be tied low to enable SPI counter must be reset by the falling edge of SYNC. the DSP-, SPI-, MICROWIRE-compatible serial interface. In serial interface mode, the user does not need to drive the parallel input data pins. The serial interface’s control pins are as follows: , DIN, SCLK—Standard 3-wire interface pins. SYNC DCEN—Selects standalone mode or daisy-chain mode. SDO—Data out pin for daisy-chain mode. Table 19. 32-Channel, 14-Bit DAC Serial Input Register Configuration MSB LSB A/B R/W 0 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Rev. B | Page 26 of 40 AD5382 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin can be Readback mode is invoked by setting the R/W bit = 1 in the used to daisy-chain several devices together. This daisy-chain serial input register write. With R/W = 1, Bits A4 to A0, in mode can be useful in system diagnostics and in reducing the association with Bits REG1 and REG0, select the register to be number of serial interface lines. read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO By connecting the DCEN (daisy-chain enable) pin high, daisy- output contains the data from the previously addressed register. chain mode is enabled. The first falling edge of starts the SYNC For a read of a single register, the NOP command can be used write cycle. The SCLK is continuously applied to the input shift in clocking out the data from the selected register on SDO. register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears Figure 30 shows the readback sequence. For example, to read on the SDO line. This data is clocked out on the rising edge of back the m register of Channel 0 on the AD5382, the following SCLK and is valid on the falling edge. By connecting the SDO sequence should be implemented. First, write 0x404XXX to the of the first device to the DIN input on the next device in the AD5382 input register. This configures the AD5382 for read chain, a multidevice interface is constructed. Twenty-four clock mode with the m register of Channel 0 selected. Data Bits DB13 pulses are required for each device in the system. Therefore, the to DB0 are don’t cares. Follow this with a second write, a NOP total number of clock cycles must equal 24N, where N is the condition, 0x000000. During this write, the data from the m total number of AD538x devices in the chain. register is clocked out on the DOUT line, that is, data clocked out contains the data from the m register in Bits DB13 to DB0, When the serial transfer to all devices is complete, is SYNC and the top 10 bits contain the address information as taken high. This latches the input data in each device in the previously written. In readback mode, the SYNC signal must daisy-chain and prevents further data from being clocked into frame the data. Data is clocked out on the rising edge of SCLK the input shift register. and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback If the SYNC is taken high before 24 clocks are clocked into the operation, the first bit of data is clocked out on the falling edge part, this is considered a bad frame and the data is discarded. of . SYNC The serial clock can be either a continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and must be taken high after the final clock to SYNC latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23 DB0 DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 30. Serial Readback Operation Rev. B | Page 27 of 40 03733-030 AD5382 2 I C SERIAL INTERFACE 2 AD5382 Slave Addresses The AD5382 features an I C-compatible 2-wire interface A bus master initiates communication with a slave device by consisting of a serial data line (SDA) and a serial clock line issuing a start condition followed by the 7-bit slave address. (SCL). SDA and SCL facilitate communication between the When idle, the AD5382 waits for a start condition followed by AD5382 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three its slave address. The LSB of the address word is the Read/ Write 2 different modes of operation. In selecting the I C operating (R/W) bit. The AD5382 is a receive-only device; when mode, first configure serial operating mode (SER/ = 1) PAR communicating with the AD5382, R/ = 0. After receiving the W 2 2 and then select I C mode by configuring the SPI/I C pin to a proper address 1010 1AD1AD0, the AD5382 issues an ACK by 2 Logic 1. The device is connected to the I C bus as a slave device pulling SDA low for one clock cycle. (no clock is generated by the AD5382). The AD5382 has a 7-bit The AD5382 has four different user-programmable addresses slave address, 1010 1AD1AD0. The 5 MSB are hard-coded and determined by the AD1 and AD0 bits. the 2 LSB are determined by the state of the AD1 and AD0 pins. Write Operation The facility to hardware configure AD1 and AD0 allows four of these devices to be configured on the bus. Data can be written to the AD5382 DAC in three specific 2 modes. I C Data Transfer One data bit is transferred during each SCL clock cycle. The 4-Byte Mode data on SDA must remain stable during the high period of the When writing to the AD5382 DACs, the user must begin with SCL clock pulse. Changes in SDA while SCL is high are control an address byte (R/W = 0) after which the DAC acknowledges signals that configure start and stop conditions. Both SDA and that it is prepared to receive data by pulling SDA low. The SCL are pulled high by the external pull-up resistors when the 2 address byte is followed by the pointer byte; this addresses the I C bus is not busy. specific channel in the DAC to be addressed and is also Start and Stop Conditions acknowledged by the DAC. Two bytes of data are then written A master device initiates communication by issuing a start to the DAC, as shown in Figure 31. A stop condition follows. condition. A start condition is a high-to-low transition on SDA This allows the user to update a single channel within the with SCL high. A stop condition is a low-to-high transition on AD5382 at anytime and requires four bytes of data to be SDA while SCL is high. A start condition from the master transferred from the master. signals the beginning of a transmission to the AD5382. The stop condition frees the bus. If a repeated start condition (Sr) is 3-Byte Mode generated instead of a stop condition, the bus remains active. In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address Repeated Start Conditions byte each time. The device address byte is required only once; A repeated start (Sr) condition can indicate a change of data subsequent channel updates require the pointer byte and the direction on the bus. Sr may be used when the bus master is data bytes. In 3-byte mode, the user begins with an address byte 2 writing to several I C devices and wants to maintain control of (R/ = 0), after which the DAC acknowledges that it is W the bus. prepared to receive data by pulling SDA low. The address byte Acknowledge Bit (ACK) is followed by the pointer byte. This addresses the specific The acknowledge bit (ACK) is the ninth bit attached to any channel in the DAC to be addressed and is also acknowledged 8-bit data-word. ACK is always generated by the receiving by the DAC. This is then followed by the two data bytes. REG1 device. The AD5382 devices generate an ACK when receiving and REG0 determine the register to be updated. an address or data by pulling SDA low during the ninth clock If a stop condition does not follow the data bytes, another period. Monitoring ACK allows detection of unsuccessful data channel can be updated by sending a new pointer byte followed transfers. An unsuccessful data transfer occurs if a receiving by the data bytes. This mode requires only three bytes to be sent device is busy or if a system fault has occurred. In the event of to update any channel once the device is initially addressed, and an unsuccessful data transfer, the bus master should reattempt reduces the software overhead in updating the AD5382 communication. channels. A stop condition at any time exits this mode. Figure 32 shows a typical configuration. Rev. B | Page 28 of 40 AD5382 SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 0 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB SDA ACK BY ACK BY STOP AD538x AD538x COND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE BY MASTER 2 Figure 31. 4-Byte AD5382, I C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 0 A4A3 A2A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 0 A4 A3A2A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP COND AD538x AD538x BY MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" 2 Figure 32. 3-Byte AD5382, I C Write Operation Rev. B | Page 29 of 40 03733-032 03733-031 AD5382 2-Byte Mode PARALLEL INTERFACE Following initialization of 2-byte mode, the user can update The SER/PAR pin must be tied low to enable the parallel channels sequentially. The device address byte is required only interface and disable the serial interfaces. Figure 7 shows the once, and the pointer address pointer is configured for auto- timing diagram for a parallel write. The parallel interface is increment or burst mode. controlled by the following pins. The user must begin with an address byte (R/W = 0), after CS Pin which the DAC acknowledges that it is prepared to receive data Active low device select pin. by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. WR Pin The address pointer initializes to Channel 0, the data following On the rising edge of , with low, the addresses on Pins WR CS the pointer is loaded to Channel 0, and the address pointer A4 to A0 are latched; data present on the data bus is loaded into automatically increments to the next address. the selected input registers. The REG0 and REG1 bits in the data byte determine which REG0, REG1 Pins register is updated. In this mode, following the initialization, The REG0 and REG1 pins determine the destination register of only the two data bytes are required to update a channel. The the data being written to the AD5382. See Table 11. channel address automatically increments from Address 0 to Pins A4 to A0 Channel 31 and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels Each of the 40 DAC channels can be addressed individually. in one block and reduces the software overhead in configuring all Pins DB13 to DB0 channels. A stop condition at any time exits this mode. Toggle The AD5382 accepts a straight 14-bit parallel word on DB13 to mode is not supported in 2-byte mode. Figure 33 shows a DB0, where DB13 is the MSB and DB0 is the LSB. typical configuration. SCL SDA 1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND ACK BY MSB ACK BY BY MASTER CONVERTER CONVERTER ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY CONVERTER CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP CONVERTER CONVERTER COND MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 33. 2-Byte, I C Write Operation Rev. B | Page 30 of 40 03733-033 AD5382 MICROPROCESSOR INTERFACING Parallel Interface When data is being transmitted to the AD5382, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid The AD5382 can be interfaced to a variety of 16-bit microcon- on the falling edge of SCK. Serial data from the 68HC11 is trollers or DSP processors. Figure 35 shows the AD5382 family transmitted in 8-bit bytes with only eight falling clock edges interfaced to a generic 16-bit microcontroller/DSP processor. occurring in the transmit cycle. The lower address lines from the processor are connected to A0–A4 on the AD5382. The upper address lines are decoded DVDD 1 to provide a CS, LDAC signal for the AD5382. The fast interface 1 AD5382 MC68HC11 timing of the AD5382 allows direct interface to a wide variety SER/PAR RESET of microcontrollers and DSPs, as shown in Figure 35. MISO SDO MOSI DIN AD5382 to MC68HC11 SCK SCLK The serial peripheral interface (SPI) on the MC68HC11 is PC7 SYNC 2 configured for master mode (MSTR = 1), Clock Polarity bit SPI/I C (CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see 1 ADDITIONAL PINS OMITTED FOR CLARITY. the 68HC11 User Manual. SCK of the 68HC11 drives the Figure 34. AD5382-to-MC68HC11 Interface SCLK of the AD5382, the MOSI output drives the serial data line (DIN) of the AD5382, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). 1 μCONTROLLER/ AD5382 1 DSP PROCESSOR D15 REG1 REG0 D13 DATA BUS D0 D0 CS UPPER BITS OF ADDRESS ADDRESS BUS DECODE LDAC A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 R/W WR 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5382-to-Parallel Interface Rev. B | Page 31 of 40 03733-035 03733-034 AD5382 1 DVDD 1 AD5382 to PIC16C6x/7x 8XC51 AD5382 SER/PAR The PIC16C6x/7x synchronous serial port (SSP) is configured as RESET an SPI master with the Clock Polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). RxD SDO DIN See the PIC16/17 Microcontroller User Manual. In this example TxD SCLK I/O, Port RA1 is being used to pulse SYNC and enable the serial P1.1 SYNC 2 port of the AD5382. This microcontroller transfers only eight SPI/I C bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed depending on 1 ADDITIONAL PINS OMITTED FOR CLARITY. the mode. Figure 36 shows the connection diagram. Figure 37. AD5382-to-8051 Interface DVDD 1 1 PIC16C6X/7X AD5382 AD5382 to ADSP-2101/ADSP-2103 SER/PAR Figure 38 shows a serial interface between the AD5382 and the RESET ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SDI/RC4 SDO SDO/RC5 DIN be set up to operate in SPORT transmit alternate framing mode. SCK/RC3 SCLK The ADSP-2101/ADSP-2103 SPORT is programmed through RA1 SYNC 2 the SPORT control register and should be configured as follows: SPI/I C internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the 1 ADDITIONAL PINS OMITTED FOR CLARITY. Tx register after the SPORT has been enabled. Figure 36. AD5382-to-PIC16C6x/7x Interface DVDD 1 ADSP-2101/ AD5382 AD5382 to 8051 1 ADSP-2103 SER/PAR The AD5382 requires a clock synchronized to the serial data. RESET The 8051 serial interface must therefore be operated in Mode 0. DR SDO DT DIN In this mode, serial data enters and exits through RxD, and a SCK SCLK shift clock is output on TxD. Figure 37 shows how the 8051 is TFS SYNC connected to the AD5382. Because the AD5382 shifts data out RFS 2 on the rising edge of the shift clock and latches data in on the SPI/I C falling edge, the shift clock must be inverted. The AD5382 requires its data to be MSB first. Since the 8051 outputs the 1 ADDITIONAL PINS OMITTED FOR CLARITY. LSB first, the transmit routine must take this into account. Figure 38. AD5382-to-ADSP-2101/ADSP-2103 Interface Rev. B | Page 32 of 40 03733-036 03733-038 03733-037 AD5382 APPLICATION INFORMATION externally from either an ADR421 or ADR431 2.5 V reference. POWER SUPPLY DECOUPLING Suitable external references for the AD5382-3 include the In any circuit where accuracy is important, careful considera- ADR280 1.2 V reference. The reference should be decoupled at tion of the power supply and ground return layout helps to the REFOUT/REFIN pin of the device with a 0.1 μF capacitor. ensure the rated performance. The printed circuit board on AVDD DVDD which the AD5382 is mounted should be designed so that the 0.1μF analog and digital sections are separated and confined to certain areas of the board. If the AD5382 is in a system where 10μF 0.1μF multiple devices require an AGND-to-DGND connection, the ADR431/ ADR421 connection should be made at one point only, a star ground point established as close to the device as possible. AVDD DVDD REFOUT/REFIN VOUT0 For supplies with multiple pins (AVDD, DVDD), these pins 0.1μF should be tied together. The AD5382 should have ample supply AD5382-5 bypassing of 10 μF in parallel with 0.1 μF on each supply, REFGND VOUT31 located as close as possible to the package and ideally right up against the device. The 10 μF capacitors are the tantalum bead DAC_GND SIGNAL_GND AGND DGND type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to Figure 39. Typical Configuration with External Reference ground at high frequencies, to handle transient currents due to internal logic switching. Figure 40 shows a typical configuration when using the internal reference. On power-up, the AD5382 defaults to an external The power supply lines of the AD5382 should use as large a reference; therefore, the internal reference needs to be config- trace as possible to provide low impedance paths and reduce ured and turned on via a write to the AD5382 control register. the effects of glitches on the power supply line. Fast switching Control Register Bit CR12 allows the user choose the reference signals such as clocks should be shielded with digital ground value; Bit CR 10 is used to select the internal reference. It is to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed recommended to use the 2.5 V reference when AVDD = 5 V, between the D and SCLK lines helps reduce crosstalk between and the 1.25 V reference when AVDD = 3 V. IN them. This is not required on a multilayer board because there AVDD DVDD is a separate ground plane, but separating the lines helps. It is 0.1μF essential to minimize noise on the VIN and REFIN lines. 10μF 0.1μF Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through AVDD DVDD the board. A microstrip technique is by far the best, but is REFOUT/REFIN VOUT0 not always possible with a double-sided board. In this tech- 0.1μF AD5382 nique, the component side of the board is dedicated to the REFGND ground plane while signal traces are placed on the solder side. VOUT31 TYPICAL CONFIGURATION CIRCUIT DAC_GND SIGNAL_GND AGND DGND Figure 39 shows a typical configuration for the AD5382-5 when configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins Figure 40. Typical Configuration with Internal Reference are tied together to a common AGND. AGND and DGND are connected together at the AD5382 device. On power-up, the Digital connections have been omitted for clarity. The AD5382 AD5382 defaults to external reference operation. All AVDD contains an internal power-on reset circuit with a 10 ms brown- lines are connected together and driven from the same 5 V out time. If the power supply ramp rate exceeds 10 ms, the user source. It is recommended to decouple close to the device should reset the AD5382 as part of the initialization process to with a 0.1 μF ceramic and a 10 μF tantalum capacitor. ensure the calibration data is loaded correctly into the device. In this application, the reference for the AD5382-5 is provided Rev. B | Page 33 of 40 03733-040 03733-039 D A 780/ 43 ADR 1 AD5382 B registers can be loaded only when toggle mode is enabled. MONITOR FUNCTION The sequence of events when configuring the AD5382 for The AD5382 channel monitor function consists of a multiplexer toggle mode is as follows: addressed via the interface, allowing any channel output to be 1. Enable toggle mode for the required channels via the routed to this pin for monitoring using an external ADC. control register. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. Table 18 2. Load data to the A registers. contains the decoding information required to route any chan- 3. Load data to the B registers. nel to MON_OUT. External signals within the AD5382’s 4. Apply LDAC. absolute maximum input range can be connected to the The LDAC is used to switch between the A and B registers in MON_IN pins and monitored at MON_OUT. Selecting determining the analog output. The first LDAC configures the Channel Address 63 three-states MON_OUT. Figure 41 shows a typical monitoring circuit implemented using a 12-bit SAR output to reflect the data in the A registers. This mode offers ADC in a 6-lead SOT-23 package. The controller output port significant advantages if the user wants to generate a square selects the channel to be monitored, and the input port reads wave at the output of all 32 channels, as might be required to the converted data from the ADC. drive a liquid crystal-based variable optical attenuator. In this case, the user writes sets the control register and enables the TOGGLE MODE FUNCTION toggle function by setting CR5 to CR2 = 1, thus enabling the The toggle mode function allows an output signal to be gener- four groups of eight for toggle mode operation. The user must ated using the control signal that switches between two LDAC then load data to all 32 A and B registers. Toggling will LDAC DAC data registers. This function is configured using the SFR set the output values to reflect the data in the A and B registers. control register as follows. A write with REG1 = REG0 = 0 and The frequency of the LDAC determines the frequency of the A4–A0 = 01100 specifies a control register write. The toggle square wave output. mode function is enabled in groups of eight channels using bits Toggle mode is disabled via the control register. The first LDAC CR5 to CR2 in the control register. See the AD5382 control following the disabling of the toggle mode updates the outputs register contents in Table 16. Figure 42 shows a block diagram with the data contained in the A registers. of toggle mode implementation. Each of the 32 DAC channels on the AD5382 contains an A and B data register. Note that the AVCC AVCC REFOUT/REFIN DIN SYNC OUTPUT PORT SCLK MON_IN1 AVCC MON_IN2 AD7476 CS MON_OUT VIN SCLK INPUT PORT SDATA VOUT0 AD5382 GND CONTROLLER VOUT31 AGND DAC_GND SIGNAL_GND Figure 41. Typical Channel Monitoring Circuit Rev. B | Page 34 of 40 03733-041 AD5382 DATA REGISTER A DAC VOUT 14-BIT DAC REGISTER DATA INPUT INPUT REGISTER DATA REGISTER B LDAC A/B CONTROL INPUT Figure 42. Toggle Mode Function +5V OUTPUT RANGE 0V TO 200V 0.01μF REFOUT/REFIN AVDD VOUT1 14-BIT DAC 8-CHANNEL ADC G = 50 ACTUATORS (AD7856) SENSOR FOR MEMS OR AND MIRROR SINGLE CHANNEL MULTIPLEXER ARRAY ADC (AD7671) 14-BIT DAC G = 50 VOUT31 AD5382 ADSP-21065L Figure 43. AD5382 in a MEMS Based Optical Switch AD5382 IN A MEMS-BASED OPTICAL SWITCH THERMAL MONITOR FUNCTION In their feed-forward control paths, MEMS-based optical The AD5382 contains a temperature shutdown function to switches require high resolution DACs that offer high channel protect the chip if multiple outputs are shorted. The short- density with 14-bit monotonic behavior. The 32-channel, 14-bit circuit current of each output amplifier is typically 40 mA. AD5382 DAC satisfies these requirements. In the circuit in Operating the AD5382 at 5 V leads to a power dissipation of Figure 43, the 0 V to 5 V outputs of the AD5382 are amplified 200 mW per shorted amplifier. With five channels shorted, this to achieve an output range of 0 V to 200 V, which is used to leads to an extra watt of power dissipation. For the 100-lead control actuators that determine the position of MEMS mirrors LQFP, the θJA is typically 44°C/W. in an optical switch. The exact position of each mirror is meas- The thermal monitor is enabled by the user via CR8 in the ured using sensors. The sensor outputs are multiplexed into a control register. The output amplifiers on the AD5382 are high resolution ADC in determining the mirror position. The automatically powered down if the die temperature exceeds control loop is closed and driven by an ADSP-21065L, a 32-bit approximately 130°C. After a thermal shutdown occurs, the SHARC® DSP with an SPI-compatible SPORT interface. The user can re-enable the part by executing a soft power-up if the ADSP-21065L writes data to the DAC, controls the multiplexer, temperature drops below 130°C or by turning off the thermal and reads data from the ADC via the serial interface. monitor function via the control register. Rev. B | Page 35 of 40 03733-042 03733-043 AD5382 OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic The AD5382 controls the optical attenuator for each wavelength, behavior, and high level of integration, the AD5382 is ideally ensuring that the power is equalized in all wavelengths before targeted at optical attenuation applications used in dynamic being multiplexed onto the fiber. This prevents information loss gain equalizers, variable optical attenuators (VOA), and optical and saturation from occurring at amplification stages further add-drop multiplexers (OADM). In these applications, each along the fiber. wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimped- ance amplifier and ADC in a closed-loop control system. ADD DROP PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM DWDM ATTENUATOR IN OUT FIBRE AWG FIBRE AWG 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) ADG731 N:1 MULTIPLEXER (32:1 MUX) AD5382, 32-CHANNEL, 14-BIT DAC AD7671 CONTROLLER 16-BIT ADC (0V TO 5V, 1MSPS) Figure 44. OADM Using the AD5382 as Part of an Optical Attenuator Rev. B | Page 36 of 40 03733-044 AD5382 OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 14.00 BSC SQ 0.75 100 76 1 75 0.60 0.45 PIN 1 12.00 TOP VIEW REF (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 25 51 0.15 0° 26 50 SEATING 0.05 0.08 MAX PLANE 0.27 COPLANARITY VIEW A 0.22 0.50 BSC VIEW A 0.17 LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 45. 100-Lead Low Profile Quad Flat package [LQFP] (ST-100-1) Dimensions shown in millimeters ORDERING GUIDE Output Linearity Package Package 1 Model Resolution Temperature Range AVDD Range Channels Error Description Option AD5382BSTZ-3 14 Bits –40°C to +85°C 2.7 V to 3.6 V 32 ±4 LSB 100-Lead LQFP ST-100-1 AD5382BSTZ-5 14 Bits –40°C to +85°C 4.5 V to 5.5 V 32 ±4 LSB 100-Lead LQFP ST-100-1 EVAL-AD5382EBZ Evaluation Kit 1 Z = RoHS Compliant Part. Rev. B | Page 37 of 40 AD5382 NOTES Rev. B | Page 38 of 40 AD5382 NOTES Rev. B | Page 39 of 40 AD5382 NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). © 2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03733–0–4/10(B) Rev. B | Page 40 of 40