ANALOG DEVICES AD5381

40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC Data Sheet AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User-programmable offset and gain adjust Power-down Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitors User interfaces: APPLICATIONS Parallel Variable optical attenuators (VOAs) Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, Level setting (ATE) featuring data readback) Optical micro-electro-mechanical systems (MEMs) 2 I C®-compatible Control systems Robust 6.5 kV HBM and 2 kV FICDM ESD rating Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3) AVDD (×5) AGND (×5) DAC_GND (×5) REFGND REFOUT/REFIN SIGNAL_GND (×5) PD AD5381 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG0 REG0 VOUT0 DB11/(DIN/SDA) 12 m REG0 DB10/(SCLK/SCL) FIFO 12 2 DB9/(SPI/I C) c REG0 R + R DB8 INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC + INPUT DAC DAC 1 DB0 REG1 REG1 CONTROL VOUT1 LOGIC 12 A5 VOUT2 m REG1 A0 12 R c REG1 VOUT3 R REG0 VOUT4 12 12 12 12 INPUT DAC VOUT5 REG1 DAC 6 REG6 REG6 VOUT6 POWER-ON RESET RESET 12 m REG6 12 BUSY R c REG6 R CLR 12 12 12 12 INPUT DAC VOUT0………VOUT38 DAC 7 REG7 REG7 VOUT7 12 VOUT8 m REG7 39-TO-1 12 c REG7 R MUX R VOUT38 ×5 VOUT39/MON_OUT LDAC Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 03732-001 AD5381 Data Sheet TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function .................................................. 25 Specifications ..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5381-5 Specifications ............................................................. 4 FIFO Operation in Parallel Mode ............................................ 25 AD5381-3 Specifications ............................................................. 6 Power-On Reset .......................................................................... 25 AC Characteristics ........................................................................ 7 Power-Down ............................................................................... 25 Timing Characteristics ..................................................................... 8 Interfaces.......................................................................................... 26 Serial Interface Timing ................................................................ 8 DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26 2 2 I C Serial Interface Timing........................................................ 10 I C Serial Interface ..................................................................... 28 Parallel Interface Timing ........................................................... 11 Parallel Interface ......................................................................... 30 Absolute Maximum Ratings .......................................................... 13 Microprocessor Interfacing ....................................................... 31 ESD Caution ................................................................................ 13 Application Information ................................................................ 33 Pin Configuration and Function Descriptions ........................... 14 Power Supply Decoupling ......................................................... 33 Terminology .................................................................................... 17 Typical Configuration Circuit .................................................. 33 Typical Performance Characteristics ........................................... 18 Monitor Function ....................................................................... 34 Functional Description .................................................................. 21 Toggle Mode Function ............................................................... 34 DAC Architecture—General ..................................................... 21 Thermal Monitor Function ....................................................... 34 Data Decoding ............................................................................ 21 Optical Attenuators .................................................................... 35 On-Chip Special Function Registers (SFR) ............................ 22 Utilizing FIFO ............................................................................. 35 SFR Commands .......................................................................... 22 Outline Dimensions ....................................................................... 37 Hardware Functions ....................................................................... 25 Ordering Guide .......................................................................... 37 Reset Function ............................................................................ 25 REVISION HISTORY 5/12—Rev. B to Rev. C 8/05—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to Table 2 ............................................................................. 3 Changes to Table 3 ............................................................................ 4 Changes to Specifications Section ................................................... 4 Changes to Table 4 ............................................................................ 6 Changes to Absolute Maximum Ratings Section ....................... 13 Changes to Output Voltage Settling Time and Slew Rate Changes to Figure 43 ...................................................................... 35 Parameters, Table 5 ........................................................................... 7 Changes to Ordering Guide .......................................................... 37 Changes to t14, t17, and t19 Parameters, Table 6 .............................. 8 6/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Table 9 .......................................................................... 13 Changes to Figure 10, Figure 11, and Figure 14 ......................... 18 Changes to Ordering Guide ........................................................... 36 Changes to Figure 16 to Figure 18 and Figure 20 ....................... 19 Updated Outline Dimensions and Changes to Ordering Guide .... 37 5/04—Revision 0: Initial Version Rev. C | Page 2 of 40 Data Sheet AD5381 GENERAL DESCRIPTION The AD5381 is a complete, single-supply, 40-channel, 12-bit An input register followed by a DAC register provides double DAC available in a 100-lead LQFP package. All 40 channels buffering, allowing the DAC outputs to be updated independ- have an on-chip output amplifier with rail-to-rail operation. ently or simultaneously using the LDAC input. The AD5381 includes a programmable internal 1.25 V/2.5 V, Each channel has a programmable gain and offset adjust 10 ppm/°C reference, an on-chip channel monitor function that register that allows the user to fully calibrate any DAC chan- multiplexes the analog outputs to a common MON_OUT pin nel. Power consumption is typically 0.25 mA/channel with for external monitoring, and an output amplifier boost mode, boost mode disabled. which allows optimization of the amplifier slew rate. The AD5381 contains a double-buffered parallel interface featuring 20 ns WR pulse width, an SPI-/QSPI-/MICROWIRE-/DSP- compatible serial interface with interface speeds in excess of 2 30 MHz, and an I C-compatible interface that supports a 400 kHz data transfer rate. Table 1. Other Low Voltage Single-Supply DACs in Product Family Linearity Error Package Model Resolution AVDD Range Output Channels (LSB) Description Package Option AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-80 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-80 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64 Table 2. 40-Channel, Bipolar Voltage Output DAC Linearity Model Resolution Analog Supplies Output Channels Error Package Package Option AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108 AD5378ABC 14 Bits ±11.4 V to ±16.5 V 32 ±3 108-Lead CSPBGA BC-108 Rev. C | Page 3 of 40 AD5381 Data Sheet SPECIFICATIONS AD5381-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T to T , MIN MAX unless otherwise noted. Table 3. 1 Parameter AD5381-5 Unit Test Conditions/Comments ACCURACY Output unloaded Resolution 12 Bits 2 Relative Accuracy (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 8 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.05 % FSR max At 25°C ±0.06 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 1 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max 4 Reference Output Enabled via CR8 in the AD5381 control register, CR10 selects the reference voltage Output Voltage 2.495/2.505 V min/max At ambient, optimized for 2.5 V operation. CR10 = 1 1.22/1.28 V min/max CR10 = 0 Reference TC ±10 ppm/°C max Temperature Range: +25°C to +85°C ±15 ppm/°C max Temperature Range: −40°C to +85°C Output Impedance 800 Ω typ 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability R = ∞ 200 pF max L RL = 5 kΩ 1000 pF max DC Output Impedance 0.6 Ω max MONITOR PIN Output Impedance 1 kΩ typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 5.5 V VIH, Input High Voltage 2 V min VIL, Input Low Voltage DVDD > 3.6 V 0.8 V max DVDD ≤ 3.6 V 0.6 V max Input Current ±10 µA max Total for all pins; T = T to T A MIN MAX Pin Capacitance 10 pF max Rev. C | Page 4 of 40 Data Sheet AD5381 1 Parameter AD5381-5 Unit Test Conditions/Comments 3 LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 × DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 × DVDD V max SMBus compatible at DVDD < 3.6 V I , Input Leakage Current ±1 µA max IN V , Input Hysteresis 0.05 × DVDD V min HYST C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns 3 LOGIC OUTPUTS ( , SDO) BUSY VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA V , Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA OH High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AI 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded, boost on.; 0.325 mA /channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 20 µA max Typically 100 nA DI (Power-Down) 20 µA max Typically 1 µA DD Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V 1 AD5381-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5381-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5381 control register; operating the AD5381-5 with a 1.25 V reference will lead to degraded accuracy specifications. Rev. C | Page 5 of 40 AD5381 Data Sheet AD5381-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter AD5381-3 Unit Test Conditions/Comments ACCURACY Output unloaded Resolution 12 Bits 2 Relative Accuracy (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 16 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.05 % FSR max At 25 °C ±0.1 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 1 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max 4 Reference Output Enabled via CR8 in the AD5381 control register CR10 selects the reference voltage. Output Voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0 2.47/2.53 V min/max CR10 = 1 Reference TC ±10 ppm/°C max Temperature Range: +25°C to +85°C ±15 ppm/°C max Temperature Range: –40°C to +85°C Output Impedance 800 Ω typ 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability R = ∞ 200 pF max L RL = 5 kΩ 1000 pF max DC Output Impedance 0.6 Ω max MONITOR PIN Output Impedance 1 kΩ typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 3.6 V VIH, Input High Voltage 2 V min V Input Low Voltage IL, DVDD > 3.6 0.8 V max DVDD ≤ 3.6 0.6 V max Input Current ±1 µA max Total for all pins; T = T to T A MIN MAX Pin Capacitance 10 pF max 3 LOGIC INPUTS (SDA, SCL ONLY) V , Input High Voltage 0.7 × DVDD V min SMBus compatible at DVDD < 3.6 V IH VIL, Input Low Voltage 0.3 × DVDD V max SMBus compatible at DVDD < 3.6 V I , Input Leakage Current ±1 µA max IN VHYST, Input Hysteresis 0.05 × DVDD V min CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. C | Page 6 of 40 Data Sheet AD5381 1 Parameter AD5381-3 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) V , Output Low Voltage 0.4 V max Sinking 200 µA OL VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 20 µA max Typically 100 nA DI (Power-Down) 20 µA max Typically 1 µA DD Power Dissipation 48 mW max Outputs unloaded, boost off, AVDD = DVDD = 3 V 1 AD5381-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5381-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5381 control register; operating the AD5381-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range. 1 AC CHARACTERISTICS AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 5. Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 1/4 scale to 3/4 scale change settling to ±1 LSB 3 µs typ 8 µs max 2 Slew Rate 1.5 V/µs typ Boost mode off, CR9 = 0 2.5 V/µs typ Boost mode on, CR9 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 Slew rate can be programmed via the current boost control bit in the AD5381 control register. Rev. C | Page 7 of 40 AD5381 Data Sheet TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , unless otherwise noted. MIN MAX Table 6. 1, 2, 3 Parameter Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 th t5 13 ns min 24 SCLK falling edge to SYNC falling edge 4 t6 33 ns min Minimum SYNC low time t 10 ns min Minimum SYNC high time 7 t 50 ns min Minimum SYNC high time in Readback mode 7A t8 5 ns min Data setup time t9 4.5 ns min Data hold time 4 th t10 30 ns max 24 SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) 4 t 20 ns min 24th SCLK falling edge to LDAC falling edge 12 t 20 ns min LDAC pulse width low 13 t14 2 µs max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t 3 µs typ DAC output settling time 17 t 20 ns min CLR pulse width low 18 t 40 µs max pulse activation time 19 CLR 5 t20 20 ns max SCLK rising edge to SDO valid 5 t21 5 ns min SCLK falling edge to SYNC rising edge 5 t22 8 ns min SYNC rising edge to SCLK rising edge t 20 ns min SYNC rising edge to LDAC falling edge 23 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of V ) and are timed from a voltage level of 1.2 V. r f CC 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. 200µA I OL V (MIN) OR OH TO OUTPUT PIN V (MAX) C OL L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Rev. C | Page 8 of 40 03732-002 Data Sheet AD5381 t 1 24 24 SCLK t 3 t 2 t t 5 4 t 6 SYNC t 7 t t 8 9 DB0 DIN DB23 t 10 t 11 BUSY t t 12 13 t 1 17 LDAC t 14 VOUT1 t 15 t 13 2 LDAC t 17 t 16 VOUT2 t 18 CLR t 19 VOUT 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t 1 SCLK 24 48 t t t 3 2 21 t 7 t 22 t 4 SYNC t t 8 9 DB23 DB0 DB23 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 20 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 13 t 23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. C | Page 9 of 40 03732-003 03732-005 03732-004 AD5381 Data Sheet 2 I C SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. 1, 2 Parameter Limit at TMIN, TMAX Unit Description FSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH, SCL high time t 1.3 µs min t , SCL low time 3 LOW t 0.6 µs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT 3 t6 0.9 µs max tHD,DAT, data hold time 0 µs min tHD,DAT, data hold time t 0.6 µs min t , setup time for repeated start 7 SU,STA t 0.6 µs min t , stop condition setup time 8 SU,STO t 1.3 µs min t , bus free time between a STOP and a START condition 9 BUF t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min t , fall time of SDA when receiving (CMOS compatible) F 300 ns max t , fall time of SCL and SDA when receiving F 4 20 + 0.1 Cb ns min tF, fall time of SCL and SDA when transmitting Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V min of the SCL signal) in order to bridge the undefined region of IH SCL’s falling edge. 4 C is the total capacitance, in pF, of one bus line. t and t are measured between 0.3 DVDD and 0.7 DVDD. b R F SDA t t t t t 9 3 10 11 4 SCL t t t t t 4 6 2 1 8 t t 5 7 START REPEATED STOP CONDITION START CONDITION CONDITION 2 Figure 6. I C-Compatible Serial Interface Timing Diagram Rev. C | Page 10 of 40 03732-006 Data Sheet AD5381 PARALLEL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 8. 1,2, 3 Parameter Limit at TMIN, TMAX Unit Description t0 4.5 ns min REG0, REG1, address to WR rising edge setup time t1 4.5 ns min REG0, REG1, address to WR rising edge hold time t 20 ns min CS pulse width low 2 t 20 ns min WR pulse width low 3 t 0 ns min CS to WR falling edge setup time 4 t5 0 ns min WR to CS rising edge hold time t6 4.5 ns min Data to WR rising edge setup time t7 4.5 ns min Data to WR rising edge hold time t 20 ns min WR pulse width high 8 4 t 700 ns min Minimum WR cycle time (single-channel write) 9 4 t 30 ns max rising edge to falling edge 10 WR BUSY 4, 5 t11 670 ns max BUSY pulse width low (single-channel update) t12 30 ns min WR rising edge to LDAC falling edge t13 20 ns min LDAC pulse width low t 100 ns max BUSY rising edge to DAC output response time 14 t 20 ns min LDAC rising edge to WR rising edge 15 t 0 ns min rising edge to falling edge 16 BUSY LDAC t17 100 ns min LDAC falling edge to DAC output response time t18 8 µs typ DAC output settling time, boost mode off t19 20 ns min CLR pulse width low t 12 µsmax CLR pulse activation time 20 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. R R 3 See Figure 7. 4 See Figure 29. 5 Measured with the load circuit of Figure 2. Rev. C | Page 11 of 40 AD5381 Data Sheet t t 0 1 REG0, REG1, A5...A0 t t 4 5 t 2 CS t 9 t t 3 8 WR t t t 15 6 7 DB11...DB0 t 10 t 11 BUSY t t 12 13 t 18 1 LDAC t 14 VOUT1 t 16 2 LDAC t 13 t 18 t 17 VOUT2 CLR t 19 t VOUT 20 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev. C | Page 12 of 40 03732-007 Data Sheet AD5381 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 9. rating only; functional operation of the device at these or any Parameter Rating other conditions above those listed in the operational sections AVDD to AGND –0.3 V to +7 V of this specification is not implied. Exposure to absolute maxi- DVDD to DGND –0.3 V to +7 V mum rating conditions for extended periods may affect device Digital Inputs to DGND –0.3 V to DVDD + 0.3 V reliability. SDA/SCL to DGND –0.3 V to +7 V Digital Outputs to DGND –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND –0.3 V to AVDD + 0.3 V AGND to DGND –0.3 V to +0.3 V VOUTx to AGND –0.3 V to AVDD + 0.3 V Analog Inputs to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (T ) 150°C J MAX 100-Lead LQFP Package θJAThermal Impedance 44°C/W Reflow Soldering Peak Temperature 230°C Reflow Soldering (Pb-free) Peak Temperature 260(0/-5)°C Time at Peak Temperature 10 sec to 40 sec ESD HBM 6.5 kV FICDM 2 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 13 of 40 AD5381 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 FIFO EN 75 RESET PIN 1 2 CLR 74 DB5 IDENTIFIER VOUT24 3 73 DB4 4 VOUT25 72 DB3 5 VOUT26 71 DB2 6 VOUT27 70 DB1 7 69 SIGNAL_GND4 DB0 8 DAC_GND4 68 NC 9 AGND4 67 NC 10 AVDD4 66 REG0 VOUT28 11 65 REG1 VOUT29 12 64 VOUT23 AD5381 13 VOUT30 63 VOUT22 TOP VIEW 14 VOUT31 (Not to Scale) 62 VOUT21 15 REFGND 61 VOUT20 16 REFOUT/REFIN 60 AVDD3 17 SIGNAL_GND1 59 AGND3 18 DAC_GND1 58 DAC_GND3 19 AVDD1 57 SIGNAL_GND3 VOUT0 20 56 VOUT19 VOUT1 21 55 VOUT18 22 VOUT2 54 VOUT17 23 VOUT3 53 VOUT16 VOUT4 24 52 AVDD2 25 AGND1 51 AGND2 NC = NO CONNECT Figure 8. 100-Lead LQFP Pin Configuration Table 10. Pin Function Descriptions Mnemonic Function VOUTx Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND(1–5) Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5381. DAC_GND(1–5) Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 12-bit DAC. These pins shound be connected to the AGND plane. AGND(1–5) Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD(1–5) Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 µF ceramic capacitor and 10 µF tantalum capacitor. Operating range for the AD5381-5 is 4.5 V to 5.5 V; operating range for the AD5381-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with a 0.1 µF ceramic and a 10 µF tantalum capacitors to DGND. REFGND Ground Reference Point for the Internal Reference. Rev. C | Page 14 of 40 26 100 SIGNAL_GND5 CS/(SYNC/AD0) DAC_GND5 27 99 DB11/(DIN/SDA) AGND5 28 98 DB10/(SCLK/SCL) 2 AVDD5 29 97 DB9/(SPI/I C) 96 VOUT5 30 DB8 VOUT6 31 95 DB7 VOUT7 32 94 DB6 VOUT32 33 93 SDO/(A/B) 34 92 VOUT33 DVDD VOUT34 35 91 DGND VOUT35 36 90 DGND VOUT36 37 89 A5 88 VOUT37 38 A4 VOUT38 39 87 A3 VOUT39/MON_OUT 40 86 A2 VOUT8 41 85 A1 42 84 VOUT9 A0 43 83 DVDD VOUT10 VOUT11 44 82 DVDD VOUT12 45 81 DGND 80 DAC_GND2 46 SER/PAR SIGNAL_GND2 47 79 PD VOUT13 48 78 WR (DCEN/AD1) VOUT14 49 77 LDAC 50 76 VOUT15 BUSY 03732-008 Data Sheet AD5381 Mnemonic Function REFOUT/REFIN The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input. VOUT39/MON_OUT This pin has a dual function. It acts as a buffered output for Channel 39 in default mode. However, when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. SER/PAR Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied high, 2 2 the serial interface mode is selected and Pin 97 (SPI/I C) is used to determine if the interface mode is SPI or I C. Parallel interface mode is selected when SER/PAR is low. /( /AD0) In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5381 CS SYNC is selected. Serial Interface Mode. This is the frame synchronization input signal for the serial clock and data. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address 2 for the device on the I C bus. WR/(DCEN/AD1) Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a 2 daisy-chain enable in SPI mode and as a hardware address pin in I C mode. Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low, and the address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction with SER/PAR high to enable the SPI serial interface daisy-chain mode. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address 2 for this device on the I C bus. DB11–DB0 Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5381. A5–A0 Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5381’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. REG1, REG0 In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. SDO/(A/B) Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5381’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels contain two data registers. In normal mode, Data Register A is the default for data transfers. BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If is taken low while is low, this event is stored. also LDAC BUSY BUSY goes low during power-on reset, and when the RESET pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the event is stored and the DAC registers are updated when LDAC BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. Rev. C | Page 15 of 40 AD5381 Data Sheet Mnemonic Function PD Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog current consumption is reduced to 2 µA and the digital current consumption is reduced to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. FIFO EN FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or 2 I C interface modes, the FIFO EN pin should be tied low. 2 DB9/(SPI/I C) Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/ = 1) and PAR this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data (DIN) input. 2 When serial interface mode is selected (SER/PAR = 1) and this input is high I C Mode is selected. In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input. DB10/(SCLK/SCL) Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial interface mode, this pin acts as a serial clock input. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 50 MHz. 2 2 I C Mode. In I C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in 2 I C mode is compatible with both 100 kHz and 400 kHz operating modes. DB11/(DIN/SDA) Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. 2 2 I C Mode. In I C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. Rev. C | Page 16 of 40 Data Sheet AD5381 TERMINOLOGY Relative Accuracy DC Output Impedance Relative accuracy, or endpoint linearity, is a measure of the This is the effective output source resistance. It is dominated by maximum deviation from a straight line passing through the package lead resistance. endpoints of the DAC transfer function. It is measured after Output Voltage Settling Time adjusting for zero-scale error and full-scale error, and is This is the amount of time it takes for the output of a DAC to expressed in LSB. settle to a specified level for a ¼ to ¾ full-scale input change, Differential Nonlinearity and is measured from the rising edge. BUSY Differential nonlinearity is the difference between the measured Digital-to-Analog Glitch Energy change and the ideal 1 LSB change between any two adjacent This is the amount of energy injected into the analog output at codes. A specified differential nonlinearity of 1 LSB maximum the major code transition. It is specified as the area of the glitch ensures monotonicity. in nV-s. It is measured by toggling the DAC register data Zero-Scale Error between 0x7FF and 0x800. Zero-scale error is the error in the DAC output voltage when all DAC-to-DAC Crosstalk 0s are loaded into the DAC register. Ideally, with all 0s loaded n – 1 to the DAC and m = all 1s, c = 2 DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and the VOUT = 0 V (Zero-Scale) subsequent analog output change at another DAC. The victim channel is loaded with midscale. DAC-to-DAC crosstalk is Zero-scale error is a measure of the difference between VOUT specified in nV-s. (actual) and VOUT (ideal), expressed in mV. It is mainly due to offsets in the output amplifier. Digital Crosstalk The glitch impulse transferred to the output of one converter Offset Error due to a change in the DAC register code of another converter Offset error is a measure of the difference between VOUT is defined as the digital crosstalk and is specified in nV-s. (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the Digital Feedthrough AD5381-5 with Code 32 loaded into the DAC register, and on When the device is not selected, high frequency logic activity the AD5381-3 with Code 64. on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the Gain Error VOUT pins. It can also be coupled along the supply and Gain Error is specified in the linear region of the output range ground lines. This noise is digital feedthrough. between VOUT = 10 mV and VOUT = AVDD – 50 mV. It is the deviation in slope of the DAC transfer characteristic from Output Noise Spectral Density the ideal and is expressed in %FSR with the DAC output This is a measure of internally generated random noise. unloaded. Random noise is characterized as a spectral density (voltage per √Hertz). It is measured by loading all DACs to midscale and DC Crosstalk measuring noise at the output. It is measured in nV/√Hz in a This is the dc change in the output level of one DAC at 1 Hz bandwidth at 10 kHz. midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB. Rev. C | Page 17 of 40 AD5381 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.00 1.00 AVDD = 5V AVDD = 3V REFIN = 2.5V REFIN = 1.25V 0.75 0.75 T = 25°C T = 25°C A A 0.50 0.50 0.25 0.25 0 0 –0.25 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 INPUT CODE INPUT CODE Figure 9. Typical AD5381-5 INL Plot Figure 12. Typical AD5381-3 INL Plot 1.254 2.510 AVDD = DVDD = 3V V = 1.25V REF 1.253 T = 25°C A 14ns/SAMPLE NUMBER 1.252 1 LSB CHANGE AROUND MIDSCALE 2.505 GLITCH IMPULSE = 5nV-s 1.251 1.250 2.500 1.249 1.248 2.995 1.247 1.246 1.245 2.990 0 50 100 150 200 250 300 350 400 450 500 550 0 2 4 6 8 10 12 SAMPLE NUMBER TIME (µs) Figure 13. AD5381-3 Glitch Impulse Figure 10. AD5381-5 Glitch Impulse LDAC LDAC VOUT VOUT AVDD = DVDD = 5V AVDD = DVDD = 5V V = 2.5V REF VREF = 2.5V T = 25°C A T = 25°C A Figure 11. Slew Rate with Boost Off Figure 14. Slew Rate with Boost On Rev. C | Page 18 of 40 INL ERROR (LSB) VOLTAGE (V) 03732-011 03732-103 03732-009 AMPLITUDE (V) INL ERROR (LSB) 03732-014 03732-013 03732-012 Data Sheet AD5381 14 AVDD = 5.5V V = 2.5V REF T = 25°C A 12 AVDD = DVDD = 5V VREF = 2.5V T = 25°C A 10 VDD 8 6 4 VOUT 2 8 9 10 11 AI (mA) DD Figure 15. AI Histogram with Boost Off Figure 18. Power-Up Transient DD 40 DVDD = 5.5V V = DVDD IH 35 10 V = DGND IL T = 25°C A 30 8 25 6 20 15 4 10 2 5 0 0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 0.5 0.6 0.7 0.8 0.9 1.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 DI (mA) DD REFERENCE DRIFT (ppm/°C) Figure 16. DI Histogram Figure 19. REFOUT Temperature Coefficient DD PD BUSY VOUT VOUT AVDD = DVDD = 5V AVDD = DVDD = 5V V = 2.5V REF V = 2.5V REF T = 25°C A T = 25°C A Figure 20. Exiting Hardware Power-Down Figure 17. Exiting Soft Power-Down Rev. C | Page 19 of 40 NUMBER OF UNITS PERCENTAGE OF UNITS (%) 03732-017 03732-015 03732-107 FREQUENCY 03732-102 03732-020 03732-019 AD5381 Data Sheet 6 6 AVDD = DVDD = 3V FULL SCALE V = 1.25V REF T = 25°C 5 5 A AVDD = DVDD = 5V V = 2.5V 3/4 SCALE REF 4 T = 25°C 4 A 3/4 SCALE FULL SCALE 3 MIDSCALE 3 MIDSCALE 2 2 1/4 SCALE 1 1 ZERO SCALE 0 0 ZERO SCALE 1/4 SCALE –1 –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 –40 –20 –10 –5 –2 0 2 5 10 20 –40 CURRENT (mA) CURRENT (mA) Figure 21. AD5381-5 Output Amplifier Source and Sink Capability Figure 24. AD5381-3 Output Amplifier Source and Sink Capability 0.20 2.456 AVDD = 5V AVDD = DVDD = 5V V = 2.5V REF V = 2.5V REF 0.15 T = 25°C A T = 25°C 2.455 A 14ns/SAMPLE NUMBER 0.10 2.454 ERROR AT ZERO SINKING CURRENT 0.05 2.453 0 2.452 –0.05 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT 2.451 –0.10 2.450 –0.15 –0.20 2.449 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 50 100 150 200 250 300 350 400 450 500 550 I /I (mA) SAMPLE NUMBER SOURCE SINK Figure 22. Headroom at Rails vs. Source/Sink Current Figure 25. Adjacent Channel DAC-to-DAC Crosstalk 600 AVDD = 5V T = 25°C A REFOUT DECOUPLED 500 AVDD = DVDD = 5V WITH 100nF CAPACITOR T = 25°C A DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE 400 Y AXIS = 5µV/DIV X AXIS = 100ms/DIV 300 REFOUT = 2.5V 200 REFOUT = 1.25V AV = DV = 5V DD DD 100 V = 2.5V REF T = 25°C A EXITS SOFT PD 0 TO MIDSCALE 100 1k 10k 100k FREQUENCY (Hz) Figure 26. 0.1 Hz to 10 Hz Noise Plot Figure 23. REFOUT Noise Spectral Density Rev. C | Page 20 of 40 VOUT (V) OUTPUT NOISE (nV/ Hz) ERROR VOLTAGE (V) 03732-021 03732-023 03732-022 VOUT (V) AMPLITUDE (V) 03732-026 03732-024 03732-025 Data Sheet AD5381 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The complete transfer function for these devices can be represented as The AD5381 is a complete, single-supply, 40-channel voltage output DAC that offers 12-bit resolution. The part is available n VOUT = 2 × VREF × x2/2 in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software where: selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used x2 is the data-word loaded to the resistor string DAC. V REF to drive the buffered reference inputs; alternatively, an external is externally applied to the DAC REFOUT/REFIN pin. For reference can be used to drive these inputs. Internal/external specified performance, an external reference voltage of 2.5 V is reference selection is via the CR8 bit in the control register; recommended for the AD5381-5, and 1.25 V for the AD5381-3. CR10 selects the reference magnitude if the internal reference DATA DECODING is selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ in parallel with a The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend- ing on the value of REG1 and REG0 (see Table 11), this data is 200 pF load. loaded into the addressed DAC input registers, offset (c) VREF AVDD registers, or gain (m) registers. The format data, offset (c), and gain (m) register contents are shown in Table 12 to Table 14. ×1 INPUT REG DAC 12-BIT Table 11. Register Selection INPUT DATA m REG ×2 REG DAC VOUT REG1 REG0 Register Selected c REG R 1 1 Input Data Register (x1) 1 0 Offset Register (c) R 0 1 Gain Register (m) 0 0 Special Function Registers (SFRs) Figure 27. Single-Channel Architecture Table 12. DAC Data Format (REG1 = 1, REG0 = 1) The architecture of a single DAC channel consists of a 12-bit DB11 to DB0 DAC Output (V) resistor-string DAC followed by an output buffer amplifier 1111 1111 1111 2 V × (4095/4096) operating at a gain of 2. This resistor-string architecture REF 1111 1111 1110 2 V × (4094/4096) guarantees DAC monotonicity. The 12-bit binary digital code REF loaded to the DAC register determines at what node on the 1000 0000 0001 2 VREF × (2049/4096) string the voltage is tapped off before being fed to the output 1000 0000 0000 2 VREF × (2048/4096) 0111 1111 1111 2 VREF × (2047/4096) amplifier. Each channel on these devices contains independent 0000 0000 0001 2 V × (1/4096) offset and gain control registers that allow the user to digitally REF 0000 0000 0000 0 trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain, including the Table 13. Offset Data Format (REG1 = 1, REG0 = 0) DAC, using the internal m and c registers, which hold the DB11 to DB0 Offset (LSB) correction factors. All channels are double buffered, allow- 1111 1111 1111 +2048 ing synchronous updating of all channels using the pin. LDAC 1111 1111 1110 +2047 Figure 27 shows a block diagram of a single channel on the 1000 0000 0001 +1 AD5381. The digital input transfer function for each DAC 1000 0000 0000 0 can be represented as 0111 1111 1111 –1 n n – 1 0000 0000 0001 –2047 x2 = [(m + 2)/ 2 × x1] + (c – 2 ) 0000 0000 0000 –2048 where: Table 14. Gain Data Format (REG1 = 0, REG0 = 1) x2 = the data-word loaded to the resistor string DAC. DB11 to DB0 Gain Factor x1 = the 12-bit data-word written to the DAC input register. 1111 1111 1110 1 m = the gain coefficient (default is 0xFFE). The gain coefficient 1011 1111 1110 0.75 is written to the 11 most significant bits (DB11 to DB1), the LSB 0111 1111 1110 0.5 (DB0) of the data-word is a 0. 0011 1111 1110 0.25 n = DAC resolution (n = 12 for AD5381). 0000 0000 0000 0 c = the12-bit offset coefficient (default is 0x800). Rev. C | Page 21 of 40 03732-027 AD5381 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5381 contains a number of special function registers REG1 = REG0 = 0, A5 to A0 = 000010 (SFRs), as outlined in Table 15. SFRs are addressed with DB11 to DB0 = Don’t Care REG1 = REG0 = 0 and are decoded using Address Bits Executing this instruction performs the CLR, which is func- A5 to A0. tionally the same as that provided by the external pin. The CLR Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) DAC outputs are loaded with the data in the CLR code register. R/W A5 A4 A3 A2 A1 A0 Function It takes 35 µs to fully execute the SOFT CLR, as indicated by the low time. X 0 0 0 0 0 0 NOP (No Operation) BUSY 0 0 0 0 0 0 1 Write CLR Code Soft Power-Down 0 0 0 0 0 1 0 Soft CLR 0 0 0 1 0 0 0 Soft Power-Down REG1 = REG0 = 0, A5 to A0 = 001000 0 0 0 1 0 0 1 Soft Power-Up DB11 to DB0 = Don’t Care 0 0 0 1 1 0 0 Control Register Write Executing this instruction performs a global power-down 1 0 0 1 1 0 0 Control Register Read feature that puts all channels into a low power mode that 0 0 0 1 0 1 0 Monitor Channel reduces the analog supply current to 2 µA max and the digi- 0 0 0 1 1 1 1 Soft Reset tal current to 20 µA max. In power-down mode, the output SFR COMMANDS amplifier can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal NOP (No Operation) registers are retained in power-down mode. No register can be REG1 = REG0 = 0, A5 to A0 = 000000 written to while in power-down. Performs no operation but is useful in serial readback mode to Soft Power-Up clock out data on D for diagnostic purposes. pulses OUT BUSY REG1 = REG0 = 0, A5 to A0 = 001001 low during a NOP operation. DB11 to DB0 = Don’t Care Write CLR Code This instruction is used to power up the output amplifiers and the internal reference. The time to exit power-down is 8 µs. REG1 = REG0 = 0, A5 to A0 = 000001 The hardware power-down and software function are internally DB11 to DB0 = Contain the CLR data combined in a digital OR function. Bringing the CLR line low or exercising the soft clear function Soft RESET will load the contents of the DAC registers with the data con- REG1 = REG0 = 0, A5 to A0 = 001111 tained in the user configurable CLR register, and will set DB11 to DB0 = Don’t Care VOUT0 to VOUT39 accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also This instruction is used to implement a software reset. All beneficial for calibration purposes; the user can load full scale internal registers are reset to their default values, which corre- or zero scale to the clear code register and then issue a hard- spond to m at full scale and c at zero scale. The contents of the ware or software clear to load this code to all DACs, removing DAC registers are cleared, setting all analog outputs to 0 V. The the need for individual writes to each DAC. Default on power- soft reset activation time is 135 µs. up is all zeros. Rev. C | Page 22 of 40 Data Sheet AD5381 Table 16. Control Register Contents MSB LSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Control Register Write/Read REG1 = REG0 = 0, A5 to A0 = 001100, R/ status determines CR7 = 0: Monitor Disabled (default on power-up). When the W monitor is disabled, the MON_OUT pin assumes its normal if the operation is a write (R/W = 0) or a read (R/W = 1). DB11 DAC output function. to DB0 contains the control register data. CR6: Thermal Monitor Function. When enabled, this function Control Register Contents is used to monitor the internal die temperature of the AD5381. CR11: Power-Down Status. This bit is used to configure the The thermal monitor powers down the output amplifiers when output amplifier state in power-down. the temperature exceeds 130°C. This function can be used to protect the device in cases where power dissipation may be CR11 = 1. Amplifier output is high impedance (default on exceeded if a number of output channels are simultaneously power-up). short-circuited. A soft power-up will re-enable the output amplifiers if the die temperature has dropped below 130°C. CR11 = 0. Amplifier output is 100 kΩ to ground. CR6 = 1: Thermal Monitor Enabled. CR10: REF Select. This bit selects the operating internal reference for the AD5381. CR10 is programmed as follows: CR6 = 0: Thermal Monitor Disabled (default on power-up). CR10 = 1: Internal reference is 2.5 V (AD5381-5 default), the CR5: Don’t Care. recommended operating reference for AD5381-5. CR4 to CR0: Toggle Function Enable. This function allows the CR10 = 0: Internal reference is 1.25 V (AD5381-3 default), user to toggle the output between two codes loaded to the A the recommended operating reference for AD5381-3. and B registers for each DAC. Control Register Bits CR4 to CR0 are used to enable individual groups of eight channels for CR9: Current Boost Control. This bit is used to boost the operation in toggle mode. A Logic 1 written to any bit enables current in the output amplifier, thereby altering its slew rate. a group of channels; a Logic 0 disables a group. LDAC is used This bit is configured as follows: to toggle between the two registers. CR9 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing Table 17. the power dissipation. CR Bit Group Channels CR4 4 32–39 CR9 = 0: Boost Mode Off (default on power-up). This CR3 3 24–31 reduces the bias current in the output amplifier and reduces CR2 2 16–23 the overall power consumption. CR1 1 8–15 CR0 0 0–7 CR8: Internal/External Reference. This bit determines if the DAC uses its internal reference or an externally applied Channel Monitor Function reference. REG1 = REG0 = 0, A5 to A0 = 001010 CR8 = 1: Internal Reference Enabled. The reference output DB11–DB6 = Contain data to address the monitored channel. depends on data loaded to CR10. A channel monitor function is provided on the AD5381. This CR8 = 0: External Reference Selected (default on power-up). feature, which consists of a multiplexer addressed via the inter- CR7: Channel Monitor Enable (see Channel Monitor Function face, allows any channel output to be routed to the MON_OUT section). pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all CR7= 1: Monitor Enabled. This enables the channel monitor monitored pins are routed. The channel monitor function must function. After a write to the monitor channel in the SFR be enabled in the control register before any channels are routed register, the selected channel output is routed to the to MON_OUT. On the AD5381, DB11 to DB6 contain the MON_OUT pin. VOUT39 operates at the MON_OUT pin. channel address for the monitored channel. Selecting Channel Address 63 three-states MON_OUT. Rev. C | Page 23 of 40 AD5381 Data Sheet Table 18. AD5381 Channel Monitor Decoding REG1 REG0 A5 A4 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB8 DB6 DB5–DB0 MON_OUT 0 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2 0 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3 0 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4 0 0 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT5 0 0 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT6 0 0 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT7 0 0 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT8 0 0 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT9 0 0 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT10 0 0 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT11 0 0 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT12 0 0 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT13 0 0 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT14 0 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15 0 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16 0 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17 0 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18 0 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19 0 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20 0 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21 0 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22 0 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23 0 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24 0 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25 0 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26 0 0 0 0 1 0 1 0 0 1 1 0 1 1 X VOUT27 0 0 0 0 1 0 1 0 0 1 1 1 0 0 X VOUT28 0 0 0 0 1 0 1 0 0 1 1 1 0 1 X VOUT29 0 0 0 0 1 0 1 0 0 1 1 1 1 0 X VOUT30 0 0 0 0 1 0 1 0 0 1 1 1 1 1 X VOUT31 0 0 0 0 1 0 1 0 1 0 0 0 0 0 X VOUT32 0 0 0 0 1 0 1 0 1 0 0 0 0 1 X VOUT33 0 0 0 0 1 0 1 0 1 0 0 0 1 0 X VOUT34 0 0 0 0 1 0 1 0 1 0 0 0 1 1 X VOUT35 0 0 0 0 1 0 1 0 1 0 0 1 0 0 X VOUT36 0 0 0 0 1 0 1 0 1 0 0 1 0 1 X VOUT37 0 0 0 0 1 0 1 0 1 0 0 1 1 0 X VOUT38 0 0 0 0 1 0 1 0 1 0 0 1 1 1 X Undefined • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State REG1 REG0A5 A4 A3 A2 A1 A0 0 0 0 0 1 0 1 0 VOUT0 VOUT1 AD5381 CHANNEL MONITOR VOUT39/MON_OUT DECODING VOUT37 VOUT38 CHANNEL ADDRESS DB11–DB6 Figure 28. Channel Monitor Decoding Rev. C | Page 24 of 40 03732-028 Data Sheet AD5381 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the line low resets the contents of all internal The AD5381 contains a FIFO to optimize operation when RESET operating in parallel interface mode. The FIFO Enable (level registers to their power-on reset state. Reset is a negative edge- sensitive, active high) is used to enable the internal FIFO. When sensitive input. The default corresponds to m at full-scale and connected to DVDD, the internal FIFO is enabled, allowing the to c at zero scale. The contents of the DAC registers are cleared, user to write to the device at full speed. FIFO is only available in setting VOUT0 to VOUT39 to 0 V. This sequence takes 270 µs. parallel interface mode. The status of the FIFO EN pin is sam- The falling edge of initiates the reset process; goes RESET BUSY pled on power-up, and after a CLR or RESET, to determine if low for the duration, returning high when RESET is complete. 2 the FIFO is enabled. In either serial or I C interface modes, While is low, all interfaces are disabled and all LDAC BUSY FIFO EN should be tied low. Up to 128 successive instructions pulses are ignored. When BUSY returns high, the part resumes can be written to the FIFO at maximum speed in parallel mode. normal operation and the status of the pin is ignored RESET When the FIFO is full, any further writes to the device are until the next falling edge is detected. ignored. Figure 29 shows a comparison between FIFO mode and non-FIFO mode in terms of channel update time. Figure 29 ASYNCHRONOUS CLEAR FUNCTION also outlines digital loading time. Bringing the line low clears the contents of the DAC CLR 25 registers to the data contained in the user configurable CLR register and sets VOUT0 to VOUT39 accordingly. This func- WITHOUT FIFO tion can be used in system calibration to load zero-scale and 20 (CHANNEL UPDATE TIME) full-scale to all channels. The execution time for a CLR is 35 µs. 15 AND FUNCTIONS BUSY LDAC BUSY is a digital CMOS output that indicates the status of the 10 AD5381. The value of x2, the internal data loaded to the DAC WITH FIFO (CHANNEL UPDATE TIME) data register, is calculated each time the user writes new data to 5 the corresponding x1, c, or m registers. During the calculation WITH FIFO of x2, the BUSY output goes low. While BUSY is low, the user (DIGITAL LOADING TIME) can continue writing new data to the x1, m, or c registers, but 0 1 4 7 10 13 16 19 22 25 28 31 34 37 40 no DAC output updates can take place. The DAC outputs are NUMBER OF WRITES updated by taking the input low. If goes low while LDAC LDAC Figure 29. Channel Update Rate (FIFO vs. NON-FIFO) is active, the event is stored and the DAC outputs BUSY LDAC update immediately after goes high. The user may hold BUSY POWER-ON RESET the input permanently low, in which case the DAC LDAC The AD5381 contains a power-on reset generator and state outputs update immediately after goes high. BUSY BUSY machine. The power-on reset resets all registers to a predefined also goes low during power-on reset and when a falling edge is state and configures the analog outputs as high impedance. The detected on the pin. During this time, all interfaces are RESET BUSY pin goes low during the power-on reset sequencing, pre- are ignored. disabled and any events on LDAC venting data writes to the device. The AD5381 contains an extra feature whereby a DAC register POWER-DOWN is not updated unless its x2 register has been written to since The AD5381 contains a global power-down feature that puts all the last time was brought low. Normally, when LDAC LDAC channels into a low power mode and reduces the analog power is brought low, the DAC registers are filled with the contents consumption to 2 µA max and digital power consumption to of the x2 registers. However, the AD5381 will only update the 20 µA max. In power-down mode, the output amplifier can be DAC register if the x2 data has changed, thereby removing configured as a high impedance output or can provide a 100 kΩ unnecessary digital crosstalk. load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values. Rev. C | Page 25 of 40 TIME (µs) 03732-029 AD5381 Data Sheet INTERFACES The AD5381 contains both parallel and serial interfaces. Figure 3 and Figure 5 show timing diagrams for a serial write Furthermore, the serial interface can be programmed to be to the AD5381 in standalone and daisy-chain modes. The 24-bit 2 either SPI-, DSP-, MICROWIRE-, or I C-compatible. The data-word format for the serial interface is shown in Table 19. SER/ pin selects parallel and serial interface modes. In PAR A/B This pin selects whether the data write is to the A or B 2 serial mode, the /I C pin is used to select DSP-, SPI-, SPI register when toggle mode is enabled. With toggle disabled, this 2 MICROWIRE-, or I C-interface mode. bit should be set to 0 to select the A data register. The devices use an internal FIFO memory to allow high speed R/W is the read or write control bit. successive writes in parallel interface mode. The user can con- tinue writing new data to the device while write instructions are A5 to A0 are used to address the input channels. being executed. The signal indicates the current status of BUSY REG1 and REG0 select the register to which data is written, the device, going low while instructions in the FIFO are being as shown in Table 11. executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO DB11 to .DB0 contain the input data-word. is full, any further writes to the device are ignored. X is a don’t care condition. To minimize both the power consumption of the device and the Standalone Mode on-chip digital noise, the active interface only powers up fully when the device is being written to, that is, on the falling edge By connecting the DCEN (daisy-chain enable) pin low, stand- of WR or the falling edge of SYNC. alone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL edge of SYNC starts the write cycle and resets a counter that INTERFACES counts the number of serial clocks to ensure the correct number The serial interface can be operated with a minimum of three of bits are shifted into the serial shift register. Any further edges wires in standalone mode or four wires in daisy-chain mode. on , except for a falling edge, are ignored until 24 bits are SYNC Daisy chaining allows many devices to be cascaded together to clocked in. Once 24 bits are shifted in, the SCLK is ignored. In increase system channel count. The SER/ pin must be tied PAR order for another serial transfer to take place, the counter must 2 high and the /I C pin (Pin 97) should be tied low to enable SPI be reset by the falling edge of . SYNC the DSP-/SPI-/MICROWIRE-compatible serial interface. In serial interface mode, the user does not need to drive the paral- lel input data pins. The serial interface’s control pins are , DIN, SCLK—Standard 3-wire interface pins. SYNC DCEN—Selects standalone mode or daisy-chain mode. SDO—Data out pin for Daisy-chain mode. Table 19. 40-Channel, 12-bit DAC Serial Input Register Configuration MSB LSB A W A5 A4 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X /B R/ Rev. C | Page 26 of 40 Data Sheet AD5381 Daisy-Chain Mode Readback Mode Readback mode is invoked by setting the R/ bit = 1 in the For systems that contain several devices, the SDO pin can be W used to daisy-chain several devices together. This daisy-chain serial input register write. With R/ = 1, Bits A5 to A0, in W mode can be useful in system diagnostics and in reducing the association with Bits REG1 and REG0, select the register to be number of serial interface lines. read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the By connecting the DCEN (daisy-chain enable) pin high, daisy- SDO output will contain the data from the previously chain mode is enabled. The first falling edge of starts the SYNC addressed register. write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are For a read of a single register, the NOP command can be used applied, the data ripples out of the shift register and appears in clocking out the data from the selected register on SDO. on the SDO line. This data is clocked out on the rising edge of Figure 30 shows the readback sequence. For example, to read SCLK and is valid on the falling edge. By connecting the SDO back the m register of Channel 0 on the AD5381, the following of the first device to the DIN input on the next device in the sequence should be implemented. First, write 0x404XXX to the chain, a multidevice interface is constructed. Twenty-four clock AD5381 input register. This configures the AD5381 for read pulses are required for each device in the system. Therefore, the mode with the m register of Channel 0 selected. Note that Data total number of clock cycles must equal 24N, where N is the Bits DB11 to DB0 are don’t cares. Follow this with a second total number of AD538x devices in the chain. write, a NOP condition, 0x000000. When the serial transfer to all devices is complete, is During this write, the data from the m register is clocked out on SYNC the DOUT line, that is, data clocked out will contain the data taken high. This latches the input data in each device in the from the m register in Bit DB11 to Bit DB0, and the top 10 bits daisy-chain and prevents further data from being clocked contain the address information as previously written. In into the input shift register. readback mode, the SYNC signal must frame the data. Data is If is taken high before 24 clocks are clocked into the part, SYNC clocked out on the rising edge of SCLK and is valid on the this is considered a bad frame and the data is discarded. falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback operation, the first The serial clock can be either a continuous or a gated clock. A bit of data is clocked out on the falling edge of SYNC. continuous SCLK source can only be used if it can be arranged that is held low for the correct number of clock cycles. In SYNC gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23 DB0 DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 30. Serial Readback Operation Rev. C | Page 27 of 40 03732-030 AD5381 Data Sheet 2 I C SERIAL INTERFACE 2 AD5381 Slave Addresses The AD5381 features an I C-compatible 2-wire interface A bus master initiates communication with a slave device by consisting of a serial data line (SDA) and a serial clock line issuing a START condition followed by the 7-bit slave address. (SCL). SDA and SCL facilitate communication between the When idle, the AD5381 waits for a START condition followed AD5381 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three by its slave address. The LSB of the address word is the Read/ 2 different modes of operation. In selecting the I C operating Write (R/W) bit. The AD5381 is a receive only device; when = 1) mode, first configure serial operating mode (SER/PAR communicating with the AD5381, R/ = 0. After receiving the W 2 2 and then select I C mode by configuring the /I C pin to a SPI proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK 2 by pulling SDA low for one clock cycle. Logic 1. The device is connected to the I C bus as a slave device (that is, no clock is generated by the AD5381). The AD5381 has The AD5381 has four different user programmable addresses a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSB are hard- determined by the AD1 and AD0 bits. coded and the 2 LSB are determined by the state of the AD1 Write Operation and AD0 pins. The facility to hardware configure AD1 and AD0 allows four of these devices to be configured on the bus. There are three specific modes in which data can be written to 2 the AD5381 DAC. I C Data Transfer One data bit is transferred during each SCL clock cycle. The 4-Byte Mode data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control When writing to the AD5381 DACs, the user must begin signals that configure START and STOP conditions. Both SDA with an address byte (R/ = 0) after which the DAC acknowl- W and SCL are pulled high by the external pull-up resistors when edges that it is prepared to receive data by pulling SDA low. 2 the I C bus is not busy. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also START and STOP Conditions acknowledged by the DAC. Two bytes of data are then written A master device initiates communication by issuing a START to the DAC, as shown in Figure 31. A STOP condition follows. condition. A START condition is a high-to-low transition on This allows the user to update a single channel within the SDA with SCL high. A STOP condition is a low-to-high AD5381 at any time and requires four bytes of data to be transition on SDA while SCL is high. A START condition transferred from the master. from the master signals the beginning of a transmission to the AD5381. The STOP condition frees the bus. If a repeated 3-Byte Mode START condition (Sr) is generated instead of a STOP condition, the bus remains active. In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte Repeated START Conditions each time. The device address byte is only required once; sub- A repeated START (Sr) condition may indicate a change of data sequent channel updates require the pointer byte and the data direction on the bus. Sr can be used when the bus master is bytes. In 3-byte mode, the user begins with an address byte 2 writing to several I C devices and wants to maintain control of (R/ = 0), after which the DAC will acknowledge that it is pre- W the bus. pared to receive data by pulling SDA low. The address byte is Acknowledge Bit (ACK) followed by the pointer byte. This addresses the specific channel The acknowledge bit (ACK) is the ninth bit attached to any in the DAC to be addressed and is also acknowledged by the 8-bit data-word. ACK is always generated by the receiving DAC. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated. device. The AD5381 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock If a STOP condition does not follow the data bytes, another period. Monitoring ACK allows for detection of unsuccess- channel can be updated by sending a new pointer byte followed ful data transfers. An unsuccessful data transfer occurs if a by the data bytes. This mode only requires three bytes to be receiving device is busy or if a system fault has occurred. sent to update any channel once the device has been initially In the event of an unsuccessful data transfer, the bus master addressed, and reduces the software overhead in updating the should reattempt communication. AD5381 channels. A STOP condition at any time exits this mode. Figure 32 shows a typical configuration. Rev. C | Page 28 of 40 Data Sheet AD5381 SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP AD538x AD538x COND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE BY MASTER 2 Figure 31. 4-Byte AD5381, I C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 A5 A4 A3 A2 A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP COND AD538x AD538x BY MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" 2 Figure 32. 3-Byte AD5381, I C Write Operation Rev. C | Page 29 of 40 03732-031 AD5381 Data Sheet 2-Byte Mode PARALLEL INTERFACE Following initialization of 2-byte mode, the user can update The SER/PAR pin must be tied low to enable the parallel channels sequentially. The device address byte is only required interface and disable the serial interfaces. Figure 7 shows the once and the pointer address pointer is configured for auto- timing diagram for a parallel write. The parallel interface is increment or burst mode. controlled by the following pins. The user must begin with an address byte (R/W = 0), after CS Pin which the DAC acknowledges that it is prepared to receive Active low device select pin. data by pulling SDA low. The address byte is followed by a WR Pin specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0, the data On the rising edge of , with low, the addresses on Pin A5 WR CS following the pointer is loaded to Channel 0, and the address to Pin A0 are latched; data present on the data bus is loaded into pointer automatically increments to the next address. the selected input registers. REG0, REG1 Pins The REG0 and REG1 bits in the data byte determine which register will be updated. In this mode, following the initializa- The REG0 and REG1 pins determine the destination register of tion, only the two data bytes are required to update a channel. the data being written to the AD5381. See Table 11. The channel address automatically increments from Address 0 Pin A5 to Pin A0 to Channel 39 and then returns to the normal 3-byte mode of Each of the 40 DAC channels can be individually addressed. operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in Pin DB11 to Pin DB0 configuring all channels. A STOP condition at any time exits The AD5381 accepts a straight 12-bit parallel word on DB11 to this mode. Toggle mode is not supported in 2-byte mode. DB0, where DB11 is the MSB and DB0 is the LSB. Figure 33 shows a typical configuration. SCL SDA 1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND ACK BY MSB ACK BY BY MASTER CONVERTER CONVERTER ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY CONVERTER CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP CONVERTER CONVERTER COND MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 33. 2-Byte, 1 C Write Operation Rev. C | Page 30 of 40 03732-033 Data Sheet AD5381 MICROPROCESSOR INTERFACING Parallel Interface When data is being transmitted to the AD5381, the SYNC line The AD5381 can be interfaced to a variety of 16-bit microcon- is taken low (PC7). Data appearing on the MOSI output is valid trollers or DSP processors. Figure 35 shows the AD5381 family on the falling edge of SCK. Serial data from the MC68HC11 is interfaced to a generic 16-bit microcontroller/DSP processor. transmitted in 8-bit bytes with only eight falling clock edges The lower address lines from the processor are connected to A0 occurring in the transmit cycle. to A5 on the AD5381. The upper address lines are decoded to DVDD MC68HC11 AD5381 provide a CS, LDAC signal for the AD5381. The fast interface SER/PAR timing of the AD5381 allows direct interface to a wide variety RESET of microcontrollers and DSPs, as shown in Figure 35. MISO SDO MOSI DIN AD5381 to MC68HC11 SCK SCLK PC7 SYNC The serial peripheral interface (SPI) on the MC68HC11 is 2 SPI/I C configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see Figure 34. AD5381-to-MC68HC11 Interface the MC68HC11 user manual. SCK of the MC68HC11 drives the SCLK of the AD5381, the MOSI output drives the serial data line (DIN) of the AD5381, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). µCONTROLLER/ AD5381 1 DSP PROCESSOR D15 REG1 REG0 D11 DATA BUS D0 D0 CS UPPER BITS OF ADDRESS ADDRESS BUS DECODE LDAC A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 R/W WR 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5381-to-Parallel Interface Rev. C | Page 31 of 40 03732-035 03731-034 AD5381 Data Sheet DVDD AD5381 to PIC16C6x/7x 8XC51 AD5381 SER/PAR The PIC16C6x/7x synchronous serial port (SSP) is configured RESET as an SPI master with the Clock Polarity Bit = 0. This is done by writing to the synchronous serial port control register RxD SDO DIN (SSPCON). See the PIC16/17 microcontroller user manual. TxD SCLK In this example I/O, Port RA1 is being used to pulse SYNC P1.1 SYNC 2 and enable the serial port of the AD5381. This microcontroller SPI/I C transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations Figure 37. AD5381-to-8051 Interface may be needed depending on the mode. Figure 36 shows the connection diagram. AD5381 to ADSP-2101/ADSP-2103 DVDD PIC16C6X/7X Figure 38 shows a serial interface between the AD5381 and the AD5381 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR RESET be set up to operate in SPORT transmit alternate framing mode. SDI/RC4 SDO The ADSP-2101/ADSP-2103 SPORT is programmed through SDO/RC5 DIN the SPORT control register and configured as follows: internal SCK/RC3 SCLK RA1 SYNC clock operation, active low framing, and 16-bit word length. 2 SPI/I C Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Figure 36. AD5381-to-PIC16C6x/7x Interface DVDD ADSP-2101/ AD5381 ADSP-2103 SER/PAR AD5381 to 8051 RESET The AD5381 requires a clock synchronized to the serial data. DR SDO DT DIN The 8051 serial interface must therefore be operated in Mode 0. SCK SCLK In this mode, serial data enters and exits through RxD, and a TFS SYNC shift clock is output on TxD. Figure 37 shows how the 8051 is RFS 2 SPI/I C connected to the AD5381. Because the AD5381 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5381 Figure 38. AD5381-to-ADSP-2101/ADSP-2103 Interface requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. Rev. C | Page 32 of 40 03732-036 03732-038 03732-037 Data Sheet AD5381 APPLICATION INFORMATION externally from either an ADR421 or ADR431 2.5 V reference. POWER SUPPLY DECOUPLING Suitable external references for the AD5381-3 include the In any circuit where accuracy is important, careful considera- ADR280 1.2 V reference. The reference should be decoupled at tion of the power supply and ground return layout helps to the REFOUT/REFIN pin of the device with a 0.1 µF capacitor. ensure the rated performance. The printed circuit board on AVDD DVDD which the AD5381 is mounted should be designed so that the 0.1µF analog and digital sections are separated and confined to certain areas of the board. If the AD5381 is in a system where 10µF 0.1µF ADR431/ multiple devices require an AGND-to-DGND connection, the ADR421 connection should be made at one point only, a star ground point established as close to the device as possible. AVDD DVDD REFOUT/REFIN VOUT0 For supplies with multiple pins (AVDD, DVDD), these pins 0.1µF should be tied together. The AD5381 should have ample supply AD5381-5 REFGND bypassing of 10 µF in parallel with 0.1 µF on each supply, VOUT39 located as close to the package as possible and ideally right up against the device. The 10 µF capacitors are the tantalum DAC_GND SIGNAL_GND AGND DGND bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to Figure 39. Typical Configuration with External Reference ground at high frequencies, to handle transient currents due to Figure 40 shows a typical configuration when using the internal internal logic switching. reference. On power-up, the AD5381 defaults to an external The power supply lines of the AD5381 should use as large a reference; therefore, the internal reference needs to be config- trace as possible to provide low impedance paths and reduce ured and turned on via a write to the AD5381 control register. the effects of glitches on the power supply line. Fast switching Control Register Bit CR10 allows the user to choose the signals such as clocks should be shielded with digital ground reference value; Bit CR8 is used to select the internal reference. to avoid radiating noise to other parts of the board, and should It is recommended to use the 2.5 V reference when AVDD = never be run near the reference inputs. A ground line routed 5 V, and the 1.25 V reference when AVDD= 3 V. between the D and SCLK lines will help reduce crosstalk IN AVDD DVDD between them (this is not required on a multilayer board 0.1µF because there will be a separate ground plane, but separat- ing the lines will help). It is essential to minimize noise on 10µF 0.1µF the REFOUT/REFIN line. Avoid crossover of digital and analog signals. Traces on AVDD DVDD opposite sides of the board should run at right angles to REFOUT/REFIN VOUT0 each other. This reduces the effects of feedthrough through 0.1µF the board. A micro-strip technique is by far the best, but is AD5381 REFGND not always possible with a double-sided board. In this tech- VOUT39 nique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. DAC_GND SIGNAL_GND AGND DGND TYPICAL CONFIGURATION CIRCUIT Figure 39 shows a typical configuration for the AD5381-5 Figure 40. Typical Configuration with Internal Reference when configured for use with an external reference. In the Digital connections have been omitted for clarity. The AD5381 circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins contains an internal power-on reset circuit with a 10 ms brown- are tied together to a common AGND. AGND and DGND are out time. If the power supply ramp rate exceeds 10 ms, the user connected together at the AD5381 device. On power-up, the should reset the AD5381 as part of the initialization process to AD5381 defaults to external reference operation. All AVDD ensure the calibration data is loaded correctly into the device. lines are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this application, the reference for the AD5381-5 is provided Rev. C | Page 33 of 40 03732-040 03732-039 AD5381 Data Sheet Note that B registers can only be loaded when toggle mode is MONITOR FUNCTION enabled. The sequence of events when configuring the AD5381 The AD5381 channel monitor function consists of a multiplexer for toggle mode is addressed via the interface, allowing any channel output to be 1. Enable toggle mode for the required channels via the routed to this pin for monitoring using an external ADC. In control register. channel monitor mode, VOUT39 becomes the MON_OUT pin, 2. Load data to the A registers. to which all monitored signals are routed. The channel monitor 3. Load data to the B registers. function must be enabled in the control register before any 4. Apply . LDAC channels are routed to MON_OUT. Table 18 contains the decoding information required to route any channel to is used to switch between the A and B registers in LDAC MON_OUT. Selecting Channel Address 63 three-states determining the analog output. The first configures the LDAC MON_OUT. Figure 41 shows a typical monitoring circuit output to reflect data in the A registers. This mode offers signif- implemented using a 12-bit SAR ADC in a 6-lead SOT-23 icant advantages if the user wants to generate a square wave at package. The controller output port selects the channel to be the output of all 40 channels, as might be required to drive a monitored, and the input port reads the converted data from liquid crystal-based variable optical attenuator. the ADC. In this case, the user writes to the control register and enables the toggle function by setting CR4 to CR2 = 0, thus enabling the five groups of eight for toggle mode operation. The user must AVDD then load data to all 40 A and B registers. Toggling sets LDAC DIN VOUT0 SYNC OUTPUT PORT the output values to reflect the data in the A and B registers. SCLK The frequency of the determines the frequency of the LDAC VDD AD5381 square wave output. AD7476 CS VOUT39/MON_OUT VIN SCLK INPUT PORT Toggle mode is disabled via the control register. The first LDAC SDATA following the disabling of the toggle mode will update the out- GND puts with the data contained in the A registers. CONTROLLER AGND VOUT38 THERMAL MONITOR FUNCTION DAC_GND SIGNAL_GND The AD5381 contains a temperature shutdown function to protect the chip if multiple outputs are shorted. The short- circuit current of each output amplifier is typically 40 mA. Figure 41. Typical Channel Monitoring Circuit Operating the AD5381 at 5 V leads to a power dissipation of TOGGLE MODE FUNCTION 200 mW per shorted amplifier. With five channels shorted, this The toggle mode function allows an output signal to be gener- leads to an extra watt of power dissipation. For the 100-lead ated using the control signal that switches between two LDAC LQFP, the θJA is typically 44°C/W. DAC data registers. This function is configured using the SFR The thermal monitor is enabled by the user via CR6 in the control register as follows. A write with REG1 = REG0 = 0 and control register. The output amplifiers on the AD5381 are A5 to A0 = 001100 specifies a control register write. The toggle automatically powered down if the die temperature exceeds mode function is enabled in groups of eight channels using Bit approximately 130°C. After a thermal shutdown has occurred, CR4 to Bit CR0 in the control register. See the AD5381 control the user can re-enable the part by executing a soft power-up if register description. Figure 42 shows a block diagram of toggle the temperature has dropped below 130°C or by turning off the mode implementation. Each of the 40 DAC channels on the thermal monitor function via the control register. AD5381 contain an A and B data register. Rev. C | Page 34 of 40 03732-041 Data Sheet AD5381 DATA REGISTER A DAC VOUT 12-BIT DAC REGISTER DATA INPUT INPUT REGISTER DATA REGISTER B LDAC A/B CONTROL INPUT Figure 42. Toggle Mode Function UTILIZING FIFO OPTICAL ATTENUATORS The AD5381 FIFO mode optimizes total system update rates Based on its high channel count, high resolution, monotonic in applications where a large number of channels need to be behavior, and high level of integration, the AD5381 is ideally updated. FIFO mode is only available when parallel interface targeted at optical attenuation applications used in dynamic mode is selected. The FIFO EN pin is used to enable the FIFO. gain equalizers, variable optical attenuators (VOAs), and optical The status of FIFO EN is sampled during the initialization add-drop multiplexers (OADMs). In these applications, each sequence. Therefore, the FIFO status can only be changed by wavelength is individually extracted using an arrayed wave resetting the device. guide; its power is monitored using a photodiode, transimped- ance amplifier and ADC in a closed-loop control system. The In a telescope that provides for the cancel-lation of atmospheric AD5381 controls the optical attenuator for each wavelength, distortion, for example, a large number of channels need to be ensuring that the power is equalized in all wavelengths before updated in a short period of time. In such systems, as many as being multiplexed onto the fiber. This prevents information loss 400 channels need to be updated within 40 µs. Four-hundred and saturation from occurring at amplification stages further channels require the use of 10 AD5381s. With FIFO mode along the fiber. enabled, the data write cycle time is 40 ns; therefore, each group consisting of 40 channels can be fully loaded in 1.6 µs. In FIFO mode, a complete group of 40 chan-nels will update in 14.4 µs. The time taken to update all 400 channels is 14.4 µs + 9 × 1.6 µs = 28.8 µs. Figure 44 shows the FIFO operation scheme. ADD DROP PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM DWDM ATTENUATOR IN OUT FIBRE AWG FIBRE AWG 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) ADG731 N:1 MULTIPLEXER (40:1 MUX) AD5381, 40-CHANNEL, 12-BIT DAC AD7671 CONTROLLER 16-BIT ADC (0V TO 5V, 1MSPS) Figure 43. OADM Using the AD5381 as Part of an Optical Attenuator Rev. C | Page 35 of 40 03732-043 03732-042 AD5381 Data Sheet GROUP A GROUP B GROUP C GROUP D GROUP E GROUP F GROUP G GROUP H GROUP I GROUP J CHNLS 0–39 CHNLS 40–79 CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS 80–119 120–159 160–199 200–239 240–279 280–319 320–359 360–399 FIFO DATA LOAD GROUP A FIFO DATA LOAD FIFO DATA LOAD 1.6µs 1.6µs 1.6µs GROUP B GROUP J OUTPUT UPDATE OUTPUT UPDATE 14.4µs 14.4µs TIME FOR GROUP A TIME FOR GROUP J OUTPUT UPDATE 14.4µs TIME FOR GROUP B TIME TO UPDATE 400 CHANNELS = 28.8µs Figure 44. Using FIFO Mode 400 Channels Updated in Under 30 µs Rev. C | Page 36 of 40 03732-044 Data Sheet AD5381 OUTLINE DIMENSIONS 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 76 1 75 0.60 0.45 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 25 51 0.15 0° 26 50 SEATING 0.08 0.05 PLANE COPLANARITY 0.27 VIEW A 0.50 0.22 BSC VIEW A 0.17 LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 45. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1) Dimensions shown in millimeters ORDERING GUIDE Temperature Output Linearity Package Package 1 Model Resolution Range AVDD Range Channels Error (LSB) Description Option AD5381BSTZ-3 12 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100-1 AD5381BSTZ-3-REEL 12 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100-1 AD5381BSTZ-5 12 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100-1 AD5381BSTZ-5-REEL 12 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100-1 EVAL-AD5380EBZ Evaluation Kit 1 Z = RoHS Compliant Part. Rev. C | Page 37 of 40 051706-A AD5381 Data Sheet NOTES Rev. C | Page 38 of 40 Data Sheet AD5381 NOTES Rev. C | Page 39 of 40 AD5381 Data Sheet NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03732-0-5/12(C) Rev. C | Page 40 of 40