ANALOG DEVICES AD5380

40-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC Data Sheet AD5380 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±4 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User programmable offset and gain adjust Power down Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm × 14 mm) Thermal monitor User interfaces: Parallel APPLICATIONS Serial (SPI®-, QSPI™-, MICROWIRE™-, DSP-compatible, Variable optical attenuators (VOA) featuring data readback) Level setting (ATE) 2 I C®-compatible Optical micro-electro-mechanical systems (MEMS) Robust 6.5 kV HBM and 2 kV FICDM ESD rating Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×3) AVDD (×5) AGND (×5) DAC_GND (×5) REFGND REFOUT/REFIN SIGNAL_GND (×5) PD AD5380 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 14 14 14 14 INPUT DAC SDO DAC 0 REG0 REG0 VOUT DB13/(DIN/SDA) 14 m REG0 DB12/(SCLK/SCL) FIFO 14 2 DB11/(SPI/I C) R c REG0 + DB10 R INTERFACE STATE CONTROL MACHINE 14 14 14 14 INPUT DAC LOGIC + DAC 1 DB0 CONTROL REG1 REG1 VOUT1 LOGIC A5 14 VOUT2 m REG1 A0 14 R c REG1 VOUT3 R REG0 VOUT4 14 14 14 14 INPUT DAC VOUT5 REG1 DAC 6 REG6 REG6 VOUT6 POWER-ON RESET RESET 14 m REG6 BUSY 14 R c REG6 R CLR 14 14 14 14 INPUT DAC VOUT0………VOUT38 DAC 7 REG7 REG7 VOUT7 14 m REG7 VOUT8 39-TO-1 14 c REG7 R MUX R ×5 VOUT38 VOUT39/MON_OUT LDAC Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 03731-001 AD5380 Data Sheet TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function .................................................. 25 Specifications ..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5380-5 Specifications ............................................................. 4 FIFO Operation in Parallel Mode ............................................ 25 AD5380-3 Specifications ............................................................. 6 Power-On Reset .......................................................................... 25 AC Characteristics ........................................................................ 7 Power-Down ............................................................................... 25 Timing Characteristics ..................................................................... 8 AD5380 Interfaces .......................................................................... 26 Serial Interface .............................................................................. 8 DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26 2 2 I C Serial Interface ...................................................................... 10 I C Serial Interface ..................................................................... 28 Parallel Interface ......................................................................... 11 Parallel Interface ......................................................................... 30 Absolute Maximum Ratings .......................................................... 13 Microprocessor Interfacing ....................................................... 31 ESD Caution ................................................................................ 13 Application Information ................................................................ 33 Pin Configuration and Function Descriptions ........................... 14 Power Supply Decoupling ......................................................... 33 Terminology .................................................................................... 17 Typical Configuration Circuit .................................................. 33 Typical Performance Characteristics ........................................... 18 AD5380 Monitor Function ....................................................... 34 Functional Description .................................................................. 21 Toggle Mode Function ............................................................... 34 DAC Architecture—General ..................................................... 21 Thermal Monitor Function ....................................................... 35 Data Decoding ............................................................................ 21 AD5380 in a MEMS Based Optical Switch ............................. 35 On-Chip Special Function Registers (SFR) ............................ 22 Optical Attenuators .................................................................... 36 SFR Commands .......................................................................... 22 Utilizing the AD5380 FIFO ...................................................... 37 Hardware Functions ....................................................................... 25 Outline Dimensions ....................................................................... 38 Reset Function ............................................................................ 25 Ordering Guide .......................................................................... 38 REVISION HISTORY 6/12—Rev. A to Rev. B 6/05—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Specifications ................................................................. 3 Changes to Table 3 ............................................................................ 4 Changes to Terminology ............................................................... 17 Changes to Table 4 ............................................................................ 6 Changes to Table 18 ....................................................................... 24 Changes to Output Voltage Settling Time and Slew Rate Changes to Figure 43 ...................................................................... 35 Parameters, Table 5 ........................................................................... 7 5/04—Revision 0: Initial Version Changes to t and t Parameters, Table 6 ..................................... 8 14 19 Changes to Table 9 .......................................................................... 13 Changes to Figure 10, Figure 11, and Figure 14 ......................... 18 Changes to Figure 16, Figure 17, Figure 18, Figure 20 .............. 19 Update Outline Dimensions and Changes to Ordering Guide ...... 38 Rev. B | Page 2 of 40 Data Sheet AD5380 GENERAL DESCRIPTION The AD5380 is a complete, single-supply, 40-channel, 14-bit An input register followed by a DAC register provides double DAC available in a 100-lead LQFP package. All 40 channels buffering, allowing the DAC outputs to be updated indepen- have an on-chip output amplifier with rail-to-rail operation. dently or simultaneously using the LDAC input. The AD5380 includes a programmable internal 1.25 V/2.5 V, Each channel has a programmable gain and offset adjust 10 ppm/°C reference, an on-chip channel monitor function that register that allows the user to fully calibrate any DAC chan- multiplexes the analog outputs to a common MON_OUT pin nel. Power consumption is typically 0.25 mA/channel with for external monitoring, and an output amplifier boost mode boost off. that allows optimization of the amplifier slew rate. The AD5380 contains a double-buffered parallel interface that features a Table 1 and Table 2 show other high channel count low voltage, 20 ns WR pulse width, an SPI-, QSPI-, -MICROWIRE, -DSP single supply and bipolar, dual supply, voltage output DACs compatible serial interface with interface speeds in excess in product portfolio. 2 of 30 MHz, and an I C-compatible interface that supports a 400 kHz data transfer rate. Table 1. Other High Channel Count, Low Voltage, Single Supply DACs in Portfolio Output Model Resolution AVDD Range Channels Linearity Error (LSB) Package Description Package Option AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64 Table 2. 40-Channel, Bipolar Voltage Output DAC Model Resolution Analog Supplies Output Linearity Error (LSB) Package Package Option Channels AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108 AD5378ABC 14 Bits ±11.4 V to ±16.5 V 32 ±3 108-Lead CSPBGA BC-108 Rev. B | Page 3 of 40 AD5380 Data Sheet SPECIFICATIONS AD5380-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications T to T , MIN MAX unless otherwise noted. Table 3. 1 Parameter AD5380-5 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy (INL) ±4 LSB max ±1 LSB typical Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic by design over temperature. Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at code 32 in the linear region. Offset Error TC ±5 µV/°C typ Gain Error ±0.05 % FSR max At 25°C ±0.06 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 1 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 µA max Typically ±30 nA Reference Range 1 to V /2 V min/max DD 4 Reference Output Enabled via CR10 in the AD5380 control register. CR12 selects the reference voltage. Output Voltage 2.495/2.505 V min/max At ambient,. CR12 = 1, optimized for 2.5 V operation. 1.22/1.28 V min/max CR12 = 0 3 Reference TC ±10 ppm max Temperature range: +25°C to +85°C ±15 ppm max Temperature range: −40°C to +85°C Output Impedance 800 Ω typ 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability R = ∞ 200 pF max L R = 5 kΩ 1000 pF max L DC Output Impedance 0.6 Ω max MONITOR PIN Output Impedance 1 kΩ typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 5.5 V VIH, Input High Voltage 2 V min VIL, Input Low Voltage DVDD > 3.6 V 0.8 V max DVDD ≤ 3.6 V 0.6 V max Input Current ±10 µA max Total for all pins; T = T to T A MIN MAX Pin Capacitance 10 pF max Rev. B | Page 4 of 40 Data Sheet AD5380 1 Parameter AD5380-5 Unit Test Conditions/Comments 3 LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 × DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 × DVDD V max SMBus compatible at DVDD < 3.6 V I , Input Leakage Current ±1 µA max IN V , Input Hysteresis 0.05 × DVDD V min HYST C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns. 3 LOGIC OUTPUTS ( , SDO) BUSY VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA V , Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA OH High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑVDD –85 dB typ AI 0.375 mA/channel max Outputs unloaded; boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded; boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 20 µA max Typically 100 nA DI (Power-Down) 20 µA max Typically 1 µA DD Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V 1 AD5380-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT= 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5380-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5380 control register; operating the AD5380-5 with a 1.25 V reference will lead to degraded accuracy specifications. Rev. B | Page 5 of 40 AD5380 Data Sheet AD5380-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter AD5380-3 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy (INL) ±4 LSB max Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 64 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.05 % FSR max At 25°C ±0.1 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 1 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max Enabled via CR10 in the AD5380 control register. 4 Reference Output CR12 selects the reference voltage. Output Voltage 1.245/1.255 V min/max At ambient; CR12 = 0; Optimized for 1.25 V operation 2.47/2.53 V min/max CR12 = 1. 3 Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C ±15 ppm/°C max Temperature range: −40°C to +85°C Output Impedance 800 Ω typ 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max DC Output Impedance 0.6 Ω max MONITOR PIN Output Impedance 1 kΩ typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 3.6 V V , Input High Voltage 2 V min IH VIL, Input Low Voltage DVDD > 3.6 V 0.8 V max DVDD ≤ 3.6 V 0.6 V max Input Current ±10 µA max Total for all pins; TA = TMIN to TMAX Pin Capacitance 10 pF max 3 LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 × DVDD V min SMBus-compatible at DVDD < 3.6 V V , Input Low Voltage 0.3 × DVDD V max SMBus-compatible at DVDD < 3.6 V IL IIN, Input Leakage Current ±1 µA max V , Input Hysteresis 0.05 × DVDD V min HYST CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. B | Page 6 of 40 Data Sheet AD5380 1 Parameter AD5380-3 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) V , Output Low Voltage 0.4 V max Sinking 200 µA OL VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑVDD –85 dB typ AIDD 0.375 mA/channel max Outputs unloaded; Boost off; 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded; Boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 20 µA max Typically 100 nA DI (Power-Down) 20 µA max Typically 1 µA DD Power Dissipation 48 mW max Outputs unloaded; Boost off, AVDD = DVDD = 3 V 1 AD5380-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5380-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5380 control register; operating the AD5380-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range. 1 AC CHARACTERISTICS AVDD = 2.7 V to 3.6 V or 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 5. Parameter All Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2 Output Voltage Settling Time 1/4 scale to 3/4 scale change settling to ±1 LSB. 3 µs typ Boost mode off, CR11 = 0 8 µs max Boost mode off, CR11 = 0 2 Slew Rate 1.5 V/µs typ Boost mode off, CR11 = 0 2.5 V/µs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5380 control register. Rev. B | Page 7 of 40 AD5380 Data Sheet TIMING CHARACTERISTICS SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , MIN MAX unless otherwise noted. Table 6. 1, 2, 3 Parameter Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 th t5 13 ns min 24 SCLK falling edge to SYNC falling edge 4 t6 33 ns min Minimum SYNC low time t 10 ns min Minimum SYNC high time 7 t 50 ns min Minimum SYNC high time in readback mode 7A t8 5 ns min Data setup time t9 4.5 ns min Data hold time 4 t10 30 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) 4 t 20 ns min 24th SCLK falling edge to LDAC falling edge 12 t 20 ns min LDAC pulse width low 13 t14 2 µs max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t 8 µs typ DAC output settling time 17 t 20 ns min CLR pulse width low 18 t 40 µs max pulse activation time 19 CLR 5 t20 20 ns max SCLK rising edge to SDO valid 5 t21 5 ns min SCLK falling edge to SYNC rising edge 5 t22 8 ns min SYNC rising edge to SCLK rising edge t 20 ns min SYNC rising edge to LDAC falling edge 23 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC), and are timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. 200µA I OL V (MIN) OR OH TO OUTPUT PIN V (MAX) C OL L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Rev. B | Page 8 of 40 03731-002 Data Sheet AD5380 t 1 24 24 SCLK t 3 t 2 t t 5 4 t 6 SYNC t 7 t t 8 9 DB0 DIN DB23 t 10 t 11 BUSY t t 12 13 t 1 17 LDAC t 14 VOUT1 t 15 t 13 2 LDAC t 17 t 16 VOUT2 t 18 CLR t 19 VOUT 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t 1 SCLK 24 48 t t t 3 2 21 t 7 t 22 t 4 SYNC t t 8 9 DB23 DB0 DB23 DB0 DIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1 t 20 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N t 13 t 23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. B | Page 9 of 40 03731-003 03731-004 03731-005 AD5380 Data Sheet 2 I C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , MIN MAX unless otherwise noted. Table 7. 1, 2 Parameter Limit at T , T Unit Description MIN MAX F 400 kHz max SCL clock frequency SCL t 2.5 µs min SCL cycle time 1 t2 0.6 µs min tHIGH, SCL high time t3 1.3 µs min tLOW, SCL low time t4 0.6 µs min tHD,STA, start/repeated start condition hold time t5 100 ns min tSU,DAT, data setup time 3 t 0.9 µs max t , data hold time 6 HD,DAT 0 µs min t , data hold time HD,DAT t7 0.6 µs min tSU,STA, setup time for repeated start t8 0.6 µs min tSU,STO, stop condition setup time t9 1.3 µs min tBUF, bus free time between a STOP and a START condition t 300 ns max t , rise time of SCL and SDA when receiving 10 R 0 ns min t , rise time of SCL and SDA when receiving (CMOS compatible) R t 300 ns max t , fall time of SDA when transmitting 11 F 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 300 ns max tF, fall time of SCL and SDA when receiving 4 20 + 0.1C ns min t , fall time of SCL and SDA when transmitting b F C 400 pF max Capacitive load for each bus line b 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD. SDA t t t t t 9 3 10 11 4 SCL t t t t t 4 6 2 1 8 t t 5 7 START REPEATED STOP CONDITION START CONDITION CONDITION 2 Figure 6. I C Compatible Serial Interface Timing Diagram Rev. B | Page 10 of 40 03731-006 Data Sheet AD5380 PARALLEL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 8. 1,2,3 Parameter Limit at TMIN, TMAX Unit Description t0 4.5 ns min REG0, REG1, address to WR rising edge setup time t1 4.5 ns min REG0, REG1, address to WR rising edge hold time t 20 ns min CS pulse width low 2 t 20 ns min WR pulse width low 3 t 0 ns min CS to WR falling edge setup time 4 t5 0 ns min WR to CS rising edge hold time t6 4.5 ns min Data to WR rising edge setup time t7 4.5 ns min Data to WR rising edge hold time t 20 ns min WR pulse width high 8 4 t 700 ns min Minimum WR cycle time (single-channel write) 9 t 30 ns max rising edge to falling edge 10 WR BUSY 4 t11 670 ns max BUSY pulse width low (single-channel update) t12 30 ns min WR rising edge to LDAC falling edge t13 20 ns min LDAC pulse width low t 100 ns max BUSY rising edge to DAC output response time 14 t 20 ns min LDAC rising edge to WR rising edge 15 t 0 ns min rising edge to falling edge 16 BUSY LDAC t17 100 ns min LDAC falling edge to DAC output response time t18 8 µs typ DAC output settling time t19 20 ns min CLR pulse width low t 35 µsmax CLR pulse activation time 20 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. R R 3 See Figure 7. 4 See Figure 29. Rev. B | Page 11 of 40 AD5380 Data Sheet t t 0 1 REG0, REG1, A5...A0 t t 4 5 t 2 CS t 9 t t 3 8 WR t t t 15 6 7 DB13...DB0 t 10 t 11 BUSY t t 12 13 t 18 1 LDAC t 14 VOUT1 t 16 2 LDAC t 13 t 18 t 17 VOUT2 CLR t 19 t VOUT 20 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev. B | Page 12 of 40 03731-007 Data Sheet AD5380 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 9. rating only; functional operation of the device at these or any Parameter Rating other conditions above those listed in the operational sections AVDD to AGND –0.3 V to +7 V of this specification is not implied. Exposure to absolute maxi- DVDD to DGND –0.3 V to +7 V mum rating conditions for extended periods may affect device Digital Inputs to DGND –0.3 V to DVDD + 0.3 V reliability. SDA/SCL to DGND –0.3 V to +7 V Digital Outputs to DGND –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND –0.3 V to AVDD + 0.3 V AGND to DGND –0.3 V to +0.3 V VOUTx to AGND –0.3 V to AVDD + 0.3 V Analog Inputs to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (T ) 150°C J MAX 100-Lead LQFP Package θJAThermal Impedance 44°C/W Reflow Soldering Peak Temperature 230°C ESD HBM 6.5 kV FICDM 2 kV 1 Transient currents of up to 100 mA will not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu- late on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 13 of 40 AD5380 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 FIFO EN 75 RESET PIN 1 2 CLR 74 DB7 IDENTIFIER VOUT24 3 73 DB6 4 VOUT25 72 DB5 5 VOUT26 71 DB4 6 VOUT27 70 DB3 7 69 SIGNAL_GND4 DB2 8 DAC_GND4 68 DB1 9 AGND4 67 DB0 10 AVDD4 66 REG0 VOUT28 11 65 REG1 VOUT29 12 64 VOUT23 AD5380 13 VOUT30 63 VOUT22 TOP VIEW 14 VOUT31 (Not to Scale) 62 VOUT21 15 REFGND 61 VOUT20 16 REFOUT/REFIN 60 AVDD3 17 SIGNAL_GND1 59 AGND3 18 DAC_GND1 58 DAC_GND3 19 AVDD1 57 SIGNAL_GND3 VOUT0 20 56 VOUT19 VOUT1 21 55 VOUT18 22 VOUT2 54 VOUT17 VOUT3 23 53 VOUT16 VOUT4 24 52 AVDD2 25 AGND1 51 AGND2 Figure 8. 100-Lead LQFP Pin Configuration Table 10. Pin Function Descriptions Mnemonic Function VOUTx Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND(1–5) Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5380. DAC_GND(1–5) Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC. These pins shound be connected to the AGND plane. AGND(1–5) Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD(1–5) Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the AD5380-5 is 4.5 V to 5.5 V; operating range for the AD5380-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND. REFGND Ground Reference Point for the Internal Reference. REFOUT/REFIN The AD5380 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input. Rev. B | Page 14 of 40 26 100 SIGNAL_GND5 CS/(SYNC/AD0) DAC_GND5 27 99 DB13/(DIN/SDA) AGND5 28 98 DB12/(SCLK/SCL) 2 AVDD5 29 97 DB11/(SPI/I C) 30 96 VOUT5 DB10 VOUT6 31 95 DB9 VOUT7 32 94 DB8 VOUT32 33 93 SDO(A/B) 34 92 VOUT33 DVDD VOUT34 35 91 DGND VOUT35 36 90 DGND VOUT36 37 89 A5 88 VOUT37 38 A4 VOUT38 39 87 A3 VOUT39/MON_OUT 40 86 A2 VOUT8 41 85 A1 42 84 VOUT9 A0 43 83 DVDD VOUT10 VOUT11 44 82 DVDD VOUT12 45 81 DGND 80 DAC_GND2 46 SER/PAR SIGNAL_GND2 47 79 PD VOUT13 48 78 WR (DCEN/AD1) VOUT14 49 77 LDAC 50 76 VOUT15 BUSY 03731-008 Data Sheet AD5380 Mnemonic Function VOUT39/MON_OUT This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. However, when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. SER/PAR Interface Select Input. This pin allows the user to select whether the serial or parallel interface will be used. If it is tied 2 2 high, the serial interface mode is selected and Pin 97 (SPI/I C) is used to determine if the interface mode is SPI or I C. Parallel interface mode is selected when SER/PAR is low. CS/(SYNC/AD0) In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5380 is selected. Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address 2 for the device on the I C bus. WR/(DCEN/AD1) Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a 2 daisy-chain enable in SPI mode and as a hardware address pin in I C mode. Parallel Interface Write Input (Edge Sensitive). The rising edge of WR is used in conjunction with CS low and the address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction with SER/PAR high to enable the SPI serial interface Daisy-Chain mode. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address 2 for this device on the I C bus. DB13–DB0 Parallel Data Bus. DB13 is the MSB and DB0 is the LSB of the input data-word on the AD5380. A5–A0 Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5380’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. REG1, REG0 In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and to decide the special function registers. SDO/( /B) Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a A number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5380’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the is used to switch the output between the data contained in the A and B data registers. All DAC channels LDAC contain two data registers. In normal mode, Data Register A is the default for data transfers. BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled and any events on are ignored. A operation also brings low. LDAC CLR BUSY LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET initiates the process and goes low for the duration, returning high when is complete. While RESET BUSY RESET BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation, and the status of the RESET pin is ignored until the next falling edge is detected. PD Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where AIDD reduces to 2 µA and DI to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the DD analog output will be configured as a high impedance output or will provide a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. Rev. B | Page 15 of 40 AD5380 Data Sheet Mnemonic Function FIFO EN FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is 2 sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I C interface modes, the FIFO EN pin should be tied low. 2 DB11/(SPI/I C) Multifunction Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. In serial interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB13 is the serial data (DIN) input. 2 When serial interface mode is selected (SER/PAR = 1) and this input is high, I C mode is selected. In this mode, DB12 is the serial clock (SCL) input, and DB13 is the serial data (SDA) input. DB12/(SCLK/SCL) Multifunction Input Pin. In parallel interface mode, this pin acts as DB12 of the parallel input data-word. In serial interface mode, this pin acts as a serial clock input. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 2 2 I C Mode. In I C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in 2 I C mode is compatible with both 100 kHz and 400 kHz operating modes. DB13/(DIN/SDA) Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB13 of the parallel input data-word. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. 2 2 I C Mode. In I C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. Rev. B | Page 16 of 40 Data Sheet AD5380 TERMINOLOGY Relative Accuracy Voltage Settling Time Relative accuracy, or endpoint linearity, is a measure of the This is the amount of time it takes for the output of a DAC to maximum deviation from a straight line passing through the settle to a specified level for a ¼ to ¾ full-scale input change, endpoints of the DAC transfer function. It is measured after and is measured from the rising edge. BUSY adjusting for zero-scale error and full-scale error, and is Digital-to-Analog Glitch Energy expressed in LSB. This is the amount of energy injected into the analog output at Differential Nonlinearity the major code transition. It is specified as the area of the glitch Differential nonlinearity is the difference between the measured in nV-s. It is measured by toggling the DAC register data change and the ideal 1 LSB change between any two adjacent between 0x1FFF and 0x2000. codes. A specified differential nonlinearity of 1 LSB maximum DAC-to-DAC Crosstalk ensures monotonicity. DAC-to-DAC crosstalk is the glitch impulse that appears at Zero-Scale Error the output of one DAC due to both the digital change and the Zero-scale error is the error in the DAC output voltage when all subsequent analog output change at another DAC. The victim 0s are loaded into the DAC register. Ideally, with all 0s loaded to channel is loaded with midscale. DAC-to-DAC crosstalk is n – 1 the DAC and m = all 1s, c = 2 specified in nV-s. VOUT = 0 V (Zero-Scale) Digital Crosstalk The glitch impulse transferred to the output of one converter Zero-scale error is a measure of the difference between VOUT due to a change in the DAC register code of another converter (actual) and VOUT (ideal), expressed in mV. It is mainly due to is defined as the digital crosstalk and is specified in nV-s. offsets in the output amplifier. Digital Feedthrough Offset Error When the device is not selected, high frequency logic activity Offset error is a measure of the difference between VOUT on the device’s digital inputs can be capacitively coupled both (actual) and VOUT (ideal) in the linear region of the transfer across and through the device to show up as noise on the function, expressed in mV. Offset error is measured on the VOUT pins. It can also be coupled along the supply and AD5380-5 with Code 32 loaded into the DAC register, and ground lines. This noise is digital feedthrough. on the AD5380-3 with Code 64. Output Noise Spectral Density Gain Error This is a measure of internally generated random noise. Gain Error is specified in the linear region of the output range Random noise is characterized as a spectral density (voltage between VOUT= 10 mV and VOUT = AVDD – 50 mV. It is the per √Hertz). It is measured by loading all DACs to midscale deviation in slope of the DAC transfer characteristic from the and measuring noise at the output. It is measured in nV/√Hz ideal and is expressed in %FSR with the DAC output unloaded. in a 1 Hz bandwidth at 10 kHz. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. Rev. B | Page 17 of 40 AD5380 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 AVDD = DVDD = 5.5V AVDD = DVDD = 3V V = 2.5V V = 1.25V REF REF 1.5 1.5 T = 25°C T = 25°C A A 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 INPUT CODE INPUT CODE Figure 9. Typical AD5380-5 INL Plot Figure 12. Typical AD5380-3 INL Plot 40 2.510 35 30 2.505 25 20 2.500 15 10 2.995 5 0 2.990 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 0 2 4 6 8 10 12 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) TIME (µs) Figure 10. AD5380-5 Glitch Impulse Figure 13. AD5380-REFOUT Temperature Coefficient LDAC LDAC VOUT VOUT AVDD = DVDD = 5V AVDD = DVDD = 5V VREF = 2.5V VREF = 2.5V T = 25°C A T = 25°C A Figure 11. Slew Rate with Boost Off Figure 14. Slew Rate with Boost On Rev. B | Page 18 of 40 INL ERROR (LSB) VOLTAGE (V) 03731-105 03731-009 03731-103 FREQUENCY INL ERROR (LSB) 03731-106 03731-013 03731-012 Data Sheet AD5380 14 AVDD = 5.5V V = 2.5V REF T = 25°C A AVDD = DVDD = 5V 12 VREF = 2.5V T = 25°C A 10 VDD 8 6 4 VOUT 2 8 9 10 11 AI (mA) DD Figure 15. AI Histogram with Boost Off Figure 18. AD5380 Power-Up Transient DD DVDD = 5.5V 14 AVDD = 5.5V V = DVDD IH REFIN = 2.5V 10 V = DGND IL T = 25°C A T = 25°C 12 A 8 10 8 6 6 4 4 2 2 0 0 0.5 0.6 0.7 0.8 0.9 1.0 –2 –1 0 1 2 DI (mA) DD INL ERROR DISTRIBUTION (LSB) Figure 16. DI Histogram Figure 19. INL Distribution DD PD BUSY VOUT VOUT AVDD = DVDD = 5V AVDD = DVDD = 5V VREF = 2.5V VREF = 2.5V T = 25°C A T = 25°C A Figure 17. Exiting Soft Power Down Figure 20. Exiting Hardware Power Down Rev. B | Page 19 of 40 PERCENTAGE OF UNITS (%) NUMBER OF UNITS 03731-100 03731-015 03731-107 NUMBER OF UNITS 03731-101 03731-102 03731-019 AD5380 Data Sheet 6 6 AVDD = DVDD = 3V FULL SCALE V = 1.25V REF T = 25°C 5 5 A AVDD = DVDD = 5V V = 2.5V 3/4 SCALE REF 4 T = 25°C 4 A 3/4 SCALE FULL SCALE MIDSCALE 3 3 MIDSCALE 2 2 1/4 SCALE 1 1 ZERO SCALE 0 0 ZERO SCALE 1/4 SCALE –1 –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 –40 –20 –10 –5 –2 0 2 5 10 20 –40 CURRENT (mA) CURRENT (mA) Figure 21. AD5380-5 Output Amplifier Source and Sink Capability Figure 24. AD5380-3 Output Amplifier Source and Sink Capability 0.20 2.456 AVDD = 5V AVDD = DVDD = 5V V = 2.5V REF V = 2.5V REF 0.15 T = 25°C A T = 25°C 2.455 A 14ns/SAMPLE NUMBER 0.10 2.454 ERROR AT ZERO SINKING CURRENT 0.05 2.453 0 2.452 –0.05 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT 2.451 –0.10 –0.15 2.450 –0.20 2.449 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 50 100 150 200 250 300 350 400 450 500 550 I /I (mA) SOURCE SINK SAMPLE NUMBER Figure 22. Headroom at Rails vs. Source/Sink Current Figure 25. Adjacent Channel DAC-to-DAC Crosstalk 600 AVDD = 5V T = 25°C A REFOUT DECOUPLED 500 AVDD = DVDD = 5V WITH 100nF CAPACITOR T = 25°C A DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE 400 Y AXIS = 5µV/DIV X AXIS = 100ms/DIV 300 REFOUT = 2.5V 200 REFOUT = 1.25V AV = DV = 5V 100 DD DD V = 2.5V REF T = 25°C A EXITS SOFT PD 0 TO MIDSCALE 100 1k 10k 100k FREQUENCY (Hz) Figure 26. 0.1 Hz to 10 Hz Noise Plot Figure 23. REFOUT Noise Spectral Density Rev. B | Page 20 of 40 VOUT (V) OUTPUT NOISE (nV/ Hz) ERROR VOLTAGE (V) 03731-023 03731-022 03731-021 VOUT (V) AMPLITUDE (V) 03731-026 03731-025 03731-024 Data Sheet AD5380 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The complete transfer function for these devices can be represented as The AD5380 is a complete, single-supply, 40-channel voltage output DAC that offers 14-bit resolution. The part is available n VOUT = 2 × VREF × x2/2 in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software x2 is the data-word loaded to the resistor string DAC. VREF is selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used the internal reference voltage or the reference voltage externally to drive the buffered reference inputs; alternatively, an external applied to the DAC REFOUT/REFIN pin. For specified reference can be used to drive these inputs. Internal/external performance, an external reference voltage of 2.5 V is recom- reference selection is via the CR10 bit in the control register; mended for the AD5380-5, and 1.25 V for the AD5380-3. CR12 selects the reference magnitude if the internal reference DATA DECODING is rail-to-rail output capable of driving 5 kΩ in parallel with a 200 pF load. The AD5380 contains a 14-bit data bus, DB13 to DB0. Depend- ing on the value of REG1 and REG0 (see Table 3), this data is V AVDD REF loaded into the addressed DAC input registers, offset (c) registers, or gain (m) registers. The format data, offset (c), and ×1 INPUT REG gain (m) register contents are shown in Table 12 to Table 14. DAC 14-BIT INPUT DATA m REG ×2 REG DAC Table 11. Register Selection VOUT c REG R REG1 REG0 Register Selected 1 1 Input Data Register (x1) R 1 0 Offset Register (c) 0 1 Gain Register (m) Figure 27. Single-Channel Architecture 0 0 Special Function Registers (SFRs) The architecture of a single DAC channel consists of a 14-bit Table 12. DAC Data Format (REG1 = 1, REG0 = 1) resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guaran- DB13 to DB0 DAC Output (V) tees DAC monotonicity. The 14-bit binary digital code loaded 11 1111 1111 1111 2 V × (16383/16384) REF to the DAC register determines at what node on the string the 11 1111 1111 1110 2 V × (16382/16384) REF voltage is tapped off before being fed to the output amplifier. 10 0000 0000 0001 2 V × (8193/16384) REF Each channel on these devices contains independent offset and 10 0000 0000 0000 2 VREF × (8192/16384) gain control registers that allow the user to digitally trim offset 01 1111 1111 1111 2 VREF × (8191/16384) and gain. These registers give the user the ability to calibrate out 00 0000 0000 0001 2 V × (1/16384) REF errors in the complete signal chain, including the DAC, using 00 0000 0000 0000 0 the internal m and c registers, which hold the correction factors. Table 13. Offset Data Format (REG1 = 1, REG0 = 0) All channels are double buffered, allowing synchronous updat- DB13 to DB0 Offset (LSB) ing of all channels using the pin. Figure 27 shows a block LDAC 11 1111 1111 1111 +8191 diagram of a single channel on the AD5380. The digital input 11 1111 1111 1110 +8190 transfer function for each DAC can be represented as 10 0000 0000 0001 +1 n n – 1 x2 = [(m + 2)/ 2 × x1] + (c – 2 ) 10 0000 0000 0000 0 01 1111 1111 1111 –1 where: 00 0000 0000 0001 –8191 x2 is the data-word loaded to the resistor string DAC. 00 0000 0000 0000 –8192 x1 is the 14-bit data-word written to the DAC input register. m is the gain coefficient (default is 0x3FFE on the AD5380). Table 14. Gain Data Format (REG1 = 0, REG0 = 1) The gain coefficient is written to the 13 most significant bits DB13 to DB0 Gain Factor (DB13 to DB1) and the LSB (DB0) is zero. 11 1111 1111 1110 1 n = DAC resolution (n = 14 for AD5380). 10 1111 1111 1110 0.75 c is the14-bit offset coefficient (default is 0x2000). 01 1111 1111 1110 0.5 00 1111 1111 1110 0.25 00 0000 0000 0000 0 Rev. B | Page 21 of 40 03731-027 AD5380 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5380 contains a number of special function registers REG1 = REG0 = 0, A5 to A0 = 000010 (SFRs), as outlined in Table 15. SFRs are addressed with REG1 DB13 to DB0 = Don’t Care = REG0 = 0 and are decoded using Address Bits A5 to A0. Executing this instruction performs the CLR, which is func- Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) tionally the same as that provided by the external pin. CLR R/W A5 A4 A3 A2 A1 A0 Function The DAC outputs are loaded with the data in the CLR code X 0 0 0 0 0 0 NOP (No Operation) register. It takes 35 µs to fully execute the SOFT CLR, as 0 0 0 0 0 0 1 Write CLR Code indicated by the low time. BUSY 0 0 0 0 0 1 0 Soft CLR 0 0 0 1 0 0 0 Soft Power-Down Soft Power-Down 0 0 0 1 0 0 1 Soft Power-Up 0 0 0 1 1 0 0 Control Register Write REG1 = REG0 = 0, A5 to A0 = 001000 1 0 0 1 1 0 0 Control Register Read DB13 to DB0 = Don’t Care 0 0 0 1 0 1 0 Channel Monitor Executing this instruction performs a global power-down 0 0 0 1 1 1 1 Soft Reset feature that puts all channels into a low power mode that reduces the analog supply current to 2 µA max and the digital SFR COMMANDS current to 20 µA max. In power-down mode, the output NOP (No Operation) amplifier can be configured as a high impedance output or can provide a 100 kΩ load to ground. The contents of all internal REG1 = REG0 = 0, A5 to A0 = 000000 registers are retained in power-down mode. No register can be Performs no operation, but is useful in serial readback mode to written to while in power-down. clock out data on DOUT for diagnostic purposes. BUSY pulses Soft Power-Up low during a NOP operation. REG1 = REG0 = 0, A5 to A0 = 001001 Write CLR Code DB13 to DB0 = Don’t Care REG1 = REG0 = 0, A5–A0 = 000001 This instruction is used to power up the output amplifiers and DB13 to DB0 = Contain the CLR data the internal reference. The time to exit power-down is 8 µs. The hardware power-down and software function are internally Bringing the CLR line low or exercising the soft clear function combined in a digital OR function. will load the contents of the DAC registers with the data con- Soft RESET tained in the user configurable register, and will set CLR REG1 = REG0 = 0, A5 to A0 = 001111 VOUT0 to VOUT39 accordingly. This can be very useful for DB13 to DB0 = Don’t Care setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale This instruction is used to implement a software reset. All or zero scale to the clear code register and then issue a hard- internal registers are reset to their default values, which ware or software clear to load this code to all DACs, removing correspond to m at full scale and c at zero scale. The contents of the need for individual writes to each DAC. Default on power- the DAC registers are cleared, setting all analog outputs to 0 V. up is all zeros. The soft reset activation time is 135 µs. Rev. B | Page 22 of 40 Data Sheet AD5380 Table 16. Control Register Contents MSB LSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Control Register Write/Read REG1 = REG0 = 0, A5 to A0 = 001100, R/ status determines CR8: Thermal Monitor Function. This function is used to W monitor the AD5380’s internal die temperature when enabled. if the operation is a write (R/ = 0) or a read (R/ = 1). DB13 W W The thermal monitor powers down the output amplifiers when to DB0 contains the control register data. the temperature exceeds 130°C. This function can be used to Control Register Contents protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously CR13: Power-Down Status. This bit is used to configure the short-circuited. A soft power-up will re-enable the output output amplifier state in power down. amplifiers if the die temperature has dropped below 130°C. CR13 = 1. Amplifier output is high impedance (default on CR8 = 1: Thermal Monitor Enabled. power-up). CR8 = 0: Thermal Monitor Disabled (default on power-up). CR13 = 0. Amplifier output is 100 kΩ to ground. CR7: Don’t Care. CR12: REF Select. This bit selects the operating internal reference for the AD5380. CR12 is programmed as follows: CR6 to CR2: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A CR12 = 1: Internal reference is 2.5 V (AD5380-5 default), and B registers for each DAC. Control Register Bits CR6 to CR2 the recommended operating reference for AD5380-5. are used to enable individual groups of eight channels for operation in toggle mode. A Logic 1 written to any bit enables CR12 = 0: Internal reference is 1.25 V (AD5380-3 default), a group of channels; a Logic 0 disables a group. is used to LDAC the recommended operating reference for AD5380-3. toggle between the two registers. Table 17 shows the decoding CR11: Current Boost Control. This bit is used to boost the for toggle mode operation. For example, CR6 controls Group w, current in the output amplifier, thereby altering its slew rate. which contains Channel 32 to Channel 39, CR6 = 1 enables This bit is configured as follows: these channels. CR11 = 1: Boost Mode On. This maximizes the bias current CR1 and CR0: Don’t Care. in the output amplifier, optimizing its slew rate but increasing the power dissipation. Table 17. CR Bit Group Channels CR11 = 0: Boost Mode Off (default on power-up). This CR6 4 32–39 reduces the bias current in the output amplifier and reduces CR5 3 24–31 the overall power consumption. CR4 2 16–23 CR10: Internal/External Reference. This bit determines if the CR3 1 8–15 DAC uses its internal reference or an externally applied CR2 0 0–7 reference. Channel Monitor Function CR10 = 1: Internal Reference Enabled. The reference output REG1 = REG0 = 0, A5 to A0 = 001010 depends on data loaded to CR12. DB13 to DB8 = Contain data to address the monitored channel. CR10 = 0: External Reference Selected (default on power-up). A channel monitor function is provided on the AD5380. This CR9: Channel Monitor Enable (see Channel Monitor Function). feature, which consists of a multiplexer addressed via the inter- face, allows any channel output to be routed to the MON_OUT CR9 = 1: Monitor Enabled. This enables the channel monitor pin for monitoring using an external ADC. In channel monitor function. After a write to the monitor channel in the SFR mode, VOUT39 becomes the MON_OUT pin, to which all register, the selected channel output is routed to the monitored pins are routed. The channel monitor function must MON_OUT pin. VOUT39 operates as the MON_OUT pin. be enabled in the control register before any channels are routed CR9 = 0: Monitor Disabled (default on power-up). When the to MON_OUT. On the AD5380, DB13 to DB8 contain the monitor is disabled, the MON_OUT pin assumes its normal channel address for the monitored channel. Selecting Channel DAC output function. Address 63 three-states MON_OUT. Rev. B | Page 23 of 40 AD5380 Data Sheet Table 18. AD5380 Channel Monitor Decoding REG1 REG0 A5 A4 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7–DB0 MON_OUT 0 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2 0 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3 0 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4 0 0 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT5 0 0 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT6 0 0 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT7 0 0 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT8 0 0 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT9 0 0 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT10 0 0 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT11 0 0 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT12 0 0 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT13 0 0 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT14 0 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15 0 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16 0 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17 0 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18 0 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19 0 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20 0 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21 0 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22 0 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23 0 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24 0 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25 0 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26 0 0 0 0 1 0 1 0 0 1 1 0 1 1 X VOUT27 0 0 0 0 1 0 1 0 0 1 1 1 0 0 X VOUT28 0 0 0 0 1 0 1 0 0 1 1 1 0 1 X VOUT29 0 0 0 0 1 0 1 0 0 1 1 1 1 0 X VOUT30 0 0 0 0 1 0 1 0 0 1 1 1 1 1 X VOUT31 0 0 0 0 1 0 1 0 1 0 0 0 0 0 X VOUT32 0 0 0 0 1 0 1 0 1 0 0 0 0 1 X VOUT33 0 0 0 0 1 0 1 0 1 0 0 0 1 0 X VOUT34 0 0 0 0 1 0 1 0 1 0 0 0 1 1 X VOUT35 0 0 0 0 1 0 1 0 1 0 0 1 0 0 X VOUT36 0 0 0 0 1 0 1 0 1 0 1 1 0 1 X VOUT37 0 0 0 0 1 0 1 0 1 0 0 1 1 0 X VOUT38 0 0 0 0 1 0 1 0 1 0 0 1 1 1 X Undefined • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 0 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State REG1 REG0A5 A4 A3 A2 A1 A0 0 0 0 0 1 0 1 0 VOUT0 VOUT1 AD5380 CHANNEL MONITOR VOUT39/MON_OUT DECODING VOUT37 VOUT38 CHANNEL ADDRESS DB13–DB8 Figure 28. Channel Monitor Decoding Rev. B | Page 24 of 40 03731-028 Data Sheet AD5380 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE The AD5380 contains a FIFO to optimize operation when Bringing the line low resets the contents of all internal RESET operating in parallel interface mode. The FIFO Enable (level registers to their power-on reset state. Reset is a negative edge- sensitive, active high) is used to enable the internal FIFO. When sensitive input. The default corresponds to m at full scale and to connected to DVDD, the internal FIFO is enabled allowing the c at zero scale. The contents of the DAC registers are cleared, user to write to the device at full speed. FIFO is only available in setting VOUT0 to VOUT39 to 0 V. The hardware reset parallel interface mode. The status of the FIFO EN pin is sam- activation time takes 270 µs. The falling edge of initiates RESET pled on power-up, and after a CLR or RESET, to determine if the reset process; BUSY goes low for the duration, returning 2 the FIFO is enabled. In either serial or I C interface modes, high when is complete. While is low, all interfaces RESET BUSY FIFO EN should be tied low. Up to 128 successive instructions are disabled and all LDAC pulses are ignored. When BUSY can be written to the FIFO at maximum speed in parallel mode. returns high, the part resumes normal operation and the status When the FIFO is full, any further writes to the device are of the pin is ignored until the next falling edge is RESET ignored. Figure 29 shows a comparison between FIFO mode detected. and non-FIFO mode in terms of channel update time. Figure 29 also outlines digital loading time. ASYNCHRONOUS CLEAR FUNCTION Bringing the line low clears the contents of the DAC CLR 25 registers to the data contained in the user configurable CLR register and sets VOUT0 to VOUT9 accordingly. This func- WITHOUT FIFO 20 (CHANNEL UPDATE TIME) tion can be used in system calibration to load zero scale and full scale to all channels. The execution time for a CLR is 35 µs. 15 AND FUNCTIONS BUSY LDAC BUSY is a digital CMOS output that indicates the status of the 10 WITH FIFO AD5380. The value of x2, the internal data loaded to the DAC (CHANNEL UPDATE TIME) data register, is calculated each time the user writes new data to 5 WITH FIFO the corresponding x1, c, or m registers. During the calculation (DIGITAL LOADING TIME) of x2, the BUSY output goes low. While BUSY is low, the user 0 can continue writing new data to the x1, m, or c registers, but 1 4 7 10 13 16 19 22 25 28 31 34 37 40 NUMBER OF WRITES no DAC output updates can take place. The DAC outputs are updated by taking the input low. If goes low while LDAC LDAC Figure 29. Channel Update Rate (FIFO vs. NON-FIFO) BUSY is active, the LDAC event is stored and the DAC outputs update immediately after goes high. The user may hold BUSY POWER-ON RESET the LDAC input permanently low, in which case the DAC The AD5380 contains a power-on reset generator and state outputs update immediately after goes high. also BUSY BUSY machine. The power-on reset resets all registers to a predefined goes low during power-on reset and when a falling edge is state and configures the analog outputs as high impedance. The also detected on the RESET pin. During this time, all interfaces BUSY pin goes low during the power-on reset sequencing, are disabled and any events on are ignored. The AD5380 preventing data writes to the device. LDAC contains an extra feature whereby a DAC register is not up- POWER-DOWN dated unless its x2 register has been written to since the last The AD5380 contains a global power-down feature that puts all time was brought low. Normally, when is brought LDAC LDAC channels into a low power mode and reduces the analog power low, the DAC registers are filled with the contents of the x2 consumption to 2 µA max and digital power consumption to registers. However, the AD5380 will only update the DAC 20 µA max. In power-down mode, the output amplifier can be register if the x2 data has changed, thereby removing configured as a high impedance output or provide a 100 kΩ unnecessary digital crosstalk. load to ground. The contents of all internal registers are re- tained in power-down mode. When exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values. Rev. B | Page 25 of 40 TIME (µs) 03731-029 AD5380 Data Sheet AD5380 INTERFACES The AD5380 contains both parallel and serial interfaces. Figure 3 and Figure 5 show timing diagrams for a serial write to Furthermore, the serial interface can be programmed to be the AD5380 in standalone and daisy-chain modes. The 24-bit 2 either SPI-, DSP-, MICROWIRE-, or I C-compatible. The data-word format for the serial interface is shown in Table 19. SER/ pin selects parallel and serial interface modes. PAR A/B. When toggle mode is enabled, this pin selects whether the 2 In serial mode, the /I C pin is used to select DSP, SPI, SPI data write is to the A or B register. With toggle disabled, this bit 2 MICROWIRE, or I C interface mode. should be set to zero to select the A data register. The devices use an internal FIFO memory to allow high speed R/W is the read or write control bit. successive writes in parallel interface mode. The user can con- tinue writing new data to the device while write instructions are A5 to A0 are used to address the input channels. being executed. The signal indicates the current status of BUSY REG1 and REG0 select the register to which data is written, as the device, going low while instructions in the FIFO are being shown in Table 11. executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO DB13 to DB0 contain the input data-word. is full, any further writes to the device are ignored. X is a don’t care condition. To minimize both the power consumption of the device and the Standalone Mode on-chip digital noise, the active interface only powers up fully when the device is being written to, that is, on the falling edge By connecting the DCEN (daisy-chain enable) pin low, stand- of WR or the falling edge of SYNC. alone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL edge of starts the write cycle and resets a counter that SYNC INTERFACES counts the number of serial clocks to ensure that the correct The serial interface can be operated with a minimum of three number of bits are shifted into the serial shift register. Any wires in standalone mode or four wires in daisy-chain mode. further edges on SYNC, except for a falling edge, are ignored Daisy chaining allows many devices to be cascaded together to until 24 bits are clocked into the register. Once 24 bits have been increase system channel count. The SER/ pin must be tied PAR shifted in, the SCLK is ignored. In order for another serial 2 high and the /I C pin (Pin 97) should be tied low to enable SPI transfer to take place, the counter must be reset by the falling the DSP-/SPI-/MICROWIRE-compatible serial interface. In edge of SYNC. serial interface mode, the user does not need to drive the parallel input data pins. The serial interface’s control pins are , DIN, SCLK—Standard 3-wire interface pins. SYNC DCEN—Selects standalone mode or daisy-chain mode. SDO—Data out pin for daisy-chain mode. Table 19. 40-Channel, 14-Bit DAC Serial Input Register Configuration MSB LSB A W A5 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 /B R/ Rev. B | Page 26 of 40 Data Sheet AD5380 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin may be Readback mode is invoked by setting the R/W bit = 1 in the used to daisy-chain several devices together. This daisy-chain serial input register write. With R/ = 1, Bits A5 to A0, in W mode can be useful in system diagnostics and in reducing the association with Bits REG1 and REG0, select the register to be number of serial interface lines. read. The remaining data bits in the write sequence are don’t cares. During the next write, the data appearing on the SPI By connecting the DCEN (daisy-chain enable) pin high, daisy- SDO output will contain the data from the previously addressed chain mode is enabled. The first falling edge of SYNC starts the register. For a read of a single register, the NOP command can be write cycle. The SCLK is continuously applied to the input shift used in clocking out the data from the selected register on SDO. register when is low. If more than 24 clock pulses are SYNC applied, the data ripples out of the shift register and appears Figure 30 shows the readback sequence. For example, to read on the SDO line. This data is clocked out on the rising edge of back the m register of Channel 0 on the AD5380, the following SCLK and is valid on the falling edge. By connecting the SDO sequence should be implemented. First, write 0x404XXX to the of the first device to the DIN input on the next device in the AD5380 input register. This configures the AD5380 for read chain, a multidevice interface is constructed. Twenty-four clock mode with the m register of Channel 0 selected. Note that Data pulses are required for each device in the system. Therefore, the Bits DB13 to DB0 are don’t cares. Follow this with a second total number of clock cycles must equal 24N, where N is the write, a NOP condition, 0x000000. During this write, the data total number of AD538x devices in the chain. from the m register is clocked out on the SDO line, that is, data clocked out will contain the data from the m register in Bits When the serial transfer to all devices is complete, SYNC is DB13 to DB0, and the top 10 bits contain the address infor- taken high. This latches the input data in each device in the mation as previously written. In readback mode, the SYNC daisy-chain and prevents any further data from being clocked signal must frame the data. Data is clocked out on the rising into the input shift register. edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read If the SYNC is taken high before 24 clocks are clocked into the operations of a readback operation, the first bit of data is part, this is considered a bad frame and the data is discarded. clocked out on the falling edge of . SYNC The serial clock may be either a continuous or a gated clock. A continuous SCLK source can only be used if it can be arranged that SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and must be taken high after SYNC the final clock to latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23 DB0 DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 30. Serial Readback Operation Rev. B | Page 27 of 40 03731-030 AD5380 Data Sheet 2 I C SERIAL INTERFACE AD5380 Slave Addresses 2 The AD5380 features an I C-compatible 2-wire interface A bus master initiates communication with a slave device by consisting of a serial data line (SDA) and a serial clock line issuing a START condition followed by the 7-bit slave address. (SCL). SDA and SCL facilitate communication between the When idle, the AD5380 waits for a START condition followed AD5380 and the master at rates up to 400 kHz. Figure 6 by its slave address. The LSB of the address word is the Read/ shows the 2-wire interface timing diagrams that incorporate 2 Write (R/ ) bit. The AD5380 is a receive only device; when three different modes of operation. In selecting the I C W = 0. After receiving the operating mode, first configure serial operating mode communicating with the AD5380, R/W 2 (SER/PAR = 1) and then select I C mode by configuring the proper address 1010 1(AD1)(AD0), the AD5380 issues an ACK 2 2 /I C pin to a Logic 1. The device is connected to the I C bus by pulling SDA low for one clock cycle. SPI as a slave device (that is, no clock is generated by the AD5380). The AD5380 has four different user programmable addresses The AD5380 has a 7-bit slave address 1010 1(AD1)(AD0). determined by the AD1 and AD0 bits. The 5 MSBs are hard-coded, and the 2 LSBs are determined Write Operation by the state of the AD1 and AD0 pins. The facility to hardware- configure AD1 and AD0 allows four of these devices to be There are three specific modes in which data can be written to configured on the bus. the AD5380 DAC. 2 I C Data Transfer 4-Byte Mode One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the When writing to the AD5380 DACs, the user must begin with SCL clock pulse. Changes in SDA while SCL is high are control an address byte (R/W = 0), after which the DAC acknowledges signals that configure START and STOP conditions. Both SDA that it is prepared to receive data by pulling SDA low. The and SCL are pulled high by the external pull-up resistors when address byte is followed by the pointer byte; this addresses the 2 the I C bus is not busy. specific channel in the DAC to be addressed and is also acknowledged by the DAC. Two bytes of data are then written START and STOP Conditions to the DAC, as shown in Figure 31. A STOP condition follows. A master device initiates communication by issuing a START This allows the user to update a single channel within the condition. A START condition is a high-to-low transition on AD5380 at any time and requires four bytes of data to be SDA with SCL high. A STOP condition is a low-to-high transferred from the master. transition on SDA while SCL is high. A START condition from the master signals the beginning of a transmission to 3-Byte Mode the AD5380. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, In 3-byte mode, the user can update more than one channel in a the bus remains active. write sequence without having to write the device address byte each time. The device address byte is only required once; sub- Repeated START Conditions sequent channel updates require the pointer byte and the data A repeated START (Sr) condition may indicate a change of data bytes. In 3-byte mode, the user begins with an address byte direction on the bus. Sr may be used when the bus master is (R/ = 0), after which the DAC will acknowledge that it is W 2 writing to several I C devices and wants to maintain control of prepared to receive data by pulling SDA low. The address byte the bus. is followed by the pointer byte. This addresses the specific chan- Acknowledge Bit (ACK) nel in the DAC to be addressed and is also acknowledged by the The acknowledge bit (ACK) is the ninth bit attached to any DAC. This is then followed by the two data bytes. REG1 and 8-bit data-word. ACK is always generated by the receiving REG0 determine the register to be updated. device. The AD5380 devices generate an ACK when receiving If a STOP condition does not follow the data bytes, another an address or data by pulling SDA low during the ninth clock channel can be updated by sending a new pointer byte followed period. Monitoring ACK allows for detection of unsuccessful by the data bytes. This mode only requires three bytes to be data transfers. An unsuccessful data transfer occurs if a receiv- sent addressed, and reduces the software overhead in updating ing device is busy or if a system fault has occurred. In the the AD5380 channels. A STOP condition at any time exits this event of an unsuccessful data transfer, the bus master should mode. Figure 32 shows a typical configuration. reattempt communication. Rev. B | Page 28 of 40 Data Sheet AD5380 SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP AD538x AD538x COND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE BY MASTER 2 Figure 31. 4-Byte AD5380, I C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 A5 A4 A3 A2 A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP COND AD538x AD538x BY MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" 2 Figure 32. 3-Byte AD5380, I C Write Operation Rev. B | Page 29 of 40 03731-032 03731-031 AD5380 Data Sheet PARALLEL INTERFACE 2-Byte Mode The SER/PAR pin must be tied low to enable the parallel inter- Following initialization of 2-byte mode, the user can update face and disable the serial interfaces. Figure 7 shows the timing channels sequentially. The device address byte is only required diagram for a parallel write. The parallel interface is controlled once and the pointer address pointer is configured for auto- by the following pins: increment or burst mode. Pin CS The user must begin with an address byte (R/W = 0), after Active low device select pin. which the DAC will acknowledge that it is prepared to receive WR Pin data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of On the rising edge of WR, with CS low, the addresses on Pin A5 operation. The address pointer initializes to Channel 0, the to Pin A0 are latched; data present on the data bus is loaded data following the pointer is loaded to Channel 0, and the into the selected input registers. address pointer automatically increments to the next address. REG0, REG1 Pins The REG0 and REG1 bits in the data byte determine which The REG0 and REG1 pins determine the destination register of register will be updated. In this mode, following the initializa- the data being written to the AD5380. See Table 11. tion, only the two data bytes are required to update a channel. Pins A5 to A0 The channel address automatically increments from Address 0 Each of the 40 DAC channels can be individually addressed. to Channel 39 and then returns to the normal 3-byte mode of Pins DB13 to DB0 operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in The AD5380 accepts a straight 14-bit parallel word on DB13 to configuring all channels. A STOP condition at any time exits DB0, where DB13 is the MSB and DB0 is the LSB. this mode. Toggle mode is not supported in 2-byte mode. Figure 33 shows a typical configuration. SCL SDA 1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND ACK BY MSB ACK BY BY MASTER CONVERTER CONVERTER ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY CONVERTER CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP CONVERTER CONVERTER COND MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 33. 2-Byte, 1 C Write Operation Rev. B | Page 30 of 40 03731-033 Data Sheet AD5380 MICROPROCESSOR INTERFACING Parallel Interface The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5380, the line SYNC The AD5380 can be interfaced to a variety of 16-bit microcon- trollers or DSP processors. Figure 35 shows the AD5380 family is taken low (PC7). Data appearing on the MOSI output is valid interfaced to a generic 16-bit microcontroller/DSP processor. on the falling edge of SCK. Serial data from the 68HC11 is The lower address lines from the processor are connected to transmitted in 8-bit bytes with only eight falling clock edges A0 to A5 on the AD5380. The upper address lines are decoded occurring in the transmit cycle. to provide a , signal for the AD5380. The fast interface CS LDAC timing of the AD5380 allows direct interface to a wide variety DVDD MC68HC11 AD5380 of microcontrollers and DSPs, as shown in Figure 35. SER/PAR RESET AD5380 to MC68HC11 MISO SDO The serial peripheral interface (SPI) on the MC68HC11 is MOSI DIN SCK SCLK configured for Master mode (MSTR = 1), Clock Polarity bit PC7 SYNC (CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is 2 SPI/I C configured by writing to the SPI control register (SPCR)—see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK Figure 34. AD5380-to-MC68HC11 Interface of the AD5380, the MOSI output drives the serial data line (DIN) of the AD5380, and the MISO input is driven from SDO. µCONTROLLER/ AD5380 1 DSP PROCESSOR D15 REG1 REG0 D13 DATA BUS D0 D0 CS UPPER BITS OF ADDRESS ADDRESS BUS DECODE LDAC A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 R/W WR 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5380-to-Parallel Interface Rev. B | Page 31 of 40 03731-035 03731-034 AD5380 Data Sheet DVDD AD5380 to PIC16C6x/7x 8XC51 AD5380 SER/PAR The PIC16C6x/7x synchronous serial port (SSP) is configured RESET as an SPI master with the Clock Polarity bit = 0. This is done by writing to the synchronous serial port control register RxD SDO DIN (SSPCON). See the PIC16/17 Microcontroller User Manual. TxD SCLK In this example, I/O, port RA1, is being used to pulse SYNC P1.1 SYNC 2 and enable the serial port of the AD5380. This microcontroller SPI/I C transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations Figure 37. AD5380-to-8051 Interface may be needed depending on the mode. Figure 36 shows the connection diagram. AD5380 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5380 and the DVDD PIC16C6X/7X AD5380 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR be set up to operate in SPORT transmit alternate framing mode. RESET The ADSP-2101/ADSP-2103 SPORT is programmed through SDI/RC4 SDO SDO/RC5 DIN the SPORT control register and should be configured as follows: SCK/RC3 SCLK internal clock operation, active low framing, and 16-bit word RA1 SYNC length. Transmission is initiated by writing a word to the 2 SPI/I C Tx register after the SPORT has been enabled. Figure 36. AD5380-to-PIC16C6x/7x Interface DVDD ADSP-2101/ AD5380 ADSP-2103 SER/PAR AD5380 to 8051 RESET The AD5380 requires a clock synchronized to the serial data. DR SDO DT DIN Therefore, the 8051 serial interface must be operated in Mode 0. SCK SCLK In this mode, serial data enters and exits through RxD, and a TFS SYNC shift clock is output on TxD. Figure 37 shows how the 8051 is RFS 2 SPI/I C connected to the AD5380. Because the AD5380 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5380 Figure 38. AD5380-to-ADSP-2101/ADSP-2103 Interface requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. Rev. B | Page 32 of 40 03731-036 03731-038 03731-037 Data Sheet AD5380 APPLICATION INFORMATION externally from either an ADR421 or ADR431 2.5 V reference. POWER SUPPLY DECOUPLING Suitable external references for the AD5380-3 include the In any circuit where accuracy is important, careful considera- ADR280 1.2 V reference. The reference should be decoupled at tion of the power supply and ground return layout helps to the REFOUT/REFIN pin of the device with a 0.1 µF capacitor. ensure the rated performance. The printed circuit board on AVDD DVDD which the AD5380 is mounted should be designed so that the 0.1µF analog and digital sections are separated and confined to certain areas of the board. If the AD5380 is in a system where 10µF 0.1µF ADR431/ multiple devices require an AGND-to-DGND connection, the ADR421 connection should be made at one point only, a star ground point established as close to the device as possible. AVDD DVDD REFOUT/REFIN VOUT0 For supplies with multiple pins (AVDD, DVDD), these pins 0.1µF should be tied together. The AD5380 should have ample supply AD5380-5 REFGND bypassing of 10 µF in parallel with 0.1 µF on each supply, VOUT39 located as close to the package as possible and ideally right up against the device. The 10 µF capacitors are the tantalum bead DAC_GND SIGNAL_GND AGND DGND type. The 0.1 µF capacitor should have low effective series resis- tance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to Figure 39. Typical Configuration with External Reference ground at high frequencies, to handle transient currents due to Figure 40 shows a typical configuration when using the internal internal logic switching. reference. On power-up, the AD5380 defaults to an external The power supply lines of the AD5380 should use as large a reference; therefore, the internal reference needs to be config- trace as possible to provide low impedance paths and reduce the ured and turned on via a write to the AD5380 control register. effects of glitches on the power supply line. Fast switching Control Register Bit CR12 allows the user to choose the signals such as clocks should be shielded with digital ground reference value; Bit CR 10 is used to select the internal to avoid radiating noise to other parts of the board, and should reference. It is recommended to use the 2.5 V reference when never be run near the reference inputs. A ground line routed AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. between the DIN and SCLK lines will help reduce crosstalk AVDD DVDD between them (this is not required on a multilayer board 0.1µF because there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on the 10µF 0.1µF REFOUT/REFIN line. Avoid crossover of digital and analog signals. Traces on AVDD DVDD opposite sides of the board should run at right angles to REFOUT/REFIN VOUT0 each other. This reduces the effects of feedthrough through 0.1µF the board. A micro-strip technique is the best, but is not always AD5380 REFGND possible with a double-sided board. In this technique, the VOUT39 component side of the board is dedicated to the ground plane DAC_GND SIGNAL_GND AGND DGND while signal traces are placed on the solder side. TYPICAL CONFIGURATION CIRCUIT Figure 39 shows a typical configuration for the AD5380-5 Figure 40. Typical Configuration with Internal Reference when configured for use with an external reference. In the Digital connections have been omitted for clarity. The AD5380 circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins contains an internal power-on reset circuit with a 10 ms brown- are tied together to a common AGND. AGND and DGND are out time. If the power supply ramp rate exceeds 10 ms, the user connected together at the AD5380 device. On power-up, the should reset the AD5380 as part of the initialization process to AD5380 defaults to external reference operation. All AVDD ensure the calibration data gets loaded correctly into the device. lines are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this application, the reference for the AD5380-5 is provided Rev. B | Page 33 of 40 03731-040 03731-039 AD5380 Data Sheet AD5380 MONITOR FUNCTION TOGGLE MODE FUNCTION The AD5380 contains a channel monitor function that consists The toggle mode function allows an output signal to be gener- of a multiplexer addressed via the interface, allowing any chan- ated using the LDAC control signal that switches between two nel output to be routed to this pin for monitoring using an DAC data registers. This function is configured using the SFR external ADC. In channel monitor mode, VOUT39 becomes control register as follows. A write with REG1 = REG0 = 0 and the MON_OUT pin, to which all monitored signals are routed. A5 to A0 = 001100 specifies a control register write. The toggle The channel monitor function must be enabled in the control mode function is enabled in groups of eight channels using Bits register before any channels are routed to MON_OUT. Table 18 CR6 to CR2 in the control register. See the AD5380 control contains the decoding information required to route any chan- register description. Figure 42 shows a block diagram of toggle nel to MON_OUT. Selecting Channel Address 63 three-states mode implementation. Each of the 40 DAC channels on the MON_OUT. Figure 41 shows a typical monitoring circuit AD5380 contain an A and B data register. Note that the B implemented using a 12-bit SAR ADC in a 6-lead SOT-23 registers can only be loaded when toggle mode is enabled. The package. The controller output port selects the channel to be sequence of events when configuring the AD5380 for toggle monitored, and the input port reads the converted data from mode is the ADC. 1. Enable toggle mode for the required channels via the control register. AVDD 2. Load data to A registers. DIN VOUT0 SYNC OUTPUT PORT 3. Load data to B registers. SCLK VDD 4. Apply . LDAC AD5380 CS AD7476 VOUT39/MON_OUT VIN SCLK INPUT PORT The is used to switch between the A and B registers in LDAC SDATA determining the analog output. The first LDAC configures the GND output to reflect the data in the A registers. This mode offers CONTROLLER significant advantages if the user wants to generate a square AGND VOUT38 DAC_GND SIGNAL_GND wave at the output of all 40 channels, as might be required to drive a liquid crystal based variable optical attenuator. In this case, the user writes to the control register and enables the toggle function by setting CR6 to CR2 = 1, thus enabling the Figure 41. Typical Channel Monitoring Circuit five groups of eight for toggle mode operation. The user must then load data to all 40 A and B registers. Toggling will LDAC set the output values to reflect the data in the A and B registers. The frequency of the will determine the frequency of the LDAC square wave output. Toggle mode is disabled via the control register. The first LDAC following the disabling of the toggle mode will update the outputs with the data contained in the A registers. DATA REGISTER A DAC 14-BIT DAC VOUT REGISTER DATA INPUT INPUT REGISTER DATA REGISTER B LDAC A/B CONTROL INPUT Figure 42. Toggle Mode Function Rev. B | Page 34 of 40 03731-041 03731-042 Data Sheet AD5380 AD5380 IN A MEMS BASED OPTICAL SWITCH THERMAL MONITOR FUNCTION In their feed-forward control paths, MEMS based optical The AD5380 contains a temperature shutdown function to switches require high resolution DACs that offer high channel protect the chip in case multiple outputs are shorted. The short- density with 14-bit monotonic behavior. The 40-channel, 14-bit circuit current of each output amplifier is typically 40 mA. AD5380 DAC satisfies these requirements. In the circuit in Operating the AD5380 at 5 V produces a power dissipation of Figure 43, the 0 V to 5 V outputs of the AD5380 are amplified 200 mW per shorted amplifier. With five channels shorted, this to achieve an output range of 0 V to 200 V, which is used to gives an extra watt of power dissipation. For the 100-lead LQFP, control actuators that determine the position of MEMS mirrors the θJA is typically 44°C/W. in an optical switch. The exact position of each mirror is The thermal monitor is enabled by the user via CR8 in the measured using sensors. The sensor outputs are multiplexed control register. The output amplifiers on the AD5380 are into a high resolution ADC in determining the mirror position. automatically powered down if the die temperature exceeds The control loop is closed and driven by an ADSP-21065L, a approximately 130°C. After a thermal shutdown has occurred, 32-bit SHARC® DSP with an SPI-compatible SPORT interface. the user can re-enable the part by executing a soft power-up if The ADSP-21065L writes data to the DAC, controls the the temperature has dropped below 130°C or by turning off the multiplexer, and reads data from the ADC via the serial thermal monitor function via the control register. interface. +5V OUTPUT RANGE 0V TO 200V 0.01µF REFOUT/REFIN AVDD VOUT1 14-BIT DAC 8-CHANNEL ADC G = 50 ACTUATORS (AD7856) SENSOR FOR MEMS OR AND MIRROR SINGLE CHANNEL MULTIPLEXER ARRAY ADC (AD7671) 14-BIT DAC G = 50 VOUT39 AD5380 ADSP-21065L Figure 43. AD5380 in a MEMS Based Optical Switch Rev. B | Page 35 of 40 03731-043 AD5380 Data Sheet OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic The AD5380 controls the optical attenuator for each behavior, and high level of integration, the AD5380 is ideally wavelength, ensuring that the power is equalized in all targeted at optical attenuation applications used in dynamic wavelengths before being multiplexed onto the fiber. This gain equalizers, variable optical attenuators (VOA), and optical prevents information loss and saturation from occurring at add-drop multiplexers (OADM). In these applications, each amplification stages further along the fiber. wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transim- pedance amplifier and ADC in a closed-loop control system. ADD DROP PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM DWDM ATTENUATOR IN OUT FIBRE AWG FIBRE AWG 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) ADG731 N:1 MULTIPLEXER (40:1 MUX) AD5380, 40-CHANNEL, 14-BIT DAC AD7671 CONTROLLER 16-BIT ADC (0V TO 5V, 1MSPS) Figure 44. OADM Using the AD5380 as Part of an Optical Attenuator Rev. B | Page 36 of 40 03731-044 Data Sheet AD5380 UTILIZING THE AD5380 FIFO The AD5380 FIFO mode optimizes total system update rates In such systems, as many as 400 channels need to be updated in applications where a large number of channels need to be within 40 µs. Four-hundred channels requires the use of 10 updated. FIFO mode is only available when parallel interface AD5380s. With FIFO mode enabled, the data write cycle time mode is selected. The FIFO EN pin is used to enable the FIFO. is 40 ns; therefore, each group consisting of 40 channels can be The status of FIFO EN is sampled during the initialization fully loaded in 1.6 µs. In FIFO mode, a complete group of 40 sequence. Therefore, the FIFO status can only be changed by channels will update in 14.4 µs. The time taken to update all resetting the device. In a telescope that provides for the cancella- 400 channels is 14.4 µs + 9 × 1.6 µs = 28.8 µs. Figure 45 shows tion of atmospheric distortion, for example, a large number of the FIFO operation scheme. channels need to be updated in a short period of time. GROUP A GROUP B GROUP C GROUP D GROUP E GROUP F GROUP G GROUP H GROUP I GROUP J CHNLS 0–39 CHNLS 40–79 CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS CHNLS 80–119 120–159 160–199 200–239 240–279 280–319 320–359 360–399 FIFO DATA LOAD GROUP A FIFO DATA LOAD FIFO DATA LOAD 1.6µs 1.6µs 1.6µs GROUP B GROUP J OUTPUT UPDATE OUTPUT UPDATE 14.4µs 14.4µs TIME FOR GROUP A TIME FOR GROUP J OUTPUT UPDATE 14.4µs TIME FOR GROUP B TIME TO UPDATE 400 CHANNELS = 28.8µs Figure 45. Using FIFO Mode 400 Channels Updated in Under 30 µs Rev. B | Page 37 of 40 03731-045 AD5380 Data Sheet OUTLINE DIMENSIONS 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 76 1 75 0.60 0.45 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 25 51 0.15 0° 26 50 SEATING 0.05 0.08 PLANE COPLANARITY 0.27 VIEW A 0.50 0.22 BSC VIEW A 0.17 LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 46. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1) Dimensions shown in millimeters ORDERING GUIDE AVDD Output Linearity Package Package 1 Model Resolution Temperature Range Range Channels Error (LSB) Description Option AD5380BSTZ-3 14 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100-1 AD5380BSTZ-5 14 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100-1 EVAL-AD5380EBZ Evaluation Kit 1 Z = RoHS-Compliant Part. Rev. B | Page 38 of 40 051706-A Data Sheet AD5380 NOTES Rev. B | Page 39 of 40 AD5380 Data Sheet NOTES 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03731-0-6/12(B) Rev. B | Page 40 of 40