ANALOG DEVICES AD5347

2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs AD5346/AD5347/AD5348 FEATURES GENERAL DESCRIPTION AD5346: octal 8-bit DAC 1 The AD5346/AD5347/AD5348 are octal 8-, 10-, and 12-bit AD5347: octal 10-bit DAC DACs, operating from a 2.5 V to 5.5 V supply. These devices AD5348: octal 12-bit DAC incorporate an on-chip output buffer that can drive the output Low power operation: 1.4 mA (max) @ 3.6 V to both supply rails, and also allow a choice of buffered or Power-down to 120 nA @ 3 V, 400 nA @ 5 V unbuffered reference input. Guaranteed monotonic by design over all codes The AD5346/AD5347/AD5348 have a parallel interface. CS Rail-to-rail output range: 0 V to V or 0 V to 2 × V REF REF selects the device and data is loaded into the input registers on Power-on reset to 0 V WR LDAC the rising edge of . A readback feature allows the internal Simultaneous update of DAC outputs via pin DAC registers to be read back through the digital port. CLR Asynchronous facility Readback The GAIN pin on these devices allows the output range to be Buffered/unbuffered reference inputs set at 0 V to VREF or 0 V to 2 × VREF. 20 ns WR time Input data to the DACs is double-buffered, allowing simultane- 38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging ous update of multiple DACs in a system using the LDAC pin. Temperature range: –40°C to +105°C CLR An asynchronous input is also provided, which resets the APPLICATIONS contents of the input register and the DAC register to all zeros. Portable battery-powered instruments These devices also incorporate a power-on reset circuit that Digital gain and offset adjustment ensures that the DAC output powers on to 0 V and remains Programmable voltage and current sources there until valid data is written to the device. Optical networking Automatic test equipment All three parts are pin compatible, which allows users to select Mobile communications the amount of resolution appropriate for their application Programmable attenuators without redesigning their circuit board. Industrial process control FUNCTIONAL BLOCK DIAGRAM V AGND DGND V AB V CD DD REF REF POWER-ON AD5348 RESET BUF INPUT DAC STRING REGISTER REGISTER GAIN BUFFER V A DAC A OUT DB11 INPUT DAC . STRING . BUFFER V B REGISTER REGISTER OUT DAC B . DB0 INPUT DAC STRING V C BUFFER REGISTER REGISTER OUT DAC C INTER- CS INPUT DAC STRING V D BUFFER FACE OUT REGISTER REGISTER DAC D RD LOGIC INPUT DAC STRING WR REGISTER BUFFER V E REGISTER DAC E OUT DAC INPUT STRING REGISTER BUFFER V F A2 REGISTER OUT DAC F INPUT DAC A1 STRING BUFFER V G REGISTER REGISTER OUT DAC G A0 DAC INPUT STRING REGISTER BUFFER V H REGISTER OUT DAC H CLR POWER-DOWN LDAC LOGIC V GH V EF REF REF PD Figure 1. 1 Protected by U.S. Patent No. 5,969,657. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. 03331-0-001 AD5346/AD5347/AD5348 TABLE OF CONTENTS Specifications..................................................................................... 3 Power-On Reset.......................................................................... 17 AC Characteristics............................................................................ 4 Power-Down Mode.................................................................... 17 Timing Characteristics..................................................................... 5 Suggested Data Bus Formats..................................................... 18 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 19 ESD Caution.................................................................................. 6 Typical Application Circuits ..................................................... 19 AD5346 Pin Configurations and Function Descriptions ........... 7 Driving V from the Reference Voltage................................. 19 DD AD5347 Pin Configurations and Function Descriptions ........... 8 Bipolar Operation Using the AD5346/AD5347/AD5348..... 19 AD5348 Pin Configurations and Function Descriptions ........... 9 Decoding Multiple AD5346/AD5347/AD5348s.................... 20 Terminology .................................................................................... 10 AD5346/AD5347/AD5348 as Digitally Programmable Window Detectors ...................................................................... 20 Typical Performance Characteristics ........................................... 12 Programmable Current Source ................................................ 20 Functional Description .................................................................. 16 Coarse and Fine Adjustment Using the Digital-to-Analog Section ......................................................... 16 AD5346/AD5347/AD5348 ....................................................... 21 Resistor String............................................................................. 16 Power Supply Bypassing and Grounding................................ 21 DAC Reference Input................................................................. 16 Outline Dimensions ....................................................................... 23 Output Amplifier........................................................................ 16 Ordering Guides......................................................................... 24 Parallel Interface ......................................................................... 17 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD5346/AD5347/AD5348 SPECIFICATIONS Table 1. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted 1 B Version 2 Parameter Min Typ Max Unit Conditions/Comments 3,4 DC PERFORMANCE AD5346 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5347 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5348 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.1 ±1 % of FSR 5 Lower Deadband 10 60 mV Lower deadband exists only if offset error is negative 5 Upper Deadband 10 60 mV V = 5 V; upper deadband exists only if V = V DD REF DD 6 Offset Error Drift –12 ppm of FSR/°C 6 Gain Error Drift –5 ppm of FSR/°C DC Power Supply Rejection –60 dB ∆VDD = ±10% 6 Ratio 6 DC Crosstalk 200 µV R = 2 kΩ to GND, 2 kΩ to V ; C = 200 pF to GND; L DD L Gain = +1 6 DAC REFERENCE INPUT V Input Range 1 V V Buffered reference mode REF DD VREF Input Range 0.25 VDD V Unbuffered reference mode VREF Input Impedance >10 MΩ Buffered reference mode and power-down mode 90 kΩ Gain = +1; input impedance = RDAC 45 kΩ Gain = +2; input impedance = R DAC Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –75 dB Frequency = 10 kHz 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-rail operation 4, 7 Maximum Output Voltage V max VDD – 0.001 DC Output Impedance 0.5 Ω Short Circuit Current 25 mA V = 5 V DD 16 mA V = 3 V DD Power-Up Time 2.5 µs Coming out of power-down mode; V = 5 V DD 5 µs Coming out of power-down mode; VDD = 3 V LOGIC INPUTS6 Input Current ±1 µA VIL, Input Low Voltage 0.8 V VDD = 5 V ±10% 0.7 V VDD = 3 V ±10% 0.6 V VDD = 2.5 V V , Input High Voltage 1.7 V V = 2.5 V to 5.5 V IH DD Pin Capacitance 5 pF Rev. 0 | Page 3 of 24 AD5346/AD5347/AD5348 1 B Version 2 Parameter Min Typ Max Unit Conditions/Comments 6 LOGIC OUTPUTS V = 4.5 V to 5.5 V DD Output Low Voltage, V 0.4 V I = 200 µA OL SINK Output High Voltage, V V – 1 V I = 200 µA OH DD SOURCE VDD = 2.5 V to 3.6 V Output Low Voltage, VOL 0.4 V ISINK = 200 µA Output High Voltage, VOH VDD – 0.5 V ISOURCE = 200 µA POWER REQUIREMENTS VDD 2.5 5.5 V IDD (Normal Mode) VIH = VDD, VIL = GND V = 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode, DD V = 2.5 V to 3.6 V 0.8 1.4 mA extra current is typically x µA per DAC, where x = 5 µA + DD VREF/RDAC IDD (Power-Down Mode) VIH = VDD, VIL = GND VDD = 4.5 V to 5.5 V 0.4 1 µA V = 2.5 V to 3.6 V 0.12 1 µA DD See footnotes after the AC Characteristics table. 6 AC CHARACTERISTICS Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted 1 B Version 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = 2 V AD5346 6 8 µs 1/4 scale to 3/4 scale change (40 H to C0 H) AD5347 7 9 µs 1/4 scale to 3/4 scale change (100 H to 300 H) AD5348 8 10 µs 1/4 scale to 3/4 scale change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch 8 nV-s 1 LSB change around major carry Energy Digital Feedthrough 0.5 nV-s Digital Crosstalk 1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ±0.1 V p-p; unbuffered mode Total Harmonic Distortion –70 dB VREF = 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode 1 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 2 See Terminology section. 3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V = V and REF DD the offset plus gain error must be positive. 200µA I OL TO OUTPUT V (min) + V (max) OH OL PIN C L 2 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 4 of 24 03331-0-002 AD5346/AD5347/AD5348 1, 2, 3 TIMING CHARACTERISTICS Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted Parameter Limit at T , T Unit Condition/Comments MIN MAX Data Write Mode (Figure 3) t 0 ns min CS to WR setup time 1 CS to WR hold time t2 0 ns min t3 20 ns min WR pulse width t4 5 ns min Data, GAIN, BUF setup time t 4.5 ns min Data, GAIN, BUF hold time 5 t 5 ns min Synchronous mode. WR falling to LDAC falling. 6 Synchronous mode. LDAC falling to WR rising. t7 5 ns min WR t8 4.5 ns min Synchronous mode. rising to LDAC rising. Asynchronous mode. LDAC rising to WR rising. t9 5 ns min t10 4.5 ns min Asynchronous mode. WR rising to LDAC falling. t 20 ns min LDAC pulse width 11 CLR t12 10 ns min pulse width t 20 ns min Time between WR cycles 13 t 20 ns min A0, A1, A2 setup time 14 t15 0 ns min A0, A1, A2 hold time Data Readback Mode (Figure 4) CS t16 0 ns min A0, A1, A2 to setup time t17 0 ns min A0, A1, A2 to CS hold time RD t18 0 ns min CS to falling edge of RD pulse width; V = 3.6 V to 5.5 V t19 20 ns min DD 30 ns min RD pulse width; VDD = 2.5 V to 3.6 V CS to RD hold time t20 0 ns min t 22 ns max Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V 21 Data access time after falling edge of RD V = 2.5 V to 3.6 V 30 ns max DD t22 4 ns min Bus relinquish time after rising edge of RD 30 ns max CS falling edge to data; V = 3.6 V to 5.5 V t23 22 ns max DD 30 ns max CS falling edge to data; VDD = 2.5 V to 3.6 V RD t24 30 ns min Time between cycles t 30 ns min Time from RD to WR 25 Time from WR to RD, V = 3.6 V to 5.5 V t26 30 ns min DD 50 ns min Time from WR to RD, VDD = 2.5 V to 3.6 V 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. t t 1 2 CS A0–A2 t t 3 13 t 17 t 16 WR t CS t 5 4 DATA, t t 18 20 GAIN, BUF t t 19 24 t 6 t 8 t 7 RD 1 LDAC t t t t 21 22 9 10 t 11 2 LDAC DATA t t 23 12 CLR t 25 t t 14 15 WR A0–A2 t 26 NOTES 1. SYNCHRONOUS LDAC UPDATE MODE 2. ASYNCHRONOUS LDAC UPDATE MODE Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram Rev. 0 | Page 5 of 24 03331-0-003 03331-0-004 AD5346/AD5347/AD5348 ABSOLUTE MAXIMUM RATINGS Table 4. TA = 25°C, unless otherwise noted Parameter Rating V to GND –0.3 V to +7 V DD Digital Input Voltage to GND –0.3 V to V + 0.3 V DD Digital Output Voltage to GND –0.3 V to V + 0.3 V DD Reference Input Voltage to GND –0.3 V to VDD + 0.3 V VOUT to GND –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) –40°C to +105°C Storage Temperature Range –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings Junction Temperature 150°C may cause permanent damage to the device. This is a stress 38-Lead TSSOP Package rating only; functional operation of the device at these or any Power Dissipation (TJ max − TA)/ θJA mW other conditions above those listed in the operational sections θ Thermal Impedance 98.3°C/W JA of this specification is not implied. Exposure to absolute θ Thermal Impedance 8.9°C/W JC maximum rating conditions for extended periods may affect 40-Lead LFCSP Package device reliability. Power Dissipation (TJ max − TA)/ θJA mW θJA Thermal Impedance (3-layer 29.6°C/W board) Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD5346/AD5347/AD5348 AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V GH 1 38 PD REF V EF 2 37 REF CLR V CD 3 36 REF 40 39 38 37 36 35 34 33 32 31 GAIN 4 35 V V A DD WR 1 30 OUT RD V AB 5 34 REF V B 2 29 RD CS OUT V A 6 33 OUT 8-BIT CS V C 3 28 DB OUT 7 7 AD5346 32 V B DB OUT 7 V D 4 27 DB OUT 6 TOP VIEW 8-BIT 8 31 V C DB OUT 6 (Not to Scale) AGND 5 26 DB 5 AD5346 9 30 V D DB OUT 5 AGND 6 25 DB TOP VIEW 4 10 29 DB AGND 4 (Not to Scale) V E 7 24 DB OUT 3 V E 11 28 DB 3 OUT V F 8 23 DB OUT 2 DB V F 12 27 2 OUT V G 9 22 DB OUT 1 DB 13 26 1 V G OUT V H 10 21 DB OUT 0 DB 14 25 V H 0 OUT 11 12 13 14 15 16 17 18 19 20 DGND DGND 15 24 BUF 16 23 DGND DGND 17 22 LDAC DGND 18 21 A0 Figure 6. AD5346 Pin Configuration—LFCSP A1 19 20 A2 Figure 5. AD5346 Pin Configuration—TSSOP Table 5. AD5346 Pin Function Descriptions Pin Number TSSOP LFCSP Mnemonic Function 1 35 VREFGH Reference Input for DACs G and H. 2 36 VREFEF Reference Input for DACs E and F. 3 37 V CD Reference Input for DACs C and D. REF 4 38, 39 V Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled DD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. 5 40 VREFAB Reference Input for DACs A and B. 6–9, 1–4, V X Output of DAC X. Buffered output with rail-to-rail operation. OUT 11–14 7–10 10 5, 6 AGND Analog Ground. Ground reference for analog circuitry. 15, 11, DGND Digital Ground. Ground reference for digital circuitry. 21–24 17–20 16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. 17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. 18 14 A0 LSB Address Pin. Selects which DAC is to be written to. 19 15 A1 Address Pin. Selects which DAC is to be written to. 20 16 A2 MSB Address Pin. Selects which DAC is to be written to. 25–32 21–28 DB –DB Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. 0 7 33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. 34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. 35 31 WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. 36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF. 37 33 CLR Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. 38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. Rev. 0 | Page 7 of 24 03331-0-005 DGND V AB REF BUF V DD V LDAC DD A0 V CD REF A1 V EF REF A2 V GH REF DGND PD DGND CLR DGND GAIN WR DGND 03331-0-006 AD5346/AD5347/AD5348 AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V GH 1 38 PD REF V EF 2 37 CLR REF V CD REF 3 36 40 39 38 37 36 35 34 33 32 31 GAIN V 4 35 V A DD WR 1 30 OUT RD V AB 5 34 REF V B 2 29 RD CS OUT V A OUT 6 33 10-BIT CS V C 3 28 DB OUT 9 AD5347 V B 7 32 DB OUT 9 V D 4 27 DB OUT 8 10-BIT TOP VIEW V C 8 31 DB OUT 8 AGND 5 26 DB (Not to Scale) 7 AD5347 V D 9 30 DB OUT 7 AGND 6 25 DB TOP VIEW 6 10 29 DB AGND 6 (Not to Scale) V E 7 24 DB OUT 5 11 28 DB V E 5 OUT V F 8 23 DB OUT 4 12 27 DB V F 4 OUT V G 9 22 DB OUT 3 DB 13 26 V G 3 OUT V H 10 21 DB OUT 2 DB 14 25 V H 2 OUT 11 12 13 14 15 16 17 18 19 20 DGND 15 24 DB 1 BUF 16 23 DB 0 DGND 17 22 LDAC 18 21 DGND A0 Figure 8. AD5347 Pin Configuration—LFCSP 19 20 A2 A1 Figure 7. AD5347 Pin Configuration—TSSOP Table 6. AD5347 Pin Function Descriptions Pin Number TSSOP LFCSP Mnemonic Function 1 35 V GH Reference Input for DACs G and H. REF 2 36 VREFEF Reference Input for DACs E and F. 3 37 VREFCD Reference Input for DACs C and D. 4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V pins on the LFCSP package DD must be at the same potential. 5 40 V AB Reference Input for DACs A and B. REF 6–9, 1–4, VOUTX Output of DAC X. Buffered output with rail-to-rail operation. 11–14 7–10 10 5, 6 AGND Analog Ground. Ground reference for analog circuitry. 15, 21–22 11, DGND Digital Ground. Ground reference for digital circuitry. 17–18 16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. 17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. 18 14 A0 LSB Address Pin. Selects which DAC is to be written to. 19 15 A1 Address Pin. Selects which DAC is to be written to. 20 16 A2 MSB Address Pin. Selects which DAC is to be written to. 23–32 19–28 DB0–DB9 Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits. 33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. 34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. 35 31 WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. 36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 37 33 CLR Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. 38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. Rev. 0 | Page 8 of 24 03331-0-007 DGND V AB REF BUF V DD V LDAC DD A0 V CD REF A1 V EF REF A2 V GH REF DGND PD DGND CLR DB GAIN 0 WR DB 1 03331-0-008 AD5346/AD5347/AD5348 AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V GH 1 38 PD REF V EF 2 37 CLR REF V CD REF 3 36 40 39 38 37 36 35 34 33 32 31 GAIN V 4 35 V A DD WR 1 30 OUT RD V AB 5 34 REF V B 2 29 RD CS OUT V A OUT 6 33 12-BIT CS V C 3 28 DB OUT 11 AD5348 V B 7 32 DB OUT 11 V D 4 27 DB OUT 10 12-BIT TOP VIEW V C 8 31 DB OUT 10 AGND 5 26 DB (Not to Scale) 9 AD5348 V D 9 30 DB OUT 9 AGND 6 25 DB TOP VIEW 8 10 29 DB AGND 8 (Not to Scale) V E 7 24 DB OUT 7 11 28 DB V E 7 OUT V F 8 23 DB OUT 6 12 27 DB V F 6 OUT V G 9 22 DB OUT 5 DB 13 26 V G 5 OUT V H 10 21 DB OUT 4 DB 14 25 V H 4 OUT 11 12 13 14 15 16 17 18 19 20 DGND 15 24 DB 3 BUF 16 23 DB 2 DB 17 22 LDAC 1 18 21 DB A0 0 Figure 10. AD5348 Pin Configuration—LFCSP 19 20 A2 A1 Figure 9. AD5348 Pin Configuration—TSSOP Table 7. AD5348 Pin Function Descriptions Pin Number TSSOP LFCSP Mnemonic Function 1 35 V GH Reference Input for DACs G and H. REF 2 36 VREFEF Reference Input for DACs E and F. 3 37 VREFCD Reference Input for DACs C and D. 4 38, 39 VDD Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V pins on the LFCSP package must be at DD the same potential. 5 40 V AB Reference Input for DACs A and B. REF 6–9, 1–4, VOUTX Output of DAC X. Buffered output with rail-to-rail operation. 11–14 7–10 10 5, 6 AGND Analog Ground. Ground reference for analog circuitry. 15 11 DGND Digital Ground. Ground reference for digital circuitry. 16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. 17 13 LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. 18 14 A0 LSB Address Pin. Selects which DAC is to be written to. 19 15 A1 Address Pin. Selects which DAC is to be written to. 20 16 A2 MSB Address Pin. Selects which DAC is to be written to. 21–32 17–28 DB –DB Twelve Parallel Data Inputs. DB is the MSB of these 12 bits. 0 11 11 33 29 CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. 34 30 RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. 35 31 WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. 36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 37 33 Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. CLR 38 34 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. Rev. 0 | Page 9 of 24 03331-0-009 DGND V AB REF BUF V DD V LDAC DD A0 V CD REF A1 V EF REF A2 V GH REF DB PD 0 DB CLR 1 DB GAIN 2 WR DB 3 03331-0-010 AD5346/AD5347/AD5348 TERMINOLOGY Relative Accuracy GAIN ERROR For the DAC, relative accuracy or integral nonlinearity (INL) is AND OFFSET a measure of the maximum deviation, in LSBs, from a straight ERROR line passing through the actual endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 14, ACTUAL Figure 15, and Figure 16. Differential Nonlinearity OUTPUT VOLTAGE Differential nonlinearity (DNL) is the difference between the IDEAL measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be POSITIVE seen in Figure 17, Figure 18, and Figure 19. OFFSET Gain Error DAC CODE This is a measure of the span error of the DAC, including any Figure 12. Positive Offset Error and Gain Error error in the gain of the buffer amplifier. It is the deviation in slope of the actual DAC transfer characteristic from the ideal and is expressed as a percentage of the full-scale range. This is GAIN ERROR illustrated in Figure 11. AND OFFSET ERROR Offset Error IDEAL This is a measure of the offset error of the DAC and the output OUTPUT VOLTAGE amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage still positive at ACTUAL zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier NEGATIVE DAC CODE OFFSET footroom). Below this code there is a dead band over which the output voltage does not change. This is illustrated in Figure 13. POSITIVE GAIN ERROR DEADBAND CODES AMPLIFIER NEGATIVE ACTUAL FOOTROOM GAIN ERROR (~1mV) OUTPUT VOLTAGE NEGATIVE OFFSET IDEAL Figure 13. Negative Offset Error and Gain Error DAC CODE Figure 11. Gain Error Rev. 0 | Page 10 of 24 03331-0-011 03331-0-012 03331-0-013 AD5346/AD5347/AD5348 Offset Error Drift Digital Crosstalk This is a measure of the change in offset error with changes in This is the glitch impulse transferred to the output of one DAC temperature. It is expressed in (ppm of full-scale range)/°C. at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is Gain Error Drift expressed in nV-s. This is a measure of the change in gain error with changes in Analog Crosstalk temperature. It is expressed in (ppm of full-scale range)/°C. This is the glitch impulse transferred to the output of one DAC DC Power-Supply Rejection Ratio (PSRR) due to a change in the output of another DAC. It is measured by This indicates how the output of the DAC is affected by changes loading one of the input registers with a full-scale code change in the supply voltage. PSRR is the ratio of the change in V to OUT LDAC (all 0s to all 1s and vice versa) while keeping high. Then a change in V for full-scale output of the DAC. It is measured DD LDAC pulse low and monitor the output of the DAC whose in dB. V is held at 2 V and V is varied ±10%. REF DD digital code was not changed. The area of the glitch is expressed DC Crosstalk in nV-s. This is the dc change in the output level of one DAC at midscale DAC-to-DAC Crosstalk in response to a full-scale code change (all 0s to all 1s and vice This is the glitch impulse transferred to the output of one DAC versa) and output change of another DAC. It is expressed in µV. due to a digital code change and subsequent output change of Reference Feedthrough another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code This is the ratio of the amplitude of the signal at the DAC change (all 0s to all 1s and vice versa) with the LDAC pin set output to the reference input when the DAC output is not being LDAC low and monitoring the output of another DAC. The energy of updated, i.e., is high. It is expressed in dB. the glitch is expressed in nV-s. Channel-to-Channel Isolation Multiplying Bandwidth This is a ratio of the amplitude of the signal at the output of one The amplifiers within the DAC have a finite bandwidth. The DAC to a sine wave on the reference inputs of the other DACs. multiplying bandwidth is a measure of this. A sine wave on the It is measured by grounding one V pin and applying a 10 kHz, REF reference (with full-scale code loaded to the DAC) appears on 4 V p-p sine wave to the other V pins. It is expressed in dB. REF the output. The multiplying bandwidth is the frequency at Major-Code Transition Glitch Energy which the output amplitude falls to 3 dB below the input. This is the energy of the impulse injected into the analog output Total Harmonic Distortion (THD) when the DAC changes state. It is normally specified as the area This is the difference between an ideal sine wave and its of the glitch in nV-s and is measured when the digital code is attenuated version using the DAC. The sine wave is used as the changed by 1 LSB at the major carry transition (011 . . . 11 to reference for the DAC, and the THD is a measure of the 100 . . . 00 or 100 . . . 00 to 011 . . . 11). harmonics present on the DAC output. It is measured in dB. Digital Feedthrough This is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but it is CS measured when the DAC is not being written to, held high. It is specified in nV-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. Rev. 0 | Page 11 of 24 AD5346/AD5347/AD5348 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 14. AD5346 Typical INL Plot Figure 17. AD5346 Typical DNL Plot 3 0.6 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.4 2 0.2 1 0 0 –0.2 –1 –2 –0.4 –3 –0.6 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 15. AD5347 Typical INL Plot Figure 18. AD5347 Typical DNL Plot 12 1.0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 8 0.5 4 0 0 –4 –0.5 –8 –12 –1.0 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE CODE Figure 16. AD5348 Typical INL Plot Figure 19. AD5348 Typical DNL Plot Rev. 0 | Page 12 of 24 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 03331-0-015 03331-0-016 03331-0-014 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 03331-0-019 03331-0-018 03331-0-017 AD5346/AD5347/AD5348 0.5 0.2 V = 5V DD T = 25°C A 0.4 T = 25°C A V = 2V REF 0.1 MAX INL 0.3 0 GAIN ERROR 0.2 MAX DNL –0.1 0.1 0 –0.2 –0.1 MIN DNL –0.3 –0.2 MIN INL –0.4 OFFSET ERROR –0.3 –0.5 –0.4 –0.5 –0.6 01 2 3 4 5 0 1 2 3 45 6 V (V) V (V) REF DD Figure 20. AD5346 INL and DNL Error vs. VREF Figure 23. Offset Error and Gain Error vs. VDD 0.5 5 V = 5V DD 0.4 V = 2V REF MAX INL 5V SOURCE 0.3 4 0.2 3V SOURCE MAX DNL 0.1 3 0 2 –0.1 MIN DNL –0.2 –0.3 1 3V SINK 5V SINK –0.4 MIN INL –0.5 0 –40 –204 0 200 60 80 100 0 1 2 3 45 6 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 21. AD5346 INL and DNL Error vs. Temperature Figure 24. VOUT Source and Sink Current Capability 1.0 1.0 V = 5V DD V = 2V 0.9 REF V = 5V DD 0.8 T = 25°C A 0.5 0.7 0.6 0 0.5 OFFSET ERROR 0.4 0.3 –0.5 0.2 GAIN ERROR 0.1 –1.0 0 –40 –20 0 20 40 60 80 100 ZERO SCALE HALF SCALE FULL SCALE TEMPERATURE (°C) DAC CODE Figure 22. AD5346 Offset Error and Gain Error vs. Temperature Figure 25. Supply Current vs. DAC Code Rev. 0 | Page 13 of 24 ERROR (% FSR) ERROR (LSB) ERROR (LSB) 03331-0-033 03331-0-032 03331-0-031 I (mA) V (V) ERROR (% FSR) DD OUT 03331-0-036 03331-0-035 03331-0-034 AD5346/AD5347/AD5348 1.4 T = 25°C V = 2V REF A V = 5V GAIN = 1 UNBUFFERED DD V = 5V 1.2 REF T = –40°C A T = +25°C A 1.0 V A OUT 0.8 T = +105°C A CH1 0.6 LDAC CH2 0.4 0.2 0 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Figure 29. Half-Scale Settling (¼ to ¾ Scale Code) Figure 26. Supply Current vs. Supply Voltage 1.0 T = 25°C A 0.9 V = 5V T = 25°C A DD V = 2V REF 0.8 CH1 0.7 V DD 0.6 0.5 0.4 V A OUT 0.3 CH2 0.2 0.1 0 CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DD Figure 30. Power-On Reset to 0 V Figure 27. Power-Down Current vs. Supply Voltage 2.5 T = 25°C A V = 5V DD 2.0 V 1 OUT CH2 1.5 1.0 PD V = 3V DD 0.5 CH1 0 CH1 2.00V, CH2 1.00V, TIME BASE = 20µs/DIV 0 1 2 3 4 5 VLOGIC (V) Figure 31. Exiting Power-Down to Midscale Figure 28. Supply Current vs. Logic Input Voltage Rev. 0 | Page 14 of 24 I POWER-DOWN (µA) DD I (mA) I (mA) DD DD 03331-0-039 03331-0-037 03331-0-038 03331-0-042 03331-0-041 03331-0-040 AD5346/AD5347/AD5348 21 0.02 V = 5V DD T = 25°C A 18 0.01 15 V = 3V V = 5V DD DD 12 0 9 6 –0.01 3 –0.02 0 0 1 2 3 45 6 0.6 0.8 1.0 1.2 1.4 V (V) REF I (mA) DD Figure 35. Full-Scale Error vs. VREF Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V 2.50 1.999 2.49 1.998 2.48 1.997 1.996 2.47 1µs/DIV Figure 36. DAC-to-DAC Crosstalk Figure 33. AD5348 Major Code Transition Glitch Energy 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 34. Multiplying Bandwidth (Small Signal Frequency Response) Rev. 0 | Page 15 of 24 V (V) FREQUENCY OUT dB 03331-0-045 03331-0-044 03331-0-043 FULL-SCALE ERROR (V) 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 511 03331-0-047 03331-0-046 AD5346/AD5347/AD5348 FUNCTIONAL DESCRIPTION V REF The AD5346/AD5347/AD5348 are octal resistor-string DACs R fabricated by a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. R They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers offer rail-to-rail output swing. The gain TO OUTPUT R AMPLIFIER of the buffer amplifiers can be set to 1 or 2 to give an output voltage range of 0 V to V or 0 V to 2 × V The AD5346/ REF REF. AD5347/AD5348 have reference inputs that may be buffered to draw virtually no current from the reference source. The devices R have a power-down feature that reduces current consumption R to only 100 nA @ 3 V. DIGITAL-TO-ANALOG SECTION Figure 38. Resistor String The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer DAC REFERENCE INPUT amplifier. The voltage at the VREF pin provides the reference The DACs operate with an external reference. The AD5346/ voltage for the DAC. Figure 37 shows a block diagram of the AD5347/AD5348 have a reference input for each pair of DACs. DAC architecture. Because the input coding to the DAC is The reference inputs may be configured as buffered or straight binary, the ideal output voltage is given by unbuffered. This option is controlled by the BUF pin. D VOUT= VREF× ×Gain In buffered mode (BUF = 1), the current drawn from an N 2 external reference voltage is virtually zero because the imped- ance is at least 10 MΩ. The reference input range is 1 V to VDD. where: In unbuffered mode (BUF = 0), the user can have a reference D is the decimal equivalent of the binary code, which is loaded voltage as low as 0.25 V and as high as V because there is no DD to the DAC register: restriction due to headroom and footroom of the reference 0–255 for AD5346 (8 bits) amplifier. The impedance is still large at typically 90 kΩ for 0 V 0–1023 for AD5347 (10 bits) to VREF mode and 45 kΩ for 0 V to 2 × VREF mode. 0–4095 for AD5348 (12 bits) N is the DAC resolution. If using an external buffered reference (such as REF192), there Gain is the output amplifier gain (1 or 2). is no need to use the on-chip buffer. V AB REF OUTPUT AMPLIFIER The output buffer amplifier is capable of generating output REFERENCE BUF BUFFER voltages to within 1 mV of either rail. Its actual range depends (GAIN = +1 OR +2) on VREF, GAIN, the load on VOUT, and offset error. If a gain of +1 is selected (GAIN = 0), the output range is DAC RESISTOR INPUT V A OUT REGISTER REGISTER STRING 0.001 V to V . REF OUTPUT If a gain of +2 is selected (GAIN = +1), the output range is BUFFER AMPLIFIER 0.001 V to 2 × V . However, because of clamping, the REF Figure 37. Single DAC Channel Architecture maximum output is limited to V – 0.001 V. DD RESISTOR STRING The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source The resistor string section is shown in Figure 38. It is simply a and sink capabilities of the output amplifier can be seen in string of resistors, each of value R. The digital code loaded to Figure 24. the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB voltage is tapped off by closing one of the switches connecting (at 8 bits) of 6 s with the output unloaded. See Figure 29. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. 0 | Page 16 of 24 03331-0-020 03331-0-021 AD5346/AD5347/AD5348 where I = cvf and PARALLEL INTERFACE DYNAMIC c = capacitance or the data bus The AD5346/AD5347/AD5348 load their data as a single 8-, v = V DD 10-, or 12-bit word. f = readback frequency Double-Buffered Interface Load DAC Input (LDAC) The AD5346/AD5347/AD5348 DACs all have double-buffered LDAC transfers data from the input register to the DAC register, interfaces consisting of an input register and a DAC register. LDAC and therefore updates the outputs. The function enables DAC data, BUF, and GAIN inputs are written to the input regis- double-buffering of the DAC data, GAIN data, and BUF. There ter under control of the Chip Select (CS) and Write (WR) pins. LDAC are two modes: Access to the DAC register is controlled by the LDAC function. • Synchronous Mode. In this mode, the DAC register is LDAC When is high, the DAC register is latched and the input updated after new data is read in on the rising edge of the register may change state without affecting the contents of the WR input. LDAC can be tied permanently low or pulsed as LDAC DAC register. However, when is brought low, the DAC shown in Figure 3. register becomes transparent and the contents of the input • Asynchronous Mode. In this mode, the outputs are not register are transferred to it. The gain and buffer control signals updated at the same time that the input register is written are also double-buffered and are updated only when LDAC is LDAC to. When goes low, the DAC register is updated with taken low. the contents of the input register. This is useful if the user requires simultaneous updating of all POWER-ON RESET DACs and peripherals. The user can write to all input registers The AD5346/AD5347/AD5348 have a power-on reset function, LDAC individually and then, by pulsing the input low, all so that they power up in a defined state. The power-on state is outputs update simultaneously. • Normal operation These parts contain an extra feature whereby the DAC register • Reference input buffered is not updated unless its input register has been updated since • 0 V to VREF output range the last time that LDAC was brought low. Normally, when • Output voltage set to 0 V LDAC is brought low, the DAC registers are filled with the Both input and DAC registers are filled with zeros and remain contents of the input registers. In the case of the AD5346/ so until a valid write sequence is made to the device. This is AD5347/AD5348, the part updates the DAC register only if the particularly useful in applications where it is important to know input register has been changed since the last time the DAC the state of the DAC outputs while the device is powering up. register was updated. This removes unnecessary crosstalk. Clear Input (CLR) POWER-DOWN MODE CLR is an active low, asynchronous clear that resets the input The AD5346/AD5347/AD5348 have low power consumption, and DAC registers. dissipating typically 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when CS Chip Select Input ( ) the DACs are not in use by putting them into power-down CS is an active low input that selects the device. mode, which is selected by taking the PD pin low. Write Input (WR) When the PD pin is high, the DACs work normally with a typi- WR is an active low input that controls writing of data to the cal power consumption of 1 mA at 5 V (0.8 mA at 3 V). In device. Data is latched into the input register on the rising edge power-down mode, however, the supply current falls to 400 nA WR at 5 V (120 nA at 3 V) when the DACs are powered down. Not of . only does the supply current drop, but the output stage is also Read Input (RD) internally switched from the output of the amplifier, making it RD is an active low input that controls when data is read back open-circuit. This has the advantage that the outputs are three- RD from the internal DAC registers. On the falling edge of , data state while the part is in power-down mode, and provides a is shifted onto the data bus. Under the conditions of a high defined input condition for whatever is connected to the outputs capacitive load and high supplies, the user must ensure that the of the DAC amplifiers. The output stage is illustrated in Figure 39. dynamic current remains at an acceptable level, therefore RESISTOR ensuring that the die temperature is within specification. The AMPLIFIER V OUT STRING DAC die temperature can be calculated as POWER-DOWN CIRCUITRY TDIE = TAMBIENT + VDD (IDD + IDYNAMIC)θJA Figure 39. Output Stage During Power-Down Rev. 0 | Page 17 of 24 03331-0-022 AD5346/AD5347/AD5348 The bias generator, the output amplifier, the resistor string, and The AD5347 and AD5348 data bus must be at least 10 and 12 all other associated linear circuitry are all shut down when the bits wide, respectively, and are best suited to a 16-bit data bus power-down mode is activated. However, the contents of the system. registers are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 µs when VDD = Examples of data formats for putting GAIN and BUF on a 3 V. This is the time from a rising edge on the PD pin to when 16-bit data bus are shown in Figure 40. Note that any unused bits above the actual DAC data may be used for GAIN and BUF. the output voltage deviates from its power-down voltage. See Figure 31. AD5347 X X X X BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SUGGESTED DATA BUS FORMATS AD5348 In many applications, the GAIN and BUF pins are hardwired. X X BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 However, if more flexibility is required, they can be included in X = UNUSED BIT a data bus. This enables the user to software program GAIN, Figure 40. AD5347/AD5348 Data Format for Word Load with giving the option of doubling the resolution in the lower half of GAIN and BUF Data on 16-Bit Bus the DAC range. In a bused system, GAIN and BUF may be treated as data inputs because they are written to the device during a write operation and take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. Note that GAIN and BUF are RD not read back during an operation. Table 8. AD5346/AD5347/AD5348 Truth Table CLR LDAC CS WR RD A2 A1 A0 Function 1 1 1 X X X X X No Data Transfer 1 1 X 1 1 X X X No Data Transfer 0 X X X X X X X Clear All Registers 1 1 0 0→1 1 0 0 0 Load DAC A Input Register 1 1 0 1 0 0 1 Load DAC B Input Register 0→1 1 1 0 0→1 1 0 1 0 Load DAC C Input Register 1 1 0 0→1 1 0 1 1 Load DAC D Input Register 1 1 0 1 1 0 0 Load DAC E Input Register 0→1 1 1 0 1 1 0 1 Load DAC F Input Register 0→1 1 1 0 0→1 1 1 1 0 Load DAC G Input Register 1 1 0 0→1 1 1 1 1 Load DAC H Input Register 1 X 0 1 0 0 0 Read Back DAC Register A 1→0 1 X 0 1 1→0 0 0 1 Read Back DAC Register B 1 X 0 1 1→0 0 1 0 Read Back DAC Register C 1 X 0 1 0 1 1 Read Back DAC Register D 1→0 1 X 0 1 1→0 1 0 0 Read Back DAC Register E 1 X 0 1 1→0 1 0 1 Read Back DAC Register F 1 X 0 1 1 1 0 Read Back DAC Register G 1→0 1 X 0 1 1→0 1 1 1 Read Back DAC Register H 1 0 X X 1 X X X Update DAC Registers X X 0 0 0 X X X Invalid Operation X = Don’t Care Rev. 0 | Page 18 of 24 03331-0-048 AD5346/AD5347/AD5348 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS BIPOLAR OPERATION USING THE AD5346/AD5347/AD5348 The AD5346/AD5347/AD5348 can be used with a wide range of reference voltages, especially if the reference inputs are The AD5346/AD5347/AD5348 have been designed for single- configured as unbuffered, in which case the devices offer full, supply operation, but a bipolar output range is also possible by one-quadrant multiplying capability over a reference range of using the circuit shown in Figure 43. This circuit has an output 0.25 V to VDD. More typically, these devices may be used with a voltage range of ±5 V. Rail-to-rail operation at the amplifier fixed, precision reference voltage. Figure 41 shows a typical output is achievable using an AD820, an AD8519, or an OP196 setup for the devices when using an external reference as the output amplifier. connected to the reference inputs. Suitable references for 5 V 5V operation are the AD780, ADR381, and REF192 (2.5 V refer- R4 20kΩ ences). For 2.5 V operation, suitable external references are the 0.1µF 10µF AD589 and the AD1580 (1.2 V band gap references). +5V R3 10kΩ V = 2.5V to 5.5V DD V IN ±5V V DD EXT AD820/AD8519/ V * V OUT REF REF OP196 0.1µF 10µF –5V 0.1µF AD5346/AD5347/ GND R1 AD5348 10kΩ V IN V * OUT V DD EXT V V * R2 OUT REF REF V * OUT 20kΩ GND GND AD5346/AD5347/ AD5348 *ONLY ONE CHANNEL OF V AND V SHOWN AD780/ADR381/REF192 REF OUT WITH V = 5V DD OR AD589/AD1580 WITH GND Figure 43. Bipolar Operation with the AD5346/ AD5347/AD5348 V = 2.5V DD *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT The output voltage for any input code can be calculated as follows: Figure 41. AD5346/AD5347/AD5348 Using an External Reference N VOUT = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2 )] – DRIVING V FROM THE REFERENCE VOLTAGE DD R4 × VREF/R3 If an output range of 0 V to VDD is required, the simplest where: solution is to connect the reference inputs to VDD. Because this supply may not be very accurate and may be noisy, the devices D is the decimal equivalent of the code loaded to the DAC. can be powered from the reference voltage, for example, by N is the DAC resolution. using a 5 V reference such as the ADM663 or ADM666, as V is the reference voltage input. REF shown in Figure 42. with: 6V TO 16V VREF = 5 V 10µF 0.1µF R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ V IN V = 5 V DD ADM663/ADM666 GAIN = 2 SENSE V EXT DD V * REF V OUT OUT(2) V * REF N V = (10 × D/2 ) – 5 OUT 0.1µF GND VSET GND SHDN AD5346/AD5347/ AD5348 GND *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT Figure 42. Using an ADM663/ADM666 as Power and Reference to the AD5346/AD5347/AD5348 Rev. 0 | Page 19 of 24 03331-0-025 03331-0-024 03331-0-026 AD5346/AD5347/AD5348 5V DECODING MULTIPLE AD5346/AD5347/AD5348s 0.1µF 10µF 1kΩ 1kΩ V IN FAIL PASS The CS pin on these devices can be used in applications to V DD V V AB REF REF decode a number of DACs. In this application, all DACs in the V A OUT WR CS system receive the same data and pulses, but only the to PASS/ 1/2 AD5346/AD5347/ FAIL CMP04 one of the DACs will be active at any one time, so data will only AD5348 CS be written to the DAC whose is low. V B OUT 1/6 74HC05 GND The 74HC139 is used as a 2-line to 4-line decoder to address Figure 45. Programmable Window Detector any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive PROGRAMMABLE CURRENT SOURCE state while the coded address inputs are changing state. Figure 46 shows the AD5346/AD5347/AD5348 used as the Figure 44 shows a diagram of a typical setup for decoding control element of a programmable current source. In this multiple devices in a system. Once data has been written example, the full-scale current is set to 1 mA. The output sequentially to all DACs in a system, all the DACs can be voltage from the DAC is applied across the current setting LDAC updated simultaneously using a common line. A com- resistor of 4.7 kΩ in series with the 470 Ω adjustment CLR mon line can also be used to reset all DAC outputs to 0 V. potentiometer, which gives an adjustment of about ±5%. AD5346/AD5347 Suitable transistors to place in the feedback loop of the ampli- A0 A0 /AD5348 A1 fier include the BC107 and the 2N3904, which enable the A1 A2 A2 current source to operate from a minimum VSOURCE of 6 V. The WR WR DATA LDAC LDAC INPUTS operating range is determined by the operating characteristics CLR CLR CS of the transistor. Suitable amplifiers include the AD820 and the AD5346/AD5347 OP295, both having rail-to-rail operation on their outputs. The /AD5348 A0 current for any digital input code and resistor value can be A1 A2 calculated as follows: WR DATA LDAC INPUTS V DD CLR D CS I= G×VREF mA N V CC (2 × R) 1G AD5346/AD5347 1Y0 ENABLE /AD5348 A0 1A 1Y1 A1 CODED where: 74HC139 ADDRESS A2 1Y2 1B WR DATA INPUTS LDAC 1Y3 G is the gain of the buffer amplifier (1 or 2). CLR DGND CS D is the digital input code. AD5346/AD5347 N is the DAC resolution (8, 10, or 12 bits). /AD5348 A0 R is the sum of the resistor plus adjustment potentiometer in kΩ. A1 A2 WR DATA V = 5V DD LDAC INPUTS CLR CS 0.1µF 10µF Figure 44. Decoding Multiple DAC Devices V SOURCE AD5346/AD5347/AD5348 AS DIGITALLY V IN 5V LOAD PROGRAMMABLE WINDOW DETECTORS V DD EXT V V*V * OUT REF OUT REF A digitally programmable upper/lower limit detector using two 0.1µF AD5346/AD5347/ GND of the DACs in the AD5346/AD5347/AD5348 is shown in AD5348 Figure 45. Any pair of DACs in the device may be used, but for simplicity the description refers to DACs A and B. 4.7kΩ The upper and lower limits for the test are loaded to DACs A GND 470Ω and B which, in turn, set the limits on the CMP04. If a signal at *ONLY ONE CHANNEL OF V AND V SHOWN the VIN input is not within the programmed window, an LED REF OUT indicates the fail condition. Figure 46. Programmable Current Source Rev. 0 | Page 20 of 24 DATA BUS 03331-0-027 03331-0-028 03331-0-029 AD5346/AD5347/AD5348 COARSE AND FINE ADJUSTMENT USING POWER SUPPLY BYPASSING AND GROUNDING THE AD5346/AD5347/AD5348 In any circuit where accuracy is important, careful consideration Two of the DACs in the AD5346/AD5347/AD5348 can be of the power supply and ground return layout helps to ensure paired together to form a coarse and fine adjustment function, the rated performance. as shown in Figure 47. As with the window comparator The printed circuit board on which the AD5346/AD5347/ previously described, the description refers to DACs A and B. AD5348 is mounted should be designed so that the analog and DAC A provides the coarse adjustment, while DAC B provides digital sections are separated and are confined to certain areas the fine adjustment. Varying the ratio of R1 and R2 changes the of the board. This facilitates the use of ground planes that can relative effect of the coarse and fine adjustments. With the be separated easily. A minimum etch technique is generally best resistor values shown, the output amplifier has unity gain for for ground planes because it gives the best shielding. Digital and the DAC A output, so the output range is 0 V to (V – 1 LSB). REF analog ground planes should be joined in one place only. If the –3 For DAC B, the amplifier has a gain of 7.6 × 10 , giving DAC B AD5346/AD5347/AD5348 is the only device requiring an a range equal to 2 LSBs of DAC A. AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5346/ The circuit is shown with a 2.5 V reference, but reference AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a voltages up to VDD may be used. The op amps indicated allow a system where multiple devices require AGND-to-DGND rail-to-rail output swing. connections, the connection should be made at one point only, a V = 5V DD star ground point that should be established as close as possible R4 R3 390Ω 51.2kΩ to the AD5346/AD5347/AD5348. 0.1µF 10µF 5V The AD5346/AD5347/AD5348 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located V DD V V OUT IN as close to the package as possible, ideally right up against the A V OUT EXT R1 V V AB device. The 10 µF capacitors are the tantalum bead type. The REF OUT REF 390Ω 0.1µF AD5346/AD5347/ 0.1 µF capacitor should have low effective series resistance GND R2 AD5348 (ESR) and effective series inductance (ESI), such as the 51.2kΩ V B OUT common ceramic types that provide a low impedance path to AD780/ADR381/REF192 WITH V = 5V DD ground at high frequencies to handle transient currents due to GND internal logic switching. Figure 47. Coarse and Fine Adjustment The power supply lines of the device should use the largest trace possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. Rev. 0 | Page 21 of 24 03331-0-030 AD5346/AD5347/AD5348 Table 9. Overview of AD53xx Parallel Devices Additional Pin Functions Part No. Resolution DNL V Pins Settling Time BUF GAIN HBEN CLR Package Pins REF SINGLES AD5330 8 ±0.25 1 6 µs TSSOP 20 9 9 9 AD5331 10 ±0.5 1 7 µs 9 9 TSSOP 20 AD5340 12 ±1.0 1 8 µs 9 9 9 TSSOP 24 AD5341 12 ±1.0 1 8 µs TSSOP 20 9 9 9 9 DUALS AD5332 8 ±0.25 2 6 µs TSSOP 20 9 AD5333 10 ±0.5 2 7 µs 9 9 9 TSSOP 24 AD5342 12 ±1.0 2 8 µs TSSOP 28 9 9 9 AD5343 12 ±1.0 1 8 µs 9 9 TSSOP 20 QUADS AD5334 8 ±0.25 2 6 µs 9 9 TSSOP 24 AD5335 10 ±0.5 2 7 µs 9 9 TSSOP 24 AD5336 10 ±0.5 4 7 µs 9 9 TSSOP 28 AD5344 12 ±1.0 4 8 µs TSSOP 28 OCTALS AD5346 8 ±0.25 4 6 µs 9 9 9 TSSOP, LFCSP 38, 40 AD5347 10 ±0.5 4 7 µs TSSOP, LFCSP 38, 40 9 9 9 AD4348 12 ±1.0 4 8 µs 9 9 9 TSSOP, LFCSP 38, 40 Table 10. Overview of AD53xx Serial Devices Part No. Resolution DNL VREF Pins Settling Time Interface Package Pins SINGLES AD5300 8 ±0.25 0 (VREF = VDD) 4 µs SPI® SOT-23, MSOP 6, 8 AD5310 10 ±0.5 0 (V = V ) 6 µs SPI SOT-23, MSOP 6, 8 REF DD AD5320 12 ±1.0 0 (VREF = VDD) 8 µs SPI SOT-23, MSOP 6, 8 AD5301 8 ±0.25 0 (V = V ) 6 µs 2-Wire SOT-23, MSOP 6, 8 REF DD AD5311 10 ±0.5 0 (VREF = VDD) 7 µs 2-Wire SOT-23, MSOP 6, 8 AD5321 12 ±1.0 0 (V = V ) 8 µs 2-Wire SOT-23, MSOP 6, 8 REF DD DUALS AD5302 8 ±0.25 2 6 µs SPI MSOP 8 AD5312 10 ±0.5 2 7 µs SPI MSOP 8 AD5322 12 ±1.0 2 8 µs SPI MSOP 8 AD5303 8 ±0.25 2 6 µs SPI TSSOP 16 AD5313 10 ±0.5 2 7 µs SPI TSSOP 16 AD5323 12 ±1.0 2 8 µs SPI TSSOP 16 QUADS AD5304 8 ±0.25 1 6 µs SPI MSOP 10 AD5314 10 ±0.5 1 7 µs SPI MSOP 10 AD5324 12 ±1.0 1 8 µs SPI MSOP 10 AD5305 8 ±0.25 1 6 µs 2-Wire MSOP 10 AD5315 10 ±0.5 1 7 µs 2-Wire MSOP 10 AD5325 12 ±1.0 1 8 µs 2-Wire MSOP 10 AD5306 8 ±0.25 4 6 µs 2-Wire TSSOP 16 AD5316 10 ±0.5 4 7 µs 2-Wire TSSOP 16 AD5326 12 ±1.0 4 8 µs 2-Wire TSSOP 16 AD5307 8 ±0.25 2 6 µs SPI TSSOP 16 AD5317 10 ±0.5 2 7 µs SPI TSSOP 16 AD5327 12 ±1.0 2 8 µs SPI TSSOP 16 OCTALS AD5308 8 ±0.25 2 6 µs SPI TSSOP 16 AD5318 10 ±0.5 2 7 µs SPI TSSOP 16 AD5328 12 ±1.0 2 8 µs SPI TSSOP 16 Rev. 0 | Page 22 of 24 AD5346/AD5347/AD5348 OUTLINE DIMENSIONS 9.80 9.70 9.60 38 20 4.50 4.40 4.30 6.40 BSC 1 19 PIN 1 1.20 MAX 0.15 0.05 8° 0.50 0° 0.27 0.70 SEATING 0.20 COPLANARITY BSC 0.17 0.60 PLANE 0.10 0.09 0.45 COMPLIANT TO JEDEC STANDARDS MO-153BD-1 Figure 48. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimensions shown in millimeters 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 1 30 PIN 1 0.50 INDICATOR 4.25 BSC TOP 5.75 BOTTOM 4.10 SQ VIEW BSC SQ VIEW 3.95 0.50 0.40 21 10 20 11 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.30 0.20 REF COPLANARITY 0.80 0.23 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters Rev. 0 | Page 23 of 24 AD5346/AD5347/AD5348 ORDERING GUIDES Table 11. AD5346 Ordering Guide Model Temperature Range Package Description Package Option AD5346BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5346BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5346BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5346BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5346BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5346BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 Table 12. AD5347 Ordering Guide Model Temperature Range Package Description Package Option AD5347BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5347BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5347BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5347BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5347BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5347BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 Table 13. AD5348 Ordering Guide Model Temperature Range Package Description Package Option AD5348BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5348BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5348BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38 AD5348BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5348BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 AD5348BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03331–0–11/03(0) Rev. 0 | Page 24 of 24