ANALOG DEVICES AD5344

2.5 V to 5.5 V, 500 �A, Parallel Interface a Quad Voltage-Output 8-/10-/12-Bit DACs AD5334/AD5335/AD5336/AD5344* FEATURES GENERAL DESCRIPTION AD5334: Quad 8-Bit DAC in 24-Lead TSSOP The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and AD5335: Quad 10-Bit DAC in 24-Lead TSSOP 12-bit DACs. They operate from a 2.5 V to 5.5 V supply con- AD5336: Quad 10-Bit DAC in 28-Lead TSSOP suming just 500 µA at 3 V, and feature a power-down mode that AD5344: Quad 12-Bit DAC in 28-Lead TSSOP further reduces the current to 80 nA. These devices incorporate Low Power Operation: 500 �A @ 3 V, 600 �A @ 5 V an on-chip output buffer that can drive the output to both sup- Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin ply rails. 2.5 V to 5.5 V Power Supply The AD5334/AD5335/AD5336/AD5344 have a parallel interface. Double-Buffered Input Logic CS selects the device and data is loaded into the input registers Guaranteed Monotonic by Design Over All Codes on the rising edge of WR. Output Range: 0–V or 0–2 V REF REF Power-On Reset to Zero Volts The GAIN pin on the AD5334 and AD5336 allows the output Simultaneous Update of DAC Outputs via LDAC Pin range to be set at 0 V to V or 0 V to 2 × V . REF REF Asynchronous CLR Facility Input data to the DACs is double-buffered, allowing simultaneous Low Power Parallel Data Interface update of multiple DACs in a system using the LDAC pin. On-Chip Rail-to-Rail Output Buffer AmpliŢers On the AD5334, AD5335 and AD5336 an asynchronous CLR Temperature Range: –40�C to +105�C input is also provided. This resets the contents of the Input APPLICATIONS Register and the DAC Register to all zeros. These devices also Portable Battery-Powered Instruments incorporate a power-on-reset circuit that ensures that the DAC Digital Gain and Offset Adjustment output powers on to 0 V and remains there until valid data is Programmable Voltage and Current Sources written to the device. Programmable Attenuators The AD5334/AD5335/AD5336/AD5344 are available in Thin Industrial Process Control Shrink Small Outline Packages (TSSOP). AD5334 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) V A/B V REF DD POWER-ON AD5334 RESET GAIN DAC INPUT DB 7 8-BIT . BUFFER V A REGISTER REGISTER OUT . DAC . DB 0 CS INPUT DAC 8-BIT BUFFER V B REGISTER REGISTER OUT DAC WR INTER- FACE A0 LOGIC DAC INPUT 8-BIT 8-BIT A1 BUFFER REGISTER V C REGISTER OUT DAC DAC INPUT DAC 8-BIT BUFFER V D OUT REGISTER REGISTER DAC TO ALL DACS CLR AND BUFFERS LDAC POWER-DOWN LOGIC V C/D PD GND REF *Protected by U.S. Patent Number 5,969,657 . REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k� to GND; C =200 pF to GND; all speciŢcations T to T unless otherwise noted.) DD REF L L MIN MAX 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5334 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic By Design Over All Codes AD5335/AD5336 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic By Design Over All Codes AD5344 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.2 ±1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.1 ±1 % of FSR 5 Lower Deadband 10 60 mV Lower Deadband Exists Only if Offset Error Is Negative Upper Deadband 10 60 mV V = 5 V. Upper Deadband Exists Only if V V DD REF = DD 6 Offset Error Drift –12 ppm of FSR/°C 6 Gain Error Drift –5 ppm of FSR/°C 6 DC Power Supply Rejection Ratio –60 dB ∆V = ±10% DD 6 DC Crosstalk 200 µVR = 2 kΩ to GND, 2 kΩ to V ; C = 200 pF to GND; L DD L Gain = 0 6 DAC REFERENCE INPUT V Input Range 0.25 V V REF DD V Input Impedance 180 kΩ Gain = 1. Input Impedance = R (AD5336/AD5344) REF DAC 90 kΩ Gain = 2. Input Impedance = R (AD5336) DAC 90 kΩ Gain = 1. Input Impedance = R (AD5334/AD5335) DAC 45 kΩ Gain = 2. Input Impedance = R (AD5334) DAC Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –90 dB Frequency = 10 kHz 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-Rail Operation 4, 7 Maximum Output Voltage V – 0.001 V max DD DC Output Impedance 0.5 Ω Short Circuit Current 50 mA V = 5 V DD 20 mA V = 3 V DD Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V = 5 V DD 5 µs Coming Out of Power-Down Mode. V = 3 V DD 6 LOGIC INPUTS Input Current ±1 µA V , Input Low Voltage 0.8 V V = 5 V ± 10% IL DD 0.6 V V = 3 V ± 10% DD 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 V V = 5 V ± 10% IH DD 2.1 V V = 3 V ± 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3.5 pF POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) All DACs active and excluding load currents. DD V = 4.5 V to 5.5 V 600 900 µAV = V , V = GND. DD IH DD IL V = 2.5 V to 3.6 V 500 700 µAI increases by 50 µA at V > V – 100 mV. DD DD REF DD I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 µA DD V = 2.5 V to 3.6 V 0.08 1 µA DD NOTES 1 See Terminology section. 2 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V = V and REF DD “Offset plus Gain” Error must be positive. Specifications subject to change without notice. –2– REV. 0 AD5334/AD5335/AD5336/AD5344 (V = 2.5 V to 5.5 V. R = 2 k� to GND; C = 200 pF to GND. All speciŢcations T to T unless other- DD L L MIN MAX 1 AC CHARACTERISTICS wise noted.) 3 B Version 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = 2 V. See Figure 20 REF AD5334 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H) AD5335 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5336 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5344 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch Energy 8 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 3 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p. Unbuffered Mode REF Total Harmonic Distortion –70 dB V = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz REF NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Terminology section. 3 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. Specifications subject to change without notice. 1, 2, 3 (V = 2.5 V to 5.5 V, All speciŢcations T to T unless otherwise noted.) TIMING CHARACTERISTICS DD MIN MAX Parameter Limit at T , T Unit Condition/Comments MIN MAX t 0 ns min CS to WR Setup Time 1 t 0 ns min CS to WR Hold Time 2 t 20 ns min WR Pulsewidth 3 t 5 ns min Data, GAIN, HBEN Setup Time 4 t 4.5 ns min Data, GAIN, HBEN Hold Time 5 t 5 ns min Synchronous Mode. WR Falling to LDAC Falling. 6 t 5 ns min Synchronous Mode. LDAC Falling to WR Rising. 7 t 4.5 ns min Synchronous Mode. WR Rising to LDAC Rising. 8 t 5 ns min Asynchronous Mode. LDAC Rising to WR Rising. 9 t 4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling. 10 t 20 ns min LDAC Pulsewidth 11 t 20 ns min CLR Pulsewidth 12 t 50 ns min Time Between WR Cycles 13 t 20 ns min A0, A1 Setup Time 14 t 0 ns min A0, A1 Hold Time 15 NOTES 1 Guaranteed by design and characterization, not production tested. t t 2 2 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) DD CS and timed from a voltage level of (V + V )/2. IL IH 3 See Figure 1. t t 13 3 Specifications subject to change without notice. WR t 5 t 4 DATA, GAIN, HBEN t 8 t 6 t 7 1 LDAC t t t 9 10 11 2 LDAC t 12 t CLR t 15 14 A0, A1 NOTES: 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 1. Parallel Interface Timing Diagram REV. 0 –3– AD5334/AD5335/AD5336/AD5344 ABSOLUTE MAXIMUM RATINGS* Reflow Soldering (T = 25°C unless otherwise noted) A Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Digital Input Voltage to GND . . . . . . . .–0.3 V to V + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- DD nent damage to the device. This is a stress rating only; functional operation of the Digital Output Voltage to GND . . . . . .–0.3 V to V + 0.3 V DD device at these or any other conditions above those listed in the operational Reference Input Voltage to GND . . . . –0.3 V to V + 0.3 V DD sections of this specification is not implied. Exposure to absolute maximum rating V to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT DD conditions for extended periods may affect device reliability. Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C TSSOP Package Power Dissipation . . . . . . . . . . . . . . . (T max – T )/θ mW J A JA θ Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W JA θ Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W JA θ Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W JC θ Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W JC ORDERING GUIDE Model Temperature Range Package Description Package Option AD5334BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24 AD5335BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24 AD5336BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28 AD5344BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD SENSITIVE DEVICE ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 AD5334/AD5335/AD5336/AD5344 AD5334 FUNCTIONAL BLOCK DIAGRAM AD5334 PIN CONFIGURATION V A/B V REF DD V C/D 1 24 REF CLR POWER-ON V A/B 2 23 GAIN REF AD5334 RESET V A 3 22 DB OUT 7 GAIN V B 4 21 DB OUT 6 DAC INPUT DB 7 8-BIT 8-BIT . BUFFER V A REGISTER REGISTER OUT V C 5 20 DB . DAC OUT 5 . AD5334 DB 0 V D 6 19 DB OUT 4 TOP VIEW (Not to Scale) GND 7 18 DB 3 CS INPUT DAC 8-BIT 8 17 DB CS 2 BUFFER V B REGISTER REGISTER OUT DAC WR 9 16 DB WR 1 INTER- FACE A0 10 15 DB 0 A0 LOGIC A1 11 14 V DD INPUT DAC 8-BIT 8-BIT A1 12 13 LDAC PD BUFFER V C REGISTER REGISTER OUT DAC DAC INPUT DAC 8-BIT BUFFER V D REGISTER REGISTER OUT DAC TO ALL DACS CLR AND BUFFERS LDAC POWER-DOWN LOGIC V C/D PD GND REF AD5334 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V C/D Unbuffered Reference Input for DACs C and D. REF 2V A/B Unbuffered Reference Input for DACs A and B. REF 3V A Output of DAC A. Buffered Output with Rail-to-Rail Operation. OUT 4V B Output of DAC B. Buffered Output with Rail-to-Rail Operation. OUT 5V C Output of DAC C. Buffered Output with Rail-to-Rail Operation. OUT 6V D Output of DAC D. Buffered Output with Rail-to-Rail Operation. OUT 7 GND Ground Reference Point for All Circuitry on the Part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to. 11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to. 12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. 13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 14 V Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10µF capacitor in parallel with a 0.1µF capacitor to GND. 15–22 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 23 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V or 0–2 V REF REF 24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 –5– AD5334/AD5335/AD5336/AD5344 AD5335 FUNCTIONAL BLOCK DIAGRAM AD5335 PIN CONFIGURATION V A/B V REF DD V C/D 1 24 REF CLR POWER-ON RESET V A/B 2 23 HBEN REF AD5335 V A 3 22 DB OUT 7 HIGH BYTE REGISTER V B 4 21 DB OUT 6 10-BIT V C 5 20 DB DB OUT 5 7 . AD5335 . . V D 6 19 DB OUT 4 . LOW BYTE TOP VIEW DAC . 10-BIT . REGISTER BUFFER V A (Not to Scale) REGISTER OUT GND 7 18 DB DAC 3 DB 0 8 17 DB CS 2 CS 9 16 DB WR 1 HIGH BYTE REGISTER A0 10 15 DB 0 WR A1 11 14 V DD A0 12 13 LOW BYTE DAC LDAC PD 10-BIT REGISTER REGISTER BUFFER V B OUT DAC INTER- A1 FACE LOGIC HIGH BYTE HBEN REGISTER LOW BYTE DAC 10-BIT BUFFER V C REGISTER REGISTER OUT DAC HIGH BYTE REGISTER LOW BYTE DAC 10-BIT BUFFER V D REGISTER REGISTER OUT DAC TO ALL DACS RESET AND BUFFERS CLR POWER-DOWN LDAC LOGIC V C/D REF PD GND AD5335 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V C/D Unbuffered Reference Input for DACs C and D. REF 2V A/B Unbuffered Reference Input for DACs A and B. REF 3V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 4V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 5V C Output of DAC C. Buffered output with rail-to-rail operation. OUT 6V D Output of DAC D. Buffered output with rail-to-rail operation. OUT 7 GND Ground Reference Point for All Circuitry on the Part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to. 11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to. 12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. 13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 14 V Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10µF capacitor in parallel with a 0.1µF capacitor to GND. 15–22 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 23 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. –6– REV. 0 AD5334/AD5335/AD5336/AD5344 AD5336 PIN CONFIGURATION AD5336 FUNCTIONAL BLOCK DIAGRAM V A V B V REF REF DD V D 1 28 REF CLR POWER-ON V C 2 27 GAIN REF AD5336 RESET V B 3 26 DB REF 9 GAIN V A 4 25 DB REF 8 DAC INPUT DB 9 10-BIT . BUFFER V A REGISTER REGISTER OUT V A 5 24 . DB OUT 7 DAC . 10-BIT DB 0 V B 6 23 DB OUT 6 AD5336 V C 7 22 DB OUT TOP VIEW 5 CS (Not to Scale) INPUT DAC V D 8 21 DB 10-BIT OUT 4 BUFFER V B OUT REGISTER REGISTER DAC WR GND 9 20 DB 3 INTER- FACE 10 19 DB CS 2 A0 LOGIC 11 18 DB WR 1 DAC INPUT 10-BIT A1 A0 12 17 DB 0 BUFFER V C REGISTER OUT REGISTER DAC A1 13 16 V DD 14 15 LDAC PD INPUT DAC 10-BIT BUFFER V D REGISTER REGISTER OUT DAC TO ALL DACS CLR AND BUFFERS RESET LDAC POWER-DOWN LOGIC V D V C PD GND REF REF AD5336 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V D Unbuffered Reference Input for DAC D. REF 2V C Unbuffered Reference Input for DAC C. REF 3V B Unbuffered Reference Input for DAC B. REF 4V A Unbuffered Reference Input for DAC A. REF 5V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7V C Output of DAC C. Buffered output with rail-to-rail operation. OUT 8V D Output of DAC D. Buffered output with rail-to-rail operation. OUT 9 GND Ground Reference Point for All Circuitry on the Part. 10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 11 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 12 A0 LSB Address Pin for Selecting which DAC Is to Be Written to. 13 A1 MSB Address Pin for Selecting which DAC is to Be Written to. 14 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. 15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 16 V Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10µF capacitor in parallel with a 0.1µF capacitor to GND. 17–26 DB –DB 10 Parallel Data Inputs. DB is the MSB of these 10 bits. 0 9 9 27 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V or 0–2 V . REF REF 28 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 –7– AD5334/AD5335/AD5336/AD5344 AD5344 PIN CONFIGURATION AD5344 FUNCTIONAL BLOCK DIAGRAM V A V B V REF REF DD V D 1 28 DB REF 11 V C 2 27 DB REF 10 POWER-ON AD5344 RESET V B 3 26 DB REF 9 V A 4 25 DB REF 8 DB 11 . . DAC INPUT V A 5 24 . DB 12-BIT OUT 7 . REGISTER BUFFER V A . REGISTER OUT 12-BIT DAC . V B 6 23 DB OUT 6 DB AD5344 0 V C 7 22 DB OUT TOP VIEW 5 (Not to Scale) CS V D 8 21 DB OUT 4 INPUT DAC 12-BIT BUFFER V B REGISTER OUT REGISTER GND 9 20 DB DAC 3 WR INTER- 10 19 DB CS 2 FACE A0 LOGIC 11 18 DB WR 1 A0 12 17 DB 0 INPUT DAC 12-BIT A1 BUFFER V C REGISTER REGISTER OUT DAC A1 13 16 V DD 14 15 LDAC PD INPUT DAC 12-BIT BUFFER V D REGISTER REGISTER OUT DAC TO ALL DACS AND BUFFERS LDAC POWER-DOWN LOGIC V D V C PD GND REF REF AD5344 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V D Unbuffered Reference Input for DAC D. REF 2V C Unbuffered Reference Input for DAC C. REF 3V B Unbuffered Reference Input for DAC B. REF 4V A Unbuffered Reference Input for DAC A. REF 5V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7V C Output of DAC C. Buffered output with rail-to-rail operation. OUT 8V D Output of DAC D. Buffered output with rail-to-rail operation. OUT 9 GND Ground Reference Point for All Circuitry on the Part. 10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 11 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 12 A0 LSB Address Pin for Selecting which DAC Is to Be Written to. 13 A1 MSB Address Pin for Selecting which DAC Is to Be Written to. 14 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers. This allows all DAC outputs to be simultaneously updated. 15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 16 V Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10µF capacitor in parallel with a 0.1µF capacitor to GND. 17–28 DB –DB 12 Parallel Data Inputs. DB is the MSB of these 12 bits. 0 11 11 –8– REV. 0 AD5334/AD5335/AD5336/AD5344 TERMINOLOGY RELATIVE ACCURACY GAIN ERROR For the DAC, Relative Accuracy or Integral Nonlinearity (INL) AND OFFSET is a measure of the maximum deviation, in LSBs, from a straight ERROR line passing through the actual endpoints of the DAC transfer function. Typical INL versus Code plot can be seen in Figures ACTUAL 5, 6, and 7. OUTPUT DIFFERENTIAL NONLINEARITY VOLTAGE Differential Nonlinearity (DNL) is the difference between the IDEAL measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed mono- tonic by design. Typical DNL versus Code plot can be seen in Figures 8, 9, and 10. POSITIVE OFFSET OFFSET ERROR DAC CODE This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Figure 3. Positive Offset Error and Gain Error If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 3. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there will GAIN ERROR be a code close to zero at which the amplifier output saturates AND OFFSET (amplifier footroom). Below this code there will be a deadband ERROR over which the output voltage will not change. This is illustrated IDEAL in Figure 4. OUTPUT VOLTAGE GAIN ERROR This is a measure of the span error of the DAC (including any ACTUAL error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- trated in Figure 2. NEGATIVE DAC CODE OFFSET POSITIVE GAIN ERROR NEGATIVE ACTUAL GAIN ERROR DEADBAND CODES AMPLIFIER FOOTROOM OUTPUT (~1mV) VOLTAGE IDEAL NEGATIVE OFFSET DAC CODE Figure 4. Negative Offset Error and Gain Error Figure 2. Gain Error REV. 0 –9– AD5334/AD5335/AD5336/AD5344 OFFSET ERROR DRIFT DIGITAL FEEDTHROUGH This is a measure of the change in Offset Error with changes in Digital Feedthrough is a measure of the impulse injected into temperature. It is expressed in (ppm of full-scale range)/°C. the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to GAIN ERROR DRIFT (CS held high). It is specified in nV-secs and is measured with a This is a measure of the change in Gain Error with changes in full-scale change on the digital input pins, i.e. from all 0s to all temperature. It is expressed in (ppm of full-scale range)/°C. 1s and vice versa. DC POWER-SUPPLY REJECTION RATIO (PSRR) DIGITAL CROSSTALK This indicates how the output of the DAC is affected by changes in This is the glitch impulse transferred to the output of one DAC the supply voltage. PSRR is the ratio of the change in V to a OUT at midscale in response to a full-scale code change (all 0s to all change in V for full-scale output of the DAC. It is measured DD 1s and vice versa) in the input register of another DAC. It is in dBs. V is held at 2 V and V is varied ±10%. REF DD expressed in nV secs. DC CROSSTALK ANALOG CROSSTALK This is the dc change in the output level of one DAC at mid- This is the glitch impulse transferred to the output of one DAC scale in response to a full-scale code change (all 0s to all 1s and due to a change in the output of another DAC. It is measured vice versa) and output change of another DAC. It is expressed by loading one of the input registers with a full-scale code change in µV. (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose REFERENCE FEEDTHROUGH digital code was not changed. The area of the glitch is expressed This is the ratio of the amplitude of the signal at the DAC output in nV secs. to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs. DAC-TO-DAC CROSSTALK This is the glitch impulse transferred to the output of one DAC CHANNEL-TO-CHANNEL ISOLATION due to a digital code change and subsequent output change of This is a ratio of the amplitude of the signal at the output of one another DAC. This includes both digital and analog crosstalk. It DAC to a sine wave on the reference inputs of the other DACs. is measured by loading one of the DACs with a full-scale code It is measured by grounding one V pin and applying a 10 kHz, REF change (all 0s to all 1s and vice versa) with the LDAC pin set 4 V peak-to-peak sine wave to the other V pins. It is expressed REF low and monitoring the output of another DAC. The energy of in dBs. the glitch is expressed in nV secs. MAJOR-CODE TRANSITION GLITCH ENERGY MULTIPLYING BANDWIDTH Major-Code Transition Glitch Energy is the energy of the The amplifiers within the DAC have a finite bandwidth. The impulse injected into the analog output when the DAC changes Multiplying Bandwidth is a measure of this. A sine wave on the state. It is normally specified as the area of the glitch in nV secs reference (with full-scale code loaded to the DAC) appears on and is measured when the digital code is changed by 1 LSB at the output. The Multiplying Bandwidth is the frequency at which the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 the output amplitude falls to 3 dB below the input. to 011 . . . 11). TOTAL HARMONIC DISTORTION This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs. –10– REV. 0 Typical Performance Characteristics–AD5334/AD5335/AD5336/AD5344 12 1.0 3 T = 25�C A T = 25�C A T = 25�C A V = 5V DD V = 5V V = 5V DD 8 2 DD 0.5 4 1 0 0 0 –4 –1 –0.5 –8 –2 –12 –1.0 –3 0 4000 0 50 100 150 200 250 1000 2000 3000 0 200 400 600 800 1000 CODE CODE CODE Figure 5. AD5334 Typical INL Plot Figure 7. AD5336 Typical INL Plot Figure 6. AD5335 Typical INL Plot 0.3 1 0.6 T = 25�C T = 25�C A T = 25�C A A V = 5V V = 5V DD V = 5V DD DD 0.2 0.4 0.5 0.1 0.2 0 0 0 –0.1 –0.2 –0.5 –0.2 –0.4 –0.3 –1 –0.6 050 100 150 200 250 0 1000 2000 3000 4000 0 200 400 600 800 1000 CODE CODE CODE Figure 8. AD5334 Typical DNL Plot Figure 10. AD5336 Typical DNL Plot Figure 9. AD5335 Typical DNL Plot 0.5 1 0.5 V = 5V V = 5V DD V = 5V DD 0.4 DD V = 2V T = 25�C V = 2V REF A REF MAX INL MAX INL 0.3 0.25 0.5 0.2 MAX DNL MAX DNL 0.1 GAIN ERROR 0 0 0 –0.1 MIN DNL OFFSET ERROR MIN DNL –0.2 –0.25 –0.5 –0.3 MIN INL MIN INL –0.4 –0.5 –1 –0.5 01 23 4 5 �40 0 40 80 120 �40 0 40 80 120 V – V TEMPERATURE – �C REF TEMPERATURE – �C Figure 13. AD5334 Offset Error Figure 11. AD5334 INL and DNL Figure 12. AD5334 INL Error and and Gain Error vs. Temperature Error vs. V DNL Error vs. Temperature REF REV. 0 –11– ERROR – LSBs DNL ERROR – LSBs INL ERROR – LSBs ERROR – LSBs DNL ERROR – LSBs INL ERROR – LSBs DNL ERROR – LSBs ERROR – % INL ERROR – LSBs AD5334/AD5335/AD5336/AD5344 600 5 0.2 V = 5.5V T = 25�C A DD 0.1 5V SOURCE 500 V = 2V REF 4 0 GAIN ERROR V = 3.6V 400 DD 3V SOURCE –0.1 3 300 –0.2 2 –0.3 200 T = 25�C A V = 2V –0.4 OFFSET ERROR REF 1 100 3V SINK 5V SINK –0.5 0 0 –0.6 ZERO-SCALE FULL SCALE 0125 346 DAC CODE 0125 346 V – Volts SINK/SOURCE CURRENT – mA DD Figure 15. V Source and Sink Figure 16. Supply Current Figure 14. Offset Error and Gain OUT Current Capability vs. DAC Code Error vs. V DD 1800 0.5 600 T = 25�C A T = 25�C A 1600 500 0.4 1400 1200 400 0.3 1000 300 800 0.2 600 200 V = 5V DD 400 0.1 V = 3V 100 DD 200 0 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1 234 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V – V V – V V – V DD DD LOGIC Figure 17. Supply Current vs. Supply Figure 18. Power-Down Current vs. Figure 19. Supply Current Voltage Supply Voltage vs. Logic Input Voltage T = 25�C 5µs T = 25�C T = 25�C A A A V = 5V V = 5V DD V = 5V DD DD V = 5V V = 2V REF V = 2V REF REF CH1 CH1 V A V CH1 OUT DD V A OUT LDAC V A OUT PD CH2 CH2 CH2 CH1 1V, CH2 5V, TIME BASE= 1�s/DIV CH1 2V, CH2 200mV, TIME BASE = 200�s/DIV CH1 500mV, CH2 5V, TIME BASE = 1�s/DIV Figure 20. Half-Scale Settling (1/4 to Figure 21. Power-On Reset to 0 V Figure 22. Exiting Power-Down 3/4 Scale Code Change) to Midscale –12– REV. 0 I – �A ERROR – % DD V – Volts I – �A OUT DD I – �A I – �A DD DD AD5334/AD5335/AD5336/AD5344 0.929 10 0.928 0 0.927 –10 0.926 V = 3V V = 5V DD DD 0.925 –20 0.924 –30 0.923 0.922 –40 0.921 –50 0.920 0.919 –60 500ns/DIV 300 350 400 450 500 550 600 0.01 0.1 1 10 100 1k 10k I – �A FREQUENCY – kHz DD Figure 23. I Histogram with V = Figure 24. AD5344 Major-Code Tran- Figure 25. Multiplying Bandwidth DD DD 3 V and V = 5 V sition Glitch Energy (Small-Signal Frequency Response) DD 0.4 V = 5V DD T = 25�C A 0.3 0.2 0.1 0 –0.1 –0.2 0 1 2 345 6 750ns/DIV V – V REF Figure 27. DAC-DAC Crosstalk Figure 26. Full-Scale Error vs. V REF FUNCTIONAL DESCRIPTION where: The AD5334/AD5335/AD5336/AD5344 are quad resistor- D = decimal equivalent of the binary code which is loaded to string DACs fabricated on a CMOS process with resolutions of the DAC register: 8, 10, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 0–255 for AD5334 (8 Bits) 5.5 V and the output buffer amplifiers offer rail-to-rail output 0–1023 for AD5335/AD5336 (10 Bits) swing. The gain of the buffer amplifiers in the AD5334 and 0–4095 for AD5344 (12 Bits) AD5336 can be set to 1 or 2 to give an output voltage range of N = DAC resolution 0 to V or 0 to 2 V . The AD5335 and AD5344 have out- REF REF Gain = Output Amplifier Gain (1 or 2) put buffers with unity gain. The devices have a power-down feature that reduces current V REF consumption to only 80 nA @ 3 V. GAIN Digital-to-Analog Section RESISTOR INPUT DAC The architecture of one DAC channel consists of a reference V OUT REGISTER STRING REGISTER buffer and a resistor-string DAC followed by an output buffer OUTPUT amplifier. The voltage at the V pin provides the reference REF BUFFER AMPLIFIER voltage for the DAC. Figure 28 shows a block diagram of the DAC architecture. Since the input coding to the DAC is Figure 28. Single DAC Channel Architecture straight binary, the ideal output voltage is given by: D VV =× × Gain OUT REF N 2 REV. 0 –13– FULL-SCALE ERROR – %FSR FREQUENCY V – Volts OUT 1mV/DIV dB AD5334/AD5335/AD5336/AD5344 Access to the DAC register is controlled by the LDAC function. Resistor String When LDAC is high, the DAC register is latched and the input The resistor string section is shown in Figure 29. It is simply a register may change state without affecting the contents of the string of resistors, each of value R. The digital code loaded DAC register. However, when LDAC is brought low, the DAC to the DAC register determines at what node on the string the register becomes transparent and the contents of the input voltage is tapped off to be fed into the output amplifier. The register are transferred to it. The gain control signal is also voltage is tapped off by closing one of the switches connecting double-buffered and is only updated when LDAC is taken low. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. This is useful if the user requires simultaneous updating of all DACs and peripherals. The user may write to all input registers V REF individually and then, by pulsing the LDAC input low, all out- R puts will update simultaneously. Double-buffering is also useful where the DAC data is loaded in R two bytes, as in the AD5335, because it allows the whole data word to be assembled in parallel before updating the DAC register. TO OUTPUT R AMPLIFIER This prevents spurious outputs that could occur if the DAC register were updated with only the high byte or the low byte. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since R the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the R contents of the input registers. In the case of the AD5334/ AD5335/AD5336/AD5344, the part will only update the DAC register if the input register has been changed since the last Figure 29. Resistor String time the DAC register was updated. This removes unnecessary DAC Reference Input crosstalk. The DACs operate with an external reference. The reference Clear Input (CLR) inputs are unbuffered and have an input range of 0.25 V to V . DD CLR is an active low, asynchronous clear that resets the input and The impedance per DAC is typically 180 kΩ for 0–V mode REF DAC registers. Note that the AD5344 has no CLR function. and 90 kΩ for 0–2 V mode. The AD5336 and AD5344 have REF Chip Select Input (CS) separate reference inputs for each DAC, while the AD5334 and CS is an active low input that selects the device. AD5335 have a reference inputs for each pair of DACS (A/B and C/D). Write Input (WR) WR is an active low input that controls writing of data to the Output AmpliŢer device. Data is latched into the input register on the rising edge The output buffer amplifier is capable of generating output of WR. voltages to within 1 mV of either rail. Its actual range depends on V , GAIN, the load on V , and offset error. REF OUT Load DAC Input (LDAC) LDAC transfers data from the input register to the DAC register If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V (and hence updates the outputs). Use of the LDAC function to V . REF enables double buffering of the DAC and GAIN data. There If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V are two LDAC modes: to 2 V . However because of clamping the maximum output REF Synchronous Mode: In this mode the DAC register is updated is limited to V – 0.001 V. DD after new data is read in on the rising edge of the WR input. The output amplifier is capable of driving a load of 2 kΩ to LDAC can be tied permanently low or pulsed as in Figure 1. GND or V , in parallel with 500 pF to GND or V . The DD DD Asynchronous Mode: In this mode the outputs are not updated source and sink capabilities of the output amplifier can be seen at the same time that the input register is written to. When LDAC in Figure 15. goes low the DAC register is updated with the contents of the The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB input register. (at 8 bits) of 6 µs with the output unloaded. See Figure 20. High-Byte Enable Input (HBEN) High-Byte Enable is a control input on the AD5335 only that PARALLEL INTERFACE determines if data is written to the high-byte input register or The AD5334, AD5336, and AD5344 load their data as a single the low-byte input register. 8-, 10-, or 12-bit word, while the AD5335 loads data as a low byte of 8 bits and a high byte containing 2 bits. The low data byte of the AD5335 consists of data bits 0 to 7 at data inputs DB to DB , while the high byte consists of Data Double-Buffered Interface 0 7 Bits 8 and 9 at data inputs DB and DB . DB to DB are The AD5334/AD5335/AD5336/AD5344 DACs all have double- 0 1 2 7 ignored during a high byte write. See Figure 30. buffered interfaces consisting of an input register and a DAC register. DAC data and GAIN inputs (when available) are written to the input register under control of the Chip Select (CS) and Write (WR). –14– REV. 0 AD5334/AD5335/AD5336/AD5344 When the PD pin is high, the DACs work normally with a typical HIGH BYTE X DB9 power consumption of 600 µA at 5 V (500 µA at 3 V). In power- X X XX X DB8 down mode, however, the supply current falls to 200 nA at 5 V LOW BYTE (80 nA at 3 V) when the DACs are powered down. Not only DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 does the supply current drop, but the output stage is also internally X = UNUSED BIT switched from the output of the amplifier, making it open-circuit. Figure 30. Data Format For AD5335 This has the advantage that the outputs are three-state while the part is in power-down mode, and provides a defined input POWER-ON RESET condition for whatever is connected to the outputs of the The AD5334/AD5335/AD5336/AD5344 are provided with a DAC amplifiers. The output stage is illustrated in Figure 31. power-on reset function, so that they power up in a defined state. The power-on state is: • Normal operation RESISTOR AMPLIFIER V OUT STRING DAC •0 – V output range REF • Output voltage set to 0 V POWER-DOWN Both input and DAC registers are filled with zeros and remain CIRCUITRY so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know Figure 31. Output Stage During Power-Down the state of the DAC outputs while the device is powering up. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the POWER-DOWN MODE power-down mode is activated. However, the contents of the The AD5334/AD5335/AD5336/AD5344 have low power con- registers are unaffected when in power-down. The time to exit sumption, dissipating typically 1.5 mW with a 3 V supply and power-down is typically 2.5 µs for V = 5 V and 5 µs when DD 3 mW with a 5 V supply. Power consumption can be further V = 3 V. This is the time from a rising edge on the PD pin DD reduced when the DACs are not in use by putting them into to when the output voltage deviates from its power-down volt- power-down mode, which is selected by taking pin PD low. age. See Figure 22. Table I. AD5334/AD5336/AD5344 Truth Table CLR LDAC CS WR A1 A0 Function 1 1 1 X X X No Data Transfer 1 1 X 1 X X No Data Transfer 0 X X X X X Clear All Registers 11 0 0➝1 0 0 Load DAC A Input Register, GAIN A (AD5334/AD5336) 11 0 0➝1 0 1 Load DAC B Input Register, GAIN B (AD5334/AD5336) 11 0 0➝1 1 0 Load DAC C Input Register, GAIN C (AD5334/AD5336) 11 0 0➝1 1 1 Load DAC D Input Register, GAIN D (AD5334/AD5336) 1 0 X X X X Update DAC Registers X = don’t care. Table II. AD5335 Truth Table CLR LDAC CS WR A1 A0 HBEN Function 1 1 1 X X X X No Data Transfer 1 1 X 1 X X X No Data Transfer 0 X X X X X X Clear All Registers 11 0 0➝1 0 0 0 Load DAC A Low Byte Input Register 11 0 0➝1 0 0 1 Load DAC A High Byte Input Register 11 0 0➝1 0 1 0 Load DAC B Low Byte Input Register 11 0 0➝1 0 1 1 Load DAC B High Byte Input Register 11 0 0➝1 1 0 0 Load DAC C Low Byte Input Register 11 0 0➝1 1 0 1 Load DAC C High Byte Input Register 11 0 0➝1 1 1 0 Load DAC D Low Byte Input Register 11 0 0➝1 1 1 1 Load DAC D High Byte Input Register 1 0 X X X X X Update DAC Registers X = don’t care. REV. 0 –15– AD5334/AD5335/AD5336/AD5344 SUGGESTED DATABUS FORMATS 6V TO 16V In many applications the GAIN input of the AD5334 and AD5336 may be hard-wired. However, if more flexibility is 0.1�F 10�F required, it can be included in a data bus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system V IN GAIN may be treated as a data input since it is written to the ADM663/ADM666 device during a write operation and takes effect when LDAC is V SENSE DD taken low. This means that the output amplifier gain of multiple V OUT(2) V * REF V * OUT DAC devices can be controlled using a common GAIN line. VSET GND SHDN 0.1�F AD5334/AD5335/ The AD5336 databus must be at least 10 bits wide and is best AD5336/AD5344 suited to a 16-bit databus system. GND Examples of data formats for putting GAIN on a 16-bit databus are shown in Figure 32. Note that any unused bits above the *ONLY ONE CHANNEL OF V AND V SHOWN actual DAC data may be used for GAIN. REF OUT Figure 34. Using an ADM663/ADM666 as Power and AD5336 Reference to AD5334/AD5335/AD5336/AD5344 X X X X X GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X = UNUSED BIT Bipolar Operation Using the AD5334/AD5335/AD5336/AD5344 The AD5334/AD5335/AD5336/AD5344 have been designed Figure 32. AD5336 Data Format for Byte Load with GAIN for single supply operation, but bipolar operation is achievable Data on 8-Bit Bus using the circuit shown in Figure 35. The circuit shown has been configured to achieve an output voltage range of –5 V < V < O APPLICATIONS INFORMATION +5 V. Rail-to-rail operation at the amplifier output is achievable Typical Application Circuits using an AD820 or OP295 as the output amplifier. The AD5334/AD5335/AD5336/AD5344 can be used with a The output voltage for any input code can be calculated as wide range of reference voltages and offer full, one-quadrant follows: multiplying capability over a reference range of 0.25 V to V . DD N More typically, these devices may be used with a fixed, preci- V = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V × D/2 )] – R4 × V /R3 O REF REF sion reference voltage. Figure 33 shows a typical setup for the where: devices when using an external reference connected to the refer- ence inputs. Suitable references for 5 V operation are the AD780 D is the decimal equivalent of the code loaded to the DAC, N is and REF192. For 2.5 V operation, a suitable external reference DAC resolution and V is the reference voltage input. REF would be the AD589, a 1.23 V bandgap reference. With: V = 2.5 V V = 2.5V TO 5.5V REF DD R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ and V = 5 V. DD N 0.1�F 10�F V = (10 × D/2 ) – 5 OUT V IN V = 5V V DD DD EXT V * V R4 OUT REF REF 20k� V * OUT GND 0.1�F 10�F AD5334/AD5335/ +5V R3 AD5336/AD5344 10k� AD780/REF192 V �5V IN WITH V = 5V DD V DD GND EXT OR V * V REF REF OUT AD589 WITH V = 2.5V DD –5V 0.1�F AD5334/AD5335/ *ONLY ONE CHANNEL OF V AND V SHOWN GND REF OUT R1 AD5336/AD5344 10k� V * Figure 33. AD5334/AD5335/AD5336/AD5344 Using OUT AD780/REF192 R2 External Reference WITH V = 5V 20k� DD OR Driving V from the Reference Voltage DD GND AD589 WITH V = 2.5V DD If an output range of zero to V is required, the simplest DD solution is to connect the reference inputs to V . As this supply DD *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT may not be very accurate, and may be noisy, the devices Figure 35. Bipolar Operation using the AD5334/AD5335/ may be powered from the reference voltage, for example AD5336/AD5344 using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 34. –16– REV. 0 AD5334/AD5335/AD5336/AD5344 Decoding Multiple AD5334/AD5335/AD5336/AD5344 used for some other purpose. The AD5336 and AD5344 have The CS pin on these devices can be used in applications to decode separate reference inputs for each DAC. a number of DACs. In this application, all DACs in the system The upper and lower limits for the test are loaded to DACs A receive the same data and WR pulses, but only the CS to one of and B which, in turn, set the limits on the CMP04. If a signal at the DACs will be active at any one time, so data will only be the V input is not within the programmed window, an LED IN written to the DAC whose CS is low. If multiple AD5343s are will indicate the fail condition. being used, a common HBEN line will also be required to determine if the data is written to the high-byte or low-byte 5V register of the selected DAC. 10�F 0.1�F 1k� 1k� V IN FAIL PASS The 74HC139 is used as a 2- to 4-line decoder to address any V DD V of the DACs in the system. To prevent timing errors from oc- V A REF REF curring, the enable input should be brought to its inactive state V A OUT while the coded address inputs are changing state. Figure 36 shows V B REF PASS/ 1/2 FAIL a diagram of a typical setup for decoding multiple devices in a CMP04 AD5336/AD5344 system. Once data has been written sequentially to all DACs in V B a system, all the DACs can be updated simultaneously using a OUT 1/6 74HC05 common LDAC line. A common CLR line can also be used to GND reset all DAC outputs to zero (except on the AD5344). Figure 37. Programmable Window Detector AD5334/AD5335/ AD5336/AD5344 A0 A1 Programmable Current Source A1 A0 Figure 38 shows the AD5334/AD5335/AD5336/AD5344 used HBEN* HBEN WR WR DATA as the control element of a programmable current source. In this LDAC INPUTS LDAC example, the full-scale current is set to 1 mA. The output volt- CLR CLR age from the DAC is applied across the current setting resistor CS of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, AD5334/AD5335/ AD5336/AD5344 which gives an adjustment of about ±5%. Suitable transistors to A1 place in the feedback loop of the amplifier include the BC107 A0 HBEN* and the 2N3904, which enable the current source to operate WR DATA from a minimum V of 6 V. The operating range is deter- SOURCE INPUTS LDAC V DD CLR mined by the operating characteristics of the transistor. Suitable CS amplifiers include the AD820 and the OP295, both having rail- V CC to-rail operation on their outputs. The current for any digital 1G AD5334/AD5335/ ENABLE 1Y0 AD5336/AD5344 A1 input code and resistor value can be calculated as follows: 1A 1Y1 A0 CODED 74HC139 D ADDRESS HBEN* 1Y2 1B IG =×V × mA REF WR DATA N () 2 × R LDAC INPUTS 1Y3 Where: CLR DGND CS G is the gain of the buffer amplifier (1 or 2) AD5334/AD5335/ D is the digital input code AD5336/AD5344 A1 N is the DAC resolution (8, 10, or 12 bits) A0 R is the sum of the resistor plus adjustment potentiometer in kΩ HBEN* WR DATA INPUTS LDAC V = 5V DD CLR CS *AD5335 ONLY 0.1�F 10�F V SOURCE Figure 36. Decoding Multiple DAC Devices V IN 5V LOAD V DD AD5334/AD5335/AD5336/AD5344 as a Digitally Programmable EXT V * V V * REF REF OUT OUT Window Detector AD820/ 0.1�F AD5334/AD5335/ GND OP295 A digitally programmable upper/lower limit detector using two AD5336/AD5344 of the DACs in the AD5334/AD5335/AD5336/AD5344 is shown in Figure 37. AD780/REF192 4.7k� WITH V = 5V DD Any pair of DACs in the device may be used, but for simplicity GND the description will refer to DACs A and B. 470� Care must be taken to connect the correct reference inputs to *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT the reference source. The AD5334 and AD5335 have only two reference inputs, V A/B for DACs A and B and V C/D for REF REF Figure 38. Programmable Current Source DACs C and D. If DACs A and B are used (for example) then only V A/B is needed. DACs C and D and V C/D may be REF REF REV. 0 –17– DATA BUS AD5334/AD5335/AD5336/AD5344 Coarse and Fine Adjustment Using the AD5334/AD5335/ Power Supply Bypassing and Grounding AD5336/AD5344 In any circuit where accuracy is important, careful consideration Two of the DACs in the AD5334/AD5335/AD5336/AD5344 can of the power supply and ground return layout helps to ensure be paired together to form a coarse and fine adjustment function, the rated performance. The printed circuit board on which the as shown in Figure 39. As with the window comparator previ- AD5334/AD5335/AD5336/AD5344 is mounted should be ously described, the description will refer to DACs A, and B and designed so that the analog and digital sections are separated, the reference connections will depend on the actual device used. and confined to certain areas of the board. If the device is in a system where multiple devices require an AGND-to-DGND DAC A is used to provide the coarse adjustment while DAC B connection, the connection should be made at one point only. provides the fine adjustment. Varying the ratio of R1 and R2 will The star ground point should be established as closely as pos- change the relative effect of the coarse and fine adjustments. With sible to the device. The AD5334/AD5335/AD5336/AD5344 the resistor values shown the output amplifier has unity gain for should have ample supply bypassing of 10 µF in parallel with the DAC A output, so the output range is zero to (V – 1 LSB). REF –3 0.1µF on the supply located as close to the package as possible, For DAC B the amplifier has a gain of 7.6 × 10 , giving DAC B ideally right up against the device. The 10 µF capacitors are the a range equal to 2 LSBs of DAC A. tantalum bead type. The 0.1 µF capacitor should have low The circuit is shown with a 2.5 V reference, but reference volt- Effective Series Resistance (ESR) and Effective Series Inductance ages up to V may be used. The op amps indicated will allow a DD (ESI), like the common ceramic types that provide a low imped- rail-to-rail output swing. ance path to ground at high frequencies to handle transient currents due to internal logic switching. V = 5V DD R3 R4 The power supply lines of the device should use as large a trace 51.2k� 390� as possible to provide low impedance paths and reduce the 0.1�F 10�F 5V effects of glitches on the power supply line. Fast switching sig- nals such as clocks should be shielded with digital ground to V DD avoid radiating noise to other parts of the board, and should V V OUT IN V A OUT never be run near the reference inputs. Avoid crossover of digital EXT R1 V V A REF OUT REF 390� and analog signals. Traces on opposite sides of the board should 0.1�F GND run at right angles to each other. This reduces the effects of AD5336/AD5344 R2 51.2k� feedthrough through the board. A microstrip technique is by V B OUT far the best, but not always possible with a double-sided board. AD780/REF192 V B REF WITH V = 5V DD In this technique, the component side of the board is dedicated GND to ground plane while signal traces are placed on the solder side. Figure 39. Coarse and Fine Adjustment –18– REV. 0 AD5334/AD5335/AD5336/AD5344 Table III. Overview of AD53xx Parallel Devices Part No. Resolution DNL V Pins Settling Time Additional Pin Functions Package Pins REF SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 µs �� � TSSOP 20 AD5331 10 ±0.5 1 7 µs �� TSSOP 20 AD5340 12 ±1.0 1 8 µs �� � TSSOP 24 AD5341 12 ±1.0 1 8 µs � ��� TSSOP 20 DUALS AD5332 8 ±0.25 2 6 µs � TSSOP 20 AD5333 10 ±0.5 2 7 µs �� � TSSOP 24 AD5342 12 ±1.0 2 8 µs �� � TSSOP 28 AD5343 12 ±1.0 1 8 µs �� TSSOP 20 QUADS AD5334 8 ±0.25 2 6 µs �� TSSOP 24 AD5335 10 ±0.5 2 7 µs �� TSSOP 24 AD5336 10 ±0.5 4 7 µs �� TSSOP 28 AD5344 12 ±1.0 4 8 µs TSSOP 28 Table IV. Overview of AD53xx Serial Devices Part No. Resolution No. of DACS DNL Interface Settling Time Package Pins SINGLES AD5300 8 1 ±0.25 SPI 4 µs SOT-23, MicroSOIC 6, 8 AD5310 10 1 ±0.5 SPI 6 µs SOT-23, MicroSOIC 6, 8 AD5320 12 1 ±1.0 SPI 8 µs SOT-23, MicroSOIC 6, 8 AD5301 8 1 ±0.25 2-Wire 6 µs SOT-23, MicroSOIC 6, 8 AD5311 10 1 ±0.5 2-Wire 7 µs SOT-23, MicroSOIC 6, 8 AD5321 12 1 ±1.0 2-Wire 8 µs SOT-23, MicroSOIC 6, 8 DUALS AD5302 8 2 ±0.25 SPI 6 µs MicroSOIC 8 AD5312 10 2 ±0.5 SPI 7 µs MicroSOIC 8 AD5322 12 2 ±1.0 SPI 8 µs MicroSOIC 8 AD5303 8 2 ±0.25 SPI 6 µs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 µs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 µs TSSOP 16 QUADS AD5304 8 4 ±0.25 SPI 6 µs MicroSOIC 10 AD5314 10 4 ±0.5 SPI 7 µs MicroSOIC 10 AD5324 12 4 ±1.0 SPI 8 µs MicroSOIC 10 AD5305 8 4 ±0.25 2-Wire 6 µs MicroSOIC 10 AD5315 10 4 ±0.5 2-Wire 7 µs MicroSOIC 10 AD5325 12 4 ±1.0 2-Wire 8 µs MicroSOIC 10 AD5306 8 4 ±0.25 2-Wire 6 µs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 µs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 µs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 µs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 µs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 µs TSSOP 16 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 –19– AD5334/AD5335/AD5336/AD5344 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24) 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.020 (0.50) 0.0035 (0.090) 28-Lead Thin Shrink Small Outline Package TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.020 (0.50) 0.0035 (0.090) –20– REV. 0 PRINTED IN U.S.A. C3830–2.5–4/00 (rev. 0)