ANALOG DEVICES AD5343

2.5 V to 5.5 V, 230 �A, Parallel Interface a Dual Voltage-Output 8-/10-/12-Bit DACs AD5332/AD5333/AD5342/AD5343* FEATURES GENERAL DESCRIPTION AD5332: Dual 8-Bit DAC in 20-Lead TSSOP The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and AD5333: Dual 10-Bit DAC in 24-Lead TSSOP 12-bit DACs. They operate from a 2.5 V to 5.5 V supply con- AD5342: Dual 12-Bit DAC in 28-Lead TSSOP suming just 230 µA at 3 V, and feature a power-down pin, PD AD5343: Dual 12-Bit DAC in 20-Lead TSSOP that further reduces the current to 80 nA. These devices incor- Low Power Operation: 230 �A @ 3 V, 300 �A @ 5 V porate an on-chip output buffer that can drive the output to via PD Pin both supply rails, while the AD5333 and AD5342 allow a choice Power-Down to 80 nA @ 3 V, 200 nA @ 5 V of buffered or unbuffered reference input. 2.5 V to 5.5 V Power Supply The AD5332/AD5333/AD5342/AD5343 have a parallel interface. Double-Buffered Input Logic CS selects the device and data is loaded into the input registers Guaranteed Monotonic by Design Over All Codes on the rising edge of WR. Buffered/Unbuffered Reference Input Options The GAIN pin on the AD5333 and AD5342 allows the output Output Range: 0–V or 0–2 V REF REF range to be set at 0 V to V or 0 V to 2 × V . REF REF Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Input data to the DACs is double-buffered, allowing simultaneous Asynchronous CLR Facility update of multiple DACs in a system using the LDAC pin. Low Power Parallel Data Interface An asynchronous CLR input is also provided, which resets the On-Chip Rail-to-Rail Output Buffer AmpliŢers contents of the Input Register and the DAC Register to all zeros. Temperature Range: –40�C to +105�C These devices also incorporate a power-on reset circuit that ensures APPLICATIONS that the DAC output powers on to 0 V and remains there until Portable Battery-Powered Instruments valid data is written to the device. Digital Gain and Offset Adjustment The AD5332/AD5333/AD5342/AD5343 are available in Thin Programmable Voltage and Current Sources Shrink Small Outline Packages (TSSOP). Programmable Attenuators Industrial Process Control AD5332 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) V A V REF DD POWER-ON AD5332 RESET DAC INPUT DB 8-BIT 7 . V A REGISTER BUFFER REGISTER OUT . DAC . DB 0 INTER- FACE LOGIC CS INPUT DAC 8-BIT BUFFER V B REGISTER OUT REGISTER DAC WR A0 RESET POWER-DOWN CLR LOGIC LDAC V B GND PD REF *Protected by U.S. Patent Number 5,969,657 . REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k� to GND; C =200 pF to GND; all speciŢcations T to T unless otherwise noted.) DD REF L L MIN MAX 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5332 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic By Design Over All Codes AD5333 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic By Design Over All Codes AD5342/AD5343 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.2 ±1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR 5 Lower Deadband 10 60 mV Lower Deadband Exists Only if Offset Error Is Negative Upper Deadband 10 60 mV V = 5 V. Upper Deadband Exists Only if V V DD REF = DD 6 Offset Error Drift –12 ppm of FSR/°C 6 Gain Error Drift –5 ppm of FSR/°C 6 DC Power Supply Rejection Ratio –60 dB ∆V = ±10% DD 6 DC Crosstalk 200 µVR = 2 kΩ to GND, 2 kΩ to V ; C = 200 pF to GND; L DD L Gain = 0 6 DAC REFERENCE INPUT V Input Range 1 V V Buffered Reference (AD5333 and AD5342) REF DD 0.25 V V Unbuffered Reference DD V Input Impedance >10 MΩ Buffered Reference (AD5333 and AD5342) REF 180 kΩ Unbuffered Reference. Gain = 1, Input Impedance = R DAC 90 kΩ Unbuffered Reference. Gain = 2, Input Impedance = R DAC Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –90 dB Frequency = 10 kHz (AD5332, AD5333, and AD5342) 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-Rail Operation 4, 7 Maximum Output Voltage V – 0.001 V max DD DC Output Impedance 0.5 Ω Short Circuit Current 25 mA V = 5 V DD 16 mA V = 3 V DD Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V = 5 V DD 5 µs Coming Out of Power-Down Mode. V = 3 V DD 6 LOGIC INPUTS Input Current ±1 µA V , Input Low Voltage 0.8 V V = 5 V ± 10% IL DD 0.6 V V = 3 V ± 10% DD 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 V V = 5 V ± 10% IH DD 2.1 V V = 3 V ± 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3.5 pF POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) All DACs active and excluding load currents DD V = 4.5 V to 5.5 V 300 450 µA Unbuffered Reference. V = V , V = GND. DD IH DD IL V = 2.5 V to 3.6 V 230 350 µA I increases by 50 µA at V > V – 100 mV. DD DD REF DD In Buffered Mode extra current is (5 +V /R ) µA. REF DAC I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 µA DD V = 2.5 V to 3.6 V 0.08 1 µA DD NOTES 1 See Terminology section. 2 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V = V and REF DD “Offset plus Gain” Error must be positive. Specifications subject to change without notice. –2– REV. 0 AD5332/AD5333/AD5342/AD5343 (V = 2.5 V to 5.5 V. R = 2 k� to GND; C = 200 pF to GND; all speciŢcations T to T unless DD L L MIN MAX 1 otherwise noted.) AC CHARACTERISTICS 3 B Version 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = 2 V. See Figure 20 REF AD5332 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H) AD5333 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5342 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) AD5343 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch Energy 6 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 3 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p. Unbuffered Mode REF Total Harmonic Distortion –70 dB V = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz REF NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Terminology section. 3 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. Specifications subject to change without notice. 1, 2, 3 TIMING CHARACTERISTICS (V = 2.5 V to 5.5 V, All speciŢcations T to T unless otherwise noted.) DD MIN MAX Parameter Limit at T , T Unit Condition/Comments MIN MAX t 0 ns min CS to WR Setup Time 1 t 0 ns min CS to WR Hold Time 2 t 20 ns min WR Pulsewidth 3 t 5 ns min Data, GAIN, BUF, HBEN Setup Time 4 t 4.5 ns min Data, GAIN, BUF, HBEN Hold Time 5 t 5 ns min Synchronous Mode. WR Falling to LDAC Falling 6 t 5 ns min Synchronous Mode. LDAC Falling to WR Rising 7 t 4.5 ns min Synchronous Mode. WR Rising to LDAC Rising 8 t 5 ns min Asynchronous Mode. LDAC Rising to WR Rising 9 t 4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling 10 t 20 ns min LDAC Pulsewidth 11 t 20 ns min CLR Pulsewidth 12 t 50 ns min Time Between WR Cycles 13 t 20 ns min A0 Setup Time 14 t 0 ns min A0 Hold Time 15 NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and DD t t 1 2 timed from a voltage level of (V + V )/2. IL IH 3 CS See Figure 1. t t 13 3 Specifications subject to change without notice. WR t t 5 4 DATA, GAIN, BUF, HBEN t t t 6 7 8 1 LDAC t t t 9 10 11 2 LDAC t 12 t t CLR 14 15 A0 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 1. Parallel Interface Timing Diagram REV. 0 –3– AD5332/AD5333/AD5342/AD5343 ABSOLUTE MAXIMUM RATINGS* θ Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W JA (T = 25°C unless otherwise noted) A θ Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W JA θ Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W JC V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD θ Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W JC Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V DD θ Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W JC Digital Output Voltage to GND . . . . . –0.3 V to V + 0.3 V DD Reflow Soldering Reference Input Voltage to GND . . . . –0.3 V to V + 0.3 V DD Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C V to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT DD Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C device at these or any other conditions above those listed in the operational Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C sections of this specification is not implied. Exposure to absolute maximum rating TSSOP Package conditions for extended periods may affect device reliability. Power Dissipation . . . . . . . . . . . . . . . (T max – T )/θ mW J A JA θ Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W JA ORDERING GUIDE Package Model Temperature Range Package Description Option AD5332BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 AD5333BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24 AD5342BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28 AD5343BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD SENSITIVE DEVICE ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 AD5332/AD5333/AD5342/AD5343 AD5332 FUNCTIONAL BLOCK DIAGRAM AD5332 PIN CONFIGURATION V A V REF DD 1 20 DB V B 7 REF V A 2 19 DB REF 6 POWER-ON AD5332 RESET V A 3 18 DB OUT 5 V B 4 17 DB OUT 4 8-BIT DAC INPUT DB 8-BIT 7 . V A GND 5 16 DB REGISTER BUFFER 3 REGISTER OUT AD5332 . DAC . TOP VIEW DB CS 6 15 DB 2 0 (Not to Scale) WR 7 14 DB 1 INTER- FACE DB A0 8 13 0 LOGIC CS INPUT DAC 8-BIT 9 12 V BUFFER V B CLR DD REGISTER REGISTER OUT DAC WR 10 11 PD LDAC A0 RESET POWER-DOWN CLR LOGIC LDAC V B PD GND REF AD5332 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1V B Unbuffered reference input for DAC B. REF 2V A Unbuffered reference input for DAC A. REF 3V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 4V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 A0 Address pin for selecting which DAC A and DAC B. 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 12 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10�F capacitor in parallel with a 0.1�F capacitor to GND. 13–20 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 REV. 0 –5– AD5332/AD5333/AD5342/AD5343 AD5333 FUNCTIONAL BLOCK DIAGRAM AD5333 PIN CONFIGURATION V V A REF DD 1 24 DB GAIN 9 2 23 BUF DB 8 AD5333 V B 3 22 REF DB 7 POWER-ON RESET DAC V A 4 21 DB REF 6 REGISTER 10-BIT BUF V A 5 20 DB OUT 5 AD5333 GAIN INPUT 10-BIT V B 6 19 DB BUFFER V A OUT 4 TOP VIEW OUT REGISTER DAC DB 9 (Not to Scale) . GND 7 18 DB . 3 . DB 8 17 DB CS 2 0 INTER- 9 16 DB WR 1 FACE LOGIC CS A0 10 15 DB 0 INPUT 10-BIT BUFFER V B OUT REGISTER DAC 11 14 V CLR WR DD DAC 12 13 LDAC PD A0 REGISTER RESET POWER-DOWN CLR LOGIC LDAC V B REF PD GND AD5333 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V or 0–2 V . REF REF 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3V B Reference input for DAC B. REF 4V A Reference input for DAC A. REF 5V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7 GND Ground reference point for all circuitry on the part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 A0 Address pin for selecting between DAC A and DAC B. 11 CLR Asynchronous active-low control input that clears all input registers and DAC registers to zeros. 12 LDAC Active-low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 14 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10�F capacitor in parallel with a 0.1�F capacitor to GND. 15–24 DB –DB 10 Parallel Data Inputs. DB is the MSB of these 10 bits. 0 9 9 –6– REV. 0 AD5332/AD5333/AD5342/AD5343 AD5342 FUNCTIONAL BLOCK DIAGRAM AD5342 PIN CONFIGURATION V A V REF DD GAIN 1 28 DB 11 2 27 BUF DB 10 AD5342 V B 3 26 DB REF 9 POWER-ON DAC RESET V A 4 25 DB REF 8 REGISTER V A 5 24 DB OUT 7 12-BIT INPUT 12-BIT V B 6 23 DB BUFFER V A OUT 6 REGISTER OUT DB DAC AD5342 11 . 7 22 DB . NC TOP VIEW 5 . (Not to Scale) DB 8 21 DB 0 NC 4 INTER- GND 9 20 DB FACE 3 LOGIC CS 10 19 DB CS 2 INPUT 12-BIT BUFFER V B REGISTER DAC OUT 11 18 DB WR WR 1 DAC A0 12 17 DB 0 A0 REGISTER CLR 13 16 V DD 14 15 LDAC PD RESET POWER-DOWN CLR LOGIC NC = NO CONNECT LDAC V B REF PD GND AD5342 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0-V or 0-2 V . REF REF 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3V B Reference Input for DAC B. REF 4V A Reference Input for DAC A. REF 5V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7, 8 NC No Connect. 9 GND Ground reference point for all circuitry on the part. 10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 11 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface. 12 A0 Address pin for selecting between DAC A and DAC B. 13 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 14 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 16 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10�F capacitor in parallel with a 0.1�F capacitor to GND. 17–28 DB –DB 12 Parallel Data Inputs. DB is the MSB of these 12 bits. 0 11 11 REV. 0 –7– AD5332/AD5333/AD5342/AD5343 AD5343 FUNCTIONAL BLOCK DIAGRAM AD5343 PIN CONFIGURATION V V REF DD HBEN 1 20 DB 7 2 19 DB V REF 6 POWER-ON RESET V A 3 18 DB OUT 5 AD5343 V B 4 17 DB HIGH BYTE OUT 4 REGISTER 12-BIT GND 5 16 DB 3 DB AD5343 7 . . TOP VIEW . CS 6 15 DB 2 . . (Not to Scale) . LOW BYTE DAC 12-BIT WR 7 14 DB 1 DB BUFFER V A REGISTER REGISTER OUT 0 DAC DB A0 8 13 0 HBEN 9 12 V CLR DD INTER- HIGH BYTE FACE CS REGISTER 10 11 PD LDAC LOGIC WR LOW BYTE DAC 12-BIT BUFFER V B REGISTER REGISTER OUT A0 DAC RESET CLR LDAC POWER-DOWN LOGIC PD GND AD5343 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2V Unbuffered reference input for both DACs. REF 3V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 4V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 A0 Address pin for selecting between DAC A and DAC B. 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 12 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10�F capacitor in parallel with a 0.1�F capacitor to GND. 13–20 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 –8– REV. 0 AD5332/AD5333/AD5342/AD5343 TERMINOLOGY GAIN ERROR RELATIVE ACCURACY AND OFFSET For the DAC, Relative Accuracy or Integral Nonlinearity (INL) ERROR is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer ACTUAL function. Typical INL versus Code plot can be seen in Figures OUTPUT 5, 6, and 7. VOLTAGE DIFFERENTIAL NONLINEARITY IDEAL Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed mono- tonic by design. Typical DNL versus Code plot can be seen in POSITIVE Figures 8, 9, and 10. OFFSET DAC CODE OFFSET ERROR This is a measure of the offset error of the DAC and the output Figure 3. Positive Offset Error and Gain Error amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 3. Because the DACs operate from a single supply, a negative offset cannot GAIN ERROR appear at the output of the buffer amplifier. Instead, there will AND OFFSET be a code close to zero at which the amplifier output saturates ERROR (amplifier footroom). Below this code there will be a deadband IDEAL over which the output voltage will not change. This is illustrated OUTPUT VOLTAGE in Figure 4. GAIN ERROR ACTUAL This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- NEGATIVE DAC CODE OFFSET trated in Figure 2. POSITIVE GAIN ERROR NEGATIVE GAIN ERROR ACTUAL DEADBAND CODES AMPLIFIER FOOTROOM OUTPUT (~ 1mV) VOLTAGE IDEAL NEGATIVE OFFSET DAC CODE Figure 4. Negative Offset Error and Gain Error Figure 2. Gain Error REV. 0 –9– AD5332/AD5333/AD5342/AD5343 OFFSET ERROR DRIFT DIGITAL CROSSTALK This is a measure of the change in Offset Error with changes in This is the glitch impulse transferred to the output of one DAC temperature. It is expressed in (ppm of full-scale range)/°C. at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of the other DAC. It is GAIN ERROR DRIFT expressed in nV-secs. This is a measure of the change in Gain Error with changes in tem- perature. It is expressed in (ppm of full-scale range)/°C. ANALOG CROSSTALK This is the glitch impulse transferred to the output of one DAC POWER-SUPPLY REJECTION RATIO (PSRR) due to a change in the output of the other DAC. It is measured This indicates how the output of the DAC is affected by changes in by loading one of the input registers with a full-scale code change the supply voltage. PSRR is the ratio of the change in V to a (all 0s to all 1s and vice versa) while keeping LDAC high. Then OUT change in V for full-scale output of the DAC. It is measured pulse LDAC low and monitor the output of the DAC whose DD in dBs. V is held at 2 V and V is varied ±10%. digital code was not changed. The area of the glitch is expressed REF DD in nV-secs. DC CROSSTALK This is the dc change in the output level of one DAC at mid- DAC-TO-DAC CROSSTALK scale in response to a full-scale code change (all 0s to all 1s and This is the glitch impulse transferred to the output of one DAC vice versa) and output change of the other DAC. It is expressed due to a digital code change and subsequent output change of in µV. the other DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code REFERENCE FEEDTHROUGH change (all 0s to all 1s and vice versa) with the LDAC pin set This is the ratio of the amplitude of the signal at the DAC output low and monitoring the output of the other DAC. The energy of to the reference input when the DAC output is not being updated the glitch is expressed in nV-secs. (i.e., LDAC is high). It is expressed in dBs. MULTIPLYING BANDWIDTH CHANNEL-TO-CHANNEL ISOLATION The amplifiers within the DAC have a finite bandwidth. The This is a ratio of the amplitude of the signal at the output of one Multiplying Bandwidth is a measure of this. A sine wave on the DAC to a sine wave on the reference input of the other DAC. It reference (with full-scale code loaded to the DAC) appears on is measured by grounding one V pin and applying a 10 kHz, the output. The Multiplying Bandwidth is the frequency at which REF 4 V peak-to-peak sine wave to the other V pin. It is expressed the output amplitude falls to 3 dB below the input. REF in dBs. TOTAL HARMONIC DISTORTION MAJOR-CODE TRANSITION GLITCH ENERGY This is the difference between an ideal sine wave and its attenuated Major-Code Transition Glitch Energy is the energy of the version using the DAC. The sine wave is used as the reference impulse injected into the analog output when the DAC changes for the DAC and the THD is a measure of the harmonics present state. It is normally specified as the area of the glitch in nV secs on the DAC output. It is measured in dBs. and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). DIGITAL FEEDTHROUGH Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to (CS held high). It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e. from all 0s to all 1s and vice versa. –10– REV. 0 Typical Performance Characteristics–AD5332/AD5333/AD5342/AD5343 12 1.0 3 T = 25�C A T = 25�C A T = 25�C A V = 5V DD V = 5V DD V = 5V 8 DD 2 0.5 4 1 0 0 0 –4 –1 –0.5 –8 –2 –1.0 –12 –3 0 50 100 150 200 250 0 0 1000 2000 3000 4000 200 400 600 800 1000 CODE CODE CODE Figure 5. AD5332 Typical INL Plot Figure 6. AD5333 Typical INL Plot Figure 7. AD5342 Typical INL Plot 0.3 0.6 1.0 T = 25�C T = 25�C A A T = 25�C A V = 5V V = 5V DD DD V = 5V DD 0.2 0.4 0.5 0.1 0.2 0 0 0 –0.1 –0.2 –0.5 –0.2 –0.4 –0.3 –0.6 –1 0 50 100 150 200 250 0 200 400 600 800 1000 0 1000 2000 3000 4000 CODE CODE CODE Figure 8. AD5332 Typical DNL Plot Figure 9. AD5333 Typical DNL Plot Figure 10. AD5342 Typical DNL Plot 1.0 1.00 1.00 V = 5V V = 5V DD DD V = 5V DD 0.75 T = 25�C 0.75 V = 2V A REF V = 2V REF 0.50 0.5 0.50 MAX DNL MAX INL GAIN ERROR 0.25 0.25 MAX INL MAX DNL 0.00 0 0.0 MIN DNL –0.25 MIN INL –0.25 OFFSET ERROR MIN INL MIN DNL –0.50 –0.50 –0.5 –0.75 –0.75 –1.0 –1.00 –1.00 2 345 –40 0 40 80 120 –40 0 40 80 120 V – V TEMPERATURE – �C REF TEMPERATURE – �C Figure 11. AD5332 INL and DNL Figure 12. AD5332 INL Error and Figure 13. AD5332 Offset Error Error vs. V DNL Error vs. Temperature and Gain Error vs. Temperature REF REV. 0 –11– ERROR – LSBs INL ERROR – LSBs DNL ERROR – LSBs ERROR – LSBs DNL ERROR – LSBs INL ERROR – LSBs DNL ERROR – LSBs ERROR – % INL ERROR – LSBs AD5332/AD5333/AD5342/AD5343 400 5 0.2 T = 25�C A � T = 25 C 350 V = 2V A 0.1 REF V = 5.5V 5V SOURCE DD V = 2V REF 4 300 0 GAIN ERROR 3V SOURCE V = 3.6V DD 250 –0.1 3 200 –0.2 2 150 –0.3 100 –0.4 OFFSET ERROR 1 3V SINK 5V SINK 50 –0.5 0 0 –0.6 0125 346 0125 346 ZERO-SCALE FULL-SCALE SINK/SOURCE CURRENT – mA DAC CODE V – Volts DD Figure 15. V Source and Sink Figure 16. Supply Current vs. DAC OUT Figure 14. Offset Error and Gain Current Capability Code Error vs. V DD 1600 0.5 400 T = 25�C A T = 25�C T = 25�C A A 1400 0.4 1200 300 1000 0.3 800 200 0.2 600 V = 5V 400 DD 100 0.1 200 V = 3V DD 0 0 0 0 12 3 4 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V – V V – V DD LOGIC V – V DD Figure 18. Power-Down Current vs. Figure 19. Supply Current vs. Logic Figure 17. Supply Current vs. Supply Supply Voltage Input Voltage Voltage � � V = 5V T = 25 C DD T = 25 C A A T = 25�C V = 5V V = 5V A DD DD CH2 V = 2V V = 2V LDAC REF REF CH1 V CH1 DD V A OUT V OUT V A OUT PD CH2 CH2 CH1 CH1 2V, CH2 200mV, TIME BASE = 200�s/DIV CH1 500mV, CH2 5V, TIME BASE = 1�s/DIV CH1 1V, CH2 5V, TIME BASE = 5�s/DIV Figure 21. Power-On Reset to 0 V Figure 20. Half-Scale Settling (1/4 to Figure 22. Exiting Power-Down to 3/4 Scale Code Change) Midscale –12– REV. 0 I – �A DD ERROR – % I – �A V – Volts DD OUT I – �A I – �A DD DD AD5332/AD5333/AD5342/AD5343 0.939 10 0.938 0 V = +5V DD 0.937 V = +3V –10 DD 0.936 0.935 –20 0.934 –30 0.933 0.932 –40 0.931 –50 0.930 0 0.929 –60 100 150 200 250 300 350 400 0.01 0.1 1 10 100 1k 10k 500 ns/DIV I – �A DD FREQUENCY – kHz Figure 24. AD5342 Major-Code Tran- Figure 25. Multiplying Bandwidth Figure 23. I Histogram with V = 3 DD DD sition Glitch Energy (Small-Signal Frequency Response) V and V = 5 V DD 0.2 T = 25�C A V = 2V REF 0 –0.2 –0.4 06 12 3 4 5 750ns/DIV V – V REF Figure 26. Full-Scale Error vs. V Figure 27. DAC-DAC Crosstalk REF FUNCTIONAL DESCRIPTION where: The AD5332/AD5333/AD5342/AD5343 are dual DACs fabri- D = decimal equivalent of the binary code which is loaded to cated on a CMOS process with resolutions of 8, 10, 12, and the DAC register: 12 bits, respectively. They are written to using a parallel inter- 0–255 for AD5332 (8 Bits) face. They operate from single supplies of 2.5 V to 5.5 V and 0–1023 for AD5333 (10 Bits) the output buffer amplifiers offer rail-to-rail output swing. The 0–4095 for AD5342/AD5343 (12 Bits) AD5333 and AD5342 have reference inputs that may be buff- ered to draw virtually no current from the reference source. N = DAC resolution Their output voltage range may be configured to be 0 to V REF Gain = Output Amplifier Gain (1 or 2) or 0 to 2 V . The reference inputs of the AD5332 and AD5343 REF are unbuffered and their output range is 0 to V . The devices REF V REF have a power-down feature that reduces current consumption to only 80 nA @ 3 V. REFERENCE BUF Digital-to-Analog Section BUFFER The architecture of one DAC channel consists of a reference GAIN buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the V pin provides the reference REF INPUT DAC RESISTOR V OUT voltage for the DAC. Figure 28 shows a block diagram of the REGISTER REGISTER STRING DAC architecture. Since the input coding to the DAC is straight OUTPUT binary, the ideal output voltage is given by: BUFFER AMPLIFIER D Figure 28. Single DAC Channel Architecture VV =× × Gain OUT REF N 2 REV. 0 –13– FULL-SCALE ERROR – %FSR FREQUENCY V – Volts OUT 4mV/DIV dB AD5332/AD5333/AD5342/AD5343 Resistor String PARALLEL INTERFACE The resistor string section is shown in Figure 29. It is simply a The AD5332, AD5333, and AD5342 load their data as a single string of resistors, each of value R. The digital code loaded to 8-, 10-, or 12-bit word, while the AD5343 loads data as a low the DAC register determines at what node on the string the byte of 8 bits and a high byte containing 4 bits. voltage is tapped off to be fed into the output amplifier. The Double-Buffered Interface voltage is tapped off by closing one of the switches connecting The AD5332/AD5333/AD5342/AD5343 DACs all have double- the string to the amplifier. Because it is a string of resistors, it buffered interfaces consisting of an input register and a DAC is guaranteed monotonic. register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write V REF (WR). R Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input R register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC TO OUTPUT R AMPLIFIER register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when LDAC is taken low. R This is useful if the user requires simultaneous updating of all DACs and peripherals. The user may write to both input regis- R ters individually and then, by pulsing the LDAC input low, both outputs will update simultaneously. Figure 29. Resistor String Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5343, because it allows the whole data DAC Reference Input word to be assembled in parallel before updating the DAC register. The DACs operate with an external reference. The AD5332, This prevents spurious outputs that could occur if the DAC AD5333, and AD5342 have separate reference inputs for each register were updated with only the high byte or the low byte. DAC, while the AD5343 has a single reference input for both DACs. The reference inputs on the AD5333 and AD5342 may These parts contain an extra feature whereby the DAC register be configured as buffered or unbuffered. The reference inputs is not updated unless its input register has been updated since of the AD5332 and AD5343 are unbuffered. The buffered/ the last time that LDAC was brought low. Normally, when unbuffered option is controlled by the BUF pin. LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5332/ In buffered mode (BUF = 1) the current drawn from an exter- AD5333/AD5342/AD5343, the part will only update the DAC nal reference voltage is virtually zero, as the impedance is at register if the input register has been changed since the last least 10 MΩ. The reference input range is 1 V to V . DD time the DAC register was updated. This removes unnecessary In unbuffered mode (BUF = 0) the user can have a reference crosstalk. voltage as low as 0.25 V and as high as V since there is no DD Clear Input (CLR) restriction due to headroom and footroom of the reference ampli- CLR is an active low, asynchronous clear that resets the input and fier. The impedance is still large at typically 180 kΩ for 0–V REF DAC registers. mode and 90 kΩ for 0–2 V mode. REF Chip Select Input (CS) If using an external buffered reference (e.g., REF192) there is CS is an active low input that selects the device. no need to use the on-chip buffer. Write Input (WR) Output AmpliŢer WR is an active low input that controls writing of data to the The output buffer amplifier is capable of generating output volt- device. Data is latched into the input register on the rising edge ages to within 1 mV of either rail. Its actual range depends on of WR. V , GAIN, the load on V and offset error. REF OUT Load DAC Input (LDAC) If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V LDAC transfers data from the input register to the DAC register to V . REF (and hence updates the outputs). Use of the LDAC function enables If a gain of 2 is selected (GAIN = 1), on the AD5333 and AD5342 double buffering of the DAC data, GAIN and BUF. There are the output range is 0.001 V to 2 V . REF two LDAC modes: The output amplifier is capable of driving a load of 2 kΩ to Synchronous Mode: In this mode the DAC register is updated GND or V , in parallel with 500 pF to GND or V . The DD DD after new data is read in on the rising edge of the WR input. source and sink capabilities of the output amplifier can be seen LDAC can be tied permanently low or pulsed as in Figure 1. in Figure 15. Asynchronous Mode: In this mode the outputs are not updated The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB at the same time that the input register is written to. When LDAC (at 8 bits) of 6 µs with the output unloaded. See Figure 20. goes low the DAC register is updated with the contents of the input register. –14– REV. 0 AD5332/AD5333/AD5342/AD5343 High-Byte Enable Input (HBEN) POWER-DOWN MODE High-Byte Enable is a control input on the AD5343 only that The AD5332/AD5333/AD5342/AD5343 have low power con- determines if data is written to the high-byte input register or sumption, dissipating typically 0.69 mW with a 3 V supply and the low-byte input register. 1.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into The low data byte of the AD5343 consists of data bits 0 to 7 at power-down mode, which is selected by taking pin PD low. data inputs DB to DB , while the high byte consists of data 0 7 bits 8 to 11 at data inputs DB to DB . DB to DB are ignored When the PD pin is high, the DACs work normally with a typical 0 3 4 7 during a high byte write, but they may be used for data to power consumption of 300 µA at 5 V (230 µA at 3 V). In power- set up the reference input as buffered/unbuffered, and buffer down mode, however, the supply current falls to 200 nA at 5 V amplifier gain. See Figure 32. (80 nA at 3 V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also internally HIGH BYTE switched from the output of the amplifier, making it open-circuit. X X XX DB11 DB10 DB9 DB8 This has the advantage that the outputs are three-state while the part is in power-down mode, and provides a defined input LOW BYTE condition for whatever is connected to the outputs of the DAC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 amplifiers. The output stage is illustrated in Figure 31. X = UNUSED BIT Figure 30. Data Format for AD5343 RESISTOR POWER-ON RESET AMPLIFIER VOUT STRING DAC The AD5332/AD5333/AD5342/AD5343 are provided with a power-on reset function, so that they power up in a defined state. POWER-DOWN CIRCUITRY The power-on state is: • Normal operation Figure 31. Output Stage During Power-Down • Reference input unbuffered The bias generator, the output amplifier, the resistor string, and •0 – V output range REF all other associated linear circuitry are all shut down when the • Output voltage set to 0 V power-down mode is activated. However, the contents of the Both input and DAC registers are filled with zeros and remain registers are unaffected when in power-down. The time to exit so until a valid write sequence is made to the device. This is power-down is typically 2.5 µs for V = 5 V and 5 µs when DD particularly useful in applications where it is important to know V = 3 V. This is the time from a rising edge on the PD pin to DD the state of the DAC outputs while the device is powering up. when the output voltage deviates from its power-down voltage. See Figure 22. Table I. AD5332/AD5333/AD5342 Truth Table CLR LDAC CS WR A0 Function 111X X No Data Transfer 1 1 X 1 X No Data Transfer 0 X X X X Clear All Registers 1100➝1 0 Load DAC A Input Register 1100➝1 1 Load DAC B Input Register 1 0 X X X Update DAC Registers X = don’t care. Table II. AD5343 Truth Table CLR LDAC CS WR A0 HBEN Function 1 1 1 X X X No Data Transfer 1 1 X 1 X X No Data Transfer 0 X X X X X Clear All Registers 11 0 0➝1 0 0 Load DAC A Low Byte Input Register 11 0 0➝1 0 1 Load DAC A High Byte Input Register 11 0 0➝1 1 0 Load DAC B Low Byte Input Register 11 0 0➝1 1 1 Load DAC B High Byte Input Register 1 0 X X X X Update DAC Registers X = don’t care. REV. 0 –15– AD5332/AD5333/AD5342/AD5343 SUGGESTED DATABUS FORMATS Driving V from the Reference Voltage DD In most applications GAIN and BUF are hard-wired. However, If an output range of zero to V is required when the reference DD if more flexibility is required, they can be included in a databus. inputs are configured as unbuffered, the simplest solution is to This enables you to software program GAIN, giving the option connect the reference inputs to V . As this supply may not be DD of doubling the resolution in the lower half of the DAC range. very accurate, and may be noisy, the devices may be powered In a bused system GAIN and BUF may be treated as data inputs from the reference voltage, for example using a 5 V reference since they are written to the device during a write operation and such as the ADM663 or ADM666, as shown in Figure 34. take effect when LDAC is taken low. This means that the refer- 6V TO 16V ence buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. 0.1�F 10�F The AD5333 and AD5342 databuses must be at least 10, and 12 bits wide respectively, and are best suited to a 16-bit data- bus system. V IN AD5332/AD5333/ Examples of data formats for putting GAIN and BUF on a 16- ADM663/ADM666 AD5342/AD5343 V bit databus are shown in Figure 32. Note that any unused bits SENSE DD above the actual DAC data may be used for BUF and GAIN. V OUT(2) V * REF V * OUT VSET GND SHDN 0.1�F AD5333 GND X X X BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X AD5342 *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT X X DB11 DB10 DB9 DB8 DB6 DB4 DB2 DB1 BUF GAIN DB7 DB5 DB3 DB0 Figure 34. Using an ADM663/ADM666 as Power and Refer- X = UNUSED BIT ence to AD5332/AD5333/AD5342/AD5343 Figure 32. GAIN and BUF Data on a 16-Bit Bus Bipolar Operation Using the AD5332/AD5333/AD5342/AD5343 The AD5332/AD5333/AD5342/AD5343 have been designed APPLICATIONS INFORMATION for single supply operation, but bipolar operation is achievable Typical Application Circuits using the circuit shown in Figure 35. The circuit shown has been The AD5332/AD5333/AD5342/AD5343 can be used with a configured to achieve an output voltage range of –5 V < V < O wide range of reference voltages, especially if the reference inputs +5 V. Rail-to-rail operation at the amplifier output is achievable are configured to be unbuffered, in which case the devices offer using an AD820 or OP295 as the output amplifier. full, one-quadrant multiplying capability over a reference range of 0.25 V to V . More typically, these devices may be used with a DD The output voltage for any input code can be calculated as fixed, precision reference voltage. Figure 33 shows a typical follows: setup for the devices when using an external reference connected to N V = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V × D/2 )] – R4 × V /R3 O REF REF the unbuffered reference inputs. If the reference inputs are unbuf- where: fered, the reference input range is from 0.25 V to V , but if the DD on-chip reference buffers are used, the reference range is reduced. D is the decimal equivalent of the code loaded to the DAC, N is Suitable references for 5 V operation are the AD780 and REF192. DAC resolution and V is the reference voltage input. REF For 2.5 V operation, a suitable external reference would be the With: AD589, a 1.23 V bandgap reference. V = 2.5 V REF V = 2.5V TO 5.5V DD R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ and V = 5 V. DD N V = (10 × D/2 ) – 5 OUT 10�F 0.1�F V = 5V DD R4 V IN 20k� V DD EXT V * V OUT REF 0.1�F 10�F REF V * +5V OUT R3 GND 10k� AD5332/AD5333/ V AD5342/AD5343 �5V IN V AD780/REF192 DD EXT V * V REF WITH V = 5V REF OUT DD OR –5V 0.1�F GND GND AD5332/AD5333/ AD589 WITH V = 2.5V DD R1 AD5342/AD5343 10k� *ONLY ONE CHANNEL OF V AND V SHOWN V * REF OUT OUT AD780/REF192 R2 GND WITH V = 5V DD Figure 33. AD5332/AD5333/AD5342/AD5343 Using 20k� OR External Reference AD589 WITH V = 2.5V DD *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT Figure 35. Bipolar Operation using the AD5332/AD5333/ AD5342/AD5343 –16– REV. 0 AD5332/AD5333/AD5342/AD5343 Decoding Multiple AD5332/AD5333/AD5342/AD5343 Note that the AD5343 has only a single reference input. If using The CS pin on these devices can be used in applications to decode the AD5332, AD5333, or AD5342, both reference inputs must a number of DACs. In this application, all DACs in the system be connected. receive the same data and WR pulses, but only the CS to one of 5V the DACs will be active at any one time, so data will only be 0.1�F 10�F 1k� 1k� written to the DAC whose CS is low. If multiple AD5343s are V IN FAIL PASS being used, a common HBEN line will also be required to V DD determine if the data is written to the high-byte or low-byte V V A* REF REF register of the selected DAC. V OUT V B* REF PASS/ The 74HC139 is used as a 2- to 4-line decoder to address any 1/2 FAIL AD5332/AD5333/ CMP04 of the DACs in the system. To prevent timing errors from AD5342 occurring, the enable input should be brought to its inactive V B OUT 1/6 74HC05 state while the coded address inputs are changing state. Figure 36 shows a diagram of a typical setup for decoding multiple devices GND in a system. Once data has been written sequentially to all DACs in *NOT AD5343 a system, all the DACs can be updated simultaneously using a Figure 37. Programmable Window Detector common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero. Programmable Current Source Figure 38 shows the AD5332/AD5333/AD5342/AD5343 used as the control element of a programmable current source. In this AD5332/AD5333/ AD5342/AD5343 example, the full-scale current is set to 1 mA. The output volt- A1 A0 age from the DAC is applied across the current setting resistor HBEN* HBEN of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, WR WR DATA LDAC LDAC INPUTS which gives an adjustment of about ±5%. Suitable transistors to CLR CLR place in the feedback loop of the amplifier include the BC107 CS and the 2N3904, which enable the current source to operate AD5332/AD5333/ from a minimum V of 6 V. The operating range is deter- SOURCE AD5342/AD5343 mined by the operating characteristics of the transistor. Suitable A0 HBEN* amplifiers include the AD820 and the OP295, both having rail- WR DATA to-rail operation on their outputs. The current for any digital LDAC V INPUTS DD input code and resistor value can be calculated as follows: CLR CS V CC D 1G ENABLE 1Y0 AD5332/AD5333/ IG =×V × mA REF N AD5342/AD5343 () 2 × R 1A 1Y1 A0 CODED Where: 74HC139 HBEN* ADDRESS 1Y2 1B WR DATA G is the gain of the buffer amplifier (1 or 2) LDAC INPUTS 1Y3 D is the digital equivalent of the digital input code CLR N is the DAC resolution (8, 10, or 12 bits) DGND CS R is the sum of the resistor plus adjustment potentiometer in kΩ AD5332/AD5333/ AD5342/AD5343 V = 5V DD A0 HBEN* *AD5343 ONLY WR DATA LDAC INPUTS 0.1�F 10�F CLR V SOURCE CS V 5V IN LOAD V Figure 36. Decoding Multiple DAC Devices DD EXT V * V V * REF OUT OUT REF 0.1�F GND AD5332/AD5333/ AD5332/AD5333/AD5342/AD5343 as a Digitally Program- AD5342/AD5343 mable Window Detector AD780/REF192 A digitally programmable upper/lower limit detector using the WITH V = 5V 4.7k� DD two DACs in the AD5332/AD5333/AD5342 is shown in Figure GND 37. The upper and lower limits for the test are loaded to DACs 470� A and B which, in turn, set the limits on the CMP04. If a signal *ONLY ONE CHANNEL OF V AND V SHOWN REF OUT at the V input is not within the programmed window, an LED IN will indicate the fail condition. Figure 38. Programmable Current Source REV. 0 –17– DATA BUS AD5332/AD5333/AD5342/AD5343 Coarse and Fine Adjustment Using the AD5332/AD5333/ Power Supply Bypassing and Grounding AD5342/AD5343 In any circuit where accuracy is important, careful consideration The DACs in the AD5332/AD5333/AD5342/AD5343 can be of the power supply and ground return layout helps to ensure paired together to form a coarse and fine adjustment function, the rated performance. The printed circuit board on which the as shown in Figure 39. DAC A is used to provide the coarse AD5332/AD5333/AD5342/AD5343 is mounted should be adjustment while DAC B provides the fine adjustment. Varying designed so that the analog and digital sections are separated, the ratio of R1 and R2 will change the relative effect of the coarse and confined to certain areas of the board. If the device is in a and fine adjustments. With the resistor values shown the output system where multiple devices require an AGND-to-DGND amplifier has unity gain for the DAC A output, so the output connection, the connection should be made at one point only. range is 0 V to 2.5 V – 1 LSB. For DAC B the amplifier has a gain The star ground point should be established as closely as pos- –3 of 7.6 × 10 , giving DAC B a range equal to 2 LSBs of DAC A. sible to the device. The AD5332/AD5333/AD5342/AD5343 should have ample supply bypassing of 10 µF in parallel with The circuit is shown with a 2.5 V reference, but reference volt- 0.1 µF on the supply located as close to the package as pos- ages up to V may be used. The op amps indicated will allow a DD sible, ideally right up against the device. The 10 µF capacitors rail-to-rail output swing. are the tantalum bead type. The 0.1 µF capacitor should have Note that the AD5343 has only a single reference input. If using low Effective Series Resistance (ESR) and Effective Series Induc- the AD5332, AD5333, or AD5342, both reference inputs must tance (ESI), like the common ceramic types that provide a low be connected. impedance path to ground at high frequencies to handle tran- sient currents due to internal logic switching. V = 5V DD R3 R4 The power supply lines of the device should use as large a trace 51.2k� 390� as possible to provide low impedance paths and reduce the effects 0.1�F10�F +5V of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiat- V IN R1 V DD V ing noise to other parts of the board, and should never be run 390� OUT EXT V V A* V A REF OUT OUT REF near the reference inputs. Avoid crossover of digital and ana- 0.1�F AD5332/AD5333/ GND log signals. Traces on opposite sides of the board should run AD5342/AD5343 R2 51.2k� at right angles to each other. This reduces the effects of feed- V B OUT AD780/REF192 through through the board. A microstrip technique is by far V B* REF WITH V = 5V DD the best, but not always possible with a double-sided board. In GND this technique, the component side of the board is dedicated to *NOT AD5343 ground plane while signal traces are placed on the solder side. Figure 39. Coarse and Fine Adjustment –18– REV. 0 AD5332/AD5333/AD5342/AD5343 Table III. Overview of AD53xx Parallel Devices Part No. Resolution DNL V Pins Settling Time Additional Pin Functions Package Pins REF SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 µs �� � TSSOP 20 AD5331 10 ±0.5 1 7 µs �� TSSOP 20 AD5340 12 ±1.0 1 8 µs �� � TSSOP 24 AD5341 12 ±1.0 1 8 µs � ��� TSSOP 20 DUALS AD5332 8 ±0.25 2 6 µs � TSSOP 20 AD5333 10 ±0.5 2 7 µs �� � TSSOP 24 AD5342 12 ±1.0 2 8 µs �� � TSSOP 28 AD5343 12 ±1.0 1 8 µs �� TSSOP 20 QUADS AD5334 8 ±0.25 2 6 µs �� TSSOP 24 AD5335 10 ±0.5 2 7 µs �� TSSOP 24 AD5336 10 ±0.5 4 7 µs �� TSSOP 28 AD5344 12 ±1.0 4 8 µs TSSOP 28 Table IV. Overview of AD53xx Serial Devices Part No. Resolution No. of DACS DNL Interface Settling Time Package Pins SINGLES AD5300 8 1 ±0.25 SPI 4 µs SOT-23, MicroSOIC 6, 8 AD5310 10 1 ±0.5 SPI 6 µs SOT-23, MicroSOIC 6, 8 AD5320 12 1 ±1.0 SPI 8 µs SOT-23, MicroSOIC 6, 8 AD5301 8 1 ±0.25 2-Wire 6 µs SOT-23, MicroSOIC 6, 8 AD5311 10 1 ±0.5 2-Wire 7 µs SOT-23, MicroSOIC 6, 8 AD5321 12 1 ±1.0 2-Wire 8 µs SOT-23, MicroSOIC 6, 8 DUALS AD5302 8 2 ±0.25 SPI 6 µs MicroSOIC 8 AD5312 10 2 ±0.5 SPI 7 µs MicroSOIC 8 AD5322 12 2 ±1.0 SPI 8 µs MicroSOIC 8 AD5303 8 2 ±0.25 SPI 6 µs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 µs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 µs TSSOP 16 QUADS AD5304 8 4 ±0.25 SPI 6 µs MicroSOIC 10 AD5314 10 4 ±0.5 SPI 7 µs MicroSOIC 10 AD5324 12 4 ±1.0 SPI 8 µs MicroSOIC 10 AD5305 8 4 ±0.25 2-Wire 6 µs MicroSOIC 10 AD5315 10 4 ±0.5 2-Wire 7 µs MicroSOIC 10 AD5325 12 4 ±1.0 2-Wire 8 µs MicroSOIC 10 AD5306 8 4 ±0.25 2-Wire 6 µs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 µs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 µs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 µs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 µs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 µs TSSOP 16 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 –19– AD5332/AD5333/AD5342/AD5343 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Thin Shrink Small Outline Package TSSOP (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 10 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) 0.020 (0.50) PLANE 0.0035 (0.090) 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24) 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.020 (0.50) 0.0035 (0.090) 28-Lead Thin Shrink Small Outline Package TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.020 (0.50) 0.0035 (0.090) –20– REV. 0 PRINTED IN U.S.A. C3829–2.5–4/00 (rev. 0)