ANALOG DEVICES AD5341

2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION 1 AD5330: single 8-bit DAC in 20-lead TSSOP The AD5330/AD5331/AD5340/AD5341 are single 8-/10-/12- AD5331: single 10-bit DAC in 20-lead TSSOP bit DACs. They operate from a 2.5 V to 5.5 V supply consuming AD5340: single 12-bit DAC in 24-lead TSSOP just 115 μA at 3 V and feature a power-down mode that further AD5341: single 12-bit DAC in 20-lead TSSOP reduces the current to 80 nA. The devices incorporate an on-chip Low power operation: 115 μA @ 3 V, 140 μA @ 5 V output buffer that can drive the output to both supply rails, but PD Power-down to 80 nA @ 3 V, 200 nA @ 5 V via Pin the AD5330, AD5340, and AD5341 allow a choice of buffered 2.5 V to 5.5 V power supply or unbuffered reference input. Double-buffered input logic The AD5330/AD5331/AD5340/AD5341 have a parallel Guaranteed monotonic by design over all codes CS interface. selects the device and data is loaded into the Buffered/unbuffered reference input options input registers on the rising edge of WR. Output range: 0 V to V or 0 V to 2 × V REF REF Power-on reset to 0 V The GAIN pin allows the output range to be set at 0 V to VREF or LDAC Simultaneous update of DAC outputs via pin 0 V to 2 × VREF. CLR Asynchronous facility Input data to the DACs is double-buffered, allowing simultane- Low power parallel data interface LDAC ous update of multiple DACs in a system using the pin. On-chip rail-to-rail output buffer amplifiers CLR An asynchronous input is also provided, which resets the Temperature range: −40°C to +105°C contents of the input register and the DAC register to all zeros. APPLICATIONS These devices also incorporate a power-on reset circuit that Portable battery-powered instruments ensures that the DAC output powers on to 0 V and remains Digital gain and offset adjustment there until valid data is written to the device. Programmable voltage and current sources The AD5330/AD5331/AD5340/AD5341 are available in thin Programmable attenuators shrink small outline packages (TSSOP). Industrial process control 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM V V REF DD 3 12 POWER-ON RESET AD5330 BUF 1 INPUT DAC GAIN 8 REGISTER REGISTER 8-BIT DB 20 BUFFER 4 7 V . OUT . DAC DB 13 0 6 CS 7 WR RESET POWER-DOWN 9 CLR LOGIC 10 LDAC 11 5 PD GND Figure 1. AD5330 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 06852-001 AD5330/AD5331/AD5340/AD5341 TABLE OF CONTENTS Features .............................................................................................. 1 Double-Buffered Interface ........................................................ 18 Applications ....................................................................................... 1 Clear Input (CLR) ...................................................................... 18 General Description ......................................................................... 1 Chip Select Input (CS) ............................................................... 18 Functional Block Diagram .............................................................. 1 Write Input (WR) ....................................................................... 18 Revision History ............................................................................... 2 LDAC Load DAC Input ( ) .......................................................... 18 Specif ica t ions ..................................................................................... 3 High-Byte Enable Input (HBEN) ............................................. 18 AC Characteristics ........................................................................ 4 Power-On Reset .......................................................................... 18 Timing Characteristics ................................................................ 5 Power-Down Mode ........................................................................ 19 Absolute Maximum Ratings ............................................................ 6 Suggested Databus Formats .......................................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configurations and Function Descriptions ........................... 7 Typical Application Circuits ..................................................... 21 Terminology .................................................................................... 11 Driving VDD From the Reference Voltage ............................... 21 Typical Performance Characteristics ........................................... 13 Bipolar Operation Using the AD5330/AD5331/ Theory of Operation ...................................................................... 17 AD5340/AD5341 ......................................................................... 21 Digital-to-Analog Section ......................................................... 17 Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21 Resistor String ............................................................................. 17 Programmable Current Source ................................................ 22 DAC Reference Input ................................................................. 17 Power Supply Bypassing and Grounding ................................ 22 Output Amplifier ........................................................................ 17 Outline Dimensions ....................................................................... 24 Parallel Interface ............................................................................. 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 2/08—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 4 .......................................................................... 16 Replaced Driving V from the Reference Voltage Section ..... 21 DD Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 25 4/00—Revision 0: Initial Version Rev. A | Page 2 of 28 AD5330/AD5331/AD5340/AD5341 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5330 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5331 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5340/AD5341 Resolution 12 Bits Relative Accuracy ±2 ±16 LSBs Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR 5 Lower Deadband 10 60 mV Lower deadband exists only if offset error is negative Upper Deadband 10 60 mV V = 5 V; upper deadband exists only if V = V DD REF DD 6 Offset Error Drift −12 ppm of FSR/°C 6 Gain Error Drift −5 ppm of FSR/°C 6 DC Power Supply Rejection Ratio −60 dB ΔVDD = ±10% 6 DAC REFERENCE INPUT VREF Input Range 1 VDD V Buffered reference (AD5330, AD5340, and AD5341) 0.25 VDD V Unbuffered reference VREF Input Impedance >10 MΩ Buffered reference (AD5330, AD5340, and AD5341) 180 kΩ Unbuffered reference; gain = 1, input impedance = R DAC 90 kΩ Unbuffered reference; gain = 2, input impedance = R DAC Reference Feedthrough −90 dB Frequency = 10 kHz 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-rail operation 4, 7 Maximum Output Voltage V − 0.001 V max DD DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V 15 mA V = 3 V DD Power-Up Time 2.5 μs Coming out of power-down mode; V = 5 V DD 5 μs Coming out of power-down mode; V = 3 V DD 6 LOGIC INPUTS Input Current ±1 μA Input Low Voltage, V 0.8 V V = 5 V ± 10% IL DD 0.6 V VDD = 3 V ± 10% 0.5 V VDD = 2.5 V Input High Voltage, VIH 2.4 V VDD = 5 V ± 10% 2.1 V V = 3 V ± 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3 pF Rev. A | Page 3 of 28 AD5330/AD5331/AD5340/AD5341 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS VDD 2.5 5.5 V IDD (Normal Mode) DACs active and excluding load currents. Unbuffered VDD = 4.5 V to 5.5 V 140 250 μA Reference, VIH = VDD, VIL = GND V = 2.5 V to 3.6 V 115 200 μA I increases by 50 μA at V > V − 100 mV. DD DD REF DD In buffered mode, extra current is (5 + V /R ) μA, REF DAC where RDAC is the resistance of the resistor string. IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V 0.2 1 μA VDD = 2.5 V to 3.6 V 0.08 1 μA 1 See the Terminology section. 2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095). 4 DC specifications tested with output unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 1 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 3 B Version 2 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = 2 V; see Figure 29 AD5330 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5331 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5340 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) AD5341 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major Code Transition Glitch Energy 6 nV/s 1 LSB change around major carry Digital Feedthrough 0.5 nV/s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p; unbuffered mode REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p; frequency = 10 kHz REF 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. Rev. A | Page 4 of 28 AD5330/AD5331/AD5340/AD5341 1, 2, 3 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Condition/Comments t 0 ns min 1 CS to WR setup time. t 0 ns min CS to WR hold time. 2 t 20 ns min WR pulse width. 3 t 5 ns min Data, GAIN, BUF, HBEN setup time. 4 t5 4.5 ns min Data, GAIN, BUF, HBEN hold time. t6 5 ns min Synchronous mode; WR falling to LDAC falling. t 5 ns min Synchronous mode; LDAC falling to WR rising. 7 t 4.5 ns min Synchronous mode; WR rising to LDAC rising. 8 t 5 ns min Asynchronous mode; LDAC rising to WR rising. 9 t10 4.5 ns min Asynchronous mode; WR rising to LDAC falling. t11 20 ns min LDAC pulse width. t12 20 ns min CLR pulse width. t 50 ns min Time between WR cycles. 13 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. R F DD IL IH 3 See Figure 2. t t 1 2 CS t t 3 13 WR t 5 DATA, t 4 GAIN, BUF, HBEN t 8 t t 6 7 1 LDAC t 9 t t 10 11 2 LDAC t 12 CLR NOTES: 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 2. Parallel Interface Timing Diagram Rev. A | Page 5 of 28 06852-002 AD5330/AD5331/AD5340/AD5341 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to VDD + 0.3 V device reliability. Reference Input Voltage to GND −0.3 V to V + 0.3 V DD VOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range ESD CAUTION Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package Power Dissipation (T max – T )/θ mW J A JA 1 θ Thermal Impedance (20-Lead TSSOP) 85°C/W JA 1 θJA Thermal Impedance (24-Lead TSSOP) 80°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec 1 Thermal resistance (JEDEC 4-layer (2S2P) board). Rev. A | Page 6 of 28 AD5330/AD5331/AD5340/AD5341 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V V REF DD 3 12 POWER-ON RESET AD5330 BUF 1 BUF 1 20 DB 7 INPUT DAC GAIN 8 NC 2 19 DB REGISTER REGISTER 6 8-BIT DB 20 4 7 BUFFER V . OUT . DAC V 3 18 DB REF 5 DB 13 0 8-BIT V 4 17 DB OUT 4 AD5330 6 CS 5 16 GND DB TOP VIEW 3 (Not to Scale) 7 6 15 CS DB WR 2 RESET 7 14 WR DB 9 POWER-DOWN 1 CLR LOGIC 8 13 GAIN DB 0 10 LDAC 9 12 CLR V DD 10 11 LDAC PD 11 5 PD GND NC = NO CONNECT Figure 3. AD5330 Functional Block Diagram Figure 4. AD5330 Pin Configuration Table 5. AD5330 Pin Function Descriptions Pin No. Mnemonic Description 1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 2 NC No Connect. 3 VREF Reference Input. 4 VOUT Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 Asynchronous active low control input that clears all input registers and DAC registers to zero. CLR 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 Rev. A | Page 7 of 28 INTERFACE LOGIC 06852-003 06852-004 AD5330/AD5331/AD5340/AD5341 V V REF DD 3 12 POWER-ON RESET AD5331 DB 1 8 DB 2 9 DAC INPUT GAIN 8 1 20 DB DB 8 7 REGISTER REGISTER 10-BIT DB 20 7 BUFFER 4 V . OUT 2 19 DAC DB DB . 9 6 DB 13 0 V 3 18 DB REF 5 6 10-BIT CS V 4 17 OUT DB 4 AD5331 5 16 GND DB 7 TOP VIEW 3 WR (Not to Scale) RESET 6 15 CS DB 2 POWER-DOWN 9 CLR LOGIC WR 7 14 DB 1 10 LDAC GAIN 8 13 DB 0 CLR 9 12 V DD 11 5 10 11 LDAC PD PD GND Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration Table 6. AD5331 Pin Function Descriptions Pin No. Mnemonic Description 1 DB8 Parallel Data Input. 2 DB9 Most Significant Bit of Parallel Data Input. 3 VREF Unbuffered Reference Input. 4 VOUT Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 CLR Active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. 0 7 Rev. A | Page 8 of 28 INTERFACE LOGIC 06852-005 06852-006 AD5330/AD5331/AD5340/AD5341 V V REF DD 4 14 POWER-ON RESET AD5340 DB 1 10 DB 2 11 1 24 DB DB 10 9 BUF 3 INPUT DAC DB 2 23 DB 11 8 GAIN 10 REGISTER REGISTER 12-BIT 5 BUF 3 22 BUFFER V DB OUT DB 24 DAC 7 9 . . V 4 21 DB 15 REF 6 DB 0 12-BIT V 5 20 OUT DB 5 8 CS AD5340 NC 6 19 DB TOP VIEW 4 9 WR (Not to Scale) 7 18 GND DB 3 RESET POWER-DOWN 11 8 17 DB CLR CS 2 LOGIC 9 16 DB WR 1 12 LDAC 10 15 DB GAIN 0 11 14 CLR V DD 13 7 12 13 LDAC PD PD GND Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration Table 7. AD5340 Pin Function Descriptions Pin No. Mnemonic Description 1 DB Parallel Data Input. 10 2 DB Most Significant Bit of Parallel Data Input. 11 3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 4 V Reference Input. REF 5 VOUT Output of DAC. Buffered output with rail-to-rail operation. 6 NC No Connect. 7 GND Ground reference point for all circuitry on the part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 11 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 12 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 13 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 14 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 15 to 24 DB to DB Ten Parallel Data Inputs. 0 9 Rev. A | Page 9 of 28 INTERFACE LOGIC 06852-007 06852-008 AD5330/AD5331/AD5340/AD5341 V V REF DD 3 12 POWER-ON RESET AD5341 HIGH BYTE REGISTER BUF 2 GAIN 8 1 20 HBEN DB 7 DB 20 7 . 2 19 LOW BYTE BUF DB . 12-BIT 6 4 BUFFER V OUT REGISTER 13 DAC DB 0 V 3 18 REF DB 5 10-BIT 1 V 4 17 HBEN OUT DB 4 AD5341 5 16 GND DB TOP VIEW 3 6 CS (Not to Scale) CS 6 15 RESET DB 2 7 POWER-DOWN WR LOGIC WR 7 14 DB 1 9 CLR GAIN 8 13 DB 0 10 LDAC CLR 9 12 V DD 11 5 10 11 LDAC PD PD GND Figure 9. AD5341 Functional Block Diagram Figure 10. AD5341 Pin Configuration Table 8. AD5341 Pin Function Descriptions Pin No. Mnemonic Description 1 HBEN High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3 V Reference Input. REF 4 VOUT Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 Rev. A | Page 10 of 28 INTERFACE LOGIC DAC REGISTER 06852-009 06852-010 AD5330/AD5331/AD5340/AD5341 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) GAIN ERROR AND For the DAC, relative accuracy or INL is a measure of the OFFSET ERROR maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 14, Figure 15, and Figure 16. OUTPUT Differential Nonlinearity (DNL) VOLTAGE ACTUAL IDEAL DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures mono- tonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 17, Figure 18, and POSITIVE Figure 19. OFFSET Gain Error DAC CODE This is a measure of the span error of the DAC (including any Figure 12. Positive Offset Error and Gain Error error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. This is illustrated in Figure 11. GAIN ERROR AND OFFSET ERROR Offset Error This is a measure of the offset error of the DAC and the output OUTPUT amplifier. It is expressed as a percentage of the full-scale range. VOLTAGE If the offset voltage is positive, the output voltage is still positive ACTUAL at zero input code. This is shown in Figure 12. Because the IDEAL DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code, there is a deadband over NEGATIVE DAC CODE OFFSET which the output voltage does not change. This is illustrated in Figure 13. POSITIVE GAIN ERROR NEGATIVE GAIN ERROR DEADBAND CODES AMPLIFIER OUTPUT FOOTROOM VOLTAGE (~1mV) ACTUAL IDEAL NEGATIVE OFFSET DAC CODE Figure 13. Negative Offset Error and Gain Error Figure 11. Gain Error Rev. A | Page 11 of 28 06852-011 06852-012 06852-013 AD5330/AD5331/AD5340/AD5341 Offset Error Drift Digital Feedthrough This is a measure of the change in offset error with changes in Digital Feedthrough is a measure of the impulse injected into temperature. It is expressed in (ppm of full-scale range)/°C. the analog output of the DAC from the digital input pins of the CS device; it is measured when the DAC is not being written to ( Gain Error Drift held high). It is specified in nV/s and is measured with a full- This is a measure of the change in gain error with changes in scale change on the digital input pins, that is, from all 0s to all temperature. It is expressed in (ppm of full-scale range)/°C. 1s and vice versa. Power-Supply Rejection Ratio (PSRR) Multiplying Bandwidth This indicates how the output of the DAC is affected by changes The amplifiers within the DAC have a finite bandwidth. The in the supply voltage. PSRR is the ratio of the change in V to OUT multiplying bandwidth is a measure of this. A sine wave on the a change in V for full-scale output of the DAC. It is measured DD reference (with a full-scale code loaded to the DAC) appears on in decibels. V is held at 2 V and V is varied ±10%. REF DD the output. The multiplying bandwidth is the frequency at Reference Feedthrough which the output amplitude falls to 3 dB below the input. This is the ratio of the amplitude of the signal at the DAC Total Harmonic Distortion (THD) output to the reference input when the DAC output is not being This is the difference between an ideal sine wave and its atte- updated (that is, LDAC is high). It is expressed in decibels. nuated version using the DAC. The sine wave is used as the Major-Code Transition Glitch Energy reference for the DAC and THD is a measure of the harmonics Major-code transition glitch energy is the energy of the impulse present on the DAC output. It is measured in decibels. injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV/s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 … 11 to 100 … 00 or 100 … 00 to 011 … 11). Rev. A | Page 12 of 28 AD5330/AD5331/AD5340/AD5341 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C A T = 25°C A V = 5V DD V = 5V DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 14. AD5330 Typical INL Plot Figure 17. AD5330 Typical DNL Plot 3 0.6 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 2 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 0 200 400 500 800 1000 0 200 400 600 800 1000 CODE CODE Figure 15. AD5331 Typical INL Plot Figure 18. AD5331 Typical DNL Plot 12 1.0 T = 25°C A T = 25°C V = 5V A DD V = 5V DD 8 0.5 4 0 0 –4 –0.5 –8 –12 –1.0 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE CODE Figure 16. AD5340/AD5341 Typical INL Plot Figure 19. AD5340/AD5341 Typical DNL Plot Rev. A | Page 13 of 28 INL ERROR (LSBs) INL ERROR (LSBs) INL ERROR (LSBs) 06852-015 06852-017 06852-016 DNL ERROR (LSBs) DNL ERROR (LSBs) DNL ERROR (LSBs) 06852-018 06852-020 06852-019 AD5330/AD5331/AD5340/AD5341 1.00 0.2 T = 25°C A V = 5V DD T = 25°C A 0.75 0.1 V = 2V REF 0.50 0 GAIN ERROR 0.25 –0.1 MAX INL MAX DNL 0 –0.2 MIN DNL –0.25 –0.3 MIN INL –0.50 –0.4 OFFSET ERROR –0.75 –0.5 –1.00 –0.6 2345 0123 456 V (V) V (V) REF DD Figure 20. AD5330 INL and DNL Error vs. VREF Figure 23. Offset Error and Gain Error vs. VDD 1.00 5 V = 5V DD V = 3V REF 0.75 5V SOURCE 4 0.50 3V SOURCE MAX DNL MAX INL 0.25 3 0 2 –0.25 MIN DNL MIN INL –0.50 1 5V SINK 3V SINK –0.75 –1.00 0 –40 0 40 80 120 012 3456 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 21. AD5330 INL Error and DNL Error vs. Temperature Figure 24. V Source and Sink Current Capability OUT 1.0 300 V = 5V DD T = 25°C A V = 2V REF V = 2V REF 250 V = 5.5V DD 0.5 200 GAIN ERROR 0 150 V = 3.6V DD 100 OFFSET ERROR –0.5 50 –1.0 0 –40 0 40 80 120 ZERO-SCALE FULL-SCALE TEMPERATURE (°C) DAC CODE Figure 22. AD5330 Offset Error and Gain Error vs. Temperature Figure 25. Supply Current vs. DAC Code Rev. A | Page 14 of 28 ERROR (%) ERROR (LSBs) ERROR (LSBs) 06852-023 06852-022 06852-021 ERROR (%) V (V) I (µA) OUT DD 06852-026 06852-025 06852-024 AD5330/AD5331/AD5340/AD5341 300 T = 25°C A T = 25°C A V = 5V DD CH2 CLK 5V 200 V 100 OUT CH1 1V 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) TIME BASE = 5µs/DIV DD Figure 26. Supply Current vs. Supply Voltage Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 T = 25°C A T = 25°C A V = 5V DD 0.4 V = 2V REF CH1 2V V DD 0.3 0.2 V A OUT 0.1 CH2 200mV 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) TIME BASE = 200µs/DIV DD Figure 27. Power-Down Current vs. Supply Voltage Figure 30. Power-On Reset to 0 V 1800 T = 25°C A 1600 T = 25°C A V = 5V DD 1400 V = 2V REF CH1 1200 500mV V = 5V DD 1000 V A OUT 800 600 PD 400 CH2 5V 200 V = 3V DD 0 01 2345 V (V) TIME BASE = 1µs/DIV LOGIC Figure 28. Supply Current vs. Logic Input Voltage Figure 31. Exiting Power-Down to Midscale Rev. A | Page 15 of 28 I (µA) I (µA) DD DD I (µA) DD 06852-029 06852-028 06852-027 06852-030 06852-032 06852-031 AD5330/AD5331/AD5340/AD5341 10 0 –10 V = 3V DD V = 5V DD –20 –30 –40 –50 –60 80 90 100 110 120 130 140 150 160 170 180 190 200 0.01 0.1 1 10 100 1k 10k I (µA) FREQUENCY (kHz) DD Figure 32. I Histogram with V = 3 V and V = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response) DD DD DD 0.4 0.917 T = 25°C A V = 5V 0.916 DD 0.915 0.914 0.913 0.2 0.912 0.911 0.910 0.909 0 0.908 0.907 0.906 0.905 0.904 –0.2 01 235 4 0.903 250ns/DIV V (V) REF Figure 33. AD5340 Major-Code Transition Glitch Energy Figure 35. Full-Scale Error vs. VREF Rev. A | Page 16 of 28 VOLTS FREQUENCY 06852-033 06852-034 FULL-SCALE ERROR (%FSR) (dB) 06852-036 06852-035 AD5330/AD5331/AD5340/AD5341 THEORY OF OPERATION V REF The AD5330/AD5331/AD5340/AD5341 are single resistor- R string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a R parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer rail-to-rail output TO OUTPUT R AMPLIFIER swing. The AD5330, AD5340, and AD5341 have a reference input that can be buffered to draw virtually no current from the reference source. The reference input of the AD5331 is unbuffered. The devices have a power-down feature that R reduces current consumption to only 80 nA @ 3 V. R DIGITAL-TO-ANALOG SECTION The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer Figure 37. Resistor String amplifier. The voltage at the VREF pin provides the reference DAC REFERENCE INPUT voltage for the DAC. Figure 36 shows a block diagram of the There is a reference input pin for the DAC. The reference DAC architecture. Because the input coding to the DAC is input is buffered on the AD5330, AD5340, and AD5341 but straight binary, the ideal output voltage is given by can be configured as unbuffered also. The reference input of D V =V × ×Gain the AD5331 is unbuffered. The buffered/unbuffered option is OUT REF N 2 controlled by the BUF pin. where: In buffered mode (BUF = 1), the current drawn from an D is the decimal equivalent of the binary code, which is loaded external reference voltage is virtually zero because the to the DAC register: impedance is at least 10 MΩ. The reference input range is 0 to 255 for AD5330 (8 Bits) 1 V to 5 V with a 5 V supply. 0 to 1023 for AD5331 (10 Bits) In unbuffered mode (BUF = 0), the user can have a reference 0 to 4095 for AD5340/AD5341 (12 Bits) voltage as low as 0.25 V and as high as V because there is no DD N is the DAC resolution. restriction due to headroom and footroom of the reference Gain is the output amplifier gain (1 or 2). amplifier. The impedance is still large at typically 180 kΩ for V REF 0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is an external buffered reference (for example, REF192), there is no need to use the on-chip buffer. REFERENCE BUF BUFFER OUTPUT AMPLIFIER GAIN The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends INPUT DAC RESISTOR V REGISTER REGISTER STRING OUT on VREF, GAIN, the load on VOUT, and offset error. OUTPUT If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V BUFFER AMPLIFIER to V . REF Figure 36. Single DAC Channel Architecture If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V RESISTOR STRING to 2 × V . However, because of clamping, the maximum REF The resistor-string section is shown in Figure 37. It is simply a – 0.001 V. output is limited to VDD string of resistors, each of value R. The digital code loaded to The output amplifier is capable of driving a load of 2 kΩ to the DAC register determines at what node on the string the GND or 2 kΩ to VDD in parallel with 500 pF to GND or 500 pF voltage is tapped off to be fed into the output amplifier. The to VDD. The source and sink capabilities of the output amplifier voltage is tapped off by closing one of the switches connecting can be seen in Figure 24. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see Figure 29). Rev. A | Page 17 of 28 06852-037 06852-038 AD5330/AD5331/AD5340/AD5341 PARALLEL INTERFACE LOAD DAC INPUT (LDAC) The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low LDAC transfers data from the input register to the DAC register byte of eight bits and a high byte containing four bits. LDAC (and therefore updates the outputs). Use of the function enables double-buffering of the DAC data, GAIN, and BUF. DOUBLE-BUFFERED INTERFACE There are two LDAC modes: synchronous mode and The AD5330/AD5331/AD5340/AD5341 DACs all have double- asynchronous mode. buffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the In synchronous mode, the DAC register is updated after new input register under the control of chip select (CS) and write (WR). data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed, as shown in Figure 2. LDAC Access to the DAC register is controlled by the function. In asynchronous mode, the outputs are not updated at the same LDAC When is high, the DAC register is latched and the input LDAC time that the input register is written to. When goes low, register may change state without affecting the contents of the the DAC register is updated with the contents of the input LDAC DAC register. However, when is brought low, the DAC register. register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals HIGH BYTE ENABLE INPUT (HBEN) are also double-buffered and are only updated when LDAC is High byte enable is a control input on the AD5341 only. It taken low. determines if data is written to the high byte input register Double-buffering is also useful where the DAC data is loaded or the low byte input register. in two bytes, as in the AD5341, because it allows the whole The low data byte of the AD5341 consists of Data Bits [0:7] data word to be assembled in parallel before updating the DAC at the data inputs DB0 to DB7, whereas the high byte consists register. This prevents spurious outputs that can occur if the DAC of Data Bits [8:11] at the data inputs DB to DB , as shown in 0 3 register is updated with only the high byte or the low byte. Figure 38. DB to DB are ignored during a high byte write, but 4 7 These parts contain an extra feature whereby the DAC register they can be used for data to set up the reference input as buffered/ is not updated unless its input register has been updated since unbuffered, and buffer amplifier gain (see Figure 42). LDAC the last time that was brought low. Normally, when HIGH BYTE LDAC is brought low, the DAC register is filled with the X X XX DB DB DB DB 11 10 9 8 contents of the input register. In the case of the AD5330/ LOW BYTE AD5331/AD5340/AD5341, the parts only update the DAC DB DB DB DB DB DB DB DB register if the input register has been changed since the last time 7 6 5 4 3 2 1 0 X = UNUSED BIT the DAC register was updated. This removes unnecessary crosstalk. Figure 38. Data Format for AD5341 CLEAR INPUT (CLR) POWER-ON RESET CLR is an active low, asynchronous clear that resets the input The AD5330/AD5331/AD5340/AD5341 are provided with a and DAC registers. power-on reset function, so that they power up in a defined CHIP SELECT INPUT (CS) state. The power-on state is CS is an active low input that selects the device. • Normal operation WRITE INPUT (WR) • Reference input unbuffered • 0 V to VREF output range WR is an active low input that controls writing of data to the • Output voltage set to 0 V device. Data is latched into the input register on the rising WR edge of . Both input and DAC registers are filled with zeros and remain as such until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. A | Page 18 of 28 06852-039 AD5330/AD5331/AD5340/AD5341 POWER-DOWN MODE The AD5330/AD5331/AD5340/AD5341 have low power RESISTOR consumption, dissipating only 0.35 mW with a 3 V supply and AMPLIFIER V OUT STRING DAC 0.7 mW with a 5 V supply. Power consumption can be further reduced when the DAC is not in use by putting it into power- POWER-DOWN CIRCUITRY PD down mode, which is selected by taking Pin low. Figure 39. Output Stage During Power-Down PD When the pin is high, the DAC works normally with a typical power consumption of 140 μA at 5 V (115 μA at 3 V). The bias generator, the output amplifier, the resistor string, and In power-down mode, however, the supply current falls to all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the 200 nA at 5 V (80 nA at 3 V) when the DAC is powered down. registers are unaffected when in power-down. The time to exit Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, power-down is typically 2.5 μs for VDD = 5 V and 5 μs when making it open-circuit. This has the advantage that the output V = 3 V. This is the time from a rising edge on the PD pin to DD is three-state while the part is in power-down mode and provides when the output voltage deviates from its power-down voltage a defined input condition for whatever is connected to the (see Figure 31). output of the DAC amplifier. The output stage is illustrated in Figure 39. 1 Table 9. AD5330/AD5331/AD5340 Truth Table CLR LDAC CS WR Function 1 1 1 X No data transfer 1 1 X 1 No data transfer 0 X X X Clear all registers 1 1 0 Load input register 0→1 1 0 0 Load input register and DAC register 0→1 1 0 X X Update DAC register 1 X = don’t care. 1 Table 10. AD5341 Truth Table CLR LDAC CS WR HBEN Function 1 1 1 X X No data transfer 1 1 X 1 X No data transfer 0 X X X X Clear all registers 1 1 0 0→1 0 Load low byte input register 1 1 0 0→1 1 Load high byte input register 1 0 0 0 Load low byte input register and DAC register 0→1 1 0 0 0→1 1 Load high byte input register and DAC register 1 0 X X X Update DAC register 1 X = don’t care. Rev. A | Page 19 of 28 06852-040 AD5330/AD5331/AD5340/AD5341 SUGGESTED DATABUS FORMATS The AD5341 is a 12-bit device that uses byte load, so only four In most applications, GAIN and BUF are hard-wired. However, bits of the high byte are actually used as data. Two of the unused if more flexibility is required, they can be included in a databus. bits can be used for GAIN and BUF data by connecting them to This enables the user to software program GAIN, giving the the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as option of doubling the resolution in the lower half of the DAC shown in Figure 41 and Figure 42. range. In a bused system, GAIN and BUF can be treated as data inputs because they are written to the device during a write 8-BIT DATA LDAC operation and take effect when is taken low. This means DATA BUS INPUTS DB DB 6 7 that the reference buffers and the output amplifier gain of BUF multiple DAC devices can be controlled using common GAIN AD5341 GAIN and BUF lines. LDAC In the case of the AD5330, this means that the databus must be CLR wider than eight bits. The AD5331 and AD5340 databuses must CS be at least 10 bits and 12 bits wide, respectively, and are best WR HBEN suited to a 16-bit databus system. Examples of data formats for putting GAIN and BUF on a Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data on 8-Bit Bus 16-bit databus are shown in Figure 40. Note that any unused bits above the actual DAC data can be used for BUF and GAIN. DAC In this case, the low byte is written to first in a write operation devices can be controlled using common GAIN and BUF lines. with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into AD5330 GAIN and BUF registers but have no effect. The high byte is BUF GAIN X X X X X X DB DB DB DB DB DB DB DB 7 6 4 3 2 1 0 5 then written to. Only the lower four bits of data are written into AD5331 the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and BUF GAIN X X X X DB DB DB DB DB DB DB DB DB DB 9 8 7 6 5 4 3 2 1 0 BUF data. AD5340 LDAC is used to update the DAC, GAIN, and BUF values. BUF GAIN X X DB DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1 0 X = UNUSED BIT HIGH BYTE BUF GAIN XX DB DB DB DB 11 10 9 8 Figure 40. GAIN and BUF Data on a 16-Bit Bus LOW BYTE DB DB DB DB DB DB DB DB 7 6 5 4 3 2 1 0 X = UNUSED BIT Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus Rev. A | Page 20 of 28 06852-041 06852-042 06852-043 AD5330/AD5331/AD5340/AD5341 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS BIPOLAR OPERATION USING THE AD5330/AD5331/ AD5340/AD5341 The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference The AD5330/AD5331/AD5340/AD5341 are designed for inputs are configured to be unbuffered, in which case the single-supply operation, but bipolar operation is achievable devices offer full, one-quadrant multiplying capability over a using the circuit shown in Figure 45. The circuit shown has reference range of 0.25 V to VDD. More typically, these devices been configured to achieve an output voltage range of –5 V < can be used with a fixed, precision reference voltage. Figure 43 V < +5 V. Rail-to-rail operation at the amplifier output is O shows a typical setup for the devices when using an external achievable using an AD820 or OP295 as the output amplifier. reference connected to the unbuffered reference inputs. If the The output voltage for any input code can be calculated as follows: reference inputs are unbuffered, the reference input range is N VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2 )] – from 0.25 V to V , but if the on-chip reference buffers are DD R4 × VREF/R3 used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192. For 2.5 V operation, a where: suitable external reference is the AD589, a 1.23 V band gap D is the decimal equivalent of the code loaded to the DAC. reference. N is the DAC resolution. V = 2.5V TO 5.5V V is the reference voltage input. REF DD + with: 0.1µF 10µF VREF = 2.5 V. V R1 = R3 = 10 kΩ. IN V DD R2 = R4 = 20 kΩ and VDD = 5 V. EXT V V OUT REF REF N V OUT VO = (10 × D/2 ) − 5. GND AD5330/AD5331/ V = 5V DD R4 AD5340/AD5341 20kΩ AD780/REF192 + WITH V = 5V 0.1µF 10µF DD +5V OR R3 GND AD589 WITH V = 2.5V DD 10kΩ V IN = ±5V V O EXT V OUT REF V DD Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference V REF GND 0.1µF –5V AD5330/AD5331/ DRIVING V FROM THE REFERENCE VOLTAGE DD R1 AD5340/AD5341 10kΩ AD780/REF192 V WITH V = 5V OUT If an output range of 0 V to V is required, the simplest DD DD OR R2 solution is to connect the reference inputs to V . Because this AD589 WITH V = 2.5V 20kΩ DD DD GND supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example using a 5 V reference such as the ADP667, as shown in Figure 44. Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341 6V TO 16V DECODING MULTIPLE AD5330/AD5331/ + AD5340/AD5341 0.1µF 10µF CS The pin on these devices can be used in applications to V IN decode a number of DACs. In this application, all DACs in the ADP667 WR CS system receive the same data and pulses, but only to one V DD of the DACs is active at any one time, so data is only written to V REF V OUT V OUT the DAC whose CS is low. If multiple AD5341s are being used, a VSET GND SHDN 0.1µF AD5330/AD5331/ common HBEN line is also required to determine if the data is AD5340/AD5341 written to the high byte or low byte register of the selected DAC. The 74HC139 is used as a 2-line to 4-line decoder to address GND any of the DACs in the system. To prevent timing errors, the enable input should be brought to its inactive state while the Figure 44. Using an ADP667 as Power and Reference to coded address inputs are changing state. Figure 46 shows a AD5330/AD5331/AD5340/AD5341 diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in Rev. A | Page 21 of 28 06852-045 06852-044 06852-046 AD5330/AD5331/AD5340/AD5341 V = 5V DD a system, all the DACs can be updated simultaneously using a LDAC CLR common line. A common line can also be used to + 0.1µF 10µF reset all DAC outputs to zero. V SOURCE V IN AD5330/AD5331/ AD5340/AD5341 EXT LOAD V OUT 5V V REF DD HBEN* HBEN* V V REF OUT WR WR DATA 0.1µF GND AD820/ INPUTS LDAC LDAC AD5330/AD5331/ OP295 CLR CLR AD5340/AD5341 AD780/REF192 CS WITH V = 5V DD 4.7kΩ AD5330/AD5331/ AD5340/AD5341 GND HBEN* 470Ω WR DATA LDAC INPUTS V DD CLR CS Figure 47. Programmable Current Source V CC ENABLE G1 1Y0 POWER SUPPLY BYPASSING AND GROUNDING AD5330/AD5331/ 74HC139 AD5340/AD5341 A1 1Y1 CODED In any circuit where accuracy is important, careful consid- ADDRESS HBEN* 1Y2 B1 eration of the power supply and ground return layout helps WR DATA 1Y3 LDAC INPUTS DGND to ensure the rated performance. The printed circuit board on CLR CS which the AD5330/AD5331/AD5340/AD5341 are mounted should be designed so that the analog and digital sections are AD5330/AD5331/ separated and confined to certain areas of the board. If the AD5340/AD5341 device is in a system where multiple devices require an AGND- HBEN* WR DATA to-DGND connection, the connection should be made at one INPUTS LDAC CLR point only. The star ground point should be established as CS closely as possible to the device. The AD5330/AD5331/ *AD5341 ONLY AD5340/AD5341 should have ample supply bypassing of Figure 46. Decoding Multiple DAC Devices 10 μF in parallel with 0.1 μF on the supply located as close to PROGRAMMABLE CURRENT SOURCE the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used capacitor should have low effective series resistance (ESR) and as the control element of a programmable current source. In effective series inductance (ESI), like the common ceramic this example, the full-scale current is set to 1 mA. The output types that provide a low impedance path to ground at high voltage from the DAC is applied across the current setting frequencies to handle transient currents due to internal logic resistor of 4.7 kΩ in series with the 470 Ω adjustment poten- switching. tiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include The power supply lines of the device should use as large a trace the BC107 and the 2N3904, which enable the current source to as possible to provide low impedance paths and reduce the operate from a minimum V of 6 V. The operating range is SOURCE effects of glitches on the power supply line. Fast switching determined by the operating characteristics of the transistor. signals such as clocks should be shielded with digital ground Suitable amplifiers include the AD820 and the OP295, both to avoid radiating noise to other parts of the board, and should having rail-to-rail operation on their outputs. The current for never be run near the reference inputs. Avoid crossover of any digital input code and resistor value can be calculated as digital and analog signals. Traces on opposite sides of the board follows: should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by D I=G×V × mA REF N far the best, but not always possible with a double-sided board. (2 ×R) In this technique, the component side of the board is dedicated to where: the ground plane while signal traces are placed on the solder side. G is the gain of the buffer amplifier (1 or 2). D is the digital equivalent of the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer in kilo ohms. Rev. A | Page 22 of 28 DATA BUS 06852-047 06852-048 AD5330/AD5331/AD5340/AD5341 Table 11. Overview of AD53xx Parallel Devices Additional Pin Functions CLR Part No. Resolution Bits DNL No. of VREF Pins Settling Time BUF GAIN HBEN Package No. of Pins Singles AD5330 8 ±0.25 1 6 μs BUF GAIN CLR TSSOP 20 AD5331 10 ±0.5 1 7 μs GAIN CLR TSSOP 20 AD5340 12 ±1.0 1 8 μs BUF GAIN CLR TSSOP 24 AD5341 12 ±1.0 1 8 μs BUF GAIN HBEN CLR TSSOP 20 Duals AD5332 8 ±0.25 2 6 μs CLR TSSOP 20 AD5333 10 ±0.5 2 7 μs BUF GAIN CLR TSSOP 24 AD5342 12 ±1.0 2 8 μs BUF GAIN CLR TSSOP 28 AD5343 12 ±1.0 1 8 μs HBEN CLR TSSOP 20 Quads AD5334 8 ±0.25 2 6 μs GAIN CLR TSSOP 24 AD5335 10 ±0.5 2 7 μs HBEN CLR TSSOP 24 AD5336 10 ±0.5 4 7 μs GAIN CLR TSSOP 28 AD5344 12 ±1.0 4 8 μs TSSOP 28 Table 12. Overview of AD53xx Serial Devices Part No. Resolution Bits No. of DACs DNL Interface Settling Time Package No of Pins Singles AD5300 8 1 ±0.25 SPI 4 μs SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 μs SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 μs SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 μs SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-Wire 7 μs SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-Wire 8 μs SOT-23, MSOP 6, 8 Duals AD5302 8 2 ±0.25 SPI 6 μs MSOP 10 AD5312 10 2 ±0.5 SPI 7 μs MSOP 10 AD5322 12 2 ±1.0 SPI 8 μs MSOP 10 AD5303 8 2 ±0.25 SPI 6 μs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 μs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 μs TSSOP 16 Quads AD5304 8 4 ±0.25 SPI 6 μs MSOP, LFCSP 10 AD5314 10 4 ±0.5 SPI 7 μs MSOP, LFCSP 10 AD5324 12 4 ±1.0 SPI 8 μs MSOP, LFCSP 10 AD5305 8 4 ±0.25 2-Wire 6 μs MSOP 10 AD5315 10 4 ±0.5 2-Wire 7 μs MSOP 10 AD5325 12 4 ±1.0 2-Wire 8 μs MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 μs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 μs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 μs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 μs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 μs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 μs TSSOP 16 Rev. A | Page 23 of 28 AD5330/AD5331/AD5340/AD5341 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 8° 0.60 0.30 0° 0.45 COPLANARITY 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0° 0.30 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Rev. A | Page 24 of 28 AD5330/AD5331/AD5340/AD5341 ORDERING GUIDE Model Temperature Range Package Description Package Option AD5330BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5330BRUZ –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5330BRUZ-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5330BRUZ-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5331BRUZ –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5331BRUZ-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5331BRUZ-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5340BRU –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL7 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD5340BRUZ –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD5340BRUZ-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD5340BRUZ-REEL7 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5341BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5341BRUZ –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5341BRUZ-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 AD5341BRUZ-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 Z = RoHS Compliant Part. Rev. A | Page 25 of 28 AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 26 of 28 AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 27 of 28 AD5330/AD5331/AD5340/AD5341 NOTES ©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06852-0-2/08(A) Rev. A | Page 28 of 28