ANALOG DEVICES AD5320

2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 12-Bit DAC in an SOT-23 AD5320 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 12-bit DAC V DD GND 6-lead SOT-23 and 8-lead MSOP packages Micropower operation: 140 μA @ 5 V AD5320 POWER-ON Power-down to 200 nA @ 5 V, 50 nA @ 3 V RESET 2.7 V to 5.5 V power supply REF (+) REF (–) Guaranteed monotonic by design OUTPUT DAC V OUT 12-BIT BUFFER REGISTER Reference derived from power supply DAC Power-on reset to zero volts Three power-down functions INPUT CONTROL POWER-DOWN REGISTER Low power serial interface with Schmitt-triggered inputs CONTROL LOGIC LOGIC NETWORK On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility APPLICATIONS Portable battery-powered instruments SYNC SCLK DIN Digital gain and offset adjustment Figure 1. Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION 1 The AD5320 is one of a family of pin-compatible DACs. The The AD5320 is a single, 12-bit buffered voltage out digital-to- AD5300 is the 8-bit version and the AD5310 is the 10-bit analog converter (DAC) that operates from a single 2.7 V to version. The AD5300/AD5310/AD5320 are available in 6-lead 5.5 V supply consuming 115 μA at 3 V. Its on-chip precision SOT-23 packages and 8-lead MSOP packages. output amplifier allows rail-to-rail output swing to be achieved. The AD5320 utilizes a versatile 3-wire serial interface that PRODUCT HIGHLIGHTS operates at clock rates up to 30 MHz and is compatible with 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. standard SPI®, QSPI™, MICROWIRE™ and digital signal processing (DSP) interface standards. 2. Low power, single-supply operation. This part operates from a single 2.7 V to 5.5 V supply and typically consumes The reference for AD5320 is derived from the power supply 0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for inputs and thus gives the widest dynamic output range. The battery-powered applications. part incorporates a power-on reset circuit that ensures that the DAC output powers up to zero volts and remains there until a 3. The on-chip output buffer amplifier allows the output of valid write takes place to the device. The part contains a power- the DAC to swing rail-to-rail with a slew rate of 1 V/μs. down feature that reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output 4. Reference derived from the power supply. loads while in power-down mode. The part is put into power- 5. High speed serial interface with clock speeds up to down mode over the serial interface. 30 MHz. Designed for very low power consumption. The The low power consumption of this part in normal operation interface only powers up during a write cycle. makes it ideally suited to portable, battery-operated equipment. 6. Power-down capability. When powered down, the DAC The power consumption is 0.7 mW at 5 V reducing to 1 μW in typically consumes 50 nA at 3 V and 200 nA at 5 V. power-down mode. 1 Patent pending; protected by U.S. Patent No. 5684481. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00934-001 AD5320 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ................................................................................ 12 Applications....................................................................................... 1 Input Shift Register .................................................................... 12 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 12 General Description ......................................................................... 1 Power-On Reset.......................................................................... 12 Product Highlights ........................................................................... 1 Power-Down Modes .................................................................. 13 Revision History ............................................................................... 2 Microprocessor Interfacing........................................................... 14 Specifications..................................................................................... 3 AD5320 to ADSP-2101/ADSP-2103 Interface ....................... 14 Timing Characteristics ................................................................ 4 AD5320 to 68HC11/68L11 Interface....................................... 14 Absolute Maximum Ratings............................................................ 5 AD5320 to 80C51/80L51 Interface .......................................... 14 ESD Caution.................................................................................. 5 AD5320 to MICROWIRE Interface......................................... 14 Pin Configurations and Function Descriptions ........................... 6 Applications..................................................................................... 15 Terminology ...................................................................................... 7 Using REF19x as a Power Supply for AD5320 ....................... 15 Typical Performance Characteristics ............................................. 8 Bipolar Operation Using the AD5320 ..................................... 15 Theory of Operation ...................................................................... 11 Using AD5320 with an Opto-Isolated Interface .................... 15 D/A Section................................................................................. 11 Power Supply Bypassing and Grounding................................ 16 Resistor String............................................................................. 11 Outline Dimensions....................................................................... 17 Output Amplifier........................................................................ 11 Ordering Guide .......................................................................... 17 REVISION HISTORY 11/05—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 4............................................................................ 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 Rev. C | Page 2 of 20 AD5320 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Version Parameter Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy ±16 LSB See Figure 5 Differential Nonlinearity ±1 LSB Guaranteed monotonic by design (see Figure 6) Zero-Code Error 5 40 mV All zeroes loaded to DAC register (see Figure 9) Full-Scale Error −0.15 −1.25 % of FSR All ones loaded to DAC register (see Figure 9) Gain Error ±1.25 % of FSR Zero-Code Error Drift −20 μV/°C Gain Temperature Coefficient −5 ppm of FSR/°C 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD V Output Voltage Settling Time 8 10 μs 1/4 scale to 3/4 scale change (400 hex to C00 hex) R = 2 kΩ, 0 pF < C < 200 pF (see Figure 19) L L 12 μs R = 2 kΩ, C = 500 pF L L Slew Rate 1 V/μs Capacitive Load Stability 470 pF RL = ∞ 1000 pF RL = 2 kΩ Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB change around major carry (see Figure 22) Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Ω Short Circuit Current 50 mA VDD = 5 V 20 mA VDD = 3 V Power-Up Time 2.5 μs Coming out of power-down mode, V = 5 V DD 5 μs Coming out of power-down mode, V = 3 V DD 3 LOGIC INPUTS Input Current ±1 μA V , Input Low Voltage 0.8 V V = 5 V INL DD V , Input Low Voltage 0.6 V V = 3 V INL DD VINH, Input High Voltage 2.4 V VDD = 5 V VINH, Input High Voltage 2.1 V VDD = 3 V Pin Capacitance 3 pF POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) DAC active and excluding load current V = 4.5 V to 5.5 V 140 250 μA V = V and V = GND DD IH DD IL V = 2.7 V to 3.6 V 115 200 μA V = V and V = GND DD IH DD IL IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.2 1 μA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 0.05 1 μA VIH = VDD and VIL = GND POWER EFFICIENCY IOUT/IDD 93 % ILOAD = 2 mA, VDD = 5 V 1 Temperature range is as follows: B Version: −40°C to +105°C. 2 Linearity calculated using a reduced code range of 48 to 4047; output unloaded. 3 Guaranteed by design and characterization, not production tested. Rev. C | Page 3 of 20 AD5320 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX 1, 2 Parameter V = 2.7 V to 3.6 V V = 3.6 V to 5.5 V Unit Description DD DD 3 t1 50 33 ns min SCLK cycle time t2 13 13 ns min SCLK high time t 22.5 13 ns min SCLK low time 3 t 0 0 ns min SYNC to SCLK rising edge setup time 4 t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min SCLK falling edge to SYNC rising edge t8 50 33 ns min Minimum SYNC high time 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 See Figure 2. 3 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. t 1 SCLK t 2 t 4 t t 3 7 t 8 SYNC t 6 t 5 DIN DB15 DB0 Figure 2. Serial Write Operation Rev. C | Page 4 of 20 00934-002 AD5320 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Ratings other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect VOUT to GND −0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T Max) 150°C J SOT-23 Package Power Dissipation (TJ Max − TA)/θJA θJA Thermal Impedance 240°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C MSOP Package 450 mW Power Dissipation (TJ Max − TA)/θJA θJA Thermal Impedance 206°C/W θ Thermal Impedance 44°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 20 AD5320 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 8 GND DD AD5320 NC 2 7 DIN V 1 6 SYNC OUT TOP VIEW AD5320 SCLK GND 2 5 SCLK NC 3 6 (Not to Scale) TOP VIEW V 3 4 DIN V 4 5 SYNC DD OUT (Not to Scale) NC = NO CONNECT Figure 4. MSOP Pin Configuration Figure 3. SOT-23 Pin Configuration Table 4. Pin Function Descriptions SOT-23 MSOP Pin No. Pin No. Mnemonic Description 1 4 VOUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 2 8 GND Ground Reference Point for All Circuitry on the Part. 3 1 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and V should be decoupled DD DD to GND. 4 7 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 5 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2, 3 NC No Connect. Rev. C | Page 6 of 20 00934-003 00934-004 AD5320 TERMINOLOGY Relative Accuracy Total Unadjusted Error For the DAC, relative accuracy or integral nonlinearity (INL) is Total unadjusted error (TUE) is a measure of the output error a measure of the maximum deviation, in LSBs, from a straight considering all the various errors. A typical TUE vs. code plot line passing through the endpoints of the DAC transfer can be seen in Figure 7. function. A typical INL vs. code plot can be seen in Figure 5. Zero-Code Error Drift Differential Nonlinearity This is a measure of the change in zero-code error with a Differential nonlinearity (DNL) is the difference between the change in temperature. It is expressed in μV/°C. measured change and the ideal 1 LSB change between any two Gain Error Drift adjacent codes. A specified differential nonlinearity of ±1 LSB This is a measure of the change in gain error with changes in maximum ensures monotonicity. This DAC is guaranteed temperature. It is expressed in (ppm of full-scale range)/°C. monotonic by design. A typical DNL vs. code plot can be seen in Figure 6. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the Zero-Code Error analog output when the input code in the DAC register changes Zero-code error is a measure of the output error when zero state. It is normally specified as the area of the glitch in nV code (000 hex) is loaded to the DAC register. Ideally, the output seconds and is measured when the digital input code is changed should be 0 V. The zero-code error is always positive in the by 1 LSB at the major carry transition (7FF Hex to 800 Hex); see AD5320 because the output of the DAC cannot go below 0 V Figure 22. due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. A plot of zero- Digital Feedthrough code error vs. temperature can be seen in Figure 9. Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the Full-Scale Error DAC but is measured when the DAC output is not updated. It Full-scale error is a measure of the output error when full-scale is specified in nV seconds and measured with a full-scale code code (FFF Hex) is loaded to the DAC register. Ideally the output change on the data bus, that is, from all 0s to all 1s and vice should be VDD − 1 LSB. Full-scale error is expressed in percent versa. of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 9. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Rev. C | Page 7 of 20 AD5320 TYPICAL PERFORMANCE CHARACTERISTICS 16 16 T = 25°C A 12 12 8 8 INL @ 3V 4 4 MAX INL MAX DNL 0 0 MIN DNL –4 –4 INL @ 5V MIN INL –8 –8 –12 –12 –16 –16 0 800 1600 2400 3200 4000 –40 0 40 80 120 CODE TEMPERATURE (°C) Figure 5. Typical INL Plot Figure 8. INL Error and DNL Error vs. Temperature 30 1.0 DNL @ 3V V = 5V DD DNL @ 5V T = 25°C 20 A 0.5 10 ZS ERROR FS ERROR 0 0 10 –0.5 20 –1.0 30 0 1000 2000 3000 4000 –40 0 40 80 120 CODE TEMPERATURE (°C) Figure 6. Typical DNL Plot Figure 9. Zero-Scale Error and Full-Scale Error vs. Temperature 16 2500 T = 25°C A V = 5V DD 2000 8 TUE @ 3V V = 3V DD 1500 0 TUE @ 5V 1000 –8 500 –16 0 0 800 1600 2400 3200 4000 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 CODE I (µA) DD Figure 7. Typical Total Unadjusted Error Plot Figure 10. I Histogram with V = 3 V and V = 5 V DD DD DD Rev. C | Page 8 of 20 TUE (LSBs) DNL ERROR (LSBs) INL ERROR (LSBs) 00934-007 00934-006 00934-005 FREQUENCY ERROR (LSBs) ERROR (mV) 00934-009 00934-008 00934-010 AD5320 3 300 T = 25°C V = 5V A DD 200 DAC LOADED WITH FFF HEX 2 150 1 DAC LOADED WITH 000 HEX 50 0 0 05 10 15 –40 0 40 80 120 I (mA) TEMPERATURE °C SOURCE/SINK Figure 14. Supply Current vs. Temperature Figure 11. Source and Sink Current Capability with V = 3 V DD 300 5 DAC LOADED WITH FFF HEX T = 25°C A 250 4 200 3 T = 25°C A 150 2 100 1 50 DAC LOADED WITH 000 HEX 0 0 05 10 15 2.7 3.2 3.7 3.7 4.2 4.7 5 I (mA) V (V) SOURCE/SINK DD Figure 12. Source and Sink Current Capability with V = 5 V Figure 15. Supply Current vs. Supply Voltage DD 500 1.0 THREE-STATE 0.9 CONDITION 400 0.8 0.7 300 0.6 0.5 200 0.4 V = 5V DD +105°C 0.3 100 +25°C –40°C V = 3V DD 0.2 0 0.1 0 800 1600 2400 3200 4000 CODE 0 2.7 3.2 3.7 4.2 4.7 5.2 Figure 13. Supply Current vs. Code V (V) DD Figure 16. Power-Down Current vs. Supply Voltage Rev. C | Page 9 of 20 I (µA) V (V) V (V) DD OUT OUT 00934-013 00934-012 00934-011 I (µA) DD I (µA) I (µA) DD DD 00934-015 00934-014 00934-016 AD5320 800 2kΩ LOAD TO V DD T = 25°C A 600 V DD 400 CH1 200 V = 5V DD V OUT CH2 V = 3V DD 0 05 1 2 3 4 CH1 1V, CH 2 1V, TIME BASE = 20µs/DIV V (V) LOGIC Figure 17. Supply Current vs. Logic Input Voltage Figure 20. Power-On Reset to 0 V V = 5V CH2 DD CLK CLK CH2 V OUT V OUT V = 5V DD CH1 FULL-SCALE CODE CHANGE 000 HEX – FFF HEX T = 25°C A OUTPUT LOADED WITH 2kΩ AND 200pF TO GND CH1 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV CH1 1V, CH2 5V, TIME BASE = 5µs/DIV Figure 18. Full-Scale Settling Time Figure 21. Exiting Power-Down (800 Hex Loaded) 2.56 LOADED WITH 2kΩ CH1 AND 200pF TO GND CLK 2.54 CODE CHANGE: 800 HEX TO 7FF HEX 2.52 V OUT 2.50 CH2 V = 5V DD HALF-SCALE CODE CHANGE 400 HEX – C00 HEX 2.48 T = 25°C A OUTPUT LOADED WITH 2kΩ AND 200pF TO GND 2.46 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 500ns/DIV Figure 19. Half-Scale Settling Time Figure 22. Digital-to-Analog Glitch Impulse Rev. C | Page 10 of 20 I (µA) DD 00934-019 00934-018 00934-017 V (V) OUT 00934-020 00934-021 00934-022 AD5320 THEORY OF OPERATION D/A SECTION RESISTOR STRING The AD5320 DAC is fabricated on a CMOS process. The The resistor string section is shown in Figure 24. It is simply a architecture consists of a string DAC followed by an output string of resistors, each of value R. The code loaded to the DAC buffer amplifier. Because there is no reference input pin, the register determines at which node on the string the voltage is power supply (VDD) acts as the reference. Figure 23 shows a tapped off to be fed into the output amplifier. The voltage is block diagram of the DAC architecture. tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is V DD guaranteed monotonic. REF (+) R RESISTOR DAC REGISTER V OUT STRING R REF (–) TO OUTPUT OUTPUT R AMPLIFIER AMPLIFIER GND Figure 23. DAC Architecture R Since the input coding to the DAC is straight binary, the ideal R output voltage is given by: Figure 24. Resistor String D ⎛ ⎞ V =V × ⎜ ⎟ OUT DD ⎝ 4096⎠ OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail where D = decimal equivalent of the binary code that is loaded voltages on its output that gives an output range of 0 V to V . It DD to the DAC register; it can range from 0 to 4095. is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 11 and Figure 12. The slew rate is 1 V/μs with a half-scale settling time of 8 μs with the output unloaded. Rev. C | Page 11 of 20 00934-023 00934-024 AD5320 SERIAL INTERFACE The AD5320 has a 3-wire serial interface (SYNC, SCLK, and SYNC INTERRUPT TM DIN) that is compatible with SPI®, QSPI , and SYNC In a normal write sequence, the line is kept low for at TM MICROWIRE interface standards as well as most DSPs. See least 16 falling edges of SCLK and the DAC is updated on the Figure 2 for a timing diagram of a typical write sequence. SYNC 16th falling edge. However, if is brought high before the 16th falling edge, then this acts as an interrupt to the write SYNC The write sequence begins by bringing the line low. Data sequence. The shift register is reset and the write sequence is from the DIN line is clocked into the 16-bit shift register on the seen as invalid. Neither an update of the DAC register contents falling edge of SCLK. The serial clock frequency can be as high nor a change in the operating mode occurs (see Figure 26). as 30 MHz, making the AD5320 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked POWER-ON RESET in and the programmed function is executed (that is, a change The AD5320 contains a power-on reset circuit that controls the in DAC register contents and/or a change in the mode of output voltage during power-up. The DAC register is filled with SYNC operation). At this stage, the line can be kept low or be zeros and the output voltage is 0 V. It remains there until a valid brought high. In either case, it must be brought high for a write sequence is made to the DAC. This is useful in applica- minimum of 33 ns before the next write sequence so that a tions where it is important to know the state of the output of the SYNC falling edge of can initiate the next write sequence. DAC while it is in the process of powering up. SYNC Because the buffer draws more current when V = 2.4 V IN than it does when V = 0.8 V, SYNC should be idled low IN between write sequences for even lower power operation of the part. As previously mentioned, SYNC must be brought high again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 16 bits wide (see Figure 25). The first two bits are “don’t cares.” The next two are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next twelve bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. DB15 (MSB) DB0 (LSB) X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 1 0 100kΩ TO GND POWER-DOWN MODES 1 1 THREE–STATE Figure 25. Input Register Contents SCLK SYNC DB15 DB0 DB15 DB0 DIN VALID WRITE SEQUENCE, OUTPUT UPDATES INVALID WRITE SEQUENCE: ON THE 16TH FALLING EDGE SYNC HIGH BEFORE 16TH FALLING EDGE SYNC Figure 26. Interrupt Facility Rev. C | Page 12 of 20 00934-025 00934-028 AD5320 POWER-DOWN MODES RESISTOR The AD5320 contains four separate modes of operation. These V AMPLIFIER OUT STRING DAC modes are software-programmable by setting two bits (DB13 and DB12) in the control register. Table 5 shows how the state of the bits corresponds to the mode of operation of the device. POWER-DOWN CIRCUITRY Table 5. Modes of Operation for the AD5320 RESISTOR DB13 DB12 Operating Mode NETWORK 0 0 Normal Operation Power-Down Modes Figure 27. Output Stage During Power-Down 0 1 1 kΩ to GND 1 0 100 kΩ to GND The bias generator, output amplifier, resistor string, and other 1 1 Three-State associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC register When both bits are set to 0, the part works with its normal power are unaffected when in power-down. The time to exit power- consumption of 140 μA at 5 V. However, for the three power-down down is typically 2.5 μs for V = 5 V and 5 μs for V = 3 V DD DD modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not (see Figure 21). only does the supply current fall, but the output stage is also inter- nally switched from the output of the amplifier to a resistor net- work of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options: the output is connected internally to GND through a 1 kΩ resistor, the output is connected internally to GND through a 100 kΩ resistor, or it is left open- circuited (three-state). The output stage is illustrated in Figure 27. Rev. C | Page 13 of 20 00934-026 AD5320 MICROPROCESSOR INTERFACING AD5320 TO ADSP-2101/ADSP-2103 INTERFACE AD5320 TO 80C51/80L51 INTERFACE Figure 28 shows a serial interface between the AD5320 and the Figure 30 shows a serial interface between the AD5320 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should 80C51/80L51 microcontrollers. TXD of the 80C51/80L51 drives be set up to operate in the serial port (SPORT) transmit alter- SCLK of the AD5320, while RXD drives the serial data line of nate framing mode. The ADSP-2101/ADSP-2103 SPORT are the part. The SYNC signal is again derived from a bit programmed through the SPORT control register and should programmable pin on the port. In this case, port line P3.3 is be configured as follows: internal clock operation, active low used. When data is to be transmitted to the AD5320, P3.3 is framing, and 16-bit word length. Transmission is initiated by taken low. The 80C51/80L51 transmits data only in 8-bit bytes; writing a word to the Tx register after the SPORT has been thus only eight falling clock edges occur in the transmit cycle. enabled. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit ADSP-2101/ AD5320* the second byte of data. P3.3 is taken high following the ADSP-2103* completion of this cycle. The 80C51/ 80L51 output the serial data in a format that has the LSB first. The AD5320 requires its SYNC TFS data with the MSB as the first bit received. The 80C51/80L51 DT DIN transmit routine should consider this. SCLK SCLK 80C51/80L51* AD5320* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. AD5320 to ADSP-2101/ADSP-2103 Interface SYNC AD5320 TO 68HC11/68L11 INTERFACE P3.3 TXD SCLK Figure 29 shows a serial interface between the AD5320 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 DIN RXD drives the SCLK of the AD5320, while the MOSI output drives SYNC the serial data line of the DAC. The signal is derived *ADDITIONAL PINS OMITTED FOR CLARITY from a port line (PC7). For correct operation of this interface, Figure 30. AD5320 to 80C51/80L51 Interface the 68HC11/68L11 should be configured so that the CPOL bit AD5320 TO MICROWIRE INTERFACE is a 0 and the CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the Figure 31 shows an interface between the AD5320 and any 68HC11/68L11 are configured, data appearing on the MOSI MICROWIRE-compatible device. Serial data is shifted out on output is valid on the falling edge of SCK as shown in Figure 29. the falling edge of the serial clock and is clocked into the AD5320 on the rising edge of the SK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit MICROWIRE* AD5320* cycle. Data is transmitted MSB first. In order to load data to the AD5320, PC7 is left low after the first eight bits are transferred, SYNC CS and a second serial write operation is performed to the DAC SK SCLK and PC7 is taken high at the end of this procedure. SO DIN 68HC11/68L11* AD5320* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 31. AD5320 to MICROWIRE Interface SYNC PC7 SCK SCLK DIN MOSI *ADDITIONAL PINS OMITTED FOR CLARITY Figure 29. AD5320 to 68HC11/68L11 Interface Rev. C | Page 14 of 20 00934-029 00934-027 00934-031 00934-030 AD5320 APPLICATIONS R2 = 10kΩ USING REF19X AS A POWER SUPPLY FOR AD5320 +5V +5V Because the supply current required by the AD5320 is R1 = 10kΩ extremely low, an alternative option is to use a REF19x voltage AD820/ ±5V OP295 reference (REF195 for 5 V or REF193 for 3 V) to supply the –5V V V OUT required voltage to the part (see Figure 32). This is especially DD 10µF 0.1µF AD5320 useful if the power supply is noisy or if the system supply voltages are at some value other than 5 V or 3 V (such as 15 V). The REF19x outputs a steady supply voltage for the AD5320. If the low dropout REF195 is used, the current it needs to supply 3-WIRE SERIAL INTERFACE to the AD5320 is 140 μA. This is with no load on the output of Figure 33. Bipolar Operation with the AD5320 the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current USING AD5320 WITH AN OPTO-ISOLATED required (with a 5 kΩ load on the DAC output) is: INTERFACE For process control applications in industrial environments, it is 140 μA + (5 V/5 kΩ) = 1.14 mA often necessary to use an opto-isolated interface to protect and The load regulation of the REF195 is typically 2 ppm/mA, isolate the controlling circuitry from any hazardous common- which results in an error of 2.3 ppm (11.5 μV) for the 1.14 mA mode voltages that can occur in the area where the DAC is current drawn from it. This corresponds to a 0.009 LSB error. functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5320 uses a 3-wire serial logic interface, it 15V requires only three opto-isolators to provide the required REF195 5V isolation (see Figure 34). The power supply to the part also 140µA needs to be isolated. This is done by using a transformer. On the V = 0V TO 5V OUT DAC side of the transformer, a 5 V regulator provides the 5 V SYNC 3-WIRE SERIAL SCLK AD5320 supply required for the AD5320. INTERFACE DIN 5V Figure 32. REF195 as Power Supply to AD5320 REGULATOR 10µF 0.1µF POWER BIPOLAR OPERATION USING THE AD5320 V The AD5320 is designed for single-supply operation but a bipolar DD output range is also possible using the circuit in Figure 33. The 10kΩ V DD SCLK SCLK circuit below gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or AD5320 an OP295 as the output amplifier. V DD 10kΩ The output voltage for any input code can be calculated as V OUT SYNC SYNC follows: V DD R1+ R2 ⎡ D R2 ⎤ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞ V = V × × −V × ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ O ⎢ DD DD ⎥ 10kΩ 4096 R1 R1 ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦ DIN DATA GND D represents the input code in decimal (0 to 4095). where With VDD = 5 V, R1 = R2 = 10 kΩ: Figure 34. AD5320 with An Opto-Isolated Interface 10×D ⎛ ⎞ V = − 5V ⎜ ⎟ O 4096 ⎝ ⎠ This is an output voltage range of ±5 V with 000 hex corresponding to a −5 V output and FFF hex corresponding to a +5 V output. Rev. C | Page 15 of 20 00934-032 00934-034 00934-033 AD5320 The power supply line itself should have as large a trace as POWER SUPPLY BYPASSING AND GROUNDING possible to provide a low impedance path and reduce glitch When accuracy is important in a circuit, it is helpful to consider effects on the supply line. Clocks and other fast switching carefully the power supply and ground return layout on the digital signals should be shielded from other parts of the board board. The printed circuit board containing the AD5320 should by digital ground. Avoid crossover of digital and analog signals have separate analog and digital sections, each having its own if possible. When traces cross on opposite sides of the board, area of the board. If the AD5320 is in a system where other ensure that they run at right angles to each other to reduce devices require an AGND to DGND connection, the connec- feedthrough effects through the board. The best board layout tion should be made at one point only. This ground point technique is the microstrip technique where the component should be as close as possible to the AD5320. side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not The power supply to the AD5320 should be bypassed with 10 μF capacitors and 0.1 μF capacitors. The capacitors should be physi- always possible with a two-layer board. cally as close as possible to the device with the 0.1 μF capacitors ideally against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitors have low effective series resistance (ESR) and effective series inductance (ESI), such as common ceramic types of capacitors. The 0.1 μF capacitors provide a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Rev. C | Page 16 of 20 AD5320 OUTLINE DIMENSIONS 2.90 BSC 3.20 3.00 2.80 6 5 4 2.80 BSC 8 5 5.15 1.60 BSC 3.20 4.90 1 2 3 3.00 4.65 1 2.80 PIN 1 4 INDICATOR 0.95 BSC PIN 1 1.90 0.65 BSC 1.30 BSC 1.15 0.95 0.90 0.85 1.10 MAX 0.75 1.45 MAX 0.22 0.80 0.08 8° 0.15 0.60 0.38 0.23 10° 0.60 0° 0.00 0.40 0.50 0.22 0.15 MAX 0.08 4° 0.45 SEATING 0.30 COPLANARITY SEATING 0° 0.30 PLANE 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 36. 8-Lead Mini Small Outline Package [MSOP] Figure 35. 6-Lead Small Outline Transistor Package [SOT-23] (RM-8) (RT-6) Dimensions shown in millimeters Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Branding Package Option AD5320BRM −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D4B RM-8 AD5320BRM-REEL −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D4B RM-8 AD5320BRM-REEL7 −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D4B RM-8 1 AD5320BRMZ −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D9N RM-8 1 AD5320BRMZ-REEL −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D9N RM-8 1 AD5320BRMZ-REEL7 −40°C to +105°C 8-Lead Mini Small Outline Package [MSOP] D9N RM-8 AD5320BRT-500RL7 −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D4B RT-6 AD5320BRT-REEL −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D4B RT-6 AD5320BRT-REEL7 −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D4B RT-6 1 AD5320BRTZ-500RL7 −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D9N RT-6 1 AD5320BRTZ-REEL −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D9N RT-6 1 AD5320BRTZ-REEL7 −40°C to +105°C 6-Lead Small Outline Transistor Package [SOT-23] D9N RT-6 1 Z = Pb-free part. Rev. C | Page 17 of 20 AD5320 NOTES Rev. C | Page 18 of 20 AD5320 NOTES Rev. C | Page 19 of 20 AD5320 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00934-0-11/05(C) Rev. C | Page 20 of 20