ANALOG DEVICES AD5314

2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages Data Sheet AD5304/AD5314/AD5324 FEATURES GENERAL DESCRIPTION 1 The AD5304/AD5314/AD5324 are quad 8-, 10-, and 12-bit AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and buffered voltage output DACs in 10-lead MSOP and 10-lead 10-lead LFCSP A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL LFCSP packages that operate from a single 2.5 V to 5.5 V supply, AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and consuming 500 μA at 3 V. Their on-chip output amplifiers allow 10-lead LFCSP rail-to-rail output swing to be achieved with a slew rate of 0.7 V/μs. A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL A 3-wire serial interface is used; it operates at clock rates up to AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, 10-lead LFCSP and DSP interface standards. A, W Version: ±16 LSB INL, B Version: ±10 LSB INL The references for the four DACs are derived from one reference Low power operation: 500 μA @ 3 V, 600 μA @ 5 V pin. The outputs of all DACs can be updated simultaneously using 2.5 V to 5.5 V power supply the software LDAC function. The parts incorporate a power-on Guaranteed monotonic by design over all codes reset circuit, and ensure that the DAC outputs power up to 0 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V and remains there until a valid write takes place to the device. Double-buffered input logic The parts contain a power-down feature that reduces the current Output range: 0 V to V REF consumption of the device to 200 nA @ 5 V (80 nA @ 3 V). Power-on reset to 0 V The low power consumption of these parts in normal operation LDAC Simultaneous update of outputs ( function) makes them ideally suited to portable battery-operated equipment. Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP- The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing compatible 3-wire serial interface to 1 μW in power-down mode. On-chip, rail-to-rail output buffer amplifiers Temperature range −40°C to +105°C Qualified for automotive applications APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment 1 Protected by U.S. Patent No. 5,969,657. Programmable voltage and current sources Programmable attenuators Industrial process controls FUNCTIONAL BLOCK DIAGRAM V REFIN DD AD5304/AD5314/AD5324 LDAC BUFFER INPUT DAC STRING V A OUT REGISTER REGISTER DAC A BUFFER SCLK INPUT DAC STRING V B OUT REGISTER REGISTER DAC B BUFFER SYNC INPUT DAC STRING V C OUT REGISTER REGISTER DAC C DIN BUFFER INPUT DAC STRING V D OUT REGISTER REGISTER DAC D POWER-ON RESET POWER-DOWN LOGIC GND Figure 1. Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 00929-001 AD5304/AD5314/AD5324 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 14  Applications ....................................................................................... 1  Functional Description .............................................................. 14  General Description ......................................................................... 1  Power-On Reset .......................................................................... 14  Functional Block Diagram .............................................................. 1  Serial Interface ............................................................................ 14  Revision History ............................................................................... 2  Power-Down Mode .................................................................... 16  Specif ica t ions ..................................................................................... 3  Microprocessor Interfacing ....................................................... 16  AC Characteristics ........................................................................ 4  Applications Information .............................................................. 18  Timing Characteristics ................................................................ 5  Typical Application Circuit ....................................................... 18  Absolute Maximum Ratings ............................................................ 6  Decoding Multiple AD5304/AD5314/AD5324s .................... 19  ESD Caution .................................................................................. 6  Power Supply Bypassing and Grounding ................................ 20  Pin Configurations and Function Descriptions ........................... 7  Outline Dimensions ....................................................................... 22  Typical Performance Characteristics ............................................. 8  Ordering Guide .......................................................................... 23  Terminology .................................................................................... 12  Automotive Products ................................................................. 23  REVISION HISTORY 8/03—Rev. C to Rev. D 9/11—Rev. G to Rev. H Added A Version ................................................................ Universal Changes to Table 4 ............................................................................ 6 Changes to Features .......................................................................... 1 Changes to Specifications ................................................................. 2 5/11—Rev. F to Rev. G Changes to Absolute Maximum Ratings ........................................ 4 Added W Version ............................................................... Universal Changes to Ordering Guide ............................................................. 4 Added EPAD Notation to Figure 4 ................................................. 7 Changes to Figure 6 ........................................................................ 11 Updated Outline Dimensions ....................................................... 22 Added OCTALS Section to Table 2 .............................................. 15 Changes to Ordering Guide .......................................................... 23 Updated Outline Dimensions ....................................................... 16 Added Automotive Products Section .......................................... 23 9/06—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Specifications Section .................................................. 3 Changes to Table 5 ............................................................................ 7 Updated Outline Dimensions ...................................................... 22 Changes to Ordering Guide .......................................................... 23 5/05—Rev. D to Rev. E Added 10-lead LFCSP package ......................................... Universal Changes to Title ................................................................................ 1 Changes to Ordering Guide ............................................................ 4 Rev. H | Page 2 of 24 Data Sheet AD5304/AD5314/AD5324 SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 2 2 A, W Version B Version 1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 3, 4 DC PERFORMANCE AD5304 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5314 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5324 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 2 and Figure 3 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3 Lower Dead Band 20 60 20 60 mV Lower dead band exists only if offset error is negative 5 Offset Error Drift –12 –12 ppm of FSR/°C 5 Gain Error Drift –5 –5 ppm of FSR/°C DC Power Supply Rejection –60 –60 dB ΔVDD = ±10% 5 Ratio 5 DC Crosstalk 200 200 μV R = 2 kΩ to GND or V L DD 5 DAC REFERENCE INPUTS V Input Range 0.25 V 0.25 V V REF DD DD VREF Input Impedance 37 45 37 45 kΩ Normal operation >10 >10 MΩ Power-down mode Reference Feedthrough –90 –90 dB Frequency = 10 kHz 5 OUTPUT CHARACTERISTICS 6 Minimum Output Voltage 0.001 0.001 V Measurement of the minimum and maximum 6 Maximum Output Voltage VDD – 0.001 VDD – 0.001 V drive capability of the output amplifier DC Output Impedance 0.5 0.5 Ω Short Circuit Current 25 25 mA V = 5 V DD 16 16 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power- down mode V = 5 V DD 5 5 μs Coming out of power- down mode VDD = 3 V Rev. H | Page 3 of 24 AD5304/AD5314/AD5324 Data Sheet 2 2 A, W Version B Version 1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 5 LOGIC INPUTS Input Current ±1 ±1 μA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10% 0.6 0.6 V VDD = 3 V ± 10% 0.5 0.5 V V = 2.5 V DD VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10% 2.1 2.1 V VDD = 3 V ± 10% 2.0 2.0 V V = 2.5 V DD Pin Capacitance 3 3 pF POWER REQUIREMENTS VDD 2.5 5.5 2.5 5.5 V 7 I (Normal Mode) DD VDD = 4.5 V to 5.5 V 600 900 600 900 μA VIH = VDD and VIL = GND VDD = 2.5 V to 3.6 V 500 700 500 700 μA VIH = VDD and VIL = GND I (Power-Down Mode) DD VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA VIH = VDD and VIL = GND VDD = 2.5 V to 3.6 V 0.08 1 0.08 1 μA VIH = VDD and VIL = GND 1 See the Terminology section. 2 Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5304 (Code 8 to Code 248); AD5314 (Code 28 to Code 995); AD5324 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 I specification is valid for all DAC codes; interface inactive; all DACs active; load currents excluded. DD AC CHARACTERISTICS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 3 A, B, W Version 1, 2 Parameter Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time V = V = 5 V REF DD AD5304 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5314 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5324 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-sec 1 LSB change around major carry Digital Feedthrough 1 nV-sec Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p Total Harmonic Distortion –70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz 1 See the Terminology section. 2 Guaranteed by design and characterization, not production tested. 3 Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C. Rev. H | Page 4 of 24 Data Sheet AD5304/AD5314/AD5324 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Limit at TMIN, TMAX 1, 2, 3 Parameter VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Test Conditions/Comments t 40 33 ns min SCLK cycle time 1 t 16 13 ns min SCLK high time 2 t3 16 13 ns min SCLK low time t4 16 13 ns min SYNC to SCLK falling edge setup time t5 5 5 ns min Data setup time t 4.5 4.5 ns min Data hold time 6 t 0 0 ns min SCLK falling edge to SYNC rising edge 7 t8 80 33 ns min Minimum SYNC high time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. t 1 SCLK t 2 t t 3 t 8 7 t 4 SYNC t 6 t 5 DIN DB15 DB0 Figure 2. Serial Interface Timing Diagram Rev. H | Page 5 of 24 00929-002 AD5304/AD5314/AD5324 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any 1 Parameter Rating other conditions above those indicated in the operational V to GND –0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND –0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Reference Input Voltage to GND –0.3 V to VDD + 0.3 V device reliability. VOUTA through VOUTD to GND –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B, W Version) –40°C to +105°C ESD CAUTION Storage Temperature Range –65°C to +150°C Junction Temperature (T max) 150°C J 10-Lead MSOP Power Dissipation (T max – T )/ θ J A JA θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/W 10-Lead LFCSP Power Dissipation (TJ max – TA)/ θJA θJA Thermal Impedance 84°C/W Reflow Soldering Peak Temperature (Pb-free) 260°C Peak Temperature (non Pb-free) 220°C Time at Peak Temperature 10 sec to 40 sec 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. H | Page 6 of 24 Data Sheet AD5304/AD5314/AD5324 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 10 SYNC DD AD5304/ 2 V A 9 SCLK OUT AD5314/ V B 3 8 OUT AD5324 DIN TOP VIEW V C 4 7 GND OUT (Not to Scale) REFIN V D 5 6 OUT V 1 10 SYNC DD AD5304/ 2 9 V A SCLK OUT NOTES AD5314/ V B 3 8 DIN OUT 1. THE EXPOSED PAD IS THE GROUND REFERENCE POINT AD5324 FOR ALL CIRCUITRY ON THE PART. IT CAN BE V C 4 7 GND OUT TOP VIEW CONNECTED TO 0 V OR LEFT UNCONNECTED PROVIDED (Not to Scale) REFIN 5 6 V D OUT THERE IS A CONNECTION TO 0 V VIA THE GND PIN. Figure 3. 10-Lead MSOP Pin Configuration Figure 4. 10-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND. 2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 V C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V . DD 6 V D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 7 GND Ground Reference Point for All Circuitry on the Part. 8 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is th taken high before the 16 falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Exposed Ground Reference Point for All Circuitry on the Part. Can be connected to 0 V or left unconnected provided there is 1 Paddle a connection to 0 V via the GND pin. 1 For the 10-Lead LFCSP only. Rev. H | Page 7 of 24 00929-003 00929-004 AD5304/AD5314/AD5324 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 5. AD5304 Typical INL Plot Figure 8. AD5304 Typical DNL Plot 3 0.6 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 2 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 6. AD5314 Typical INL Plot Figure 9. AD5314 Typical DNL Plot 12 1.0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 8 0.5 4 0 0 –4 –0.5 –8 –12 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 7. AD5324 Typical INL Plot Figure 10. AD5324 Typical DNL Plot Rev. H | Page 8 of 24 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 00929-005 00929-007 00929-006 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 00929-009 00929-008 00929-010 Data Sheet AD5304/AD5314/AD5324 0.50 0.2 T = 25°C A T = 25°C A GAIN ERROR V = 2V REF V = 5V DD 0.1 MAX INL 0.25 0 –0.1 MAX DNL 0 –0.2 MIN DNL –0.3 –0.25 –0.4 MIN INL OFFSET ERROR –0.5 –0.50 –0.6 01 23 4 5 06 1 2 3 4 5 V (V) V (V) REF DD Figure 11. AD5304 INL and DNL Error vs. V Figure 14. Offset Error and Gain Error vs. V REF DD 0.5 5 V = 5V DD V = 3V 0.4 REF 5V SOURCE 0.3 4 MAX INL 0.2 3V SOURCE 0.1 3 MAX DNL 0 MIN DNL –0.1 2 –0.2 5V SINK 3V SINK MIN INL –0.3 1 –0.4 –0.5 0 –40 0 40 80 120 06 1 2 3 4 5 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 12. AD5304 INL Error and DNL Error vs. Temperature Figure 15. V Source and Sink Current Capability OUT 1.0 600 T = 25°C V = 5V A DD V = 5V V = 2V DD REF V = 2V REF 500 0.5 400 GAIN ERROR 0 300 200 OFFSET ERROR –0.5 100 –1.0 0 –40 0 40 80 120 ZERO SCALE FULL SCALE TEMPERATURE (°C) CODE Figure 13. AD5304 Offset Error and Gain Error vs. Temperature Figure 16. Supply Current vs. DAC Code Rev. H | Page 9 of 24 ERROR (%) ERROR (LSB) ERROR (LSB) 00929-011 00929-013 00929-012 I (µA) V (V) ERROR (%) DD OUT 00929-016 00929-015 00929-014 AD5304/AD5314/AD5324 Data Sheet 600 T = 25°C A V = 5V –40°C DD V = 5V REF 500 CH1 V A +25°C OUT 400 +105°C 300 SCLK 200 CH2 100 0 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DD Figure 17. Supply Current vs. Supply Voltage Figure 20. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 T = 25°C A V = 5V DD V = 2V REF 0.4 V CH1 DD 0.3 –40°C 0.2 +25°C V A OUT CH2 0.1 +105°C 0 CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DD Figure 18. Power-Down Current vs. Supply Voltage Figure 21. Power-On Reset to 0 V 1000 T = 25°C A T = 25°C V = 5V A DD V = 2V REF 900 V A CH1 OUT 800 V = 5V DD 700 600 CH2 SCLK V = 3V DD 500 400 CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 V (V) LOGIC Figure 19. Supply Current vs. Logic Input Voltage Figure 22. Exiting Power-Down to Midscale Rev. H | Page 10 of 24 I (µA) I (µA) I (µA) DD DD DD 00929-019 00929-018 00929-017 00929-022 00929-021 00929-020 Data Sheet AD5304/AD5314/AD5324 0.02 V = 5V DD T = 25°C A 0.01 V = 3V V = 5V DD DD 0 –0.01 –0.02 300 350 400 450 500 550 600 06 1 2 3 4 5 I (µA) DD V (V) REF Figure 23. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 26. Full-Scale Error vs. VREF 2.50 2.49 2.48 2.47 150ns/DIV 1µs/DIV Figure 24. AD5324 Major-Code Transition Glitch Energy Figure 27. DAC-to-DAC Crosstalk 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. H | Page 11 of 24 (dB) V (V) OUT FREQUENCY 00929-023 00929-024 00929-025 FULL-SCALE ERROR (V) 1mV/DIV 00929-027 00929-026 AD5304/AD5314/AD5324 Data Sheet TERMINOLOGY Major-Code Transition Glitch Energy Relative Accuracy or Integral Nonlinearity (INL) Major-code transition glitch energy is the energy of the impulse For the DAC, relative accuracy or integral nonlinearity (INL) injected into the analog output when the code in the DAC register is a measure of the maximum deviation, in LSB, from a straight changes state. It is normally specified as the area of the glitch in line passing through the endpoints of the DAC transfer function. nV-s and is measured when the digital code is changed by 1 LSB Typical INL vs. code plots can be seen in Figure 5, Figure 6, at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . and Figure 7. 00 to 011 . . . 11). Differential Nonlinearity Digital Feedthrough Differential nonlinearity (DNL) is the difference between the Digital feedthrough is a measure of the impulse injected into the measured change and the ideal 1 LSB change between any two analog output of the DAC from the digital input pins of the adjacent codes. A specified differential nonlinearity of ±1 LSB device when the DAC output is not being written to (SYNC maximum ensures monotonicity. This DAC is guaranteed mono- held high). It is specified in nV-s and is measured with a worst- tonic by design. Typical DNL vs. code plots can be seen in Figure 8, case change on the digital input pins (for example, from all 0s Figure 9, and Figure 10. to all 1s or vice versa.) Offset Error Digital Crosstalk This is a measure of the offset error of the DAC and the output This is the glitch impulse transferred to the output of one DAC amplifier. It is expressed as a percentage of the full-scale range. at midscale in response to a full-scale code change (all 0s to all Gain Error 1s and vice versa) in the input register of another DAC. It is This is a measure of the span error of the DAC. It is the deviation expressed in nV-s. in slope of the actual DAC transfer characteristic from the ideal DAC-to-DAC Crosstalk expressed as a percentage of the full-scale range. This is the glitch impulse transferred to the output of one DAC Offset Error Drift due to a digital code change and subsequent output change of This is a measure of the change in offset error with changes in another DAC. This includes both digital and analog crosstalk. temperature. It is expressed in (ppm of full-scale range)/°C. It is measured by loading one of the DACs with a full-scale code Gain Error Drift change (all 0s to all 1s and vice versa) with the LDAC bit set low This is a measure of the change in gain error with changes in and monitoring the output of another DAC. The energy of the temperature. It is expressed in (ppm of full-scale range)/°C. glitch is expressed in nV-s. Power Supply Rejection Ratio (PSRR) Multiplying Bandwidth This indicates how the output of the DAC is affected by changes The amplifiers within the DAC have a finite bandwidth. The in the supply voltage. PSRR is the ratio of the change in V to OUT multiplying bandwidth is a measure of this. A sine wave on the a change in V for full-scale output of the DAC. It is measured DD reference (with full-scale code loaded to the DAC) appears on in decibels. V is held at 2 V and V is varied ±10%. REF DD the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. DC Crosstalk This is the dc change in the output level of one DAC at midscale Total Harmonic Distortion (THD) in response to a full-scale code change (all 0s to all 1s and vice This is the difference between an ideal sine wave and its attenuated versa) and output change of another DAC. It is expressed in version using the DAC. The sine wave is used as the reference for microvolts. the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in decibels. Rev. H | Page 12 of 24 Data Sheet AD5304/AD5314/AD5324 GAIN ERROR PLUS OFFSET ERROR OUTPUT IDEAL VOLTAGE ACTUAL NEGATIVE OFFSET DAC CODE ERROR GAIN ERROR PLUS OFFSET ERROR DEAD BAND ACTUAL OUTPUT CODES VOLTAGE AMPLIFIER FOOTROOM (1mV) IDEAL NEGATIVE OFFSET ERROR POSITIVE OFFSET DAC CODE Figure 28. Transfer Function with Negative Offset Figure 29. Transfer Function with Positive Offset Rev. H | Page 13 of 24 00929-028 00929-029 AD5304/AD5314/AD5324 Data Sheet THEORY OF OPERATION FUNCTIONAL DESCRIPTION R The AD5304/AD5314/AD5324 are quad, resistor-string DACs R fabricated on a CMOS process with resolutions of 8, 10, and 12 TO OUTPUT R AMPLIFIER bits, respectively. Each contains four output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide R rail-to-rail output swing with a slew rate of 0.7 V/μs. The four DACs share a single reference input pin. The devices have pro- R grammable power-down modes, in which all DACs can be turned off completely with a high impedance output. Figure 31. Resistor String Digital-to-Analog DAC Reference Inputs The architecture of one DAC channel consists of a resistor-string There is a single reference input pin for the four DACs. The DAC followed by an output buffer amplifier. The voltage at the reference input is not buffered. The user can have a reference REFIN pin provides the reference voltage for the DAC. Figure 30 voltage as low as 0.25 V or as high as VDD because there is no shows a block diagram of the DAC architecture. Since the input restriction due to the headroom or footroom requirements of coding to the DAC is straight binary, the ideal output voltage is any reference amplifier. It is recommended to use a buffered given by reference in the external circuit (for example, REF192). The input impedance is typically 45 kΩ. V D REF V  OUT N 2 Output Amplifier where The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to V when D = decimal equivalent of the binary code that is loaded to the DD the reference is V . It is capable of driving a load of 2 kΩ to DAC register: DD GND or V , in parallel with 500 pF to GND or V . The source DD DD 0–255 for AD5304 (8 bits) and sink capabilities of the output amplifier can be seen in the 0–1023 for AD5314 (10 bits) plot in Figure 15. 0–4095 for AD5324 (12 bits) The slew rate is 0.7 V/μs with a half-scale settling time to N = DAC resolution. ±0.5 LSB (at eight bits) of 6 μs. REFIN POWER-ON RESET The AD5304/AD5314/AD5324 are provided with a power-on reset INPUT DAC RESISTOR V A OUT function, so that they power up in a defined state. The power-on REGISTER REGISTER STRING state uses normal operation and an output voltage set to 0 V. OUTPUT BUFFER Both input and DAC registers are filled with zeros and remain AMPLIFIER so until a valid write sequence is made to the device. This is Figure 30. DAC Channel Architecture particularly useful in applications where it is important to know Resistor String the state of the DAC outputs while the device is powering up. The resistor string section is shown in Figure 31. It is simply a SERIAL INTERFACE string of resistors, each of value R. The digital code loaded to the The AD5304/AD5314/AD5324 are controlled over a versatile, DAC register determines at which node on the string the voltage 3-wire serial interface that operates at clock rates up to 30 MHz is tapped off to be fed into the output amplifier. The voltage is and are compatible with SPI, QSPI, MICROWIRE, and DSP tapped off by closing one of the switches connecting the string interface standards. to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. H | Page 14 of 24 00929-030 00929-031 Data Sheet AD5304/AD5314/AD5324 BIT15 BIT0 (MSB) (LSB) A1 A0 PD LDAC D7 D6 D5 D4 D3 D2 D1 D0 0 0 X X DATA BITS Figure 32. AD5304 Input Shift Register Contents BIT15 BIT0 (MSB) (LSB) A1 A0 PD LDAC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS Figure 33. AD5314 Input Shift Register Contents BIT15 BIT0 (MSB) (LSB) A1 A0 PD LDAC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS Figure 34. AD5324 Input Shift Register Contents Input Shift Register SYNC The input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, into the device only while SYNC is low. To start the serial data SCLK. See Figure 2 for the timing diagram of this operation. The transfer, take SYNC low, observing the minimum SYNC to SCLK 16-bit word consists of four control bits followed by 8, 10, or 12 falling edge setup time, t . After SYNC goes low, serial data shifts 4 bits of DAC data, depending on the device type. Data is loaded into the device’s input shift register on the falling edges of SCLK MSB first (Bit 15) and the first two bits determine whether the th for 16 clock pulses. Any data and clock pulses after the 16 falling data is for DAC A, DAC B, DAC C, or DAC D. Bit 13 and Bit 12 edge of SCLK are ignored because the SCLK and DIN input buffers control the operating mode of the DAC. Bit 13 is PD, and deter- are powered down. No further serial data transfer occurs until mines whether the part is in normal or power-down mode. Bit 12 is SYNC is taken high and low again. LDAC, and controls when DAC registers and outputs are updated. th SYNC can be taken high after the falling edge of the 16 SCLK pulse, observing the minimum SCLK falling edge to SYNC Table 6. Address Bits rising edge time, t7. A1 A0 DAC Addressed 0 0 DAC A After the end of the serial data transfer, data automatically transfers 0 1 DAC B from the input shift register to the input register of the selected th 1 0 DAC C SYNC DAC. If is taken high before the 16 falling edge of SCLK, 1 1 DAC D the data transfer is aborted and the DAC input registers are not updated. Address and Control Bits When data has been transferred into three of the DAC input PD 0: All four DACs go into power-down mode, consuming registers, all DAC registers and all DAC outputs are simultaneously only 200 nA @ 5 V. The DAC outputs enter a high LDAC updated by setting low when writing to the remaining impedance state. DAC input register. 1: Normal operation. Low Power Serial Interface LDAC 0: All four DAC registers and, therefore, all DAC outputs To reduce the power consumption of the device even further, the updated simultaneously on completion of the write interface fully powers up only when the device is being written sequence. to, that is, on the falling edge of SYNC. As soon as the 16-bit 1: Only addressed input register is updated. There is control word has been written to the part, the SCLK and DIN no change in the content of the DAC registers. input buffers are powered down. They power up again only The AD5324 uses all 12 bits of DAC data; the AD5314 uses 10 bits SYNC following a falling edge of . and ignores the 2 LSB Bits. The AD5304 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output (VREF − 1 LSB). Rev. H | Page 15 of 24 00929-034 00929-033 00929-032 AD5304/AD5314/AD5324 Data Sheet Double-Buffered Interface The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power- The AD5304/AD5314/AD5324 DACs have double-buffered inter- down mode is activated. However, the contents of the registers faces consisting of two banks of registers—input registers and are unaffected when in power-down. The time to exit power-down DAC registers. The input register is directly connected to the input is typically 2.5 μs for VDD = 5 V and 5 μs when VDD = 3 V. This is shift register and the digital code is transferred to the relevant input th the time from the falling edge of the 16 SCLK pulse to when register on completion of a valid write sequence. The DAC the output voltage deviates from its power down voltage. See register contains the digital code used by the resistor string. Figure 22 for a plot. LDAC Access to the DAC register is controlled by the bit. When AMPLIFIER LDAC the bit is set high, the DAC register is latched and hence RESISTOR V OUT STRING DAC the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, all DAC registers are updated after a complete write sequence. POWER-DOWN CIRCUITRY This is useful if the user requires simultaneous updating of all Figure 35. Output Stage during Power-Down DAC outputs. The user can write to three of the input registers LDAC individually and then, by setting the bit low when MICROPROCESSOR INTERFACING writing to the remaining DAC input register, all outputs AD5304/AD5314/AD5324 to ADSP-21xx update simultaneously. Figure 36 shows a serial interface between the AD5304/AD5314/ These parts contain an extra feature whereby the DAC register AD5324 and the ADSP-21xx family. The ADSP-21xx is set up is not updated unless its input register has been updated since to operate in the SPORT transmit alternate framing mode. The the last time that LDAC was brought low. Normally, when LDAC ADSP-21xx sport is programmed through the SPORT control is brought low, the DAC registers are filled with the contents of register and must be configured as follows: internal clock operation, the input registers. In the case of the AD5304/AD5314/AD5324, active-low framing, and 16-bit word length. Transmission is the part updates the DAC register only if the input register has initiated by writing a word to the Tx register after the SPORT been changed since the last time the DAC register was updated, has been enabled. The data is clocked out on each rising edge of thereby removing unnecessary digital crosstalk. the DSP’s serial clock and clocked into the AD5304/AD5314/ AD5324 on the falling edge of the DAC’s SCLK. POWER-DOWN MODE The AD5304/AD5314/AD5324 have low power consumption, ADSP-21xx* AD5304/ AD5314/ dissipating only 1.5 mW with a 3 V supply and 3 mW with a AD5324* 5 V supply. Power consumption can be further reduced when TFS SYNC the DACs are not in use by putting them into power-down mode, DT DIN selected by a 0 on Bit 13 (PD) of the control word. PD bit is set to 1, all DACs work normally with a typical SCLK SCLK When the power consumption of 600 μA at 5 V (500 μA at 3 V). However, in *ADDITIONAL PINS OMITTED FOR CLARITY. power-down mode, the supply current falls to 200 nA at 5 V Figure 36. AD5304/AD5314/AD5324 to ADSP-21xx Interface (80 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but also the output stage is internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-stated while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 35. Rev. H | Page 16 of 24 00929-035 00929-036 Data Sheet AD5304/AD5314/AD5324 AD5304/AD5314/AD5324 to 68HC11/68L11 Interface only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after Figure 37 shows a serial interface between the AD5304/AD5314/ the first eight bits are transmitted, and a second write cycle is AD5324 and the 68HC11/68L11 microcontroller. SCK of the initiated to transmit the second byte of data. P3.3 is taken high 68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324, following the completion of this cycle. The 80C51/80L51 outputs while the MOSI output drives the serial data line (DIN) of the the serial data in a format that has the LSB first. The AD5304/ SYNC DAC. The signal is derived from a port line (PC7). The AD5314/AD5324 requires its data with the MSB as the first bit setup conditions for the correct operation of this interface are as received. The 80C51/80L51 transmit routine takes this into follows: the 68HC11/68L11 is configured so that its CPOL bit is account. a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 80C51/80L51* AD5304/ AD5314/ is configured as above, data appearing on the MOSI output is AD5324* valid on the falling edge of SCK. Serial data from the 68HC11/ P3.3 SYNC 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB TxD SCLK first. To load data to the AD5304/ AD5314/AD5324, PC7 is left RxD DIN low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at *ADDITIONAL PINS OMITTED FOR CLARITY. the end of this procedure. Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface 68HC11/68L11* AD5304/ AD5304/AD5314/AD5324 to MICROWIRE Interface AD5314/ Figure 39 shows an interface between the AD5304/AD5314/ AD5324* AD5324 and any MICROWIRE-compatible device. Serial data PC7 SYNC is shifted out on the falling edge of the serial clock, SK, and is SCK SCLK clocked into the AD5304/AD5314/AD5324 on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK. MOSI DIN MICROWIRE* AD5304/ *ADDITIONAL PINS OMITTED FOR CLARITY. AD5314/ Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface AD5324* CS SYNC AD5304/AD5314/AD5324 to 80C51/80L51 Interface Figure 38 shows a serial interface between the AD5304/AD5314/ SK SCLK AD5324 and the 80C51/80L51 microcontroller. The setup for SO DIN the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5304/AD5314/AD5324, while RxD drives the serial *ADDITIONAL PINS OMITTED FOR CLARITY. data line of the part. The SYNC signal is again derived from a Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5304/AD5314/ AD5324, P3.3 is taken low. The 80C51/80L51 transmits data Rev. H | Page 17 of 24 00929-037 00929-039 00929-038 AD5304/AD5314/AD5324 Data Sheet APPLICATIONS INFORMATION Bipolar Operation Using the AD5304/AD5314/AD5324 TYPICAL APPLICATION CIRCUIT The AD5304/AD5314/AD5324 have been designed for single The AD5304/AD5314/AD5324 can be used with a wide range supply operation, but a bipolar output range is also possible of reference voltages where the devices offer full, one-quadrant using the circuit in Figure 41. This circuit gives an output voltage multiplying capability over a reference range of 0 V to V . DD range of ±5 V. Rail-to-rail operation at the amplifier output is More typically, these devices are used with a fixed, precision achievable using an AD820 or an OP295 as the output amplifier. reference voltage. Suitable references for 5 V operation are the R2 = 10kΩ AD780 and REF192 (2.5 V references). For 2.5 V operation, a +6V TO +16V suitable external reference would be the AD589, a 1.23 V band +5V R1 = 10kΩ gap reference. Figure 40 shows a typical setup for the AD5304/ 10µF 0.1µF AD820/ AD5314/AD5324 when using an external reference. ±5V OP295 +5V V V A DD OUT V = 2.5V TO 5.5V DD REF195 AD5304 V IN –5V V REFIN OUT V B OUT 1µF 0.1µF 10µF GND V C OUT AD5304/AD5314/ GND V AD5324 IN V D OUT V A V REFIN OUT OUT DIN SCLK SYNC 1µF EXTERNAL V B OUT REFERENCE SCLK AD790/REF192 V C DIN OUT SERIAL WITH V = 5V DD INTERFACE OR AD589 WITH SYNC V D OUT V = 2.5V DD Figure 41. Bipolar Operation with the AD5304 A0 GND The output voltage for any input code can be calculated as follows: SERIAL INTERFACE N   (REFIND / 2 ) (R1R2) V  REFIN (R2 /R1) Figure 40. AD5304/AD5314/AD5324 Using External Reference   OUT R1     If an output range of 0 V to V is required, the simplest solution is DD where: to connect the reference input to V . As this supply is not very DD accurate and can be noisy, the AD5304/AD5314/AD5324 can D is the decimal equivalent of the code loaded to the DAC. be powered from the reference voltage; for example, using a 5 V N is the DAC resolution. reference such as the REF195. The REF195 can output a steady REFIN is the reference voltage input: supply voltage for the AD5304/AD5314/AD5324. The current REFIN = 5 V, R1 = R2 = 10 kΩ required from the REF195 is 600 μA supply current and approxi- N VOUT = (10 × D/2 ) − 5 V mately 112 μA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is 712 μA + 4 (5 V/10 kΩ) = 2.70 mA The load regulation of the REF195 is typically 2 ppm/mA, resulting in an error of 5.4 ppm (27 μV) for the 2.7 mA current drawn from it. This corresponds to a 0.0014 LSB error at eight bits and 0.022 LSB error at 12 bits. Rev. H | Page 18 of 24 00929-040 00929-041 Data Sheet AD5304/AD5314/AD5324 Opto-Isolated Interface for Process Control Applications AD5304 SCLK V A OUT SYNC The AD5304/AD5314/AD5324 have a versatile 3-wire serial V B OUT DIN DIN V V C DD inter-face, making them ideal for generating accurate voltages OUT SCLK V D OUT in process control and industrial applications. Due to noise, V CC 1G 74HC139 safety requirements, or distance, it might be necessary to isolate ENABLE AD5304 1Y0 V A OUT the AD5304/AD5314/AD5324 from the controller. This can 1A 1Y1 SYNC CODED V B OUT ADDRESS 1Y2 DIN easily be achieved by using opto-isolators, which provide isolation 1B V C OUT 1Y3 SCLK V D in excess of 3 kV. The actual data rate achieved is limited by the OUT DGND type of optocouplers chosen. The serial loading structure of the AD5304 AD5304/AD5314/AD5324 makes them ideally suited for use in V A OUT SYNC V B OUT opto-isolated applications. Figure 42 shows an opto-isolated DIN V C OUT SCLK interface to the AD5304 where DIN, SCLK, and SYNC are driven V D OUT from optocouplers. The power supply to the part also needs to AD5304 be isolated. This is done by using a transformer. On the DAC V A OUT SYNC side of the transformer, a 5 V regulator provides the 5 V supply V B OUT DIN V C OUT required for the AD5304. SCLK V D OUT 5V Figure 43. Decoding Multiple AD5304 Devices in a System REGULATOR 10µF 0.1µF POWER AD5304/AD5314/AD5324 as a Digitally Programmable Window Detector V DD A digitally programmable upper/lower limit detector using two 10kΩ DACs in the AD5304/AD5314/AD5324 is shown in Figure 44. V DD SCLK SCLK REFIN The upper and lower limits for the test are loaded to DAC A and DAC B, which, in turn, set the limits on the CMP04. If the signal at the V input is not within the programmed window, IN AD5304 V DD an LED indicates the fail condition. Similarly, DAC C and DAC D 10kΩ can be used for window detection on a second VIN signal. V A OUT SYNC SYNC 5V V B OUT 0.1µF 10µF V IN 1kΩ 1kΩ V C OUT V FAIL PASS DD V V D DD OUT V REFIN 10kΩ REF V A OUT DIN 1/2 DIN AD5304/AD5314/ 1/2 GND PASS/FAIL AD5324* CMP04 SYNC SYNC DIN DIN V B OUT Figure 42. AD5304 in an Opto-Isolated Interface 1/6 74HC05 SCLK SCLK GND DECODING MULTIPLE AD5304/AD5314/AD5324S *ADDITIONAL PINS OMITTED FOR CLARITY. SYNC The pin on the AD5304/AD5314/AD5324 can be used Figure 44. Window Detection in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but SYNC can only be active to one of the devices at any one time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input must be brought to its inactive state while the coded address inputs are changing state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5304 devices in a system. Rev. H | Page 19 of 24 00929-042 00929-043 00929-044 AD5304/AD5314/AD5324 Data Sheet the common ceramic types that provide a low impedance path POWER SUPPLY BYPASSING AND GROUNDING to ground at high frequencies, to handle transient currents due In any circuit where accuracy is important, careful consideration of to internal logic switching. the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the The power supply lines of the AD5304/AD5314/AD5324 use as AD5304/AD5314/AD5324 is mounted is designed so that the large a trace as possible to provide low impedance paths and reduce analog and digital sections are separated and confined to certain the effects of glitches on the power supply line. Fast switching areas of the board. If the AD5304/AD5314/AD5324 are in a signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never run system where multiple devices require an AGND-to-DGND near the reference inputs. Avoid crossover of digital and analog connection, the connection is made at one point only. The star signals. Traces on opposite sides of the board run at right angles ground point is established as close as possible to the device. The AD5304/AD5314/AD5324 has ample supply bypassing of 10 μF in to each other. This reduces the effects of feedthrough through parallel with 0.1 μF on the supply located as close to the package as the board. A microstrip technique is by far the best, but is not possible, ideally right up against the device. The 10 μF capacitors always possible with a double-sided board. In this technique, are the tantalum bead type. The 0.1 μF capacitor has low effective the component side of the board is dedicated to a ground plane while signal traces are placed on the solder side. series resistance (ESR) and effective series inductance (ESI), like Table 7. Overview of AD53xx Serial Devices Part No. Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins SINGLES AD5300 8 1 ±0.25 SPI 4 SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-Wire 7 SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-Wire 8 SOT-23, MSOP 6, 8 DUALS AD5302 8 2 ±0.25 SPI 6 MSOP 8 AD5312 10 2 ±0.5 SPI 7 MSOP 8 AD5322 12 2 ±1.0 SPI 8 MSOP 8 AD5303 8 2 ±0.25 SPI 6 TSSOP 16 AD5313 10 2 ±0.5 SPI 7 TSSOP 16 AD5323 12 2 ±1.0 SPI 8 TSSOP 16 QUADS AD5304 8 4 ±0.25 SPI 6 MSOP, LFCSP 10 AD5314 10 4 ±0.5 SPI 7 MSOP, LFCSP 10 AD5324 12 4 ±1.0 SPI 8 MSOP, LFCSP 10 AD5305 8 4 ±0.25 2-Wire 6 MSOP 10 AD5315 10 4 ±0.5 2-Wire 7 MSOP 10 AD5325 12 4 ±1.0 2-Wire 8 MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 TSSOP 16 AD5307 8 4 ±0.25 SPI 6 TSSOP 16 AD5317 10 4 ±0.5 SPI 7 TSSOP 16 AD5327 12 4 ±1.0 SPI 8 TSSOP 16 OCTALS AD5308 8 8 ±0.25 SPI 6 TSSOP 16 AD5318 10 8 ±0.5 SPI 7 TSSOP 16 AD5328 12 8 ±1.0 SPI 8 TSSOP 16 Rev. H | Page 20 of 24 Data Sheet AD5304/AD5314/AD5324 Table 8. Overview of AD53xx Parallel Devices Part No. Resolution DNL V Pins Settling Time (μs) Additional Pin Functions Package Pins REF SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 TSSOP 20 ✓ ✓ ✓ AD5331 10 ±0.5 1 7 TSSOP 20 ✓ ✓ AD5340 12 ±1.0 1 8 TSSOP 24 ✓ ✓ ✓ AD5341 12 ±1.0 1 8 TSSOP 20 ✓ ✓ ✓ ✓ DUALS AD5332 8 ±0.25 2 6 TSSOP 20 ✓ AD5333 10 ±0.5 2 7 TSSOP 24 ✓ ✓ ✓ AD5342 12 ±1.0 2 8 TSSOP 28 ✓ ✓ ✓ AD5343 12 ±1.0 1 8 TSSOP 20 ✓ ✓ QUADS AD5334 8 ±0.25 2 6 TSSOP 24 ✓ ✓ AD5335 10 ±0.5 2 7 TSSOP 24 ✓ ✓ AD5336 10 ±0.5 4 7 TSSOP 28 ✓ ✓ AD5344 12 ±1.0 4 8 TSSOP 28 Rev. H | Page 21 of 24 AD5304/AD5314/AD5324 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 46. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. H | Page 22 of 24 PIN 1 INDICATOR (R 0.15) 091709-A 121009-A Data Sheet AD5304/AD5314/AD5324 ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option Branding AD5304ARM –40°C to +105°C 10-Lead MSOP RM-10 DBA AD5304ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DBA AD5304ARMZ –40°C to +105°C 10-Lead MSOP RM-10 D9W AD5304ARMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D9W AD5304ACPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DBA# AD5304BRM –40°C to +105°C 10-Lead MSOP RM-10 DBB AD5304BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 DBB AD5304BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DBB AD5304BRMZ –40°C to +105°C 10-Lead MSOP RM-10 DBB# AD5304BRMZ-REEL –40°C to +105°C 10-Lead MSOP RM-10 DBB# AD5304BRMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DBB# AD5304BCPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DBB# AD5314ACPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DCA# AD5314ARM –40°C to +105°C 10-Lead MSOP RM-10 DCA AD5314ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DCA AD5314ARMZ –40°C to +105°C 10-Lead MSOP RM-10 DCA# AD5314ARMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DCA# AD5314WARMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DCA# AD5314BCPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DCB# AD5314BRM –40°C to +105°C 10-Lead MSOP RM-10 DCB AD5314BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 DCB AD5314BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DCB AD5314BRMZ –40°C to +105°C 10-Lead MSOP RM-10 DCB# AD5314BRMZ-REEL –40°C to +105°C 10-Lead MSOP RM-10 DCB# AD5314BRMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DCB# AD5324ACPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DDA# AD5324ARM –40°C to +105°C 10-Lead MSOP RM-10 DDA AD5324ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DDA AD5324ARMZ –40°C to +105°C 10-Lead MSOP RM-10 D8F AD5324ARMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D8F AD5324BCPZ-REEL7 –40°C to +105°C 10-Lead LFCSP_WD CP-10-9 DDB# AD5324BRM –40°C to +105°C 10-Lead MSOP RM-10 DDB AD5324BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 DDB AD5324BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DDB AD5324BRMZ –40°C to +105°C 10-Lead MSOP RM-10 DDB# AD5324BRMZ-REEL –40°C to +105°C 10-Lead MSOP RM-10 DDB# AD5324BRMZ-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 DDB# 1 Z = RoHS Compliant Part; # denotes lead-free product can be top or bottom marked. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5314WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. H | Page 23 of 24 AD5304/AD5314/AD5324 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00929-0-9/11(H) Rev. H | Page 24 of 24