ANALOG DEVICES AD5313

2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5303/AD5313/AD5323 FEATURES GENERAL DESCRIPTION AD5303: 2 buffered 8-bit DACs in 1 package The AD5303/AD5313/AD5323 are dual 8-/10-/12-bit buffered A version: ±1 LSB INL, B version: ±0.5 LSB INL voltage output DACs in a 16-lead TSSOP package that operate AD5313: 2 buffered 10-bit DACs in 1 package from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. A version: ±4 LSB INL, B version: ±2 LSB INL Their on-chip output amplifiers allow the outputs to swing rail-to- AD5323: 2 buffered 12-bit DACs in 1 package rail with a slew rate of 0.7 V/μs. The AD5303/AD5313/AD5323 A version: ±16 LSB INL, B version: ±8 LSB INL utilize a versatile 3-wire serial interface that operates at clock 16-lead TSSOP package rates up to 30 MHz and is compatible with standard SPI, QSPI™, Micropower operation: 300 μA @ 5 V (including reference MICROWIRE™, and DSP interface standards. current) The references for the two DACs are derived from two reference Power-down to 200 nA @ 5 V, 50 nA @ 3 V pins (one per DAC). These reference inputs may be configured 2.5 V to 5.5 V power supply as buffered or unbuffered inputs. The parts incorporate a power- Double-buffered input logic on reset circuit, which ensures that the DAC outputs power up Guaranteed monotonic by design over all codes to 0 V and remain there until a valid write to the device takes Buffered/unbuffered reference input options CLR place. There is also an asynchronous active low pin that Output range: 0 V to V or 0 V to 2 V REF REF clears both DACs to 0 V. The outputs of both DACs may be Power-on-reset to 0 V LDAC updated simultaneously using the asynchronous input. SDO daisy-chaining option The parts contain a power-down feature that reduces the LDAC Simultaneous update of DAC outputs via pin current consumption of the devices to 200 nA at 5 V (50 nA CLR Asynchronous facility at 3 V) and provides software-selectable output loads while Low power serial interface with Schmitt-triggered inputs in power-down mode. The parts may also be used in daisy- On-chip rail-to-rail output buffer amplifiers chaining applications using the SDO pin. APPLICATIONS The low power consumption of these parts in normal operation Portable battery-powered instruments makes them ideally suited to portable battery-operated equip- Digital gain and offset adjustment ment. The power consumption is 1.5 mW at 5 V and 0.7 mW at Programmable voltage and current sources 3 V, reducing to 1 μW in power-down mode. Programmable attenuators FUNCTIONAL BLOCK DIAGRAM V V A DD BUF A REF AD5303/AD5313/AD5323 POWER-ON RESET DAC INPUT STRING V A BUFFER OUT REGISTER REGISTER DAC SYNC INTERFACE POWER-DOWN RESISTOR LOGIC SCLK LOGIC NETWORK DIN INPUT DAC STRING V B OUT BUFFER REGISTER REGISTER DAC SDO GAIN-SELECT RESISTOR LOGIC NETWORK DCEN V B GND LDAC BUF B CLR PD REF Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00472-001 AD5303/AD5313/AD5323 TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 17 Applications....................................................................................... 1 Low Power Serial Interface ....................................................... 17 General Description ......................................................................... 1 Double-Buffered Interface ........................................................ 17 Functional Block Diagram .............................................................. 1 Power-Down Modes ...................................................................... 19 Revision History ............................................................................... 2 Microprocesser Interfacing ........................................................... 20 Specifications..................................................................................... 3 AD5303/AD5313/AD5323 to ADSP-2101 Interface............. 20 AC Characteristics........................................................................ 6 AD5303/AD5313/AD5323 to 68HC11/68L11 Interface ...... 20 Timing Characteristics ................................................................ 6 AD5303/AD5313/AD5323 to 80C51/80L51 Interface.......... 20 Absolute Maximum Ratings............................................................ 8 AD5303/AD5313/AD5323 to MICROWIRE Interface ........ 20 ESD Caution.................................................................................. 8 Applications Information .............................................................. 21 Pin Configuration and Function Descriptions............................. 9 Typical Application Circuit....................................................... 21 Terminology .................................................................................... 10 Bipolar Operation Using the AD5303/AD5313/AD5323..... 21 Typical Performance Characteristics ........................................... 11 Opto-Isolated Interface for Process Control Applications ... 22 Functional Description .................................................................. 15 Decoding Multiple AD5303/AD5313/AD5323s.................... 22 Digital-to-Analog ....................................................................... 15 AD5303/AD5313/AD5323 as a Digitally Programmable Window Detector....................................................................... 22 Resistor String............................................................................. 15 Coarse and Fine Adjustment Using the DAC Reference Inputs ............................................................... 15 AD5303/AD5313/AD5323 ....................................................... 23 Output Amplifier........................................................................ 15 Daisy-Chain Mode..................................................................... 23 Power-On Reset .............................................................................. 16 Power Supply Bypassing and Grounding................................ 24 CLR Clear Function ( ) ................................................................ 16 Outline Dimensions....................................................................... 25 Serial Interface ................................................................................ 17 Ordering Guide .......................................................................... 25 REVISION HISTORY 6/07—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 4............................................................................ 8 Changes to the Ordering Guide.................................................... 25 8/03—Rev. 0 to Rev. A Added A Version.................................................................Universal Changes to Features.......................................................................... 1 Changes to Specifications................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 5 Changes to Ordering Guide ............................................................ 5 Updated Outline Dimensions ....................................................... 18 4/99—Revision 0: Initial Version Rev. B | Page 2 of 28 AD5303/AD5313/AD5323 SPECIFICATIONS VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 A Version B Version 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3 , 4 DC PERFORMANCE AD5303 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ± 0.15 ±0.5 LSB Differential Nonlinearity ±0.02 ±0.25 ± 0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5313 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ± 0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ± 0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5323 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 2 and Figure 3 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3 Lower Dead Band 10 60 10 60 mV See Figure 2 and Figure 3 5 Offset Error Drift −12 −12 ppm of FSR/°C 5 −5 −5 ppm of FSR/°C Gain Error Drift 5 −60 −60 dB ΔV = ±10% Power Supply Rejection Ratio DD 5 30 30 μV DC Crosstalk 5 DAC REFERENCE INPUTS V Input Range 1 V 1 V V Buffered reference mode REF DD DD 0 V 0 V V Unbuffered reference mode DD DD V Input Impedance >10 >10 MΩ Buffered reference mode REF 180 180 kΩ Unbuffered reference mode 0 V to V output range, input REF impedance = R DAC 90 90 kΩ Unbuffered reference mode 0 V to 2 VREF output range, input impedance = RDAC Reference Feedthrough −90 −90 dB Frequency = 10 kHz Channel-to-Channel Isolation −80 −80 dB Frequency = 10 kHz 5 OUTPUT CHARACTERISTICS 6 Minimum Output Voltage 0.001 0.001 V min This is a measure of the minimum and 6 maximum drive capability of the output Maximum Output Voltage VDD − 0.001 VDD − 0.001 V max amplifier DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 50 50 mA VDD = 5 V 20 20 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down mode; VDD = 5 V 5 5 μs Coming out of power-down mode; VDD = 3 V Rev. B | Page 3 of 28 AD5303/AD5313/AD5323 1 1 A Version B Version 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 5 LOGIC INPUTS Input Current ±1 ±1 μA Input Low Voltage, V 0.8 0.8 V V = 5 V ± 10% IL DD 0.6 0.6 V V = 3 V ± 10% DD 0.5 0.5 V V = 2.5 V DD Input High Voltage, V 2.4 2.4 V V = 5 V ± 10% IH DD 2.1 2.1 V V = 3 V ± 10% DD 2.0 2.0 V V = 2.5 V DD Pin Capacitance 2 3.5 2 3.5 pF 5 LOGIC OUTPUT (SDO) V = 5 V ± 10% DD Output Low Voltage 0.4 0.4 V I = 2 mA SINK Output High Voltage 4.0 4.0 V I = 2 mA SOURCE V = 3 V ± 10% DD Output Low Voltage 0.4 0.4 V I = 2 mA SINK Output High Voltage 2.4 2.4 V I = 2 mA SOURCE Floating-State Leakage Current 1 1 μA DCEN = GND Floating-State Output 3 3 pF DCEN = GND Capacitance POWER REQUIREMENTS VDD 2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes IDD (Normal Mode) Both DACs active and excluding load currents VDD = 4.5 V to 5.5 V 300 450 300 450 μA Both DACs in unbuffered mode; VIH = VDD and VIL = GND; in buffered VDD = 2.5 V to 3.6 V 230 350 230 350 μA mode, extra current is typically x μA per DAC, where x = 5 μA + VREF/RDAC IDD (Full Power-Down) VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA V = 2.5 V to 3.6 V 0.05 1 0.05 1 μA DD 1 Temperature range for Version A, Version B: −40°C to +105°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested. 6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V = V REF DD and offset plus gain error must be positive. Rev. B | Page 4 of 28 AD5303/AD5313/AD5323 GAIN ERROR PLUS GAIN ERROR OFFSET ERROR PLUS OFFSET ERROR OUTPUT ACTUAL OUTPUT IDEAL VOLTAGE VOLTAGE ACTUAL IDEAL POSITIVE POSITIVE OFFSET OFFSET DAC CODE ERROR ERROR DAC CODE Figure 3. Transfer Function with Positive Offset DEAD BAND AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 2. Transfer Function with Negative Offset Rev. B | Page 5 of 28 00472-005 00472-006 AD5303/AD5313/AD5323 1 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 3 A, B Version 2 Min Typ Max Parameter Unit Conditions/Comments Output Voltage Settling Time VREF = VDD = 5 V AD5303 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xc0) AD5313 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5323 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xc00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry (011 . . . 11 to 100 . . . 00) Digital Feedthrough 0.10 nV-s Analog Crosstalk 0.01 nV-s DAC-to-DAC Crosstalk 0.01 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p, unbuffered mode Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range for Version A and Version B: −40°C to +105°C. TIMING CHARACTERISTICS V = 2.5 V to 5.5 V; all specifications T to T , unless otherwise noted. DD MIN MAX Table 3. Limit at T T MIN, MAX 1, 2, 3 Parameter Unit Conditions/Comments (A, B Version) t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t 0 ns min SYNC to SCLK rising edge setup time 4 t 5 ns min Data setup time 5 t 4.5 ns min Data hold time 6 t7 0 ns min SCLK falling edge to SYNC rising edge t8 100 ns min Minimum SYNC high time t 20 ns min LDAC pulse width 9 t 20 ns min SCLK falling edge to LDAC rising edge 10 t 20 ns min CLR pulse width 11 4, 5 t12 5 ns min SCLK falling edge to SDO invalid 4, 5 t13 20 ns max SCLK falling edge to SDO valid 5 t14 0 ns min SCLK falling edge to SYNC rising edge 5 t 10 ns min SYNC rising edge to SCLK rising edge 15 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 4 and Figure 5. 4 These are measured with the load circuit of Figure 4. 5 Daisy-chain mode only (see Figure 47). Rev. B | Page 6 of 28 AD5303/AD5313/AD5323 2mA I OL TO OUTPUT 1.6V PIN C L 50pF 2mA I OH Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications t 1 SCLK t 2 t 3 t t 7 8 t 4 SYNC t 6 t 5 DIN* DB15 DB0 t 9 LDAC t 10 LDAC t 11 CLR * SEE THE INPUT SHIFT REGISTER SECTION. Figure 5. Serial Interface Timing Diagram Rev. B | Page 7 of 28 00472-002 00472-003 AD5303/AD5313/AD5323 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to VDD + 0.3 V device reliability. Reference Input Voltage to GND −0.3 V to VDD + 0.3 V VOUTA, VOUTB to GND −0.3 V to VDD + 0.3 V Operating Temperature Range ESD CAUTION Industrial (A, B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ Max) 150°C 16-Lead TSSOP Package Power Dissipation (T max − T )/θ J A JA θ Thermal Impedance 160°C/W JA Lead Temperature JEDEC Industry Standard Soldering J-STD-020 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 28 AD5303/AD5313/AD5323 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 16 CLR SDO 2 15 LDAC GND AD5303/ 3 14 V DIN DD AD5313/ 4 13 V B SCLK REF AD5323 V A 5 12 SYNC REF TOP VIEW (Not to Scale) V A 6 11 V B OUT OUT BUF A 7 10 PD BUF B 8 9 DCEN Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 Active Low Control Input. Loads all zeros to both input and DAC registers. CLR 2 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows the simultaneous update of both DAC outputs. 3 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. DD 4 V B Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state REF of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 5 VREFA Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 6 V A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 7 BUF A Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 8 BUF B Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy chain. The pin should be tied low if it is being used in standalone mode. 10 PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). 11 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 15 GND Ground Reference Point for All Circuitry on the Part. 16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock. Rev. B | Page 9 of 28 00472-004 AD5303/AD5313/AD5323 TERMINOLOGY DAC-to-DAC Crosstalk Relative Accuracy or Integral Nonlinearity (INL) This is the glitch impulse transferred to the output of one DAC For the DAC, relative accuracy or integral nonlinearity is a due to a digital code change and subsequent output change of measure of the maximum deviation, in LSB, from a straight the other DAC. This includes both digital and analog crosstalk. line passing through the actual endpoints of the DAC transfer It is measured by loading one of the DACs with a full-scale code function. A typical INL error vs. code plot can be seen in LDAC change (all 0s to all 1s and vice versa) while keeping low Figure 7, Figure 8, and Figure 9. and monitoring the output of the other DAC. The area of the Differential Nonlinearity (DNL) glitch is expressed in nV-s. Differential nonlinearity is the difference between the measured DC Crosstalk change and the ideal 1 LSB change between any two adjacent This is the dc change in the output level of one DAC in response codes. A specified DNL of ±1 LSB maximum ensures monotonic- to a change in the output of the other DAC. It is measured with ity. This DAC is guaranteed monotonic by design. A typical a full-scale output change on one DAC while monitoring the DNL error vs. code plot can be seen in Figure 10, Figure 11, and other DAC. It is expressed in microvolts. Figure 12. Power Supply Rejection Ratio (PSRR) Offset Error This indicates how the output of the DAC is affected by changes This is a measure of the offset error of the DAC and the output in the supply voltage. PSRR is the ratio of the change in VOUT to amplifier. It is expressed as a percentage of the full-scale range. a change in VDD for full-scale output of the DAC. It is measured Gain Error in decibels. VREF is held at 2 V and VDD is varied ±10%. This is a measure of the span error of the DAC. It is the devia- Reference Feedthrough tion in slope of the actual DAC transfer characteristic from the This is the ratio of the amplitude of the signal at the DAC output to ideal expressed as a percentage of the full-scale range. the reference input when the DAC output is not being updated Offset Error Drift LDAC (that is, is high). It is expressed in decibels. This is a measure of the change in offset error with changes in Total Harmonic Distortion (THD) temperature. It is expressed in (ppm of full-scale range)/°C. This is the difference between an ideal sine wave and its Gain Error Drift attenuated version using the DAC. The sine wave is used as This is a measure of the change in gain error with changes in the reference for the DAC and the THD is a measure of the temperature. It is expressed in (ppm of full-scale range)/°C. harmonics present on the DAC output. It is measured in Major-Code Transition Glitch Energy decibels. Major-code transition glitch energy is the energy of the impulse Multiplying Bandwidth injected into the analog output when the code in the DAC register The amplifiers within the DAC have a finite bandwidth. The changes state. It is normally specified as the area of the glitch in multiplying bandwidth is a measure of this. A sine wave on the nV-s and is measured when the digital code is changed by 1 LSB reference (with full-scale code loaded to the DAC) appears on at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . the output. The multiplying bandwidth is the frequency at 00 to 011 . . . 11). which the output amplitude falls to 3 dB below the input. Digital Feedthrough Channel-To-Channel Isolation Digital feedthrough is a measure of the impulse injected into This is a ratio of the amplitude of the signal at the output of one the analog output of the DAC from the digital input pins of the DAC to a sine wave on the reference input of the other DAC. It device, but is measured when the DAC is not being written to is measured in decibels. SYNC ( held high). It is specified in nV-s and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code LDAC change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. Rev. B | Page 10 of 28 AD5303/AD5313/AD5323 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 7. AD5303 Typical INL Plot Figure 10. AD5303 Typical DNL Plot 3 0.6 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 2 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 8. AD5313 Typical INL Plot Figure 11. AD5313 Typical DNL Plot 12 1.0 T = 25°C A T = 25°C A V = 5V DD V = 5V DD 8 0.5 4 0 0 –4 –0.5 –8 –12 –1.0 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE CODE Figure 9. AD5323 Typical INL Plot Figure 12. AD5323 Typical DNL Plot Rev. B | Page 11 of 28 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 00472-008 00472-007 00472-009 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 00472-012 00472-010 00472-011 AD5303/AD5313/AD5323 1.00 T = 25°C A V = 5V DD 0.75 V = 5V DD V = 3V DD 0.50 0.25 MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.50 –0.75 0 –1.00 100 150 200 250 300 350 400 2345 I (µA) DD V (V) REF Figure 13. AD5303 INL and DNL Error vs. V Figure 16. I Histogram with V = 3 V and V = 5 V REF DD DD DD 1.00 5 V = 5V DD V = 3V REF 5V SOURCE 0.75 4 0.50 MAX DNL MAX INL 0.25 3V SOURCE 3 0 2 –0.25 MIN INL MIN DNL –0.50 3V SINK 1 5V SINK –0.75 –1.00 –0 –40 040 80 120 01 23 45 6 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 14. AD5303 INL Error and DNL Error vs. Temperature Figure 17. Source and Sink Current Capability 1.0 600 T = 25°C V = 5V A DD V = 5V V =2V DD REF 500 0.5 400 GAIN ERROR 0 300 200 OFFSET ERROR –0.5 100 –1.0 0 –40 0 40 80 120 ZERO SCALE FULL SCALE TEMPERATURE (°C) Figure 15. Offset Error and Gain Error vs. Temperature Figure 18. Supply Current vs. Code Rev. B | Page 12 of 28 ERROR (LSB) ERROR (%) ERROR (LSB) 00472-013 00472-015 00472-014 I (µA) DD V (V) FREQUENCY OUT 00472-016 00472-017 00472-018 AD5303/AD5313/AD5323 600 V = 5V BOTH DACS IN GAIN-OF-TWO MODE DD T = 25°C REFERENCE INPUTS BUFFERED A 500 CLK CH2 400 –40°C 300 +105°C +25°C 200 CH1 V OUT 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CH1 1V, CH2 5V, TIME BASE = 5µs/DIV V (V) DD Figure 19. Supply Current vs. Supply Voltage Figure 22. Half-Scale Settling (¼ to ¾ Scale Code Change) 1.0 T = 25°C A BOTH DACS IN 0.9 THREE-STATE CONDITION V 0.8 DD 0.7 0.6 0.5 0.4 0.3 +25°C CH1 –40°C 0.2 V A OUT CH2 0.1 +105°C 0 CH1 1V, CH2 1V, TIME BASE = 20µs/DIV 2.7 3.2 3.7 4.2 4.7 5.2 V (V) DD Figure 20. Power-Down Current vs. Supply Voltage Figure 23. Power-On Reset to 0 V 700 T = 25°C T = 25°C A A 600 V 500 OUT CH1 400 V = 5V DD 300 CH3 CLK V = 3V 200 DD 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH1 1V, CH3 5V, TIME BASE = 1µs/DIV V (V) LOGIC Figure 21. Supply Current vs. Logic Input Voltage Figure 24. Exiting Power-Down to Midscale Rev. B | Page 13 of 28 I (µA) I (µA) DD DD I (µA) DD 00472-020 00472-021 00472-019 00472-024 00472-023 00472-022 AD5303/AD5313/AD5323 2.50 2.49 2.48 2.47 500ns/DIV 1µs/DIV Figure 27. DAC-to-DAC Crosstalk Figure 25. AD5323 Major-Code Transition 10 0.10 T = 25°C A V = 5V DD 0 0.05 –10 –20 0 –30 –40 –0.05 –50 –60 –0.10 10 100 1k 10k 100k 1M 10M 0 123 45 V (V) FREQUENCY(Hz) REF Figure 28. Full-Scale Error vs. V (Buffered) Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response) REF Rev. B | Page 14 of 28 (dB) V (V) OUT 00472-025 00472-026 FULL-SCALE ERROR (V) 2mV/DIV 00472-027 00472-028 AD5303/AD5313/AD5323 FUNCTIONAL DESCRIPTION The AD5303/AD5313/AD5323 are dual resistor-string DACs RESISTOR STRING fabricated on a CMOS process with resolutions of 8-/10-/12-bits The resistor string section of the AD5303/AD5313/AD5323 respectively. They contain reference buffers and output buffer is shown in Figure 30. It is simply a string of resistors, each of amplifiers, and are written to via a 3-wire serial interface. They value R. The digital code loaded to the DAC register determines operate from single supplies of 2.5 V to 5.5 V and the output at what node on the string the voltage is tapped off to be fed buffer amplifiers provide rail-to-rail output swing with a slew into the output amplifier. The voltage is tapped off by closing rate of 0.7 V/μs. Each DAC is provided with a separate reference one of the switches connecting the string to the amplifier. input, which may be buffered to draw virtually no current from Because it is a string of resistors, it is guaranteed monotonic. the reference source, or unbuffered to give a reference input range from GND to VDD. The devices have three programmable R power-down modes, in which one or both DACs may be turned R off completely with a high impedance output, or the output may TO OUTPUT R AMPLIFIER be pulled low by an on-chip resistor. DIGITAL-TO-ANALOG The architecture of one DAC channel consists of a reference R buffer and a resistor-string DAC followed by an output buffer R amplifier. The voltage at the V pin provides the reference REF voltage for the DAC. Figure 29 shows a block diagram of the Figure 30. Resistor String DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by DAC REFERENCE INPUTS V ×D REF There is a reference input pin for each of the two DACs. The V = OUT N 2 reference inputs are buffered, but can also be configured as unbuffered. The advantage with the buffered input is the high where: impedance it presents to the voltage source driving it. However, D is the decimal equivalent of the binary code, which is loaded if the unbuffered mode is used, the user can have a reference to the DAC register: voltage as low as GND and as high as V since there is no DD 0 to 255 for AD5303 (8 bits) restriction due to headroom and footroom of the reference 0 to 1023 for AD5313 (10 bits) amplifier. 0 to 4095 for AD5323 (12 bits) N is the DAC resolution. If there is a buffered reference in the circuit (for example, V A REF192), there is no need to use the on-chip buffers of the REF AD5303/AD5313/AD5323. In unbuffered mode, the input SWITCH impedance is still large at typically 180 kΩ per reference input CONTROLLED REFERENCE BY CONTROL for 0 V to V mode and 90 kΩ for 0 V to 2 V mode. REF REF BUFFER LOGIC The buffered/unbuffered option is controlled by the BUF A INPUT DAC RESISTOR and BUF B pins. If a BUF pin is tied high, the reference input V A OUT REGISTER REGISTER STRING is buffered; if tied low, it is unbuffered. OUTPUT BUFFER AMPLIFIER OUTPUT AMPLIFIER Figure 29. Single DAC Channel Architecture The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail, which gives an output range of 0.001 V to VDD − 0.001 V when the reference is VDD. It is capable of driving a load of 2 kΩ in parallel with 500 pF to GND and V . The source and sink capabilities of the output DD amplifier can be seen in Figure 17. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs. Rev. B | Page 15 of 28 00472-029 00472-030 AD5303/AD5313/AD5323 POWER-ON RESET particularly useful in applications where it is important to know The AD5303/AD5313/AD5323 are provided with a power-on the state of the DAC outputs while the device is powering up. reset function, so that they power up in a defined state. The power-on state is with 0V to VREF output range and the output CLEAR FUNCTION (CLR) set to 0 V. CLR The pin is an active low input that, when pulled low, loads Both input and DAC registers are filled with zeros and remain all zeros to both input registers and both DAC registers. This so until a valid write sequence is made to the device. This is enables both analog outputs to be cleared to 0 V. Rev. B | Page 16 of 28 AD5303/AD5313/AD5323 SERIAL INTERFACE After the end of serial data transfer, data is automatically The AD5303/AD5313/AD5323 are controlled over a versatile, transferred from the input shift register to the input register 3-wire serial interface, which operates at clock rates up to of the selected DAC. If SYNC is taken high before the 16th 30 MHz and is compatible with SPI, QSPI, MICROWIRE, falling edge of SCLK, the data transfer is aborted and the input and DSP interface standards. registers are not updated. INPUT SHIFT REGISTER When data has been transferred into both input registers, the The input shift register is 16 bits wide. Data is loaded into DAC registers of both DACs may be simultaneously updated, the device as a 16-bit word under the control of a serial clock LDAC CLR by taking low. is an active low, asynchronous clear input, SCLK. The timing diagram for this operation is shown in that clears the input and DAC registers of both DACs to all 0s. Figure 5. The 16-bit word consists of four control bits followed LOW POWER SERIAL INTERFACE by 8 /10 /12 bits of DAC data, depending on the device type. The first bit loaded is the MSB (Bit 15), which determines whether To reduce the power consumption of the device even further, the data is for DAC A or DAC B. Bit 14 determines the output the interface only powers up fully when the device is being range (0 V to VREF or 0 V to 2 VREF). Bit 13 and Bit 12 control the written to. As soon as the 16-bit control word has been written operating mode of the DAC. to the part, the SCLK and DIN input buffers are powered down. They only power up again following a falling edge of SYNC. Table 6. Control Bits DOUBLE-BUFFERED INTERFACE Power-On Bit Name Function Default The DACs all have double-buffered interfaces consisting of two 15 A/B 0: data written to DAC A N/A banks of registers—input registers and DAC registers. The input 1: data written to DAC B register is connected directly to the input shift register and the 14 GAIN 0: output range of 0 V to V 0 REF digital code is transferred to the relevant input register on com- 1: output range of 0 V to 2 V REF pletion of a valid write sequence. The DAC register contains the 13 PD1 Mode bit 0 digital code used by the resistor string. 12 PD0 Mode bit 0 LDAC Access to the DAC register is controlled by the function. When LDAC is high, the DAC register is latched and the input The remaining bits are DAC data bits, starting with the MSB register may change state without affecting the contents of the and ending with the LSB. The AD5323 uses all 12 bits of DAC DAC register. However, when LDAC is brought low, the DAC data; the AD5313 uses 10 bits and ignores the 2 LSBs. The register becomes transparent and the contents of the input reg- AD5303 uses eight bits and ignores the last four bits. The data ister are transferred to it. format is straight binary, with all 0s corresponding to 0 V output, and all 1s corresponding to full-scale output (VREF − 1 LSB). This is useful if the user requires simultaneous updating of both DAC outputs. The user may write to both input registers The SYNC input is a level-triggered input that acts as a frame LDAC individually and then, by pulsing the input low, both synchronization signal and chip enable. Data can be transferred outputs update simultaneously. SYNC into the device only while is low. To start the serial data SYNC transfer, should be taken low, observing the minimum These parts contain an extra feature whereby the DAC register SYNC SYNC is not updated unless its input register has been updated since to SCLK rising edge setup time, t4. After goes low, the last time that LDAC was brought low. Normally, when LDAC serial data is shifted into the device’s input shift register on the is brought low, the DAC registers are filled with the contents of falling edges of SCLK for 16 clock pulses. Any data and clock the input registers. In the case of the AD5303/AD5313/AD5323, pulses after the 16th are ignored, and no further serial data the part only updates the DAC register if the input register has transfer occurs until SYNC is taken high and low again. been changed since the last time the DAC register was updated, SYNC may be taken high after the falling edge of the 16th SCLK thereby removing unnecessary digital crosstalk. SYNC pulse, observing the minimum SCLK falling edge to rising edge time, t . 7 Rev. B | Page 17 of 28 AD5303/AD5313/AD5323 DB15 (MSB) DB0 (LSB) A/B GAIN PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS Figure 31. AD5303 Input Shift Register Contents DB15 (MSB) DB0 (LSB) A/B GAIN PD1PD0 D9 D8 D7 D6 D5D4 D3 D2 D1D0 XX DATA BITS Figure 32. AD5313 Input Shift Register Contents DB15 (MSB) DB0 (LSB) A/B GAIN PD1PD0 D11 D10 D9 D8 D7D6 D5D4D3 D2D1 D0 DATA BITS Figure 33. AD5323 Input Shift Register Contents Rev. B | Page 18 of 28 00472-033 00472-032 00472-031 AD5303/AD5313/AD5323 POWER-DOWN MODES There are three different power-down options. The output is The AD5303/AD5313/AD5323 have very low power consump- connected internally to GND through either a 1 kΩ resistor or tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW a 100 kΩ resistor, or it is left in a high impedance state (three- with a 5 V supply. Power consumption can be further reduced state). The output stage is illustrated in Figure 34. when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 13 and Bit 12 The bias generator, the output amplifier, the resistor string, and (PD1 and PD0) of the control word. Table 7 shows how the all other associated linear circuitry are shut down when the state of the bits corresponds to the mode of operation of that power-down mode is activated. However, the contents of the particular DAC. registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when Table 7. PD1/PD0 Operating Modes VDD = 3 V (see Figure 24 for a plot). PD1 PD0 Operating Mode The software power-down modes programmed by PD0 and 0 0 Normal operation PD PD1 are overridden by the pin. Taking this pin low puts 0 1 Power-down (1 kΩ load to GND) both DACs into power-down mode simultaneously and both 1 0 Power-down (100 kΩ load to GND) PD outputs are put into a high impedance state. If is not used, 1 1 Power-down (high impedance output) it should be tied high. AMPLIFIER When both bits are set to 0, the DACs work normally with their RESISTOR normal power consumption of 300 μA at 5 V. However, for the V OUT STRING DAC three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also POWER-DOWN RESISTOR CIRCUITRY NETWORK internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the Figure 34. Output Stage During Power-Down output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. Rev. B | Page 19 of 28 00472-034 AD5303/AD5313/AD5323 MICROPROCESSER INTERFACING AD5303/AD5313/AD5323 TO ADSP-2101 AD5303/AD5313/AD5323 TO 80C51/80L51 INTERFACE INTERFACE Figure 35 shows a serial interface between the AD5303/AD5313/ Figure 37 shows a serial interface between the AD5303/ AD5323 and the ADSP-2101. The ADSP-2101 should be set up AD5313/AD5323 and the 80C51/80L51 microcontroller. The to operate in the SPORT transmit alternate framing mode. The setup for the interface is as follows: TXD of the 80C51/80L51 ADSP-2101 sport is programmed through the SPORT control drives SCLK of the AD5303/AD5313/AD5323, while RXD register and should be configured as follows: internal clock SYNC drives the serial data line of the part. The signal is again operation, active-low framing, 16-bit word length. Transmission derived from a bit programmable pin on the port. In this case, is initiated by writing a word to the Tx register after the SPORT port line P3.3 is used. When data is to be transmitted to the has been enabled. AD5303/AD5313/AD5323, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock ADSP-2101 AD5303/ edges occur in the transmit cycle. To load data to the DAC, P3.3 AD5313/ AD5323* is left low after the first eight bits are transmitted and a second SYNC write cycle is initiated to transmit the second byte of data. P3.3 TFS is taken high following the completion of this cycle. The 80C51/ DT DIN 80L51 output the serial data in a format that has the LSB first. SCLK SCLK The AD5303/AD5313/AD5323 require data with MSB as the *ADDITIONAL PINS OMITTED FOR CLARITY first bit received. The 80C51/80L51 transmit routine should Figure 35. AD5303/AD5313/AD5323 to ADSP-2101 Interface take this into account. AD5303/AD5313/AD5323 TO 68HC11/68L11 80C51/80L51* AD5303/ INTERFACE AD5313/ AD5323* Figure 36 shows a serial interface between the AD5303/ P3.3 SYNC AD5313/AD5323 and the 68HC11/68L11 microcontroller. TXD SCLK SCK of the 68HC11/68L11 drives the SCLK of the AD5303/ RXD DIN AD5313/AD5323, while the MOSI output drives the serial data SYNC line (DIN) of the DAC. The signal is derived from a port *ADDITIONAL PINS OMITTED FOR CLARITY. line (PC7). The setup conditions for correct operation of this Figure 37. AD5303/AD5313/AD5323 to 80C51/80L51 Interface interface are as follows: the 68HC11/68L11 should be con- AD5303/AD5313/AD5323 TO MICROWIRE figured so that its CPOL bit is a 0 and its CPHA bit is a 1. INTERFACE When data is being transmitted to the DAC, the SYNC line Figure 38 shows an interface between the AD5303/AD5313/ is taken low (PC7). When the 68HC11/68L11 is configured AD5323 and any MICROWIRE-compatible device. Serial as previously mentioned, data appearing on the MOSI output data is shifted out on the falling edge of the serial clock and is valid on the falling edge of SCK. Serial data from the 68HC11/ is clocked into the AD5303/AD5313/AD5323 on the rising 68L11 is transmitted in 8-bit bytes with only eight falling clock edge of the SK. edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5303/AD5313/ AD5323, PC7 is left AD5303/ MICROWIRE* low after the first eight bits are transferred and a second serial AD5313/ AD5323* write operation is performed to the DAC; PC7 is taken high at CS SYNC the end of this procedure. SK SCLK 68HC11/68L11* AD5303/ SO DIN AD5313/ AD5323* SYNC *ADDITIONAL PINS OMITTED FOR CLARITY. PC7 Figure 38. AD5303/AD5313/AD5323 to MICROWIRE Interface SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 36. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface Rev. B | Page 20 of 28 00472-035 00472-038 00472-037 00472-036 AD5303/AD5313/AD5323 APPLICATIONS INFORMATION 15V TYPICAL APPLICATION CIRCUIT V 0.1µF 10µF S The AD5303/AD5313/AD5323 can be used with a wide range REF195 of reference voltages, especially if the reference inputs are con- OUTPUT V DD figured to be unbuffered, in which case the devices offer a full, V A 1µF OUT GND V A REF one-quadrant multiplying capability over a reference range of V B REF 0 V to VDD. AD5303/AD5313/ AD5323 More typically, the AD5303/AD5313/AD5323 may be used SCLK with a fixed precision reference voltage. Figure 39 shows a DIN V B OUT SYNC typical setup for the AD5303/AD5313/AD5323 when using GND BUF A BUF B an external reference. If the reference inputs are unbuffered, SERIAL the reference input range is from 0 V to V , but if the on-chip DD INTERFACE reference buffers are used, the reference range is reduced. Suit- Figure 40. Using an REF195 as Power and Reference to the able references for 5 V operation are the AD780 and REF192 AD5303/AD5313/AD5323 (2.5 V references). For 2.5 V operation, a suitable external BIPOLAR OPERATION USING THE AD5303/ reference is the REF191, a 2.048 V reference. AD5313/AD5323 V = 2.5V to 5.5V DD The AD5303/AD5313/AD5323 have been designed for single- V DD supply operation, but bipolar operation is also achievable using EXT V OUT V A V A REF OUT REF the circuit shown in Figure 41. The circuit shown has been con- 1µF V B REF AD780/REF192 figured to achieve an output voltage range of −5 V < VOUT < +5 V. AD5303/AD5313/ WITH V = 5V DD OR REF191 WITH AD5323 Rail-to-rail operation at the amplifier output is achievable using V = 2.5V DD SCLK an AD820 or OP295 as the output amplifier. DIN V B OUT 6V to 16V SYNC R2 10kΩ GND BUF A BUF B V = 5V DD 0.1µF 10µF SERIAL +5V INTERFACE R1 10kΩ V S Figure 39. AD5303/AD5313/AD5323 Using External Reference ±5V REF195 V DD AD820/ If an output range of 0 V to V is required when the reference DD OUTPUT OP295 V A/B REF –5V inputs are configured as unbuffered (for example, 0 V to 5 V), GND 1µF the simplest solution is to connect the reference inputs to V . AD5303/AD5313/ DD AD5323 As this supply may not be very accurate and may be noisy, the SCLK AD5303/AD5313/AD5323 can be powered from the reference DIN V A/B OUT SYNC voltage, for example, using a 5 V reference such as the REF195, GND BUF A BUF B as shown in Figure 40. The REF195 outputs a steady supply SERIAL voltage for the AD5303/AD5313/AD5323. The supply current INTERFACE required from the REF195 is 300 μA and approximately 30 μA Figure 41. Bipolar Operation Using the AD5303/AD5313/AD5323 or 60 μA into each of the reference inputs (if unbuffered). This is with no load on the DAC outputs. When the DAC outputs are The output voltage for any input code can be calculated as loaded, the REF195 also needs to supply the current to the follows: loads. The total current required (with a 10 kΩ load on each N V =[(V )× (D / 2 )× (R1+R2) /R1−V × (R2 /R1)] OUT REF REF output) is where: 360 μA + 2(5 V/10 kΩ) = 1.36 mA D is the decimal equivalent of the code loaded to the DAC. The load regulation of the REF195 is typically 2 ppm/mA, which N is the DAC resolution. results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA current V is the reference voltage input, and gain bit = 0, with REF drawn from it. This corresponds to a 0.0007 LSB error at eight V = 5 V REF bits and 0.011 LSB error at 12 bits. R1 = R2 = 10 kΩ and VDD = 5 V, N V = (10×D / 2 )− 5V OUT Rev. B | Page 21 of 28 00472-039 00472-040 00472-041 AD5303/AD5313/AD5323 SCLK OPTO-ISOLATED INTERFACE FOR PROCESS AD5303/ SYNC AD5313/ CONTROL APPLICATIONS DIN DIN AD5323 V SCLK DD The AD5303/AD5313/AD5323 has a versatile 3-wire serial interface making it ideal for generating accurate voltages in V CC 1G ENABLE process control and industrial applications. Due to noise, safety 1Y0 AD5303/ 74HC139 1A SYNC requirements, or distance, it may be necessary to isolate the 1Y1 AD5313/ CODED DIN AD5323 ADDRESS 1Y2 AD5303/AD5313/AD5323 from the controller. This can easily 1B SCLK 1Y3 be achieved by using opto-isolators, which provides isolation DGND in excess of 3 kV. The serial loading structure of the AD5303/ AD5303/ AD5313/AD5323 makes it ideally suited for use in opto-isolated SYNC AD5313/ applications. Figure 42 shows an opto-isolated interface to the DIN AD5323 SCLK AD5303/AD5313/AD5323 where DIN, SCLK, and SYNC are driven from opto-couplers. The power supply to the part also AD5303/ needs to be isolated. This is done by using a transformer. On the SYNC AD5313/ DAC side of the transformer, a 5 V regulator provides the 5 V DIN AD5323 SCLK supply required for the AD5303/AD5313/AD5323. Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System 5V REGULATOR 10µF 0.1µF POWER AD5303/AD5313/AD5323 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR V DD A digitally programmable upper/lower limit detector using 10kΩ the two DACs in the AD5303/AD5313/AD5323 is shown in V DD SCLK SCLK V A Figure 44. The upper and lower limits for the test are loaded REF to DAC A and DAC B, which, in turn, set the limits on the V B REF CMP04. If the signal at the VIN input is not within the pro- AD5303/AD5313/ V DD grammed window, an LED indicates the fail condition. AD5323 10kΩ V A 5V OUT SYNC 0.1µF 10µF SYNC V IN 1kΩ 1kΩ V B OUT FAIL PASS V DD V REF V A REF V V A DD OUT V B REF 10kΩ AD5303/AD5313/ 1/2 PASS/FAIL AD5323 DIN DIN CMP04 SYNC SYNC GND BUF A BUF B DIN DIN V B SCLK SCLK OUT 1/6 74HC05 GND Figure 42. AD5303/AD5313/AD5323 in an Opto-Isolated Interface Figure 44. Window Detector Using AD5303/AD5313/AD5323 DECODING MULTIPLE AD5303/AD5313/AD5323s SYNC The pin on the AD5303/AD5313/AD5323 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices is active at any one time, allowing access to two channels in this 8-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5303/AD5313/AD5323 devices in a system. Rev. B | Page 22 of 28 00472-042 00472-043 00472-044 AD5303/AD5313/AD5323 A continuous SCLK source may be used if it can be arranged COARSE AND FINE ADJUSTMENT USING THE SYNC that is held low for the correct number of clock cycles. AD5303/AD5313/AD5323 Alternatively, a burst clock containing the exact number of The DACs in the AD5303/AD5313/AD5323 can be paired clock cycles may be used and SYNC may be taken high some together to form a coarse and fine adjustment function, as time later. shown in Figure 45. DAC A provides the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio When the transfer to all input registers is complete, a common of R1 and R2 changes the relative effect of the coarse and fine LDAC signal updates all DAC registers and all analog outputs adjustments. With the resistor values and external reference are updated simultaneously. shown, the output amplifier has unity gain for the DAC A AD5303/ output, so the output range is 0 V to 2.5 V − 1 LSB. For 1 68HC11 AD5313/ –3 DAC B, the amplifier has a gain of 7.6 × 10 , giving DAC B 1 AD5323 MOSI DIN (DAC 1) a range equal to 19 mV. SCK SCLK The circuit is shown with a 2.5 V reference, but reference PC7 SYNC voltages up to VDD may be used. The op amps indicated allow PC6 LDAC MISO SDO a rail-to-rail output swing. V = 5V DD DIN R3 R4 AD5303/ 51.2kΩ 900Ω 0.1µF 10µF +5V AD5313/ V 1 IN AD5323 SCLK EXT 2.5V (DAC 2) V DD REF V SYNC OUT R1 V OUT V A V A REF OUT AD820/ LDAC 390Ω 1µF OP295 GND SDO AD5303/AD5313/ AD5323 AD780/REF192 DIN WITH V = 5V DD R2 AD5303/ V B V B REF OUT 51.2kΩ AD5313/ GND 1 AD5323 SCLK (DAC N) SYNC Figure 45. Coarse and Fine Adjustment LDAC SDO DAISY-CHAIN MODE 1 ADDITIONAL PINS OMITTED FOR CLARITY. This mode is used for updating serially connected or standalone Figure 46. Daisy-Chain Mode devices on the rising edge of SYNC. For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin may be used to daisy-chain several devices together and provide serial readback. By connecting the daisy-chain enable (DCEN) pin high, the daisy-chain mode is enabled. It is tied low in standalone mode. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out after the falling edge of SCLK and is valid on the subsequent rising and falling edges. By connect- ing this line to the DIN input on the next DAC in the chain, a multiDAC interface is constructed. Sixteen clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. When the serial transfer to all SYNC devices is complete, should be taken high. This prevents any further data from being clocked into the input shift register. Rev. B | Page 23 of 28 00472-045 00472-046 AD5303/AD5313/AD5323 t 1 SCLK t 2 t 14 t t 3 8 t 4 SYNC t t 15 6 t 5 DIN DB15 DB0 DB15 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC (N+1) DB15 DB0 SDO UNDEFINED INPUT WORD FOR DAC N SCLK t 13 V IH SDO V IL t 12 Figure 47. Daisy-Chaining Timing Diagram (ESI), like the common ceramic types that provide a low POWER SUPPLY BYPASSING AND GROUNDING impedance path to ground at high frequencies to handle In any circuit where accuracy is important, careful considera- transient currents due to internal logic switching. tion of the power supply and ground return layout helps to The power supply lines of the AD5303/AD5313/AD5323 should ensure the rated performance. The printed circuit board on use as large a trace as possible to provide low impedance paths which the AD5303/AD5313/AD5323 are mounted should be designed so that the analog and digital sections are separated and reduce the effects of glitches on the power supply line. Fast and confined to certain areas of the board. If the AD5303/ switching signals such as clocks should be shielded with digital AD5313/AD5323 are in a system where multiple devices ground to avoid radiating noise to other parts of the board, and require an AGND-to-DGND connection, the connection should never be run near the reference inputs. Avoid crossover should be made at one point only. The star ground point of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces should be established as close as possible to the AD5303/ the effects of feedthrough through the board. A microstrip AD5313/AD5323. The AD5303/AD5313/AD5323 should technique is by far the best, but is not always possible with a have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally double-sided board. In this technique, the component side of right up against the device. Use 10 μF capacitors that are of the the board is dedicated to the ground plane while signal traces tantalum bead type. The 0.1 μF capacitor should have low are placed on the solder side. effective series resistance (ESR) and effective series inductance Rev. B | Page 24 of 28 00472-047 AD5303/AD5313/AD5323 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD5303ARU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5303ARU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5303ARUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5303BRU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5303BRU-REEL –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5303BRU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5303BRUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5303BRUZ-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313ARU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313ARU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5313ARUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRU-REEL –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5313BRUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323ARU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323ARU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5323ARUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5323ARUZ-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU-REEL –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5323BRUZ –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5323BRUZ-REEL –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 AD5323BRUZ-REEL7 –40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 Z = RoHS Compliant Part. Rev. B | Page 25 of 28 AD5303/AD5313/AD5323 NOTES Rev. B | Page 26 of 28 AD5303/AD5313/AD5323 NOTES Rev. B | Page 27 of 28 AD5303/AD5313/AD5323 NOTES ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00472-0-6/07(B) Rev. B | Page 28 of 28