ANALOG DEVICES AD5311

2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs AD5301/AD5311/AD5321 FEATURES GENERAL DESCRIPTION 1 AD5301: buffered voltage output 8-bit DAC The AD5301/AD5311/AD5321 are single 8-/10-/12-bit, buff- AD5311: buffered voltage output 10-bit DAC ered, voltage-output DACs that operate from a single 2.5 V to AD5321: buffered voltage output 12-bit DAC 5.5 V supply, consuming 120 μA at 3 V. The on-chip output 6-lead SOT-23 and 8-lead MSOP packages amplifier allows rail-to-rail output swing with a slew rate of 2 Micropower operation: 120 μA @ 3 V 0.7 V/μs. It uses a 2-wire (I C-compatible) serial interface that 2 2-wire (I C®-compatible) serial interface operates at clock rates up to 400 kHz. Multiple devices can share Data readback capability the same bus. 2.5 V to 5.5 V power supply The reference for the DAC is derived from the power supply Guaranteed monotonic by design over all codes inputs and thus gives the widest dynamic output range. These Power-down to 50 nA @ 3 V parts incorporate a power-on reset circuit, which ensures that Reference derived from power supply the DAC output powers up to 0 V and remains there until a Power-on reset to 0 V valid write takes place. The parts contain a power-down feature On-chip rail-to-rail output buffer amplifier that reduces the current consumption of the device to 50 nA at 3 power-down functions 3 V and provides software-selectable output loads while in power-down mode. APPLICATIONS Portable battery-powered instruments The low power consumption in normal operation makes these Digital gain and offset adjustment DACs ideally suited to portable battery-operated equipment. The Programmable voltage and current sources power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V, Programmable attenuators reducing to 1 μW in all power-down modes. 1 Protected by U.S. Patent No. 5684481. FUNCTIONAL BLOCK DIAGRAM V DD AD5301/AD5311/AD5321 SCL REF SDA DAC 8-/10-/12-BIT BUFFER V INTERFACE OUT REGISTER DAC LOGIC A0 A1* POWER-DOWN LOGIC RESISTOR NETWORK POWER-ON RESET GND PD* *AVAILABLE ON 8-LEAD VERSION ONLY Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00927-001 AD5301/AD5311/AD5321 TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier........................................................................ 13 Applications....................................................................................... 1 Power-On Reset.......................................................................... 13 General Description ......................................................................... 1 Serial Interface ................................................................................ 14 Functional Block Diagram .............................................................. 1 2-Wire Serial Bus........................................................................ 14 Revision History ............................................................................... 2 Input Shift Register .................................................................... 14 Specifications..................................................................................... 3 Write Operation.......................................................................... 15 AC Characteristics........................................................................ 5 Read Operation........................................................................... 16 Timing Characteristics ................................................................ 5 Power-Down Modes .................................................................. 17 Absolute Maximum Ratings............................................................ 6 Application Notes........................................................................... 18 ESD Caution.................................................................................. 6 Using REF19x as a Power Supply ............................................. 18 Pin Configurations and Function Descriptions ........................... 7 Bipolar Operation Using the AD5301/AD5311/AD5321..... 18 Terminology ...................................................................................... 8 Multiple Devices on One Bus ................................................... 18 Typical Performance Characteristics ............................................. 9 CMOS Driven SCL and SDA Lines.......................................... 18 Theory of Operation ...................................................................... 13 Power Supply Decoupling ......................................................... 19 Digital-to-Analog ....................................................................... 13 Outline Dimensions....................................................................... 20 Resistor String............................................................................. 13 Ordering Guide .......................................................................... 21 REVISION HISTORY 3/07—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 4............................................................................ 6 Changes to Figure 4 Caption........................................................... 7 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 11/03—Rev. 0 to Rev. A Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 15 7/99—Revision 0: Initial Version Rev. B | Page 2 of 24 AD5301/AD5311/AD5321 SPECIFICATIONS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Version 2 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5301 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes. AD5311 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes. AD5321 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed monotonic by design over all codes. Zero-Code Error 5 20 mV All zeros loaded to DAC, see Figure 12. Full-Scale Error ±0.15 ±1.25 % of FSR All ones loaded to DAC, see Figure 12. Gain Error ±0.15 ±1 % of FSR 5 Zero-Code Error Drift –20 μV/°C 5 Gain Error Drift −5 ppm of FSR/°C 5 OUTPUT CHARACTERISTICS Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive capability of the output amplifier. Maximum Output Voltage VDD − 0.001 V DC Output Impedance 1 Ω Short-Circuit Current 50 mA VDD = 5 V. 20 mA V = 3 V. DD Power-Up Time 2.5 μs Coming out of power-down mode. V = 5 V. DD 6 μs Coming out of power-down mode. VDD = 3 V. 5 LOGIC INPUTS (A0, A1, PD) Input Current ±1 μA Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%. 0.6 V V = 3 V ± 10%. DD 0.5 V V = 2.5 V. DD Input High Voltage, V 2.4 V V = 5 V ± 10%. IH DD 2.1 V VDD = 3 V ± 10%. 2.0 V VDD = 2.5 V. Pin Capacitance 3 pF 5 LOGIC INPUTS (SCL, SDA) Input High Voltage, VIH 0.7 × VDD VDD + 0.3 V Input Low Voltage, VIL −0.3 +0.3 × VDD V Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD. Input Hysteresis, V 0.05 × V V HYST DD Input Capacitance, C 6 pF IN 6 Glitch Rejection 50 ns Pulse width of spike suppressed. Rev. B | Page 3 of 24 AD5301/AD5311/AD5321 1 B Version 2 Parameter Min Typ Max Unit Conditions/Comments 5 LOGIC OUTPUT (SDA) Output Low Voltage, V 0.4 V I = 3 mA. OL SINK 0.6 V I = 6 mA. SINK Three-State Leakage ±1 μA Current Three-State Output 6 pF Capacitance POWER REQUIREMENTS V 2.5 5.5 V I specification is valid for all DAC codes. DD DD IDD (Normal Mode) DAC active and excluding load current. VDD = 4.5 V to 5.5 V 150 250 μA VIH = VDD and VIL = GND. VDD = 2.5 V to 3.6 V 120 220 μA VIH = VDD and VIL = GND. I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 μA V = V and V = GND. DD IH DD IL V = 2.5 V to 3.6 V 0.05 1 μA V = V and V = GND. DD IH DD IL 1 Temperature range is as follows: B Version: −40°C to +105°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000). 5 Guaranteed by design and characterization, not production tested. 6 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. Rev. B | Page 4 of 24 AD5301/AD5311/AD5321 1 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 2 B Version 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VDD = 5 V AD5301 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5311 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300) AD5321 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Change Glitch Impulse 12 nV-s 1 LSB change around major carry Digital Feedthrough 0.3 nV-s 1 See the Terminology section. 2 Temperature range for the B Version is as follows: –40°C to +105°C. 3 Guaranteed by design and characterization, not production tested. 1 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Limit at TMIN, TMAX 2 Parameter (B Version) Unit Conditions/Comments f 400 kHz max SCL clock frequency SCL t 2.5 μs min SCL cycle time 1 t 0.6 μs min t , SCL high time 2 HIGH t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD,STA, start/repeated start condition hold time t 100 ns min t data setup time 5 SU,DAT, 3 t 0.9 μs max t , data hold time 6 HD,DAT 0 μs min t7 0.6 μs min tSU,STA, setup time for repeated start t8 0.6 μs min tSU,STO, stop condition setup time t9 1.3 μs min tBUF, bus free time between a stop condition and a start condition 4 t 300 ns max t , rise time of both SCL and SDA when receiving 10 R 0 ns min May be CMOS driven 4 t 250 ns max t , fall time of SDA when receiving 11 F 4 300 ns max tF, fall time of both SCL and SDA when transmitting 5 20 + 0.1Cb ns min Cb 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 Guaranteed by design and characterization, not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 tR and tF measured between 0.3 VDD and 0.7 VDD. 5 C is the total capacitance of one bus line in picofarads. b SDA t t t 11 t 9 3 4 t 10 SCL t 2 t t t 5 t t t 4 6 7 1 8 START REPEATED STOP CONDITION START CONDITION CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. B | Page 5 of 24 00927-002 AD5301/AD5311/AD5321 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute SCL, SDA to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect PD, A1, A0 to GND −0.3 V to VDD + 0.3 V device reliability. VOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range ESD CAUTION Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C SOT-23 Package Power Dissipation (TJ max − TA)/θJA θ Thermal Impedance 229.6°C/W JA MSOP Package Power Dissipation (T max – T )/θ J A JA θJA Thermal Impedance 206°C/W Lead Temperature JEDEC Industry Standard Soldering J-STD-020 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 6 of 24 AD5301/AD5311/AD5321 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V GND 1 6 DD V AD5301/ DD 1 8 GND AD5301/ AD5311/ AD5311/ A0 2 7 SDA SDA 2 5 A0 AD5321 AD5321 3 6 A1 SCL TOP VIEW TOP VIEW (Not to Scale) V OUT 4 5 PD (Not to Scale) 3 4 V SCL OUT Figure 3. 8-Lead MSOP Figure 4. 6-Lead SOT-23 (RM-8) Pin Configuration (RJ-6) Pin Configuration Table 5. Pin Function Descriptions MSOP SOT-23 Pin No. Pin No. Mnemonic Description 1 6 V DD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled with a 10 μF in parallel with a 0.1 μF capacitor to GND. 2 5 A0 Address Input. Sets the least significant bit of the 7-bit slave address. 3 N/A A1 Address Input. Sets the second least significant bit of the 7-bit slave address. 4 4 VOUT Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. 5 N/A PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down option. The DAC output goes three-state and the current consumption of the part drops to 50 nA @ 3 V (200 nA @ 5 V). 6 3 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift 2 register. Clock rates of up to 400 kbps can be accommodated in the I C-compatible interface. SCL may be CMOS/TTL driven. 7 2 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register during the write cycle and to read back one or two bytes of data (one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven. 8 1 GND Ground Reference Point for All Circuitry on the Part. Rev. B | Page 7 of 24 00927-004 00927-003 AD5301/AD5311/AD5321 TERMINOLOGY Gain Error Relative Accuracy Gain error is a measure of the span error of the DAC. It is the For the DAC, relative accuracy or integral nonlinearity (INL) is deviation in slope of the actual DAC transfer characteristic from a measure of the maximum deviation, in LSBs, from a straight the ideal expressed as a percentage of the full-scale range. line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 5 to Zero-Code Error Drift Figure 7. Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the Gain Error Drift ideal 1 LSB change between any two adjacent codes. A specified Gain error drift is a measure of the change in gain error with differential nonlinearity of ±1 LSB maximum ensures monotonic- changes in temperature. It is expressed in (ppm of full-scale ity. These DACs are guaranteed monotonic by design over all range)/°C. codes. Typical DNL vs. code plots can be seen in Figure 8 to Major Code Transition Glitch Energy Figure 10. Major code transition glitch energy is the energy of the impulse Zero-Code Error injected into the analog output when the code in the DAC register Zero-code error is a measure of the output error when zero changes state. It is normally specified as the area of the glitch in code (0x00) is loaded to the DAC register. Ideally, the output nV-s and is measured when the digital code is changed by 1 LSB should be 0 V. The zero-code error of the AD5301/AD5311/ at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 AD5321 is always positive because the output of the DAC to 011 . . . 11). cannot go below 0 V, due to a combination of the offset errors Digital Feedthrough in the DAC and output amplifier. It is expressed in millivolts, Digital feedthrough is a measure of the impulse injected into see Figure 12. the analog output of the DAC from the digital input pins of the Full-Scale Error (FSR) device, but is measured when the DAC is not being written to. It Full-scale error is a measure of the output error when full is specified in nV-s and is measured with a full-scale change on scale is loaded to the DAC register. Ideally, the output should the digital input pins, that is, from all 0s to all 1s and vice versa. be VDD – 1 LSB. Full-scale error is expressed in percent of FSR. A plot can be seen in Figure 12. Rev. B | Page 8 of 24 AD5301/AD5311/AD5321 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 255 0 50 100 150 200 255 CODE CODE Figure 5. AD5301 Typical INL Plot Figure 8. AD5301 Typical DNL Plot 3 0.6 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 2 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 0 200 400 600 800 1023 0 200 400 600 800 1023 CODE CODE Figure 6. AD5311 Typical INL Plot Figure 9. AD5311 Typical DNL Plot 3 1.0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 2 0.5 1 0 0 –4 –0.5 –8 –12 –1.0 0 1000 2000 3000 4095 0 1000 2000 3000 4095 CODE CODE Figure 7. AD5321 Typical INL Plot Figure 10. AD5321 Typical DNL Plot Rev. B | Page 9 of 24 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 00927-005 00927-007 00927-006 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 00927-010 00927-009 00927-008 AD5301/AD5311/AD5321 1.00 5 V = 5V DD 0.75 5V SOURCE 4 0.50 MAX DNL MAX INL 0.25 3 3V SOURCE 0 2 –0.25 3V SINK MIN DNL –0.50 5V SINK MIN INL 1 –0.75 –1.00 –0 –40 0 40 80 120 0369 12 15 TEMPERATURE (°C) I (mA) Figure 14. Source and Sink Current Capability Figure 11. AD5301 INL Error and DNL Error vs. Temperature 200 10 T = 25°C V = 5V A DD 180 8 160 6 ZERO CODE 140 4 V = 5V VDD = 5V DD 120 2 100 0 V = 3V 80 DD –2 60 –4 FULL SCALE 40 –6 20 –8 –10 0 ZERO SCALE FULL SCALE –40 –20 0 20 40 60 80 100 CODE TEMPERATURE (°C) Figure 15. Supply Current vs. Code Figure 12. Zero-Code Error and Full-Scale Error vs. Temperature 200 150 V = 3V DD V = 5V –40°C DD 100 +105°C +25°C 50 0 80 100 120 140 160 190 200 2.7 3.2 3.7 4.2 4.7 5.2 V (V) I (µA) DD DD Figure 16. Supply Current vs. Supply Voltage Figure 13. I Histogram with V = 3 V and V = 5 V DD DD DD Rev. B | Page 10 of 24 ERROR (LSB) ERROR (mV) FREQUENCY (Hz) 00927-013 00927-012 00927-011 V (V) I (µA) OUT I (µA) DD DD 00927-016 00927-015 00927-014 AD5301/AD5311/AD5321 1.0 V = 5V DD T = 25°C A 0.8 LOAD = 2kΩ AND 200pF TO GND 0.6 0.4 1 V OUT –40°C +25°C 0.2 +105°C 0 2.7 3.2 3.7 4.2 4.7 5.2 V (V) DD CH1 1V, TIME BASE = 5µs/DIV Figure 17. Power-Down Current vs. Supply Voltage Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Charge) 300 T = 25°C A T = 25°C A 250 V DD 200 V = 5V DD INCREASING 150 DECREASING 100 V = 3V DD CH1 50 V OUT CH2 0 0 1.0 2.0 3.0 4.0 5.0 V (V) LOGIC CH1 1V, CH2 1V, TIME BASE = 20µs/DIV Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Figure 20. Power-On Reset to 0 V Increasing and Decreasing Rev. B | Page 11 of 24 I (µA) DD I (µA) DD 00927-017 00927-018 00927-019 00927-020 AD5301/AD5311/AD5321 2.440 T = 25°C V = 5V A DD 2.445 V OUT CH1 2.450 CH2 CLK 2.455 1ns/DIV CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 21. Exiting Power-Down to Midscale Figure 23. Digital Feedthrough 2.50 2.49 2.48 2.47 1µs/DIV Figure 22. Major-Code Transition Rev. B | Page 12 of 24 V (V) OUT 00927-021 00927-022 V (V) OUT 00927-023 AD5301/AD5311/AD5321 THEORY OF OPERATION The AD5301/AD5311/AD5321 are single resistor-string DACs RESISTOR STRING fabricated on a CMOS process with resolutions of 8/10/12 bits, The resistor string section is shown in Figure 25. It is simply respectively. Data is written via a 2-wire serial interface. The a string of resistors, each with a value of R. The digital code devices operate from single supplies of 2.5 V to 5.5 V and the loaded to the DAC register determines at what node on the output buffer amplifiers provide rail-to-rail output swing with string the voltage is tapped off to be fed into the output ampli- a slew rate of 0.7 V/μs. The power supply (V ) acts as the DD fier. The voltage is tapped off by closing one of the switches reference to the DAC. The AD5301/AD5311/AD5321 have connecting the string to the amplifier. Because it is a string three programmable power-down modes, in which the DAC of resistors, it is guaranteed monotonic over all codes. can be turned off completely with a high impedance output, or the output can be pulled low by an on-chip resistor (see the R Power-Down Modes section). R TO OUTPUT R DIGITAL-TO-ANALOG AMPLIFIER The architecture of the DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the VDD pin provides the reference voltage for the DAC. Figure 24 R shows a block diagram of the DAC architecture. Since the input R coding to the DAC is straight binary, the ideal output voltage is given by Figure 25. Resistor String V × D DD V = OUTPUT AMPLIFIER OUT N 2 The output buffer amplifier is capable of generating output volt- where: ages to within 1 mV from either rail, which gives an output range N = DAC resolution of 0.001 V to VDD − 0.001 V. It is capable of driving a load of D = decimal equivalent of the binary code that is loaded to the 2 kΩ to GND and V , in parallel with 500 pF to GND. The DD DAC register: source and sink capabilities of the output amplifier can be seen in Figure 14. 0–255 for AD5301 (8 bits) 0–1023 for AD5311 (10 bits) The slew rate is 0.7 V/μs with a half-scale settling time to 0–4095 for AD5321 (12 bits) ±0.5 LSB (at 8 bits) of 6 μs with the output unloaded. V DD POWER-ON RESET REF(+) OUTPUT BUFFER The AD5301/AD5311/AD5321 are provided with a power-on AMPLIFIER DAC RESISTOR reset function, ensuring that they power up in a defined state. V OUT REGISTER STRING The DAC register is filled with zeros and remains so until a REF(–) valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state GND of the DAC output while the device is powering up. Figure 24. DAC Channel Architecture Rev. B | Page 13 of 24 00927-024 00927-025 AD5301/AD5311/AD5321 SERIAL INTERFACE SCL is high. In write mode, the master pulls the SDA line 2-WIRE SERIAL BUS th high during the 10 clock pulse to establish a stop condi- 2 The AD5301/AD5311/AD5321 are controlled via an I C- tion. In read mode, the master issues a no acknowledge for compatible serial bus. The DACs are connected to this bus the ninth clock pulse (that is, the SDA line remains high). as slave devices (no clock is generated by the AD5301/AD5311/ th The master then brings the SDA line low before the 10 AD5321 DACs). th clock pulse and then high during the 10 clock pulse to The AD5301/AD5311/AD5321 has a 7-bit slave address. In establish a stop condition. the case of the 6-lead device, the six MSBs are 000110 and the In the case of the AD5301/AD5311/AD5321, a write operation LSB is determined by the state of the A0 pin. In the case of the contains two bytes whereas a read operation may contain one or 8-lead device, the five MSBs are 00011 and the two LSBs are two bytes. See Figure 29 to Figure 34 for a graphical explanation determined by the state of the A0 and A1 pins. A1 and A0 of the serial interface. allow the user to use up to four of these DACs on one bus. A repeated write function gives the user flexibility to update the The 2-wire serial bus protocol operates as follows: DAC output a number of times after addressing the part only 1. The master initiates data transfer by establishing a start once. During the write cycle, each multiple of two data bytes condition, which is when a high-to-low transition on the updates the DAC output. For example, after the DAC acknowl- SDA line occurs while SCL is high. The following byte is edges its address byte, and receives two data bytes; the DAC the address byte that consists of the 7-bit slave address output updates after the two data bytes, if another two data W followed by an R/ bit (this bit determines whether data bytes are written to the DAC while it is still the addressed slave is read from or written to the slave device). device. These data bytes also cause an output update. A repeat read of the DAC is also allowed. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the INPUT SHIFT REGISTER ninth clock pulse (this is termed the acknowledge bit). At The input shift register is 16 bits wide. Figure 26, Figure 27, this stage, all other devices on the bus remain idle while the and Figure 28 illustrate the contents of the input shift register selected device waits for data to be written to or read from for each part. Data is loaded into the device as a 16-bit word W its serial register. If the R/ bit is high, the master reads under the control of a serial clock input, SCL. The timing W from the slave device. However, if the R/ bit is low, the diagram for this operation is shown in Figure 2. The 16-bit master writes to the slave device. word consists of four control bits followed by 8/10/12 bits of data, depending on the device type. MSB (Bit 15) is loaded first. 2. Data is transmitted over the serial bus in sequences of nine The first two bits are don’t cares. The next two are control bits clock pulses (eight data bits followed by an acknowledge that control the mode of operation of the device (normal mode bit). The transitions on the SDA line must occur during or any one of three power-down modes). See the Power-Down the low period of SCL and remain stable during the high Modes section for a complete description. The remaining bits period of SCL. are left justified DAC data bits, starting with the MSB and 3. When all data bits have been read or written, a stop con- ending with the LSB. dition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while DB15 (MSB) DB0 (LSB) XX PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 XXXX DATA BITS Figure 26. AD5301 Input Shift Register Contents DB15 (MSB) DB0 (LSB) X X PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS Figure 27. AD5311 Input Shift Register Contents DB15 (MSB) DB0 (LSB) X X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS Figure 28. AD5321 Input Shift Register Contents Rev. B | Page 14 of 24 00927-038 00927-037 00927-026 AD5301/AD5311/AD5321 WRITE OPERATION SDA low. This address byte is followed by the 16-bit word in the When writing to the AD5301/AD5311/AD5321 DACs, the form of two control bytes. The write operations for the three user must begin with an address byte, after which the DAC DACs are shown in Figure 29 to Figure 31. acknowledges that it is prepared to receive data by pulling SCL SDA 0A 00 111*A0 R/W X X PD1 PD0 D7 D6 D5 D4 START ACK ACK ADDRESS BYTE MOST SIGNIFICANT CONTROL BYTE COND BY BY BY AD5301 AD5301 MASTER SCL SDA D3 D2 D1 D0 X X X X ACK STOP LEAST SIGNIFICANT CONTROL BYTE BY COND AD5301 BY *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. MASTER Figure 29. AD5301 Write Sequence SCL SDA0A 00 111*A0 R/W X X PD1 PD0 D9 D8 D7 D6 START ACK ACK ADDRESS BYTE MOST SIGNIFICANT CONTROL BYTE COND BY BY BY AD5311 AD5311 MASTER SCL SDA D5 D4 D3 D2 D1 D0 X X ACK STOP LEAST SIGNIFICANT CONTROL BYTE BY COND AD5311 BY *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. MASTER Figure 30. AD5311 Write Sequence SCL SDA 0A 00 111*A0 R/W X X PD1 PD0 D11 D10 D9 D8 START ACK ACK ADDRESS BYTE MOST SIGNIFICANT CONTROL BYTE COND BY BY BY AD5321 AD5321 MASTER SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP LEAST SIGNIFICANT CONTROL BYTE BY COND AD5321 BY *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. MASTER Figure 31. AD5321 Write Sequence Rev. B | Page 15 of 24 00927-029 00927-028 00927-027 AD5301/AD5311/AD5321 READ OPERATION the eight data bits in the DAC register. However, in the case When reading data back from the AD5301/AD5311/AD5321 of the AD5311 and AD5321, the readback consists of two bytes DACs, the user must begin with an address byte after which that contain both the data and the power-down mode bits. The the DAC acknowledges that it is prepared to transmit data by read operations for the three DACs are shown in Figure 32 to pulling SDA low. There are two different read operations. In the Figure 34. case of the AD5301, the readback is a single byte that consists of SCL SDA A1* A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 00 0 1 1 START ACK NO ACK STOP COND ADDRESS BYTE BY DATA BYTE BY COND BY AD5301 MASTER BY MASTER MASTER *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. Figure 32. AD5301 Readback Sequence SCL SDA 0A 00 111*A0R/W X X PD1 PD0 D9 D8 D7 D6 START ACK ACK ADDRESS BYTE MOST SIGNIFICANT BYTE COND BY BY BY AD5311 AD5311 MASTER SCL D5 D4 D3 D2 D1 D0 X X SDA NO ACK STOP LEAST SIGNIFICANT CONTROL BYTE BY COND MASTER BY MASTER *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. Figure 33. AD5311 Readback Sequence SCL 0 00 1 1 A1* A0 R/W X X PD1 PD0 D11 D10 D9 D8 SDA START ACK STOP MOST SIIGNIFICANT BYTE COND ADDRESS BYTE BY COND BY AD5321 BY MASTER MASTER SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 NO ACK STOP LEAST SIGNIFICANT BYTE BY COND MASTER BY MASTER *THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION. Figure 34. AD5321 Readback Sequence Rev. B | Page 16 of 24 00927-031 00927-032 00927-030 AD5301/AD5311/AD5321 output stage is also internally switched from the output of the POWER-DOWN MODES amplifier to a resistor network of known values. This has the The AD5301/AD5311/AD5321 have very low power consump- advantage that the output impedance of the part is known while tion, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW the part is in power-down mode and provides a defined input with a 5 V supply. Power consumption can be further reduced condition for whatever is connected to the output of the DAC when the DAC is not in use by putting it into one of three amplifier. There are three different options. The output is con- power-down modes, which are selected by Bit 13 and Bit 12 (PD1 nected internally to GND through a 1 kΩ resistor, a 100 kΩ and PD0) of the control word. Table 6 shows how the state of resistor, or it is left three-stated. Resistor tolerance = ±20%. the bits corresponds to the mode of operation of the DAC. The output stage is illustrated in Figure 35. AMPLIFIER Table 6. PD1 and PD0 Operating Modes REGISTER V PD1 PD0 Operating Mode OUT STRING DAC 0 0 Normal operation 0 1 Power-down (1 kΩ load to GND) POWER-DOWN 1 0 Power-down (100 kΩ load to GND) CIRCUITRY 1 1 Power-down (three-state output) RESISTOR NETWORK The software power-down modes programmed by PD1 and PD PD0 may be overridden by the pin on the 8-lead version. Figure 35. Output Stage During Power-Down Taking this pin low puts the DAC into three-state power-down The bias generator, the output amplifier, the resistor string, and mode. If PD is not used, tie it high. all other associated linear circuitry are shut down when the When both bits are set to 0, the DAC works normally with its power-down mode is activated. However, the contents of the normal power consumption of 150 μA at 5 V, while for the three DAC register are unchanged when in power-down. The time to power-down modes, the supply current falls to 200 nA at 5 V exit power-down is typically 2.5 μs for VDD = 5 V and 6 μs when (50 nA at 3 V). Not only does the supply current drop, but the VDD = 3 V (see Figure 21). Rev. B | Page 17 of 24 00927-033 AD5301/AD5311/AD5321 APPLICATIONS NOTES R2 USING REF19x AS A POWER SUPPLY 10kΩ Because the supply current required by the AD5301/AD5311/ +5V R1 AD5321 is extremely low, the user has an alternative option to 10kΩ employ a REF195 voltage reference (for 5 V) or a REF193 voltage ±5V +5V AD820/ reference (for 3 V) to supply the required voltage to the part OP295 AD5301/ –5V (see Figure 36). AD5311/ AD5321 V V DD OUT 5V REF195 10µF 0.1µF 150µA TYP V DD V = 0V TO 5V OUT 2-WIRE SDA AD5301/ 2-WIRE SERIAL SERIAL SCL AD5311/ INTERFACE INTERFACE AD5321 Figure 37. Bipolar Operation with the AD5301/AD5311/AD5321 The output voltage for any input code can be calculated as Figure 36. REF195 as Power Supply to AD5301/AD5311/AD5321 N VOUT = [(VDD × (D/2 ) × R1 + R2)/R1) − VDD × (R2/R1)] This is especially useful if the power supply is quite noisy or if where: the system supply voltages are at some value other than 5 V or D is the decimal equivalent of the code loaded to the DAC. 3 V (for example, 15 V). The REF193/REF195 output a steady N is the DAC resolution. supply voltage for the AD5301/AD5311/AD5321. If the low dropout REF195 is used, it needs to supply a current of 150 μA With VDD = 5 V, R1 = R2 = 10 kΩ, to the AD5301/AD5311/AD5321. This is with no load on the N VOUT = (10 × D/2 ) − 5 V output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. MULTIPLE DEVICES ON ONE BUS Figure 38 shows four AD5301 devices on the same serial bus. The total current required (with a 2 kΩ load on the DAC output Each has a different slave address since the state of their A0 and full scale loaded to the DAC) is and A1 pins is different. This allows each DAC to be written to 150 μA + (5 V/2 kΩ) = 2.65 mA or read from independently. The master device output bus line 2 The load regulation of the REF195 is typically 2 ppm/mA, drivers are open-drain, pull-downs in a fully I C-compatible which results in an error of 5.3 ppm (26.5 μV) for the 2.65 mA interface. current drawn from it. This corresponds to a 0.00136 LSB error. CMOS DRIVEN SCL AND SDA LINES BIPOLAR OPERATION USING THE AD5301/ For single or multisupply systems where the minimum SCL AD5311/AD5321 swing requirements allow it, a CMOS SCL driver may be used, The AD5301/AD5311/AD5321 has been designed for single- and the SCL pull-up resistor can be removed, making the SCL supply operation, but a bipolar output range is also possible bus line fully CMOS compatible. This reduces power consump- using the circuit in Figure 37. The circuit below gives an output tion in both the SCL driver and receiver devices. The SDA line 2 voltage range of ±5 V. Rail-to-rail operation at the amplifier remains open-drain, I C compatible. output is achievable using an AD820 or an OP295 as the output Further changes, in the SDA line driver, may be made to make amplifier. the system more CMOS compatible and save more power. As the SDA line is bidirectional, it cannot be made fully CMOS compatible. A switched pull-up resistor can be combined with a CMOS device with an open-circuit (three-state) input such that the CMOS SDA driver is enabled during write cycles and 2 I C mode is enabled during shared cycles, that is, readback, acknowledge bit cycles, start conditions, and stop conditions. Rev. B | Page 18 of 24 00927-034 00927-035 AD5301/AD5311/AD5321 a ceramic 0.1 μF capacitor provides a sufficient low impedance POWER SUPPLY DECOUPLING path to ground at high frequencies. The power supply lines of In any circuit where accuracy is important, careful considera- the AD5301/AD5311/AD5321 should use as large a trace as tion of the power supply and ground return layout helps to possible to provide low impedance paths. A ground line routed ensure the rated performance. The AD5301/AD5311/AD5321 between the SDA and SCL lines helps reduce crosstalk between should be decoupled to GND with 10 μF in parallel with a them. This is not required on a multilayer board as there is a 0.1 μF capacitor, located as close to the package as possible. ground plane layer, but separating the lines helps. The 10 μF capacitor should be the tantalum bead type, while 5V R R P P SDA MASTER SCL V V V DD DD DD SDA SCL SDA SCL SDA SCL SDA SCL A1 A1 A1 A1 V V V V OUT OUT OUT OUT A0 A0 A0 A0 AD5301 AD5301 AD5301 AD5301 Figure 38. Multiple AD5301 Devices on One Bus Rev. B | Page 19 of 24 00927-036 AD5301/AD5311/AD5321 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 INDICATOR 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.60 0.50 0.15 MAX 4° 0.45 SEATING 0.30 0° 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 39. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.38 0.23 0° 0.40 0.00 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 40. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. B | Page 20 of 24 AD5301/AD5311/AD5321 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD5301BRM –40°C to +105°C 8-Lead MSOP RM-8 D8B AD5301BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 D8B AD5301BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D8B 1 AD5301BRMZ –40°C to +105°C 8-Lead MSOP RM-8 D8B# 1 AD5301BRMZ-REEL –40°C to +105°C 8-Lead MSOP RM-8 D8B# 1 AD5301BRMZ-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D8B# AD5301BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B AD5301BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B AD5301BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B 1 AD5301BRTZ-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B# 1 AD5301BRTZ-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B# 1 AD5301BRTZ-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D8B# AD5311BRM –40°C to +105°C 8-Lead MSOP RM-8 D9B AD5311BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 D9B AD5311BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D9B 1 AD5311BRMZ –40°C to +105°C 8-Lead MSOP RM-8 D9B# 1 AD5311BRMZ-REEL –40°C to +105°C 8-Lead MSOP RM-8 D9B# 1 AD5311BRMZ-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 D9B# AD5311BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B AD5311BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B AD5311BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B 1 AD5311BRTZ-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B# 1 AD5311BRTZ-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B# 1 AD5311BRTZ-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 D9B# AD5321BRM –40°C to +105°C 8-Lead MSOP RM-8 DAB AD5321BRM-REEL –40°C to +105°C 8-Lead MSOP RM-8 DAB AD5321BRM-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 DAB 1 AD5321BRMZ –40°C to +105°C 8-Lead MSOP RM-8 DAB# 1 AD5321BRMZ-REEL –40°C to +105°C 8-Lead MSOP RM-8 DAB# 1 AD5321BRMZ-REEL7 –40°C to +105°C 8-Lead MSOP RM-8 DAB# AD5321BRT-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB AD5321BRT-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB AD5321BRT-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB 1 AD5321BRTZ-500RL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB# 1 AD5321BRTZ-REEL –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB# 1 AD5321BRTZ-REEL7 –40°C to +105°C 6-Lead SOT-23 RJ-6 DAB# 1 Z = RoHS Compliant Part; # denotes RoHS Compliant product, may be top or bottom marked. Rev. B | Page 21 of 24 AD5301/AD5311/AD5321 NOTES Rev. B | Page 22 of 24 AD5301/AD5311/AD5321 NOTES Rev. B | Page 23 of 24 AD5301/AD5311/AD5321 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00927-0-3/07(B) Rev. B | Page 24 of 24