ANALOG DEVICES AD5310

OUTPUT BUFFER +2.7 V to +5.5 V, 140 mA, Rail-to-Rail a Voltage Output 10-Bit DAC in a SOT-23 AD5310* FUNCTIONAL BLOCK DIAGRAM FEATURES Single 10-Bit DAC V GND 6-Lead SOT-23 and 8-Lead mSOIC Packages DD Micropower Operation: 140 mA @ 5 V POWER-ON Power-Down to 200 nA @ 5 V, 50 nA @ 3 V AD5310 RESET +2.7 V to +5.5 V Power Supply REF (+) REF (–) Guaranteed Monotonic by Design DAC V 10-BIT Reference Derived from Power Supply OUT REGISTER DAC Power-On-Reset to Zero Volts Three Power-Down Functions Low Power Serial Interface with Schmitt-Triggered INPUT POWER-DOWN Inputs RESISTOR CONTROL LOGIC CONTROL LOGIC NETWORK On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility SYNC APPLICATIONS SCLK DIN Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5310 is a single, 10-bit buffered voltage out DAC that 1. Available in 6-lead SOT-23 and 8-lead mSOIC packages. operates from a single +2.7 V to +5.5 V supply consuming 2. Low power, single supply operation. This part operates from 115 mA at 3 V. Its on-chip precision output amplifier allows rail- a single +2.7 V to +5.5 V supply and typically consumes to-rail output swing to be achieved. The AD5310 utilizes a ver- 0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for satile three-wire serial interface that operates at clock rates up battery powered applications. to 30 MHz and is compatible with standard SPI™, QSPI™, 3. The on-chip output buffer amplifier allows the output of the MICROWIRE™ and DSP interface standards. DAC to swing rail-to-rail with a slew rate of 1 V/ms. The reference for AD5310 is derived from the power supply 4. Reference derived from the power supply. inputs and thus gives the widest dynamic output range. The part incorporates a power-on-reset circuit that ensures that the DAC 5. High speed serial interface with clock speeds up to 30 MHz. output powers up to zero volts and remains there until a valid Designed for very low power consumption. The interface write takes place to the device. The part contains a power-down only powers up during a write cycle. feature which reduces the current consumption of the device to 6. Power-down capability. When powered down, the DAC 200 nA at 5 V and provides software selectable output loads typically consumes 50 nA at 3 V and 200 nA at 5 V. while in power-down mode. The part is put into power-down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment. The power consumption is 0.7 mW at 5 V reducing to 1 mW in power-down mode. The AD5310 is one of a family of pin-compatible DACs. The AD5300 is the 8-bit version and the AD5320 is the 12-bit ver- sion. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead mSOIC packages. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. *Patent pending; protected by U.S. Patent No. 5684481. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 (V = +2.7 V to +5.5 V; R = 2 kV to GND; C = 500 pF to GND; all specifications DD L L T to T unless otherwise noted) AD5310–SPECIFICATIONS MIN MAX 1 B Version Parameter Min Typ Max Units Conditions/Comments 2 STATIC PERFORMANCE Resolution 10 Bits Relative Accuracy–4 LSB See Figure 2. Differential Nonlinearity–0.5 LSB Guaranteed Monotonic by Design. See Figure 3. Zero Code Error +5 +40 mV All Zeroes Loaded to DAC Register. See Figure 6. Full-Scale Error –0.15 –1.25 % of FSR All Ones Loaded to DAC Register. See Figure 6. Gain Error–1.25 % of FSR Zero Code Error Drift –20mV/°C Gain Temperature Coefficient –5 ppm of FSR/°C 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V V DD Output Voltage Settling Time 6 8ms 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex). R = 2 kW; 0 pF < C < 500 pF. See Figure 16. L L Slew Rate 1 V/ms Capacitive Load Stability 470 pF R = ¥L 1000 pF R = 2 kWL Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19. Digital Feedthrough 0.5 nV-s DC Output Impedance 1W Short Circuit Current 50 mA V = +5 V DD 20 mA V = +3 V DD Power-Up Time 2.5ms Coming Out of Power-Down Mode. V = +5␣ V DD 5ms Coming Out of Power-Down Mode. V = +3␣ V DD 3 LOGIC INPUTS Input Current–1mA V , Input Low Voltage 0.8 V V = +5 V INL DD V , Input Low Voltage 0.6 V V = +3␣ V INL DD V , Input High Voltage 2.4 V V = +5 V INH DD V , Input High Voltage 2.1 V V = +3 V INH DD Pin Capacitance 3 pF POWER REQUIREMENTS V 2.7 5.5 V DD I (Normal Mode) DAC Active and Excluding Load Current DD V = +4.5 V to +5.5 V 140 250mAV = V and V = GND DD IH DD IL V = +2.7 V to +3.6 V 115 200mAV = V and V = GND DD IH DD IL I (All Power-Down Modes) DD V = +4.5 V to +5.5 V 0.2 1mAV = V and V = GND DD IH DD IL V = +2.7 V to +3.6 V 0.05 1mAV = V and V = GND DD IH DD IL Power Efficiency I /I 93 % I = 2 mA. V = +5 V OUT DD LOAD DD NOTES 1 Temperature ranges are as follows: B Version: –40°C to +105°C. 2 Linearity calculated using a reduced code range of 12 to 1011. Output unloaded. 3 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. –2– REV. A AD5310 1, 2 TIMING CHARACTERISTICS (V = +2.7 V to +5.5 V; all specifications T to T unless otherwise noted) DD MIN MAX Limit at T , T MIN MAX Parameter V = 2.7 V to 3.6 V V = 3.6 V to 5.5 V Units Conditions/Comments DD DD 3 50 33 ns min SCLK Cycle Time t 1 t 13 13 ns min SCLK High Time 2 t 22.5 13 ns min SCLK Low Time 3 t 0 0 ns min SYNC to SCLK Rising Edge Setup Time 4 t 5 5 ns min Data Setup Time 5 4.5 4.5 ns min Data Hold Time t 6 t 0 0 ns min SCLK Falling Edge to SYNC Rising Edge 7 t 50 33 ns min Minimum SYNC High Time 8 NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH 2 See Figure 1. 3 Maximum SCLK frequency is 30 MHz at V = +3.6 V to +5.5 V and 20 MHz at V = +2.7 V to +3.6 V. DD DD Specifications subject to change without notice. t 1 SCLK t 2 t 8 t t 3 7 t 4 SYNC t 6 t 5 DIN DB15 DB0 Figure 1. Serial Write Operation ABSOLUTE MAXIMUM RATINGS*mSOIC Package (T = +25°C unless otherwise noted) A Power Dissipation . . . . . . . . . . . . . . . . . . . (T Max–T )/qJ A JA V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 Vq Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W DD JA Digital Input Voltage to GND . . . . . . . .–0.3 V to V + 0.3 Vq Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W DD JC V to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V Lead Temperature, Soldering OUT DD Operating Temperature Range Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- Junction Temperature (T Max) . . . . . . . . . . . . . . . . .+150°C nent damage to the device. This is a stress rating only; functional operation of the J device at these or any other conditions above those listed in the operational sections SOT-23 Package of this specification is not implied. Exposure to absolute maximum rating condi- Power Dissipation . . . . . . . . . . . . . . . . . . . (T Max–T )/qJ A JA tions for extended periods may affect device reliability. q Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W JA Lead Temperature, Soldering ORDERING GUIDE Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C Temperature Branding Package Model Range Information Options* AD5310BRT –40°C to +105°C D3B RT-6 AD5310BRM –40°C to +105°C D3B RM-8 *RT = SOT-23; RM = mSOIC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5310 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– AD5310 PIN CONFIGURATIONS SOT-23 mSOIC 6 V 1 1 8 GND SYNC V OUT DD AD5310 5 GND 2 SCLK NC 2 AD5310 7 DIN 4 V 3 DIN NC 3 6 SCLK DD TOP VIEW (Not to Scale) TOP VIEW V 4 5 SYNC OUT (Not to Scale) NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SOT-23 Pin Numbers Pin No. Mnemonic Function 1V Analog output voltage from DAC. The output amplifier has rail-to-rail operation. OUT 2 GND Ground reference point for all circuitry on the part. 3V Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and V should be de- DD DD coupled to GND. 4 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 5 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 SYNC Level triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. –4– REV. A AD5310 TERMINOLOGY Gain Error Relative Accuracy This is a measure of the span error of the DAC. It is the devia- For the DAC, relative accuracy or Integral Nonlinearity (INL) tion in slope of the DAC transfer characteristic from ideal is a measure of the maximum deviation, in LSBs, from a straight expressed as a percent of the full-scale range. line passing through the endpoints of the DAC transfer func- Total Unadjusted Error tion. A typical INL vs. code plot can be seen in Figure 2. Total Unadjusted Error (TUE) is a measure of the output error Differential Nonlinearity taking all the various errors into account. A typical TUE vs. Differential Nonlinearity (DNL) is the difference between the code plot can be seen in Figure 4. measured change and the ideal 1 LSB change between any two Zero-Code Error Drift adjacent codes. A specified differential nonlinearity of –1 LSB This is a measure of the change in zero-code error with a maximum ensures monotonicity. This DAC is guaranteed change in temperature. It is expressed in mV/°C. monotonic by design. A typical DNL vs. code plot can be seen Gain Error Drift in Figure 3. This is a measure of the change in gain error with changes in Zero-Code Error temperature. It is expressed in (ppm of full-scale range)/°C. Zero-code error is a measure of the output error when zero code Digital-to-Analog Glitch Impulse (000 Hex) is loaded to the DAC register. Ideally the output Digital-to-analog glitch impulse is the impulse injected into the should be 0 V. The zero-code error is always positive in the analog output when the input code in the DAC register changes AD5310 because the output of the DAC cannot go below 0 V. state. It is normally specified as the area of the glitch in nV secs It is due to a combination of the offset errors in the DAC and and is measured when the digital input code is changed by output amplifier. Zero-code error is expressed in mV. A plot of 1 LSB at the major carry transition (1FF Hex to 200 Hex). See zero-code error vs. temperature can be seen in Figure 6. Figure 19. Full-Scale Error Digital Feedthrough Full-scale error is a measure of the output error when full-scale Digital feedthrough is a measure of the impulse injected into the code (3FF Hex) is loaded to the DAC register. Ideally the out- analog output of the DAC from the digital inputs of the DAC put should be V – 1 LSB. Full-scale error is expressed in DD but is measured when the DAC output is not updated. It is percent of full-scale range. A plot of full-scale error vs. tem- specified in nV secs and is measured with a full-scale code perature can be seen in Figure 6. change on the data bus, i.e., from all 0s to all 1s and vice versa. REV. A –5– AD5310–Typical Performance Characteristics 4 4 0.5 0.4 3 DNL @ 3V T = +258C DNL @ 5V A 0.3 T = +258C 2 A 2 TUE @ 3V 0.2 INL @ 3V 1 0.1 0 0 0 TUE @ 5V –0.1 –1 INL @ 5V T = +258C A –0.2 –2 –2 –0.3 –3 –0.4 –4 –4 –0.5 0 0 200 400 600 800 1000 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE CODE Figure 2. Typical INL Plot Figure 3. Typical DNL Plot Figure 4. Typical Total Unadjusted Error Plot 4 30 2500 V = +5V V = +5V DD DD V = +5V DD 20 2000 2 V = +3V DD 10 MAX INL ZS ERROR 1500 MAX DNL 0 0 FS ERROR MIN DNL 1000 MIN INL –10 –2 500 –20 –30 –4 0 100 110 120 130 140 150 160 170 180190 50 60 70 80 90 –40 0 40 80 120 –40 040 80 120 I – mA TEMPERATURE – 8C TEMPERATURE – 8C DD Figure 5. INL Error and DNL Error Figure 6. Zero-Scale Error and Full- Figure 7. I Histogram with V = DD DD vs. Temperature Scale Error vs. Temperature 3 V and V = 5 V DD 3 5 500 T = +258C A DAC LOADED WITH 3FF HEX 4 400 DAC LOADED WITH 3FF HEX 2 3 300 T = +258C A 2 200 1 V = +5V DD DAC LOADED WITH 000 HEX 1 100 V = +3V DD DAC LOADED WITH 000 HEX 0 0 0 0 51 105 051 105 0 200 400 600 800 1000 I – mA I – mA SOURCE/SINK CODE SOURCE/SINK Figure 8. Source and Sink Current Figure 9. Source and Sink Current Figure 10. Supply Current vs. Code Capability with V = 3 V Capability with V = 5 V DD DD –6– REV. A ERROR – LSBs INL ERROR – LSBs V – V OUT DNL ERROR – LSBs ERROR – mV V – V OUT FREQUENCY I – mA DD TUE – LSBs AD5310 1.0 300 300 THREE–STATE V = +5V 0.9 DD CONDITION 250 250 0.8 0.7 200 200 0.6 0.5 150 150 0.4 +1058C 100 100 0.3 +258C –408C 0.2 50 50 0.1 0 0 0 2.7 3.2 3.7 4.2 4.7 5.2 –40 040 80 120 2.7 3.2 3.7 4.2 4.7 5.2 V – V V – V TEMPERATURE – 8C DD DD Figure 11. Supply Current vs. Figure 13. Power-Down Current vs. Figure 12. Supply Current vs. Sup- Temperature Supply Voltage ply Voltage 800 T = +258C A CH 2 CLK CH 2 CLK 600 400 V V OUT OUT V = +5V V = +5V DD DD CH 1 HALF-SCALE CODE CHANGE FULL-SCALE CODE CHANGE CH1 100 HEX – 300 HEX 000 HEX – 3FF HEX 200 T = +258C V = +5V A T = +258C DD A OUTPUT LOADED WITH OUTPUT LOADED WITH 2kV AND 200pF TO GND 2kV AND 200pF TO GND V = +3V DD CH1 1V, CH2 5V, TIME BASE = 1ms/DIV CH1 1V, CH 2 5V, TIME BASE = 1ms/DIV 0 01 23 4 5 V – V LOGIC Figure 14. Supply Current vs. Logic Figure 16. Half-Scale Settling Time Figure 15. Full-Scale Settling Time Input Voltage 2.54 LOADED WITH 2kV V = +5V DD 2kV LOAD AND 200pF TO GND CH2 TO V DD CODE CHANGE: CLK 2.52 200 HEX TO 1FF HEX V DD 2.50 CH1 V OUT V OUT CH2 2.48 CH1 CH1 1V, CH 2 1V, TIME BASE = 20ms/DIV CH1 1V, CH 2 5V, TIME BASE = 5ms/DIV 2.46 500ns/DIV Figure 17. Power-On Reset to 0 V Figure 19. Digital-to-Analog Glitch Figure 18. Exiting Power-Down Impulse (200 Hex Loaded) REV. A –7– I – mA I – mA DD DD I – mA DD V – V I – mA OUT DD AD5310 GENERAL DESCRIPTION Resistor String D/A Section The resistor string section is shown in Figure 21. It is simply a The AD5310 DAC is fabricated on a CMOS process. The string of resistors, each of value R. The code loaded to the DAC architecture consists of a string DAC followed by an output register determines at what node on the string the voltage is buffer amplifier. Since there is no reference input pin, the tapped off to be fed into the output amplifier. The voltage is power supply (V ) acts as the reference. Figure 20 shows a tapped off by closing one of the switches connecting the string DD block diagram of the DAC architecture. to the amplifier. Because it is a string of resistors, it is guaran- teed monotonic. V DD Output Amplifier The output buffer amplifier is capable of generating rail-to-rail REF (+) voltages on its output which gives an output range of 0 V to RESISTOR V DAC REGISTER OUT V . It is capable of driving a load of 2 kW in parallel with STRING DD 1000 pF to GND. The source and sink capabilities of the output REF (–) OUTPUT amplifier can be seen in Figures 8 and 9. The slew rate is 1 V/ms AMPLIFIER with a half-scale settling time of 6 ms with the output loaded. GND Figure 20. DAC Architecture SERIAL INTERFACE The AD5310 has a three-wire serial interface (SYNC, SCLK Since the input coding to the DAC is straight binary, the ideal and DIN) which is compatible with SPI, QSPI and MICROWIRE output voltage is given by: interface standards as well as most DSPs. See Figure 1 for a timing diagram of a typical write sequence.   D V =V·OUT DD   The write sequence begins by bringing the SYNC line low. Data 1024Łł from the DIN line is clocked into the 16-bit shift register on the where D = decimal equivalent of the binary code which is falling edge of SCLK. The serial clock frequency can be as high loaded to the DAC register; it can range from 0 to 1023. as 30 MHz making the AD5310 compatible with high speed DSPs. On the sixteenth falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of R operation). At this stage, the SYNC line may be kept low or be brought high. In either case, it must be brought high for a mini- mum of 33 ns before the next write sequence so that a falling R edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when V = 2.4 V than it does IN R TO OUTPUT when V = 0.8 V, SYNC should be idled low between write IN AMPLIFIER sequences for even lower power operation of the part. As is mentioned above, however, it must be brought high again just before the next write sequence. Input Shift Register The input shift register is 16 bits wide (see Figure 22). The first two bits are “don’t cares.” The next two are control bits which R control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes R section. The next ten bits are the data bits. These are transferred to the DAC register on the sixteenth falling edge of SCLK. Finally, the last two bits are “don’t cares.” Figure 21. Resistor String DB0 (LSB) DB15 (MSB) X X PD1 PD0 D9 D8 D7D6D5D4 D3 D2D1 D0 X X DATA BITS 0 0 NORMAL OPERATION 01 1kV TO GND POWER-DOWN MODES 1 0 100kV TO GND 1 1 THREE-STATE Figure 22. Input Register Contents –8– REV. A AD5310 SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at RESISTOR AMPLIFIER least 16 falling edges of SCLK and the DAC is updated on the V OUT STRING DAC 16th falling edge. However, if SYNC is brought high before the 16th falling edge this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as POWER-DOWN invalid. Neither an update of the DAC register contents or a RESISTOR CIRCUITRY NETWORK change in the operating mode occurs—see Figure 23. Power-On-Reset The AD5310 contains a power-on-reset circuit which controls the output voltage during power-up. The DAC register is filled Figure 24. Output Stage During Power-Down with zeros and the output voltage is 0 V. It remains there until The bias generator, the output amplifier, the resistor string and a valid write sequence is made to the DAC. This is useful in other associated linear circuitry are all shut down when the applications where it is important to know the state of the out- power-down mode is activated. However, the contents of the put of the DAC while it is in the process of powering up. DAC register are unaffected when in power-down. The time to Power-Down Modes exit power-down is typically 2.5 ms for V = 5 V and 5 ms for DD The AD5310 contains four separate modes of operation. These V = 3 V. See Figure 18 for a plot. DD modes are software-programmable by setting two bits (DB13 and DB12) in the control register. Table I shows how the state MICROPROCESSOR INTERFACING of the bits corresponds to the mode of operation of the device. AD5310 to ADSP-2101/ADSP-2103 Interface Figure 25 shows a serial interface between the AD5310 and the Table I. Modes of Operation for the AD5310 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing DB13 DB12 Operating Mode Mode. The ADSP-2101/ADSP-2103 SPORT is programmed 0 0 Normal Operation through the SPORT control register and should be configured as Power-Down Modes follows: Internal Clock Operation, Active Low Framing, 16-Bit 01 1 kW to GND Word Length. Transmission is initiated by writing a word to the 1 0 100 kW to GND Tx register after the SPORT has been enabled. 1 1 Three-State ADSP-2101/ When both bits are set to 0, the part works normally with its AD5310* ADSP-2103* normal power consumption of 140 mA at 5 V. However, for the TFS three power-down modes, the supply current falls to 200 nA at DT 5 V (50 nA at 3 V). Not only does the supply current fall but DIN the output stage is also internally switched from the output of SCLK SCLK the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known *ADDITIONAL PINS OMITTED FOR CLARITY while the part is in power-down mode. There are three differ- ent options. The output is connected internally to GND through a Figure 25. AD5310 to ADSP-2101/ADSP-2103 Interface 1 kW resistor, a 100 kW resistor or it is left open-circuited (Three- State). The output stage is illustrated in Figure 24. SCLK SYNC DB15 DB0 DB15 DB0 DIN INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES TH TH ON THE 16 FALLING EDGE SYNC HIGH BEFORE 16 FALLING EDGE Figure 23. SYNC Interrupt Facility REV. A –9– AD5310 AD5310 to 68HC11/68L11 Interface AD5310 to Microwire Interface Figure 26 shows a serial interface between the AD5310 and the Figure 28 shows an interface between the AD5310 and any 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 microwire compatible device. Serial data is shifted out on the drives the SCLK of the AD5310, while the MOSI output falling edge of the serial clock and is clocked into the AD5310 drives the serial data line of the DAC. The SYNC signal is de- on the rising edge of the SK. rived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 MICROWIRE* AD5310* should be configured so that its CPOL bit is a 0 and its CPHA CS bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is SK SCLK configured as above, data appearing on the MOSI output is valid DIN SO on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges *ADDITIONAL PINS OMITTED FOR CLARITY occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5310, PC7 is left low after the first Figure 28.␣ AD5310 to MICROWIRE Interface eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken high at the end of this APPLICATIONS procedure. Using REF19x as a Power Supply for AD5310 Because the supply current required by the AD5310 is extremely low, an alternative option is to use a REF19x voltage reference 68HC11/68L11* AD5310* (REF195 for 5 V or REF193 for 3 V) to supply the required voltage to the part—see Figure 29. This is especially useful if PC7 your power supply is quite noisy or if the system supply voltages SCK SCLK are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x MOSI DIN will output a steady supply voltage for the AD5310. If the low dropout REF195 is used, the current which it needs to supply to *ADDITIONAL PINS OMITTED FOR CLARITY the AD5310 is 140 mA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to Figure 26. AD5310 to 68HC11/68L11 Interface supply the current to the load. The total current required (with AD5310 to 80C51/80L51 Interface a 5 kW load on the DAC output) is: Figure 27 shows a serial interface between the AD5310 and the 140 mA + (5 V/5 kW) = 1.14 mA 80C51/80L51 microcontroller. The setup for the interface is as The load regulation of the REF195 is typically 2 ppm/mA follows: TXD of the 80C51/80L51 drives SCLK of the AD5310, which results in an error of 2.3 ppm (11.5 mV) for the 1.14 mA while RXD drives the serial data line of the part. The SYNC current drawn from it. This corresponds to a 0.002 LSB error. signal is again derived from a bit programmable pin on the port. In this case port line P3.3 is used. When data is to be transmit- +15V ted to the AD5310, P3.3 is taken low. The 80C51/80L51 trans- +5V mits data only in 8-bit bytes; thus only eight falling clock edges REF195 occur in the transmit cycle. To load data to the DAC, P3.3 is 140mA left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ SYNC V = 0V TO 5V OUT THREE-WIRE 80L51 outputs the serial data in a format which has the LSB SCLK AD5310 SERIAL first. The AD5310 requires its data with the MSB as the first bit INTERFACE DIN received. The 80C51/80L51 transmit routine should take this into account. Figure 29. REF195 as Power Supply to AD5310 80C51/80L51* AD5310* P3.3 TXD SCLK RXD DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 27. AD5310 to 80C51/80L51 Interface –10– REV. A AD5310 Bipolar Operation Using the AD5310 +5V REGULATOR The AD5310 has been designed for single-supply operation 10mF 0.1mF POWER but a bipolar output range is also possible using the circuit in Figure 30. The circuit below will give an output voltage V DD range of –5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output 10kV V DD SCLK SCLK amplifier. The output voltage for any input code can be calculated as AD5310 V follows: DD 10kV Øø      D R1+ R2 R2 V OUT SYNC SYNC V = V··±V·ŒœO DD DD       1024 R1 R1łŁłŁłŁŒœºß V DD where D represents the input code in decimal (0–1023). With V = 5 V, R1 = R2 = 10 kW: DD 10kV DIN DATA   10·D GND V = ±5V O   1024Łł This is an output voltage range of –5 V with 000 Hex corre- Figure 31. AD5310 with an Opto-Isolated Interface sponding to a –5 V output and 3FF Hex corresponding to a +5 V output. Power Supply Bypassing and Grounding When accuracy is important in a circuit it is helpful to consider R2 = 10kV carefully the power supply and ground return layout on the board. The printed circuit board containing the AD5310 should +5V +5V R1 = 10kV have separate analog and digital sections, each having their own AD820/ area of the board. If the AD5310 is in a system where other OP295 65V devices require an AGND to DGND connection, the connec- –5V tion should be made at one point only. This ground point V V OUT DD 10mF 0.1mF should be as close as possible to the AD5310. AD5310 The power supply to the AD5310 should be bypassed with 10 mF and 0.1 mF capacitors. The capacitors should be physi- cally as close as possible to the device with the 0.1 mF capacitor THREE-WIRE ideally right up against the device. The 10 mF capacitors are the SERIAL tantalum bead type. It is important that the 0.1 mF capacitor has INTERFACE low Effective Series Resistance (ESR) and Effective Series In- Figure 30. Bipolar Operation with the AD5310 ductance (ESI), e.g., common ceramic types of capacitors. This 0.1 mF capacitor provides a low impedance path to ground for Using AD5310 with an Opto-Isolated Interface high frequencies caused by transient currents due to internal In process-control applications in industrial environments it logic switching. is often necessary to use an opto-isolated interface in order to protect and isolate the controlling circuitry from any hazard- The power supply line itself should have as large a trace as pos- ous common-mode voltages which may occur in the area sible to provide a low impedance path and reduce glitch effects where the DAC is functioning. Opto-isolators provide isola- on the supply line. Clocks and other fast switching digital signals tion in excess of 3 kV. Because the AD5310 uses a three-wire should be shielded from other parts of the board by digital serial logic interface, it only requires three opto-isolators to ground. Avoid crossover of digital and analog signals if possible. provide the required isolation (see Figure 31). The power When traces cross on opposite sides of the board ensure that supply to the part also needs to be isolated. This is done by they run at right angles to each other to reduce feedthrough using a transformer. On the DAC side of the transformer, a effects through the board. The best board layout technique is +5 V regulator provides the +5 V supply required for the the microstrip technique where the component side of the board AD5310. is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a two-layer board. REV. A –11– AD5310 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 6-Lead SOT-23 (RT-6) 0.122 (3.10) 0.106 (2.70) 6 5 4 0.071 (1.80) 0.118 (3.00) 0.059 (1.50) 0.098 (2.50) 1 2 3 PIN 1 0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.057 (1.45) 0.035 (0.90) 0.035 (0.90) 10° 0.020 (0.50) 0.022 (0.55) SEATING 0.006 (0.15) 0° 0.009 (0.23) 0.010 (0.25) PLANE 0.014 (0.35) 0.000 (0.00) 0.003 (0.08) 8-Lead mSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 85 0.199 (5.05) 0.122 (3.10) 0.114 (2.90) 0.187 (4.75) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.84) 0.112 (2.84) 0.043 (1.09) 0.006 (0.15) 0.037 (0.94) 0.002 (0.05) 33° 0.018 (0.46) 27° SEATING 0.011 (0.28) 0.028 (0.71) 0.008 (0.20) PLANE 0.003 (0.08) 0.016 (0.41) –12– REV. A PRINTED IN U.S.A. C3192a–0–5/99