ANALOG DEVICES AD5305

2.5 V to 5.5 V, 500 μA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs AD5305/AD5315/AD5325 FEATURES GENERAL DESCRIPTION AD5305: 4 buffered 8-bit DACs in 10-lead MSOP 1 The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit A version: ±1 LSB INL, B version: ±0.625 LSB INL buffered voltage output DACs in a 10-lead MSOP that operate AD5315: 4 buffered 10-bit DACs in 10-lead MSOP from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V. A version: ±4 LSB INL, B version: ±2.5 LSB INL Their on-chip output amplifiers allow rail-to-rail output swing AD5325: 4 buffered 12-bit DACs in 10-lead MSOP with a slew rate of 0.7 V/μs. A 2-wire serial interface that A version: ±16 LSB INL, B version: ±10 LSB INL operates at clock rates up to 400 kHz is used. This interface is Low power operation: 500 μA @ 3 V, 600 μA @ 5 V SMBus compatible at V < 3.6 V. Multiple devices can be DD 2 2-wire (I C®-compatible) serial interface placed on the same bus. 2.5 V to 5.5 V power supply The references for the four DACs are derived from one Guaranteed monotonic by design over all codes reference pin. The outputs of all DACs can be updated Power-down to 80 nA @ 3 V, 200 nA @ 5 V simultaneously using the software LDAC function. Three power-down modes Double-buffered input logic The parts incorporate a power-on reset circuit, which ensures Output range: 0 V to VREF that the DAC outputs power up to 0 V and remain there until a Power-on reset to 0 V valid write takes place to the device. There is also a software Simultaneous update of outputs (LDAC function) clear function to reset all input and DAC registers to 0 V. The Software clear facility parts contain a power-down feature that reduces the current Data readback facility consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). On-chip rail-to-rail output buffer amplifiers The low power consumption of these parts in normal operation Temperature range: −40°C to +105°C makes them ideally suited for portable battery-operated equip- ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, APPLICATIONS reducing to 1 μW in power-down mode. Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources 1 Protected by U.S. Patent No. 5,969,657 and 5,684,481. Programmable attenuators Industrial process control FUNCTIONAL BLOCK DIAGRAM V DD REF IN LDAC DAC INPUT STRING BUFFER V A OUT REGISTER REGISTER DAC A INPUT DAC SCL STRING BUFFER V B OUT REGISTER REGISTER DAC B INTERFACE SDA LOGIC INPUT DAC STRING BUFFER V C OUT REGISTER REGISTER DAC C A0 INPUT DAC STRING V D BUFFER OUT REGISTER REGISTER DAC D POWER-DOWN POWER-ON LOGIC AD5305/AD5315/AD5325 RESET GND Figure 1. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00930-001 AD5305/AD5315/AD5325 TABLE OF CONTENTS Features .............................................................................................. 1 Read/Write Sequence................................................................. 16 Applications....................................................................................... 1 Pointer Byte Bits ......................................................................... 16 General Description ......................................................................... 1 Input Shift Register .................................................................... 16 Functional Block Diagram .............................................................. 1 Default Readback Condition .................................................... 17 Revision History ............................................................................... 2 Multiple-DAC Write Sequence................................................. 17 Specifications..................................................................................... 3 Multiple-DAC Readback Sequence ......................................... 17 AC Characteristics........................................................................ 5 Write Operation.......................................................................... 17 Timing Characteristics ................................................................ 5 Read Operation........................................................................... 17 Absolute Maximum Ratings............................................................ 7 Double-Buffered Interface ........................................................ 18 ESD Caution.................................................................................. 7 Power-Down Modes .................................................................. 18 Pin Configuration and Function Descriptions............................. 8 Applications..................................................................................... 20 Typical Performance Characteristics ............................................. 9 Typical Application Circuit....................................................... 20 Terminology .................................................................................... 13 Bipolar Operation....................................................................... 20 Functional Description .................................................................. 15 Multiple Devices on One Bus ................................................... 20 Digital-to-Analog Section ......................................................... 15 AD5305/AD5315/AD5325 as a Digitally Programmable Window Detector....................................................................... 21 Resistor String............................................................................. 15 Coarse and Fine Adjustment Using the DAC Reference Inputs ............................................................... 15 AD5305/AD5315/AD5325 ....................................................... 21 Output Amplifier........................................................................ 15 Power Supply Decoupling ......................................................... 21 Power-On Reset .......................................................................... 15 Outline Dimensions....................................................................... 23 Serial Interface ............................................................................ 16 Ordering Guide .......................................................................... 23 REVISION HISTORY Added Octals Section to Table II.................................................. 18 5/06—Rev. F to Rev. G Updated Outline Dimensions....................................................... 19 Updated Format..................................................................Universal Changes to Ordering Guide .......................................................... 24 4/01—Rev. C to Rev. D Edit to Features Section ....................................................................1 10/04—Rev. E to Rev. F Edit to Figure 6 ..................................................................................1 Changes to Figure 6........................................................................ 11 Edits to Right/Left and Double Sections Changes to Pointer Byte Bits Section........................................... 12 of Pointer Byte Bits Section........................................................... 11 Changes to Figure 7........................................................................ 12 Edit to Input Shift Register Section.............................................. 12 8/03—Rev. D to Rev. E Edit to Multiple-DAC Readback Sequence Section................... 12 Added A Version.................................................................Universal Edits to Figure 7.............................................................................. 12 Changes to Features.......................................................................... 1 Edits to Write Operation section.................................................. 13 Changes to Specifications................................................................ 2 Edits to Figure 8.............................................................................. 13 Changes to Absolute Maximum Ratings ....................................... 5 Edits to Read Operation section................................................... 14 Changes to Ordering Guide ............................................................ 5 Edits to Figure 9.............................................................................. 14 Changes to TPC 21......................................................................... 10 Edits to Power-Down Modes section .......................................... 15 Edits to Figure 12............................................................................ 16 Rev. G | Page 2 of 24 AD5305/AD5315/AD5325 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 A Version B Version 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5305 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5315 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5325 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR Lower Deadband 20 60 20 60 mV Lower deadband exists only if offset error is negative 5 Offset Error Drift −12 −12 ppm of FSR/°C 5 Gain Error Drift −5 −5 ppm of FSR/°C 5 Power Supply Rejection Ratio –60 –60 dB ∆VDD = ±10% 5 DC Crosstalk 200 200 μV R = 2 kΩ to GND or V L DD 5 DAC REFERENCE INPUTS VREF Input Range 0.25 VDD 0.25 VDD V V Input Impedance 37 45 37 45 kΩ Normal operation REF >10 >10 MΩ Power-down mode Reference Feedthrough −90 −90 dB Frequency = 10 kHz 5 OUTPUT CHARACTERISTICS 6 Minimum Output Voltage 0.001 0.001 V A measure of the minimum and maximum drive capability of the output amplifier 6 Maximum Output Voltage VDD − VDD − V 0.001 0.001 DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 25 25 mA V = 5 V DD 16 16 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down mode VDD = 5 V 5 5 μs Coming out of power-down mode V = 3 V DD Rev. G | Page 3 of 24 AD5305/AD5315/AD5325 1 1 A Version B Version 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 5 LOGIC INPUTS (A0) Input Current ±1 ±1 μA Input Low Voltage, V 0.8 0.8 V V = 5 V ± 10% IL DD 0.6 0.6 V V = 3 V ± 10% DD 0.5 0.5 V VDD = 2.5 V Input High Voltage, VIH 2.4 2.4 V VDD = 5 V ± 10% 2.1 2.1 V VDD = 3 V ± 10% 2.0 2.0 V V = 2.5 V DD Pin Capacitance 3 3 pF 5 LOGIC INPUTS (SCL, SDA) Input High Voltage, V 0.7 V + 0.7 V + V SMBus compatible at V < 3.6 V IH DD DD DD V 0.3 V 0.3 DD DD Input Low Voltage, VIL −0.3 0.3 VDD −0.3 0.3 VDD V SMBus compatible at VDD < 3.6 V Input Leakage Current, IIN ±1 ±1 μA Input Hysteresis, VHYST 0.05 0.05 V V V DD DD Input Capacitance, C 8 8 pF IN Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of less than 50 ns 5 LOGIC OUTPUT (SDA) Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA 0.6 0.6 V ISINK = 6 mA Three-State Leakage Current ±1 ±1 μA Three-State Output 8 8 pF Capacitance POWER REQUIREMENTS V 2.5 5.5 2.5 5.5 V DD 7 I (Normal Mode) V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 600 900 600 900 μA DD VDD = 2.5 V to 3.6 V 500 700 500 700 μA IDD (Power-Down Mode) VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 μA IDD = 4 μA (maximum) during 0 readback on SDA V = 2.5 V to 3.6 V 0.08 1 0.08 1 μA I = 1.5 μA (maximum) during DD DD 0 readback on SDA 1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents. Rev. G | Page 4 of 24 AD5305/AD5315/AD5325 AC CHARACTERISTICS VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 A, B Version 2, 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = VDD = 5 V AD5305 6 8 μs ¼ scale to ¾ scale change (0×40 to 0×C0) AD5315 7 9 μs ¼ scale to ¾ scale change (0×100 to 0×300) AD5325 8 10 μs ¼ scale to ¾ scale change (0×400 to 0×C00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 1 nV-s Digital Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz 1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization, not production tested. 3 See the Terminology section. TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1, 2 Parameter Limit at TMIN, TMAX (A, B Version) Unit Conditions/Comments f 400 kHz max SCL clock frequency SCL t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT 3 t60.9 μs max tHD,DAT, data hold time 0 μs min tHD,DAT, data hold time t7 0.6 μs min tSU,STA, setup time for repeated start t 0.6 μs min t , stop condition setup time 8 SU,STO t 1.3 μs min t , bus-free time between a stop and a start condition 9 BUF t 300 ns max t , rise time of SCL and SDA when receiving 10 R 0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible) t11 250 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS compatible) 300 ns max t , fall time of SCL and SDA when receiving F 4 20 + 0.1 C ns min t , fall time of SCL and SDA when transmitting B F 4 CB 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V min of the SCL signal) in order to bridge the undefined region of SCL’s IH falling edge. 4 C is the total capacitance of one bus line in pF. t and t measured between 0.3 V and 0.7 V . B R F DD DD Rev. G | Page 5 of 24 AD5305/AD5315/AD5325 SDA t t t t 9 3 10 11 t 4 SCL t t t t t t 7 t 4 5 1 6 2 8 START REPEATED STOP CONDITION START CONDITION CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. G | Page 6 of 24 00930-002 AD5305/AD5315/AD5325 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings 1 Parameter Rating may cause permanent damage to the device. This is a stress V to GND –0.3 V to +7 V DD rating only; functional operation of the device at these or any SCL, SDA to GND –0.3 V to V + 0.3 V DD other conditions above those indicated in the operational A0 to GND –0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Reference Input Voltage to GND –0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect VOUTA to VOUTD to GND –0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range Industrial (A, B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C MSOP Power Dissipation (TJ max − TA)/θJA θ Thermal Impedance 206°C/W JA θ Thermal Impedance 44°C/W JC Reflow Soldering Peak Temperature 220°C Time at Peak Temperature 10 sec to 40 sec 1 Transient currents of up to 100 mA do not cause SCR latcth-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G | Page 7 of 24 AD5305/AD5315/AD5325 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD 1 10 A0 AD5305/ V A 2 9 SCL OUT AD5315/ V B 3 AD5325 8 SDA OUT TOP VIEW V C 4 7 GND OUT (Not to Scale) 6 V D REFIN 5 OUT Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND. DD 2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V . DD 6 V D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 7 GND Ground Reference Point for All Circuitry on the Part. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates of up to 400 kb/s can be accommodated in the 2-wire interface. 10 A0 Address Input. Sets the least significant bit of the 7-bit slave address. Rev. G | Page 8 of 24 00930-003 AD5305/AD5315/AD5325 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 4. AD5305 Typical INL Plot Figure 7. AD5305 Typical DNL Plot 3 0.6 T = 25°C A T = 25°C A V = 5V DD V = 5V DD 2 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 5. AD5315 Typical INL Plot Figure 8. AD5315 Typical DNL Plot 12 1.0 T = 25°C T = 25°C A A V = 5V V = 5V DD DD 8 0.5 4 0 0 –4 –0.5 –8 –12 –1.0 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE CODE Figure 6. AD5325 Typical INL Plot Figure 9. AD5325 Typical DNL Plot Rev. G | Page 9 of 24 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 00930-006 00930-008 00930-007 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 00930-010 00930-009 00930-011 AD5305/AD5315/AD5325 0.50 0.2 V = 5V DD T = 25°C A GAIN ERROR T = 25°C A V = 2V REF 0.1 0.25 0 MAXINL MAXDNL –0.1 0 –0.2 MIN DNL –0.3 –0.25 –0.4 OFFSET ERROR –0.5 MININL –0.50 –0.6 01 2 3 4 5 01 2 3 4 5 6 V (V) V (V) REF DD Figure 10. AD5305 INL and DNL Error vs. V REF Figure 13. Offset Error and Gain Error vs. VDD 0.5 5 V = 5V DD 0.4 V = 3V REF 5V SOURCE 0.3 4 MAX INL 0.2 3V SOURCE MAX DNL 0.1 3 0 –0.1 2 MIN DNL –0.2 –0.3 1 3V SINK 5V SINK MIN INL –0.4 –0.5 0 –40 0 40 80 120 01 2 3 4 5 6 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 11. AD5305 INL and DNL Error vs. Temperature Figure 14. V Source and Sink Current Capability OUT 1.0 600 T = 25°C A V = 5V DD V = 5V DD V = 2V REF OFFSET ERROR V = 2V 500 REF 0.5 400 0 300 200 GAIN ERROR –0.5 100 –1.0 0 –40 0 40 80 120 ZERO SCALE FULL SCALE TEMPERATURE (°C) CODE Figure 12. AD5305 Offset Error and Gain Error vs. Temperature Figure 15. Supply Current vs. DAC Code Rev. G | Page 10 of 24 ERROR (%) ERROR (LSB) ERROR (LSB) 00930-012 00930-014 00930-013 I (µA) V (V) ERROR (%) OUT DD 00930-017 00930-016 00930-015 AD5305/AD5315/AD5325 600 T = 25°C A –40°C V = 5V DD V = 5V REF 500 CH1 +25°C 400 V A OUT +105°C 300 200 SCL CH2 100 0 CH1 1V, CH2 5V, TIME BASE = 1µs/DIV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DD Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change) Figure 16. Supply Current vs. Supply Voltage 0.5 T = 25°C A V = 5V DD V = 2V REF 0.4 CH1 0.3 V DD –40°C 0.2 +25°C V A OUT CH2 0.1 +105°C 0 CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) DD Figure 17. Power-Down Current vs. Supply Voltage Figure 20. Power-On Reset to 0 V 750 T = 25°C T = 25°C A A DECREASING V = 5V DD INCREASING V = 2V REF V = 5V DD CH1 V A OUT 650 550 SCL V = 3V CH2 DD 450 CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV 01 2 34 5 V (V) LOGIC Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Figure 21. Exiting Power-Down to Midscale Voltage Increasing and Decreasing Rev. G | Page 11 of 24 I (µA) I (µA) DD I (µA) DD DD 00930-020 00930-019 00930-018 00930-023 00930-022 00930-021 AD5305/AD5315/AD5325 0.02 V = 5V DD T = 25°C A 0.01 V = 3V V = 5V DD DD 0 –0.01 –0.02 300 350 400 450 500 550 600 01 2 3 4 5 6 I (µA) DD V (V) REF Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 25. Full-Scale Error vs. V REF 2.50 2.49 2.48 2.47 1µs/DIV 50ns/DIV Figure 23. AD5325 Major-Code Transition Glitch Energy Figure 26. DAC-to-DAC Crosstalk 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. G | Page 12 of 24 (dB) V (V) OUT FREQUENCY 00930-024 00930-025 00930-026 FULL SCALE ERROR (V) 1mV/DIV 00930-028 00930-027 AD5305/AD5315/AD5325 TERMINOLOGY Relative Accuracy Reference Feedthrough For the DAC, relative accuracy or integral nonlinearity (INL) is This is the ratio of the amplitude of the signal at the DAC a measure of the maximum deviation, in LSB, from a straight output to the reference input when the DAC output is not being line passing through the endpoints of the DAC transfer updated. It is expressed in dB. function. Typical INL versus code plots can be seen in Figure 4, Major-Code Transition Glitch Energy Figure 5, and Figure 6. Major-code transition glitch energy is the energy of the impulse Differential Nonlinearity injected into the analog output when the code in the DAC Differential nonlinearity (DNL) is the difference between the register changes state. It is normally specified as the area of the measured change and the ideal 1 LSB change between any two glitch in nV-s and is measured when the digital code is changed adjacent codes. A specified differential nonlinearity of ±1 LSB by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00, maximum ensures monotonicity. This DAC is guaranteed or 100 . . . 00 to 011 . . . 11). monotonic by design. Typical DNL vs. code plots can be seen in Digital Feedthrough Figure 7, Figure 8, and Figure 9. Digital feedthrough is a measure of the impulse injected into Offset Error the analog output of the DAC from the digital input pins of the This is a measure of the offset error of the DAC and the output device when the DAC output is not being updated. It is specified amplifier. It is expressed as a percentage of the full-scale range. in nV-s and is measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s or vice versa. Gain Error This is a measure of the span error of the DAC. It is the Digital Crosstalk deviation in slope of the actual DAC transfer characteristic from This is the glitch impulse transferred to the output of one DAC the ideal expressed as a percentage of the full-scale range. at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is Offset Error Drift expressed in nV-s. This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC Gain Error Drift due to a digital code change and subsequent output change of This is a measure of the change in gain error with changes in another DAC. This includes both digital and analog crosstalk. It temperature. It is expressed in (ppm of full-scale range)/°C. is measured by loading one of the DACs with a full-scale code LDAC change (all 0s to all 1s and vice versa) with the bit set low Power Supply Rejection Ratio (PSRR) and monitoring the output of another DAC. The energy of the This indicates how the output of the DAC is affected by changes glitch is expressed in nV-s. in the supply voltage. PSRR is the ratio of the change in V to OUT a change in V for full-scale output of the DAC. It is measured DD Multiplying Bandwidth in dB. V is held at 2 V and V is varied ±10%. REF DD The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the DC Crosstalk reference (with full-scale code loaded to the DAC) appears on This is the dc change in the output level of one DAC at midscale the output. The multiplying bandwidth is the frequency at in response to a full-scale code change (all 0s to all 1s and vice which the output amplitude falls to 3 dB below the input. versa) and output change of another DAC. It is expressed in μV. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dB. Rev. G | Page 13 of 24 AD5305/AD5315/AD5325 GAIN ERROR GAIN ERROR PLUS PLUS OFFSET ERROR OFFSET ERROR ACTUAL OUTPUT OUTPUT IDEAL VOLTAGE VOLTAGE IDEAL ACTUAL POSITIVE OFFSET NEGATIVE DAC CODE OFFSET DAC CODE ERROR Figure 28. Transfer Function with Positive Offset DEAD BAND CODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset Rev. G | Page 14 of 24 00930-004 00930-005 AD5305/AD5315/AD5325 FUNCTIONAL DESCRIPTION The AD5305/AD5315/AD5325 are quad resistor-string DACs R fabricated on a CMOS process with resolutions of 8, 10, and 12 R bits, respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from TO OUTPUT R AMPLIFIER single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. The four DACs share a single reference input pin. The devices have three programmable power-down modes, in which all R DACs can be turned off completely with a high impedance output, or the outputs can be pulled low by on-chip resistors. R DIGITAL-TO-ANALOG SECTION The architecture of one DAC channel consists of a resistor- Figure 30. Resistor String string DAC followed by an output buffer amplifier. The voltage DAC REFERENCE INPUTS at the REFIN pin provides the reference voltage for the DAC. There is a single reference input pin for the four DACs. The Figure 29 shows a block diagram of the DAC architecture. reference input is unbuffered. The user can have a reference Because the input coding to the DAC is straight binary, the ideal voltage as low as 0.25 V and as high as V because there is no output voltage is given by DD restriction due to headroom and footroom of any reference V ×D REF V = amplifier. OUT N 2 It is recommended to use a buffered reference in the external where: circuit (for example, REF192). The input impedance is typically 45 kΩ. D = decimal equivalent of the binary code, which is loaded to the DAC register: OUTPUT AMPLIFIER 0 to 255 for AD5305 (8 bits) The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to 0 to 1023 for AD5315 (10 bits) V when the reference is V . It is capable of driving a load of DD DD 2 kΩ to GND or V , in parallel with 500 pF to GND or V . DD DD 0 to 4095 for AD5325 (12 bits) The source and sink capabilities of the output amplifier can be N = DAC resolution seen in the plot in Figure 14. REFIN The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs. INPUT DAC RESISTOR POWER-ON RESET V A OUT REGISTER REGISTER STRING The AD5305/AD5315/AD5325 are provided with a power-on reset function, so that they power up in a defined state. The OUTPUT BUFFER AMPLIFIER power-on state is Figure 29. DAC Channel Architecture • Normal operation RESISTOR STRING • Output voltage set to 0 V The resistor string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to Both input and DAC registers are filled with zeros and remain the DAC register determines at what node on the string the so until a valid write sequence is made to the device. This is voltage is tapped off to be fed into the output amplifier. The particularly useful in applications where it is important to know voltage is tapped off by closing one of the switches connecting the state of the DAC outputs while the device is powering up. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. G | Page 15 of 24 00930-029 00930-030 AD5305/AD5315/AD5325 SERIAL INTERFACE READ/WRITE SEQUENCE 2 The AD5305/AD5315/AD5325 are controlled via an I C In the case of the AD5305/AD5315/AD5325, all write access compatible serial bus. The DACs are connected to this bus as sequences and most read sequences begin with the device slave devices (that is, no clock is generated by the AD5305/ W address (with R/ = 0) followed by the pointer byte. This AD5315/AD5325 DACs). This interface is SMBus compatible pointer byte specifies the data format and determines which at V < 3.6 V. DD DAC is being accessed in the subsequent read/write operation (see Figure 31). In a write operation, the data follows The AD5305/AD5315/AD5325 have a 7-bit slave address. The immediately. In a read operation, the address is resent with 6 MSB are 000110 and the LSB is determined by the state of the R/W = 1 and then the data is read back. However, it is also A0 pin. The facility to make hardwired changes to A0 allows the possible to perform a read operation by sending only the user to use up to two of these devices on one bus. The 2-wire address with R/W = 1. The previously loaded pointer settings serial bus protocol operates as follows: are then used for the readback operation. See Figure 32 for a graphical explanation of the interface. 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the MSB LSB SDA line occurs while SCL is high. The following byte is X X 0 0 DACD DACC DACB DACA the address byte, which consists of the 7-bit slave address Figure 31. Pointer Byte followed by an R/W bit (this bit determines whether data is read from or written to the slave device). POINTER BYTE BITS Table 6 explains the individual bits that make up the pointer byte. The slave whose address corresponds to the transmitted address responds by pulling SDA low during the ninth Table 6. Individual Bits of the Pointer Byte clock pulse (this is termed the acknowledge bit). At this Bit Description stage, all other devices on the bus remain idle while the X Don’t care bits. selected device waits for data to be written to or read from 0 Reserved bits. Must be set to 0. its shift register. DACD [1] The following data bytes are for DAC D. DACC [1] The following data bytes are for DAC C. 2. Data is transmitted over the serial bus in sequences of nine DACB [1] The following data bytes are for DAC B. clock pulses (eight data bits followed by an acknowledge DACA [1] The following data bytes are for DAC A. bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high INPUT SHIFT REGISTER period of SCL. The input shift register is 16 bits wide. Data is loaded into the device as two data bytes on the serial data line, SDA, under the 3. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls control of the serial clock input, SCL. The timing diagram for th this operation is shown in Figure 2. The two data bytes consist the SDA line high during the 10 clock pulse to establish a of four control bits followed by 8, 10, or 12 bits of DAC data, stop condition. In read mode, the master issues a No depending on the device type. The first two bits loaded are the Acknowledge for the ninth clock pulse (that is, the SDA PD1 and PD0 bits that control the mode of operation of the device. line remains high). The master then brings the SDA line th See the Power-Down Modes section for a complete description. low before the 10 clock pulse and then high during the th CLR LDAC 10 clock pulse to establish a stop condition. Bit 13 is , Bit 12 is , and the remaining bits are left justified DAC data bits, starting with the MSB. See Figure 32. DATA BYTES (WRITE AND READBACK) MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE LSB MSB 8-BIT AD5305 8-BIT AD5305 LSB MSB PD1 PD0 CLR LDAC D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 10-BIT AD5315 LSB MSB 10-BIT AD5315 LSB MSB PD1 PD0 CLR LDAC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 MSB 12-BIT AD5325 LSB MSB 12-BIT AD5325 LSB PD1 PD0 CLR LDAC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 32. Data Formats for Write and Readback Rev. G | Page 16 of 24 00930-032 00930-031 AD5305/AD5315/AD5325 CLR LDAC Table 7. and Bit Descriptions WRITE OPERATION Bit Description When writing to the AD5305/AD5315/AD5325 DACs, the user CLR [0] All DAC registers and input registers are filled with 0s must begin with an address byte (R/W = 0), after which the DAC on completion of the write sequence. acknowledges that it is prepared to receive data by pulling SDA [1] Normal operation. low. This address byte is followed by the pointer byte, which is LDAC [0] All four DAC registers and, therefore, all DAC outputs, also acknowledged by the DAC. Two bytes of data are then written are simultaneously updated on completion of the write to the DAC, as shown in Figure 33. A stop condition follows. sequence. [1] Only addressed input register is updated. There is no READ OPERATION change in the contents of the DAC registers. When reading data back from the AD5305/AD5315/AD5325 DEFAULT READBACK CONDITION W DACs, the user begins with an address byte (R/ = 0), after All pointer byte bits power up to 0. Therefore, if the user which the DAC acknowledges that it is prepared to receive data initiates a readback without writing to the pointer byte first, no by pulling SDA low. This address byte is usually followed by the single DAC channel has been specified. In this case, the default pointer byte, which is also acknowledged by the DAC. Following readback bits are all 0, except for the CLR bit, which is a 1. this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the MULTIPLE-DAC WRITE SEQUENCE DAC indicating that it is prepared to transmit data. Two bytes Because there are individual bits in the pointer byte for each of data are then read from the DAC, as shown in Figure 34. A DAC, it is possible to simultaneously write the same data and stop condition follows. control bits to 2, 3, or 4 DACs by setting the relevant bits to 1. However, if the master sends an ACK and continues clocking MULTIPLE-DAC READBACK SEQUENCE SCL (no STOP is sent), the DAC retransmits the same two bytes If the user attempts to read back data from more than one DAC of data on SDA. This allows continuous readback of data from the selected DAC register. at a time, the part reads back the default, power-on reset conditions, that is, all 0s except for CLR, which is 1. Alternatively, the user can send a start followed by the address W with R/ = 1. In this case, the previously loaded pointer settings are used and readback of data can commence immediately. SCL 0 0 0 1 1 0 A0 R/W X X LSB SDA START ACK MSB ACK COND BY BY ADDRESS BYTE POINTER BYTE BY AD53x5 AD53x5 MASTER SCL SDA MSB LSB MSB LSB ACK ACK STOP MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY BY COND AD53x5 AD53x5 BY MASTER Figure 33. Write Sequence Rev. G | Page 17 of 24 00930-033 AD5305/AD5315/AD5325 SCL 0 0 0 1 1 0 A0 R/W X X LSB SDA START ACK MSB ACK COND BY BY ADDRESS BYTE POINTER BYTE BY AD53x5 AD53x5 MASTER SCL SDA 0 0 0 1 1 0 A0 R/W MSB LSB REPEATED ACK ACK ADDRESS BYTE DATA BYTE START BY BY COND AD53x5 MASTER BY MASTER SCL SDA MSB LSB NO STOP LEAST SIGNIFICANT DATA BYTE ACK COND BY BY MASTER MASTER NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s. Figure 34. Readback Sequence DOUBLE-BUFFERED INTERFACE These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since The AD5305/AD5315/AD5325 DACs have double-buffered LDAC the last time that was brought low. Normally, when interfaces consisting of two banks of registers—input registers LDAC is brought low, the DAC registers are filled with the and DAC registers. The input register is directly connected to the contents of the input registers. In the case of the AD5305/AD5315/ input shift register and the digital code is transferred to the relevant AD5325, the part updates the DAC register only if the input input register on completion of a valid write sequence. The DAC register has been changed since the last time the DAC register register contains the digital code used by the resistor string. was updated, thereby removing unnecessary digital crosstalk. LDAC Access to the DAC register is controlled by the bit. When POWER-DOWN MODES the LDAC bit is set high, the DAC register is latched and, therefore, the input register can change state without affecting The AD5305/AD5315/AD5325 have very low power consumption, the contents of the DAC register. However, when the LDAC bit dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when is set low, the DAC register becomes transparent and the the DACs are not in use by putting them into one of three contents of the input register are transferred to it. power-down modes, which are selected by Bit 15 and Bit 14 This is useful if the user requires simultaneous updating of all (PD1 and PD0) of the data byte. Table 8 shows how the state of DAC outputs. The user can write to three of the input registers the bits corresponds to the mode of operation of the DAC. LDAC individually and then, by setting the bit low when Table 8. PD1/PD0 Operating Modes writing to the remaining DAC input register, all outputs update PD1 PD0 Operating Mode simultaneously. 0 0 Normal Operation 0 1 Power-Down (1 kΩ load to GND) 1 0 Power-Down (100 kΩ load to GND) 1 1 Power-Down (three-state output) Rev. G | Page 18 of 24 00930-034 AD5305/AD5315/AD5325 When both bits are set to 0, the DAC works normally with its normal power consumption of 600 μA at 5 V. However, for the RESISTOR V AMPLIFIER OUT STRING DAC three power-down modes, the supply current falls to 200 nA at 5 V (80 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of POWER-DOWN the amplifier to a resistor network of known values. This has an RESISTOR CIRCUITRY NETWORK advantageous because the output impedance of the part is known while the part is in power-down mode and provides a defined Figure 35. Output Stage During Power-Down input condition for whatever is connected to the output of the DAC amplifier. There are three different options. The output is The bias generator, the output amplifiers, the resistor string, and connected internally to GND through a 1 kΩ resistor, a 100 kΩ all other associated linear circuitry are shut down when the resistor, or it is left open-circuited (three-state). Resistor power-down mode is activated. However, the contents of the tolerance = ±20%. The output stage is illustrated in Figure 35. DAC registers are unchanged when in power-down. The time to exit power-down is typically 2.5 μs for V = 5 V and 5 μs when DD VDD = 3 V. This is the time from the rising edge of the eighth SCL pulse to when the output voltage deviates from its power- down voltage. See Figure 21 for a plot. Rev. G | Page 19 of 24 00930-035 AD5305/AD5315/AD5325 APPLICATIONS TYPICAL APPLICATION CIRCUIT BIPOLAR OPERATION The AD5305/AD5315/AD5325 can be used with a wide range The AD5305/AD5315/AD5325 have been designed for single of reference voltages where the devices offer full, one-quadrant supply operation, but a bipolar output range is also possible using multiplying capability over a reference range of 0 V to V . the circuit in Figure 37. This circuit gives an output voltage DD More typically, these devices are used with a fixed, precision range of 5 V. Rail-to-rail operation at the amplifier output is reference voltage. Suitable references for 5 V operation are the achievable using an AD820 or an OP295 as the output amplifier. AD780 and REF192 (2.5 V references). For 2.5 V operation, a R2 = 10kΩ suitable external reference is the AD589, a 1.23 V band gap +5V 6V TO 12V reference. Figure 36 shows a typical setup for the AD5305/ R1 = 10kΩ AD5315/AD5325 when using an external reference. Note that 10µF 0.1µF AD820/ ±5V +5V OP295 A0 can be high or low. V A V OUT DD AD5305 AD1585 V = 2.5V TO 5.5V DD –5V V V B IN OUT V OUT REFIN GND 1µF V C OUT 10µF 0.1µF AD5305/ V D OUT AD5315/ A0 AD5325 GND SCL SDA V IN V A OUT V REFIN OUT V B EXT OUT 1µF REF 2-WIRE V C OUT SERIAL AD780/REF192 SCL INTERFACE WITH V = 5V DD SDA V D OUT OR AD589 WITH Figure 37. Bipolar Operation with the AD5305 V = 2.5V DD A0 GND The output voltage for any input code can be calculated as follows: SERIAL INTERFACE N ⎡(REFIN×(D /2 ))×() R1+R2 ⎤ Figure 36. AD5305/AD5315/AD5325 Using External Reference V = −REFIN×() R2/R1 ⎢ ⎥ OUT R1 ⎢ ⎥ ⎣ ⎦ If an output range of 0 V to V is required, the simplest DD solution is to connect the reference input to V . As this DD where: supply may not be very accurate and may be noisy, the D is the decimal equivalent of the code loaded to the DAC. AD5305/AD5315/AD5325 can be powered from the reference N is the DAC resolution. voltage; for example, using a 5 V reference such as the REF195. REFIN is the reference voltage input. The REF195 outputs a steady supply voltage for the AD5305/ AD5315/AD5325. The typical current required from the with REF195 is 600 μA supply current and approximately 112 μA N into the reference input. This is with no load on the DAC REFIN = 5 V, R1 = R2 = 10 kΩ, VOUT (10 × D/2 ) − 5 V outputs. When the DAC outputs are loaded, the REF195 also MULTIPLE DEVICES ON ONE BUS needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is Figure 38 shows two AD5305 devices on the same serial bus. Each has a different slave address because the state of the A0 pin 712 μA + 4(5 V/10 kΩ) = 2.70 mA is different. This allows each of eight DACs to be written to or The load regulation of the REF195 is typically 2 ppm/mA, read from independently. which results in an error of 5.4 ppm (27 μV) for the 2.7 mA V DD A0 current drawn from it. This corresponds to a 0.0014 LSB error AD5305 at eight bits and 0.022 LSB error at 12 bits. PULL-UP SDA SCL RESISTORS MICRO- CONTROLLER SDA SCL A0 AD5305 Figure 38. Multiple AD5305 Devices on One Bus Rev. G | Page 20 of 24 00930-036 00930-038 00930-037 AD5305/AD5315/AD5325 AD5305/AD5315/AD5325 AS A DIGITALLY POWER SUPPLY DECOUPLING PROGRAMMABLE WINDOW DETECTOR In any circuit where accuracy is important, careful A digitally programmable upper/lower limit detector using two consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit of the DACs in the AD5305/AD5315/AD5325 is shown in board on which the AD5305/AD5315/AD5325 is mounted Figure 39. The upper and lower limits for the test are loaded to should be designed so that the analog and digital sections are DAC A and DAC B, which, in turn, set the limits on the CMP04. If separated and confined to certain areas of the board. If the the signal at the VIN input is not within the programmed window, an LED indicates the fail condition. Similarly, DAC C and DAC D AD5305/AD5315/AD5325 is in a system where multiple devices can be used for window detection on a second V signal. require an AGND-to-DGND connection, the connection IN should be made at one point only. The star ground point should 5V 0.1µF be established as close as possible to the device. The AD5305/ 10µF 1kΩ 1kΩ V IN AD5315/AD5325 should have ample supply bypassing of 10 μF PASS FAIL in parallel with 0.1 μF on the supply located as close to the V V DD REF REFIN package as possible, ideally right up against the device. The V A OUT 10 μF capacitors are the tantalum bead type. The 0.1 μF 1/2 AD5305/ 1/2 capacitor should have low effective series resistance (ESR) and PASS/FAIL AD5315/ CMP04 effective series inductance (ESI), such as the common ceramic 1 AD5325 DIN SDA types that provide a low impedance path to ground at high SCL SCL V B OUT 1/6 74HC05 GND frequencies to handle transient currents due to internal logic switching. 1 ADDITIONAL PINS OMITTED FOR CLARITY. The power supply lines of the AD5305/AD5315/AD5325 Figure 39. Window Detection should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply COARSE AND FINE ADJUSTMENT USING THE line. Fast switching signals such as clocks should be shielded AD5305/AD5315/AD5325 with digital ground to avoid radiating noise to other parts of the Two of the DACs in the AD5305/AD5315/AD5325 can be paired board, and should never be run near the reference inputs. A together to form a coarse and fine adjustment function, as shown ground line routed between the SDA and SCL lines helps reduce in Figure 40. DAC A is used to provide the coarse adjustment crosstalk between them (not required on a multilayer board as while DAC B provides the fine adjustment. Varying the ratio of there is a separate ground plane, but separating the lines does help). R1 and R2 changes the relative effect of the coarse and fine Avoid crossover of digital and analog signals. Traces on adjustments. With the resistor values and external reference shown opposite sides of the board should run at right angles to each in Figure 40, the output amplifier has unity gain for the DAC A other. This reduces the effects of feedthrough through the output. As a result, the output range is 0 V to 2.5 V − 1 LSB. For −3 board. A microstrip technique is by far the best, but is not DAC B, the amplifier has a gain of 7.6 × 10 , giving DAC B a always possible with a double-sided board. In this technique, range equal to 19 mV. Similarly, DAC C and DAC D can be the component side of the board is dedicated to ground plane paired together for coarse and fine adjustment. while signal traces are placed on the solder side. The circuit is shown with a 2.5 V reference, but reference voltages up to V can be used. The op amps indicated allows DD a rail-to-rail output swing. V = 5V DD R3 R4 51.2kΩ 390Ω 0.1µF 10µF 5V V IN V V OUT DD EXT V A V REFIN OUT OUT AD820/ REF R1 1µF 1/2 OP295 GND 390Ω AD5305/ AD5315/ AD780/REF192 1 AD5325 WITH V = 5V DD V B OUT R2 GND 51.2kΩ 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 40. Coarse/Fine Adjustment Rev. G | Page 21 of 24 00930-040 00930-039 AD5305/AD5315/AD5325 Table 9. Overview of All AD53xx Serial Devices Part No. Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins SINGLES AD5300 8 1 ±0.25 SPI® 4 SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-Wire 7 SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-Wire 8 SOT-23, MSOP 6, 8 DUALS AD53028 2 ±0.25 SPI 6 MSOP 8 AD531210 2 ±0.5 SPI 7 MSOP 8 AD5322 12 2 ±1.0 SPI 8 MSOP 8 AD53038 2 ±0.25 SPI 6 TSSOP 16 AD531310 2 ±0.5 SPI 7 TSSOP 16 AD5323 12 2 ±1.0 SPI 8 TSSOP 16 QUADS AD53048 4 ± 0.25 SPI 6 MSOP 10 AD531410 4 ± 0.5 SPI 7 MSOP 10 AD532412 4 ±1.0 SPI 8 MSOP 10 AD53058 4 ±0.25 2-Wire 6 MSOP 10 AD531510 4 ±0.5 2-Wire 7 MSOP 10 AD532512 4 ±1.0 2-Wire 8 MSOP 10 AD53068 4 ±0.25 2-Wire 6 TSSOP 16 AD531610 4 ±0.5 2-Wire 7 TSSOP 16 AD532612 4 ±1.0 2-Wire 8 TSSOP 16 AD53078 4 ±0.25 SPI 6 TSSOP 16 AD531710 4 ±0.5 SPI 7 TSSOP 16 AD532712 4 ±1.0 SPI 8 TSSOP 16 OCTALS AD53088 8 ±0.25 SPI 6 TSSOP 16 AD531810 8 ±0.5 SPI 7 TSSOP 16 AD532812 8 ±1.0 SPI 8 TSSOP 16 Table 10. Overview of AD53xx Parallel Devices Part No. Resolution DNL VREF Pins Settling Time (μs) Additional Pin Functions Package Pins SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 TSSOP 20 ✓ ✓ ✓ AD5331 10 ±0.5 1 7 TSSOP 20 ✓ ✓ AD5340 12 ±1.0 1 8 TSSOP 24 ✓ ✓ ✓ AD5341 12 ±1.0 1 8 TSSOP 20 ✓ ✓ ✓ ✓ DUALS AD5332 8 ±0.25 2 6 TSSOP 20 ✓ AD5333 10 ±0.5 2 7 TSSOP 24 ✓ ✓ ✓ AD5342 12 ±1.0 2 8 TSSOP 28 ✓ ✓ ✓ AD5343 12 ±1.0 1 8 TSSOP 20 ✓ ✓ QUADS AD5334 8 ±0.25 2 6 TSSOP 24 ✓ ✓ AD5335 10 ±0.5 2 7 TSSOP 24 ✓ ✓ AD5336 10 ±0.5 4 7 TSSOP 28 ✓ ✓ AD5344 12 ±1.0 4 8 TSSOP 28 Rev. G | Page 22 of 24 AD5305/AD5315/AD5325 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.40 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 41. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD5305ARM −40°C to +105°C 10-Lead MSOP RM-10 DEA AD5305ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DEA 1 AD5305ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D99 1 AD5305ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D99 AD5305BRM −40°C to +105°C 10-Lead MSOP RM-10 DEB AD5305BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DEB AD5305BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DEB 1 AD5305BRMZ −40°C to +105°C 10-Lead MSOP RM-10 DEB # 1 AD5305BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DEB # AD5315ARM −40°C to +105°C 10-Lead MSOP RM-10 DFA AD5315ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DFA 1 AD5315ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D8E AD5315BRM −40°C to +105°C 10-Lead MSOP RM-10 DFB AD5315BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DFB AD5315BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DFB 1 AD5315BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D6N 1 AD5315BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6N 1 AD5315BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6N AD5325ARM −40°C to +105°C 10-Lead MSOP RM-10 DGA AD5325ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DGA 1 AD5325ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D8G AD5325BRM −40°C to +105°C 10-Lead MSOP RM-10 DGB AD5325BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DGB AD5325BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DGB 1 AD5325BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D8H 1 AD5325BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D8H 1 AD5325BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D8H 1 Z = Pb-free part; # denotes lead-free product may be top or bottom marked. Rev. G | Page 23 of 24 AD5305/AD5315/AD5325 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00930-0-5/06(G) Rev. G | Page 24 of 24